Contribute FlexRAN 21.11 to the O-RAN OSC.
Issue-Id: ODULOW-17
Change-Id: Idff20bf75a873f1836bb5c717aae09905dfb9c77
Signed-off-by: Luis Farias <luis.farias@intel.com>
------------
O-RAN library implementation depends on the Data Plane Development Kit
-(DPDK v20.11.1).
+(DPDK v20.11.3).
-DPDK v20.11.1 should be patched with corresponding DPDK patch provided
+DPDK v20.11.3 should be patched with corresponding DPDK patch provided
with FlexRAN release (see *Table 1*, FlexRAN Reference Solution Software
Release Notes)
-Intel® C++ Compiler v19.0.3 is used.
+Intel OneApi DPC++/C++ Compiler is used. Version 2022.0.0 or newer.
+
+Intel® C++ Compiler v19.0.3 can also be used but not verified with the f release.
- Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64).
moment before the packet is sent to minimalize the delays added by the
Kernel processing the packet. Not every NIC supports that feature. To
confirm that currently attached NIC support Hardware Timestamps, use
-ethtool with the command::
+ethtool with the command:
- ethtool -T eth0
+ethtool -T eth0
Where the eth0 is the potential PHC port. The output from the command
should say that there is Hardware Timestamps support.
# make && make install
-22. Modify configs/default.cfg to control frequency of Sync interval to 0.0625 s. ::
+3. Modify configs/default.cfg to control frequency of Sync interval to
+0.0625 s. ::
- logSyncInterval -4
+ logSyncInterval -4
ptp4l
=====
like when synchronization is started. This means that PHC on this
machine is synchronized to the master PHC. ::
- ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
+ ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
+ ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[1434166.384]: port 1: new foreign master fcaf6a.fffe.029708-1
ptp4l[1434170.352]: selected best master clock fcaf6a.fffe.029708
- ptp4l[1434170.352]: updating UTC offset to 37
- ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
+ ptp4l[1434170.352]: updating UTC offset to 37
+ ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[1434171.763]: master offset -5873 s0 freq -18397 path delay 2778
ptp4l[1434172.763]: master offset -6088 s2 freq -18612 path delay 2778
ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
on the O-DU side, the Fronthaul port can be used as the source of PTP as
well as for U-plane and C-plane traffic.
-1. Follow the steps in Appendix *B.1.1,* *PTP for Linux\* Requirements*
-to install PTP on the O-RU server.
+1. Follow the steps in Appendix *B.1.1, PTP for Linux\* Requirements* to
+install PTP on the O-RU server.
-2.Copy configs/default.cfg to configs/default_slave.cfg and modify the
-Copied file as below::
+2. Copy configs/default.cfg to configs/default_slave.cfg and modify the
+copied file as below::
diff --git a/configs/default.cfg b/configs/default.cfg
old mode 100644
Example of output::
./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 -m
- ptp4l[3903857.249]: selected /dev/ptp3 as PTP clock
- ptp4l[3903857.266]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[3903857.267]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
+ ptp4l[3903857.249]: selected /dev/ptp3 as PTP clock
+ ptp4l[3903857.266]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
+ ptp4l[3903857.267]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[3903863.734]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best master
ptp4l[3903863.734]: assuming the grand master role
-7. Synchronize local NIC PTP master clock to local NIC PTP slave clock. ::
+7.Synchronize local NIC PTP master clock to local NIC PTP slave clock. ::
./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
Example of output::
- ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
+ ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
phc2sys[3904600.332]: enp175s0f1 phc offset 2042 s0 freq -2445 delay 4525
phc2sys[3904600.458]: enp175s0f1 phc offset 2070 s2 freq -2223 delay 4506
- phc2sys[3904600.584]: enp175s0f1 phc offset 2125 s2 freq -98 delay 4505
- phc2sys[3904600.710]: enp175s0f1 phc offset 1847 s2 freq +262 delay 4518
- phc2sys[3904600.836]: enp175s0f1 phc offset 1500 s2 freq +469 delay 4515
- phc2sys[3904600.961]: enp175s0f1 phc offset 1146 s2 freq +565 delay 4547
- phc2sys[3904601.086]: enp175s0f1 phc offset 877 s2 freq +640 delay 4542
- phc2sys[3904601.212]: enp175s0f1 phc offset 517 s2 freq +543 delay 4517
- phc2sys[3904601.337]: enp175s0f1 phc offset 189 s2 freq +370 delay 4510
- phc2sys[3904601.462]: enp175s0f1 phc offset -125 s2 freq +113 delay 4554
- phc2sys[3904601.587]: enp175s0f1 phc offset -412 s2 freq -212 delay 4513
- phc2sys[3904601.712]: enp175s0f1 phc offset -693 s2 freq -617 delay 4519
+ phc2sys[3904600.584]: enp175s0f1 phc offset 2125 s2 freq -98 delay 4505
+ phc2sys[3904600.710]: enp175s0f1 phc offset 1847 s2 freq +262 delay 4518
+ phc2sys[3904600.836]: enp175s0f1 phc offset 1500 s2 freq +469 delay 4515
+ phc2sys[3904600.961]: enp175s0f1 phc offset 1146 s2 freq +565 delay 4547
+ phc2sys[3904601.086]: enp175s0f1 phc offset 877 s2 freq +640 delay 4542
+ phc2sys[3904601.212]: enp175s0f1 phc offset 517 s2 freq +543 delay 4517
+ phc2sys[3904601.337]: enp175s0f1 phc offset 189 s2 freq +370 delay 4510
+ phc2sys[3904601.462]: enp175s0f1 phc offset -125 s2 freq +113 delay 4554
+ phc2sys[3904601.587]: enp175s0f1 phc offset -412 s2 freq -212 delay 4513
+ phc2sys[3904601.712]: enp175s0f1 phc offset -693 s2 freq -617 delay 4519
phc2sys[3904601.837]: enp175s0f1 phc offset -878 s2 freq -1009 delay 4515
phc2sys[3904601.962]: enp175s0f1 phc offset -965 s2 freq -1360 delay 4518
phc2sys[3904602.088]: enp175s0f1 phc offset -1048 s2 freq -1732 delay 4510
ptp4l[809108.055]: rms 401 max 502 freq +912 +/- 659
10. Synchronize local clock on O-DU for sample application or l1
-Application. ::
+application. ::
./phc2sys -s enp181s0f0 -w -m -R 8
except for the direction field.
Examples of default configurations used with the sample application for
-v21.03 release provided below:
+v20.04 release provided below:
1 Cell mmWave 100MHz TDD DDDS:
------------------------------
0-RU side are the same, except configuration file options may be
different.
-.. image:: images/Setup-for-xRAN-Testing.jpg
+.. image:: images/Setup-for-O-RAN-Testing.jpg
:width: 400
- :alt: Figure 26. Setup for O-RAN Testing
+ :alt: Figure 27. Setup for O-RAN Testing
-Figure 26. Setup for O-RAN Testing
+Figure 27. Setup for O-RAN Testing
-.. image:: images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3.jpg
+
+
+.. image:: images/Setup-for-O-RAN-Testing-with-PHY-and-Configuration-C3.jpg
+ :width: 400
+ :alt: Figure 28. Setup for O-RAN Testing with PHY and Configuration C3
+
+Figure 28. Setup for O-RAN Testing with PHY and Configuration C3
+
+
+
+.. image:: images/Setup-for-O-RAN-Testing-with-PHY-and-Configuration-C3-for-Massive-MIMO.jpg
:width: 400
- :alt: Figure 27. Setup for O-RAN Testing with PHY and Configuration C3
+ :alt: Figure 29. Setup for O-RAN Testing with PHY and Configuration C3 for
+
+Figure 29. Setup for O-RAN Testing with PHY and Configuration C3 for
+Massive MIMO
+
-Figure 27. Setup for O-RAN Testing with PHY and Configuration C3
A.2 Prerequisites
-----------------
-Each server in Figure 26 requires the following:
+
+Each server in *Figure 27* requires the following:
- Wolfpass server according to recommended BOM for FlexRAN such as
Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20
- cores (two sockets)
+ cores (two sockets) or higher
+
+- Wilson City or Coyote Pass server with Intel® Xeon® Icelake CPU for
+ Massive-MIMO with L1 pipeline testing
- BIOS settings:
..
-https://downloadmirror.intel.com/682037/readme_8_50.txt
-(700 series)
+https://downloadcenter.intel.com/download/24769 (700 series)
-https://downloadmirror.intel.com/709693/readme_3.10.txt
-(E810 series)
+https://downloadcenter.intel.com/download/29736 (E810 series)
PTP Grand Master is required to be available in the network to provide
synchronization of both O-DU and RU to GPS time.
patch according to FlexRAN Reference Solution Cloud-Native Setup
document (refer to Table 2). Only real-time HOST is required.
-1. Install Intel® C++ Compiler v19.0.3
+1. Install Intel® C++ Compiler v19.0.3 or OneAPI compiler (preferred)
-2. Download DPDK v20.11.1
+2. Download DPDK v20.11.3
3. Patch DPDK with FlexRAN BBDev patch as per given release.
ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
}
-5.Build and install DPDK::
+5.Build and install the DPDK::
See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html
To install and configure the sample application:
-1. Set up the environment::
+1. Set up the environment(shown for icc change for icx)::
For Skylake and Cascadelake
export GTEST_ROOT=pwd/gtest-1.7.0
- export RTE_SDK=pwd/dpdk-20.11.1
+ export RTE_SDK=pwd/dpdk-20.11.3
export RTE_TARGET=x86_64-native-linuxapp-icc
export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk
export WIRELESS_SDK_TARGET_ISA=avx512
export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
- export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog
- export XRAN_DIR=pwd/flexran_xran
+ export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
+ export XRAN_DIR=`pwd`/flexran_xran
for Icelake
- export GTEST_ROOT=pwd/gtest-1.7.0
- export RTE_SDK=pwd/dpdk-20.11.1
+ export GTEST_ROOT=`pwd`/gtest-1.7.0
+ export RTE_SDK=`pwd`/dpdk-20.11
export RTE_TARGET=x86_64-native-linuxapp-icc
- export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk
+ export DIR_WIRELESS_SDK_ROOT=`pwd`/wireless_sdk
export WIRELESS_SDK_TARGET_ISA=snc
export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
- export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog
- export XRAN_DIR=pwd/flexran_xran
+ export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
+ export XRAN_DIR=`pwd`/flexran_xran
2. export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library::
The 5G NR layer 1 application can be used for executing the scenario for
mmWave with either the RU sample application or just the O-DU side. The
current release supports the constant configuration of the slot pattern
-and RB allocation on the PHY side.
+and RB allocation on the PHY side. The build process follows the same
+basic steps as for the sample application above and is similar to
+compiling 5G NR l1app for mmWave with Front Haul FPGA. Please follow the
+general build process in the FlexRAN 5G NR Reference Solution L1 User
+Guide (refer to *Table 2*.) (For information only as a FlexRAN binary blob
+is delivered to the community)
-1. O-RAN library is enabled by default l1 application:
+1. O-RAN library is enabled by default l1 application
2. Get the FlexRAN L1 binary from https://github.com/intel/FlexRAN. Look for the l1/bin/nr5g/gnb/l1 folder for the
l1app binary and the corresponding phycfg and xrancfg files.
3. Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and
-xrancfg_sub6.xml (or other xml if it is mmwave or massive MIMO). ::
+xrancfg_sub6.xml (or other xml if it is mmW or massive MIMO). ::
- <XranConfig>
- <version>oran_e_maintenance_release_v1.0</version>
- <!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
+ <XranConfig>
+ <version>oran_f_release_v1.0</version>
+ <!-- numbers of O-RU connected to O-DU. All O-RUs are the same
+ capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
<oRuNum>1</oRuNum>
- <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
+ <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
<oRuEthLinkSpeed>25</oRuEthLinkSpeed>
- <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link in IOT spec) -->
+ <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link
+ in IOT spec) -->
<oRuLinesNumber>1</oRuLinesNumber>
<!-- O-RU 0 -->
<!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
<xRANWorker>0x8000000000, 96, 0</xRANWorker>
+ <xRANWorker_64_127>0x0000000000, 96, 0</xRANWorker_64_127>
<!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
<Category>0</Category>
+ <!-- Slot setup processing offload to pipeline BBU cores: [0: USE XRAN CORES 1: USE BBU CORES] -->
+ <xRANOffload>0</xRANOffload>
+ <!-- XRAN MLOG: [0: DISABLE 1: ENABLE] -->
+ <xRANMLog>0</xRANMLog>
<!-- XRAN: enable sleep on PMD cores -->
<xranPmdSleep>0</xranPmdSleep>
<DynamicSectionEna>0</DynamicSectionEna>
<!-- Enable Dynamic section allocation for UL -->
<DynamicSectionEnaUL>0</DynamicSectionEnaUL>
+ <!-- Enable muti section for C-Plane -->
+ <DynamicMultiSectionEna>0</DynamicMultiSectionEna>
+
<xRANSFNWrap>1</xRANSFNWrap>
<!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
<xRANNumDLPRBs>0</xRANNumDLPRBs>
<!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
<xranCompMethod>1</xranCompMethod>
+ <!-- XRAN: Uplane Compression Header type 0 - dynamic 1 - static -->
+ <xranCompHdrType>0</xranCompHdrType>
<!-- XRAN: iqWidth when DynamicSectionEna and BFP Compression enabled -->
- <xraniqWidth>8</xraniqWidth>
+ <xraniqWidth>9</xraniqWidth>
<!-- Whether Modulation Compression mode is enabled or not for DL only -->
<xranModCompEna>0</xranModCompEna>
+ <!-- XRAN: Prach Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
+ <xranPrachCompMethod>0</xranPrachCompMethod>
+ <!-- Whether Prach iqWidth when DynamicSectionEna and BFP Compression enabled -->
+ <xranPrachiqWidth>16</xranPrachiqWidth>
+ <oRu0MaxSectionsPerSlot>6</oRu0MaxSectionsPerSlot>
+ <oRu0MaxSectionsPerSymbol>6</oRu0MaxSectionsPerSymbol>
<oRu0nPrbElemDl>1</oRu0nPrbElemDl>
<!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
<!-- weight base beams -->
</XranConfig>
-4. Modify bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
+4. Modify l1/bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1
5. Use configuration of test mac per::
- /bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
+ l1//bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg (info only N/A)
phystart 4 0 40200
<!-- mmWave mu 3 100MHz -->
TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg
6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::
- [root@xran flexran] cd ./bin/nr5g/gnb/l1
+ [root@xran flexran] cd ./l1/bin/nr5g/gnb/l1
[root@xran l1]#./l1.sh –xran
-where output corresponding L1 is
7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::
- [root@xran flexran] cd ./bin/nr5g/gnb/testmac
+ [root@xran flexran] cd ./l1/bin/nr5g/gnb/testmac
-8. To execute test case type::
+8. To execute test case type (info only as file not available)::
./l2.sh
--testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
-where output corresponding to Test MAC::
-
- [root@sc12-xran-sub6 testmac]# ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
-
Configure FlexRAN 5G NR L1 Application for multiple O-RUs with multiple numerologies
====================================================================================
Look for the l1/bin/nr5g/gnb/l1 folder for the
l1app binary and the corresponding phycfg and xrancfg files.
-3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml.
+3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml.::
-<XranConfig>
- <version>oran_e_maintenance_release_v1.0<</version>
+ <XranConfig>
+ <version>oran_f_release_v1.0<</version>
<!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
<oRuNum>3</oRuNum>
<!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
<oRu2PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs0>
<oRu2PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs1>
-</XranConfig>
+ </XranConfig>
4. Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
5. Use configuration of test mac per::
+ (Info only as these files not avilable)
/bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
phystart 4 0 100200
TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg,
6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::
- [root@xran flexran] cd ./bin/nr5g/gnb/l1
+ [root@xran flexran] cd ./l1/bin/nr5g/gnb/l1
./l1.sh -xranmmimo
Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB)
+
7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::
- [root@xran flexran] cd ./bin/nr5g/gnb/testmac
+ [root@xran flexran] cd ./l1/bin/nr5g/gnb/testmac
8. To execute test case type::
+ (Info only as file not available)
./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
-where output corresponding to Test MAC::
-
- root@icelake-scs1-1 testmac]# ./l2.sh --testfile=./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
Introduction
------------
-Figure 8 presents an overview of the O-RAN Fronthaul process.
+The following figure presents an overview of the O-RAN Fronthaul process.
-.. image:: images/ORAN-Fronthaul-Process.jpg
+.. image:: images/O-RAN-Fronthaul-Process.jpg
:width: 600
:alt: Figure 8. O-RAN Fronthaul Process
Quadrature (IQ) samples between the O-DU and O-RU within the O-RAN
architecture based on functional split 7.2x. The library defines the
O-RAN packet formats to be used to transport radio samples within Front
-Haul according to the O-RAN Fronthaul specification. It provides
-functionality for generating O-RAN packets, appending IQ samples in the
-packet payload, and extracting IQ samples from O-RAN packets.
+Haul according to the O-RAN Fronthaul specification. refer to *Table* 2.
+It provides functionality for generating O-RAN packets, appending IQ samples
+in the packet payload, and extracting IQ samples from O-RAN packets.
-Note: The E Miantenance release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment.
+Note: The F release version of the library supports U-plane and C-plane only.
+M-plane is not supported. It is ready to be used in the PTP synchronized environment.
Note: Regarding the clock model and synchronization topology, configurations
C1 and C3 of the connection between O-DU and O-RU are the only
---------------------
The O-RAN Fronthaul specification defines a list of mandatory
-functionality. Not all features defined as Mandatory for O-DU are
-currently supported to fully extended. The following tables contain
+functionalities.
+
+Note: Not all features defined as Mandatory for O-DU are
+currently supported to a full extension. The following tables contain
information on what is available and the level of validation performed
for this release.
Note. Cells with a red background are listed as mandatory in the
specification but not supported in this implementation of O-RAN.
-Table 7. ORAN Mandatory and Optional Feature Support
+Table 7. O-RAN Mandatory and Optional Feature Support
+-----------------+-----------------+-----------+----------------+
| Category | Feature | O-DU | Support |
Level of Validation Specified as:
-- C: Completed code implementation for O-RAN Library
-
-- I: Integrated into Intel FlexRAN PHY
-
-- T: Tested end to end with O-RU
-
-Table 8. Levels of support
-
-+------------+------------+------------+------------+-----+-----+-----+
-| Category | Item | Status | C | I | T |
-+============+============+============+============+=====+=====+=====+
-| General || Radio | NR | N/A | N/A | N/A |
-| || access | | | | |
-| || technology | | | | |
-| || (LTE / NR) | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || Nominal || 15 | Y | Y | N |
-| || sub-carrier || /30/120KHz| | | |
-| || spacing | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| | FFT size || 512/1024 | Y | Y | N |
-| | || /2048/4096| | | |
-| +------------+------------+------------+-----+-----+-----+
-| || Channel || 5/10 | Y | Y | N |
-| || bandwidth || /20/100Mhz| | | |
-| +------------+------------+------------+-----+-----+-----+
-| || Number of | 12 | Y | Y | N |
-| || Cells | | | | |
-| || (Component | | | | |
-| || Carriers) | | | | |
-| || | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || RU | A | Y | Y | N |
-| || category | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| | TDD Config || Supported | Y | Y | N |
-| | || Flexible | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || FDD | Supported | Y | Y | N |
-| || Support | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || Tx/Rx | Supported | Y | Y | N |
-| || switching | | | | |
-| || based on | | | | |
-| || 'data | | | | |
-| || Direction' | | | | |
-| || field of | | | | |
-| || C-plane | | | | |
-| || message | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || IP version | N/A | N/A | N/A | N/A |
-| || for | | | | |
-| || Management | | | | |
-| || traffic at | | | | |
-| || fronthaul | | | | |
-| || network | | | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-| PRACH || One Type 3 | Supported | Y | Y | N |
-| || message | | | | |
-| || for all | | | | |
-| || repeated | | | | |
-| || PRACH | | | | |
-| || preambles | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Type 3 | 1 | Y | Y | N |
-| || message | | | | |
-| || per | | | | |
-| || repeated | | | | |
-| || PRACH | | | | |
-| || preambles | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || timeOffset | Supported | Y | Y | N |
-| || including | | | | |
-| || cpLength | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| | Supported | Supported | Y | Y | N |
-| +-------------------------+------------+-----+-----+-----+
-| || PRACH | Supported | Y | Y | N |
-| || preamble | | | | |
-| || format | | | | |
-| || index | | | | |
-| || number | | | | |
-| || (number of | | | | |
-| || occasions) | | | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-|| Delay || Network | Supported | Y | Y | N |
-|| management|| delay | | | | |
-| || determination | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || lls-CU | Supported | Y | Y | N |
-| || timing | | | | |
-| || advance | | | | |
-| || type | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Non-delay || Not | N | N | N |
-| || managed || supported | | | |
-| || U-plane | | | | |
-| || traffic | | | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-|| C/U-plane || Transport | Ethernet | Y | Y | N |
-|| Transport || encapsulation | | | | |
-| || (Ethernet IP) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Jumbo | Supported | Y | Y | N |
-| || frames | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Transport | eCPRI | Y | Y | N |
-| || header | | | | |
-| || (eCPRI RoE) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || IP version | N/A | N/A | N/A | N/A |
-| || when | | | | |
-| || Transport | | | | |
-| || header is | | | | |
-| || IP/UDP | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || eCPRI || Not | N | N | N |
-| || Concatenation || supported | | | |
-| || when | | | | |
-| || Transport | | | | |
-| || header is | | | | |
-| || eCPRI | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || eAxC ID | 4 \* | Y | Y | N |
-| || CU_Port_ID | | | | |
-| || bitwidth | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || eAxC ID | 4 \* | Y | Y | N |
-| || BandSector_ID | | | | |
-| || bitwidth | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || eAxC ID | 4 \* | Y | Y | N |
-| || CC_ID | | | | |
-| || bitwidth | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || eAxC ID | 4 \* | Y | Y | N |
-| || RU_Port_ID | | | | |
-| || bitwidth | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| | Fragmentation | Supported | Y | Y | N |
-| +-------------------------+------------+-----+-----+-----+
-| || Transport | N/A | N | N | N |
-| || prioritization | | | | |
-| || within | | | | |
-| || U-plane | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Separation | Supported | Y | Y | N |
-| || of | | | | |
-| || C/U-plane | | | | |
-| || and | | | | |
-| || M-plane | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Separation || VLAN ID\ | Y | Y | N |
-| || of C-plane || and/or | | | |
-| || and || eCpri | | | |
-| || U-plane || Messagge | | | |
-| | || Type | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Max Number | 16 | Y | Y | N |
-| || of VLAN | | | | |
-| || per | | | | |
-| || physical | | | | |
-| || port | | | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-|| Reception | Rx_on_time | Supported | Y | Y | N |
-|| Window | | | | | |
-|| Monitoring| | | | | |
-|| (Counters)| | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| | Rx_early | Supported | N | N | N |
-| +-------------------------+------------+-----+-----+-----+
-| | Rx_late | Supported | N | N | N |
-| +-------------------------+------------+-----+-----+-----+
-| | Rx_corrupt | Supported | N | N | N |
-| +-------------------------+------------+-----+-----+-----+
-| || Rx_pkt_dupl | Supported | N | N | N |
-| +-------------------------+------------+-----+-----+-----+
-| || Total_msgs_rcvd | Supported | Y | N | N |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-|| || RU || Index and | Y | Y | N |
-|| Beam-\ || beamforming || weights | | | |
-|| forming || type || | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Beamforming | C-plane | Y | N | N |
-| || control | | | | |
-| || method | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Number of || No res- | Y | Y | N |
-| || beams || strictions| | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-|| IQ || U-plane | Supported | Y | Y | Y |
-|| compre || data | | | | |
-| ssion || compression | | | | |
-| || method | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || U-plane || BFP: | Y | Y | Y |
-| || data IQ || 8,9,12,14 | | | |
-| || bitwidth || bits | | | |
-| || (Before / || | | | |
-| || After || | | | |
-| || compression) || | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Static | Supported | N | N | N |
-| || configuration | | | | |
-| || of U-plane | | | | |
-| || IQ format | | | | |
-| || and | | | | |
-| || compression | | | | |
-| || header | | | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-|| eCPRI || ecpriVersion | 001b | Y | Y | Y |
-|| Header || | | | | |
-|| Format || | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || ecpriReserved | Supported | Y | Y | Y |
-| +-------------------------+------------+-----+-----+-----+
-| || ecpriCon || Not | N | N | N |
-| | catenation || supported | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || ecpri\ | U-plane | Supported | Y | Y | Y |
-| || Message | | | | | |
-| | +------------+------------+-----+-----+-----+
-| | | C-plane | Supported | Y | Y | Y |
-| | +------------+------------+-----+-----+-----+
-| | || Delay | Supported | Y | Y | Y |
-| | || measure | | | | |
-| | | ment | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || ecpri\ | Supported | Y | Y | Y |
-| || Payload | | | | |
-| || (payload | | | | |
-| || size in | | | | |
-| || bytes) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || ecpriRtcid | Supported | Y | Y | Y |
-| || /ecpriPcid | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || ecpri | Supported | Y | Y | Y |
-| || Seqid: | | | | |
-| || Sequence | | | | |
-| || ID | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || ecpri\ | Supported | Y | Y | Y |
-| || Seqid: | | | | |
-| || E bit | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || ecpri\ || Not | N | N | N |
-| || Seqid: || supported | | | |
-| || Sub\ | | | | |
-| || sequence | | | | |
-| || ID | | | | |
-| | | | | | |
-+------------+------------+------------+------------+-----+-----+-----+
-|| C-plane || Section || Not | N | N | N |
-|| Type || Type 0 || supported | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Section | Supported | Y | Y | Y |
-| || Type 1 | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Section | Supported | Y | Y | Y |
-| || Type 3 | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Section || Not | N | N | N |
-| || Type 5 || supported | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Section || Not | N | N | N |
-| || Type 6 || supported | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Section || Not | N | N | N |
-| || Type 7 || supported | | | |
-| | | | | | |
-+------------+------------+------------+------------+-----+-----+-----+
-|| C-plane || *Coding*\ || data\ | Supported | Y | Y | N |
-|| Packet || *of Infor*|| Direction | | | | |
-|| Format | *mation* || (data | | | | |
-| || *Elements*|| direction | | | | |
-| || *Appli* || (gNB | | | | |
-| | *cation* || Tx/Rx)) | | | | |
-| || *Layer,*\ || | | | | |
-| || *Common* || | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || payload || 001b | Y | Y | N |
-| | | Version || | | | |
-| | || (payload || | | | |
-| | || version) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || filter | Supported | Y | Y | N |
-| | | Index | | | | |
-| | || (filter | | | | |
-| | || index) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || frameId | Supported | Y | Y | N |
-| | || (frame | | | | |
-| | || iden | | | | |
-| | | tifier) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || subframeId| Supported | Y | Y | N |
-| | || (subframe | | | | |
-| | || iden | | | | |
-| | | tifier) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || slotId | Supported | Y | Y | N |
-| | || (slot | | | | |
-| | || iden | | | | |
-| | | tifier) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || start\ | Supported | Y | Y | N |
-| | || Symbolid | | | | |
-| | || (start | | | | |
-| | || symbol | | | | |
-| | || iden | | | | |
-| | | tifier) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || number || up to the | Y | Y | N |
-| | || Ofsections|| maximum | | | |
-| | || (number of|| number of | | | |
-| | || sections) || PRBs | | | |
-| | +------------+------------+-----+-----+-----+
-| | || section\ || 1 and 3 | Y | Y | N |
-| | || Type || | | | |
-| | || (section || | | | |
-| | || type) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || udCompHdr | Supported | Y | Y | N |
-| | || (user data| | | | |
-| | || com | | | | |
-| | | pression | | | | |
-| | || header) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || number\ || Not | N | N | N |
-| | || OfUEs || supported | | | |
-| | || (number Of| | | | |
-| | || UEs) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || timeOffset| Supported | Y | Y | N |
-| | || (time | | | | |
-| | || offset) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || frame\ | mu=0,1,3 | Y | Y | N |
-| | || Structure | | | | |
-| | || (frame | | | | |
-| | || structure)| | | | |
-| | +------------+------------+-----+-----+-----+
-| | || cpLength | Supported | Y | Y | N |
-| | || (cyclic | | | | |
-| | || prefix | | | | |
-| | || length) | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || *Coding* || sectionId | Supported | Y | Y | N |
-| || *of Infor*|| (section | | | | |
-| | *mation* || iden | | | | |
-| || *Elements*| tifier) | | | | |
-| || *Ap* | | | | | |
-| | *plication*| | | | | |
-| || *Layer,* | | | | | |
-| || *Sections*| | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || rb | 0 | Y | Y | N |
-| | || (resource | | | | |
-| | || block | | | | |
-| | || indicator)| | | | |
-| | +------------+------------+-----+-----+-----+
-| | || symInc | 0 or 1 | Y | Y | N |
-| | || (symbol | | | | |
-| | || number | | | | |
-| | || increment | | | | |
-| | || command) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || startPrbc | Supported | Y | Y | N |
-| | || (starting | | | | |
-| | || PRB of | | | | |
-| | || control | | | | |
-| | || section) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || reMask | Supported | Y | Y | N |
-| | || (resource | | | | |
-| | || element | | | | |
-| | || mask) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || numPrbc | Supported | Y | Y | N |
-| | || (number of| | | | |
-| | || contiguous| | | | |
-| | || PRBs per | | | | |
-| | || control | | | | |
-| | || section) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || numSymbol | Supported | Y | Y | N |
-| | || (number of| | | | |
-| | || symbols) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || ef | Supported | Y | Y | N |
-| | || (extension| | | | |
-| | || flag) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || beamId | Support | Y | Y | N |
-| | || (beam | | | | |
-| | || iden | | | | |
-| | | tifier) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || ueId (UE || Not | N | N | N |
-| | || iden || supported | | | |
-| | | tifier) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || freqOffset| Supported | Y | Y | N |
-| | || (frequency| | | | |
-| | || offset) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || regulari || Not | N | N | N |
-| | | zation\ || supported | | | |
-| | || Factor || | | | |
-| | || (regulari | | | | |
-| | | zation | | | | |
-| | || Factor) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || ciIsample,|| Not | N | N | N |
-| | || ciQsample || supported | | | |
-| | || (channel || | | | |
-| | || infor | | | | |
-| | | mation | | | | |
-| | || I and Q | | | | |
-| | || values) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || laaMsgType|| Not | N | N | N |
-| | || (LAA || supported | | | |
-| | || message || | | | |
-| | || type) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || laaMsgLen || Not | N | N | N |
-| | || (LAA || supported | | | |
-| | || message | | | | |
-| | || length) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | | lbtHandle || Not | N | N | N |
-| | | || supported | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtDefer || Not | N | N | N |
-| | || Factor || supported | | | |
-| | || (listen || | | | |
-| | || before || | | | |
-| | || talk || | | | |
-| | || defer || | | | |
-| | || factor) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtBack || Not | N | N | N |
-| | || offCounter|| supported | | | |
-| | || (listen || | | | |
-| | || before || | | | |
-| | || talk || | | | |
-| | || backoff || | | | |
-| | || counter) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtOffset || Not | N | N | N |
-| | || (listen- || supported | | | |
-| | || before | | | | |
-| | || talk || | | | |
-| | || offset) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || MCOT || Not | N | N | N |
-| | || (maximum || supported | | | |
-| | || channel | | | | |
-| | || occupancy | | | | |
-| | || time) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtMode || Not | N | N | N |
-| | || (LBT Mode)|| supported | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbt || Not | N | N | N |
-| | | PdschRes || supported | | | |
-| | || (LBT PDSCH|| | | | |
-| | || Result) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || sfStatus || Not | N | N | N |
-| | || (subframe || supported | | | |
-| | || status) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtDrsRes || Not | N | N | N |
-| | || (LBT DRS || supported | | | |
-| | || Result) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || initial || Not | N | N | N |
-| | | PartialSF || supported | | | |
-| | || (Initial | | | | |
-| | | partial | | | | |
-| | | SF) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtBufErr || Not | N | N | N |
-| | || (LBT || supported | | | |
-| | | Buffer | | | | |
-| | || Error) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || sfnSf || Not | N | N | N |
-| | || (SFN/SF || supported | | | |
-| | | End) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbt || Not | N | N | N |
-| | || CWConfig_H|| supported | | | |
-| | || (HARQ | | | | |
-| | || Parameters| | | | |
-| | || for | | | | |
-| | || Congestion| | | | |
-| | || Window | | | | |
-| | || mana | | | | |
-| | | gement) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbt || Not | N | N | N |
-| | || CWConfig_T|| supported | | | |
-| | || (TB | | | | |
-| | | Parameters | | | | |
-| | || for | | | | |
-| | || Congestion| | | | |
-| | || Window | | | | |
-| | || mana | | | | |
-| | | gement) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtTr || Not | N | N | N |
-| | | afficClass || supported | | | |
-| | || (Traffic | | | | |
-| | || class | | | | |
-| | || priority | | | | |
-| | || for | | | | |
-| | || Congestion| | | | |
-| | || Window | | | | |
-| | || mana | | | | |
-| | | gement) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || lbtCWR_Rst|| Not | N | N | N |
-| | || (Noti || supported | | | |
-| | | cation | | | | |
-| | || about | | | | |
-| | || packet | | | | |
-| | || reception | | | | |
-| | || successful| | | | |
-| | || or not) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || reserved | 0 | N | N | N |
-| | || (reserved | | | | |
-| | || for future| | | | |
-| | || use) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || *Section* | | | | |
-| | || *Exten* | | | | |
-| | | *sion* | | | | |
-| | || *Commands*| | | | |
-| | +------------+------------+-----+-----+-----+
-| | || extType | Supported | Y | Y | N |
-| | || (extension| | | | |
-| | || type) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || ef | Supported | Y | Y | N |
-| | | (extension | | | | |
-| | || flag) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || extLen | Supported | Y | Y | N |
-| | || (extension| | | | |
-| | || length) | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || Coding of | | | | | |
-| || Infor | | | | | |
-| | mation | | | | | |
-| || Elements –| | | | | |
-| || Appli | | | | | |
-| | cation | | | | | |
-| || Layer, | | | | | |
-| || Section | | | | | |
-| || Exten | | | | | |
-| | sions | | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || | | | | | |
-| || *Ext*\ || bfw | Supported | Y | Y | N |
-| || *Type=1:* || CompHdr | | | | |
-| || *Beam* || (beam\ | | | | |
-| || *forming* | forming | | | | |
-| || *Weights* || weight | | | | |
-| || *Exten\* || compre\ | | | | |
-| | *sion* | ssion | | | | |
-| || *Type* || header) | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || | | | | |
-| || || bf | Supported | Y | Y | N |
-| || | wCompParam | | | | |
-| || || (beam | | | | |
-| || || forming | | | | |
-| || || weight | | | | |
-| || || compre\ | | | | |
-| || | ssion | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfwl | Supported | Y | Y | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || weight | | | | |
-| || || in-phase | | | | |
-| || || value) | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfwQ | Supported | Y | Y | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || weight | | | | |
-| || || quadrature| | | | |
-| || || value) | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || || bfaCompHdr| Supported | Y | N | N |
-| || *ExtType*\|| | | | | |
-| || *=2:* || (beam\ | | | | |
-| || *Beam* | forming | | | | |
-| | *forming* || attributes| | | | |
-| || *Attribu* || compre | | | | |
-| | *tes* | ssion | | | | |
-| || *Exten* || header) | | | | |
-| || *sion* | | | | | |
-| || *Type* | | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfAzPt | Supported | Y | N | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || azimuth | | | | |
-| || || pointing | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfZePt | Supported | Y | N | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || zenith | | | | |
-| || || pointing | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfAz3dd | Supported | Y | N | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || azimuth | | | | |
-| || || beamwidth | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfZe3dd | Supported | Y | N | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || zenith | | | | |
-| || || beamwidth | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfAzSl | Supported | Y | N | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || azimuth | | | | |
-| || || sidelobe | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || bfZeSl | Supported | Y | N | N |
-| || || (beam | | | | |
-| || | forming | | | | |
-| || || zenith | | | | |
-| || || sidelobe | | | | |
-| || || parameter)| | | | |
-| || +------------+------------+-----+-----+-----+
-| || || zero- | Supported | Y | N | N |
-| || | padding | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || || code\ | Supported | Y | N | N |
-| || *ExtType* || bookIndex | | | | |
-| || *=3:* || | | | | |
-| || *DL* || (precoder | | | | |
-| || *Preco* || codebook | | | | |
-| | *ding* || | | | | |
-| || *Exten* || used for | | | | |
-| | *sion* || trans | | | | |
-| || *Type* | mission | | | | |
-| | | | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || layerID | Supported | Y | N | N |
-| || || (Layer ID | | | | |
-| || || for DL | | | | |
-| || || trans | | | | |
-| || | mission) | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || txScheme | Supported | Y | N | N |
-| || || (trans | | | | |
-| || | mission | | | | |
-| || || scheme) | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || numLayers | Supported | Y | N | N |
-| || || (number of| | | | |
-| || || layers | | | | |
-| || || used for | | | | |
-| || || DL | | | | |
-| || || trans | | | | |
-| || | mission) | | | | |
-| || +------------+------------+-----+-----+-----+
-| || || crsReMask | Supported | Y | N | N |
-| || || (CRS | | | | |
-| || || resource | | | | |
-| || || element | | | | |
-| || || mask) | | | | |
-| || +------------+------------+-----+-----+-----+
-| | || crs\ | Supported | Y | N | N |
-| | || SyumINum | | | | |
-| | || (CRS | | | | |
-| | || symbol | | | | |
-| | || number | | | | |
-| | || indi | | | | |
-| | | cation) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || crsShift | Supported | Y | N | N |
-| | || (crsShift | | | | |
-| | || used for | | | | |
-| | || DL | | | | |
-| | || trans | | | | |
-| | | mission) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || beamIdAP1 | Supported | Y | N | N |
-| | || (beam id | | | | |
-| | || to be used| | | | |
-| | || for | | | | |
-| | || antenna | | | | |
-| | || port 1) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || beamIdAP2 | Supported | Y | N | N |
-| | || (beam id | | | | |
-| | || to be used| | | | |
-| | || for | | | | |
-| | || antenna | | | | |
-| | || port 2) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || beamIdAP3 | Supported | Y | N | N |
-| | || (beam id | | | | |
-| | || to be used| | | | |
-| | || for | | | | |
-| | || antenna | | | | |
-| | || port 3) | | | | |
-| | | | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| | || csf || Supported | Y | Y | N |
-| || *ExtType*\|| (cons || | | | |
-| || *=4:* | tellation || | | | |
-| || *Modula* || shift | | | | |
-| | *tion* || flag) | | | | |
-| || *Compre* || | | | | |
-| | *ssion* || | | | | |
-| || *Parame* || | | | | |
-| | *ters* || | | | | |
-| || *Exten* || | | | | |
-| | *sion* | | | | | |
-| || *Type* || | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || mod || Supported | Y | Y | N |
-| | || CompScaler|| | | | |
-| | || ( || | | | |
-| | || modulation|| | | | |
-| | || compre || | | | |
-| | | ssion || | | | |
-| | || scaler || | | | |
-| | | value) || | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || || mcScale\ || Supported | Y | N | N |
-| || *ExtType*\|| ReMask || | | | |
-| || *=5:* || ( || | | | |
-| || *Modula* || modulation|| | | | |
-| | *tion* || compre || | | | |
-| || *Compre* | ssion || | | | |
-| | *ssion* || power || | | | |
-| || *Additio* || RE || | | | |
-| || *Parame* || mask) || | | | |
-| || *ters* | || | | | |
-| || *Exten* || | | | | |
-| | *sion* || | | | | |
-| || Type* | || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || csf || Supported | Y | N | N |
-| | || (cons || | | | |
-| | | tellation || | | | |
-| | || shift || | | | |
-| | || flag) || | | | |
-| | +------------+------------+-----+-----+-----+
-| | || mcScale\ | Supported | Y | N | N |
-| | || Offset | | | | |
-| | || (scaling | | | | |
-| | || value for | | | | |
-| | || modulation| | | | |
-| | || compre | | | | |
-| | | ssion) | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || *E* || rbgSize | Supported | Y | N | N |
-| | *xtType=6:*|| (resource | | | | |
-| || *Non-con* || block | | | | |
-| | *tiguous* || group | | | | |
-| || *PRB* || size) | | | | |
-| || *alloca* | | | | | |
-| | *tion in* | | | | | |
-| || *time and*| | | | | |
-| || *frequen* | | | | | |
-| | *cy domain*| | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || rbgMask | Supported | Y | N | N |
-| | || (resource | | | | |
-| | || block | | | | |
-| | || group bit | | | | |
-| | || mask) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || symbol\ | Supported | Y | N | N |
-| | || Mask | | | | |
-| | || (symbol | | | | |
-| | || bit mask) | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || *Ext* || beam | Supported | Y | N | N |
-| | *Type=10:* || GroupType | | | | |
-| || *Section* | | | | | |
-| || *des\* | | | | | |
-| | *cription* | | | | | |
-| || *for gro\*| | | | | |
-| | *up* | | | | | |
-| || *configu\*| | | | | |
-| | *ration of*| | | | | |
-| || *multiple*| | | | | |
-| || *ports* | | | | | |
-| | | | | | | |
-| | +------------+------------+-----+-----+-----+
-| | | numPortc | Supported | Y | N | N |
-| | | | | | | |
-| +------------+------------+------------+-----+-----+-----+
-| || *Ext* || b | Supported | Y | Y | N |
-| | *Type=11:* | fwCompHdr | | | | |
-| || *Flexible*|| (beam | | | | |
-| || *Beam* | forming | | | | |
-| | *forming* || weight | | | | |
-| || *Weights* || compre | | | | |
-| || *Exten* | ssion | | | | |
-| | *sion* | | | | | |
-| || *Type* || header) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || bfw | Supported | Y | Y | N |
-| | || CompParam | | | | |
-| | || for PRB | | | | |
-| | || bundle x | | | | |
-| | || (beam | | | | |
-| | | forming | | | | |
-| | || weight | | | | |
-| | || compre | | | | |
-| | | ssion | | | | |
-| | || parameter)| | | | |
-| | +------------+------------+-----+-----+-----+
-| | || numBund\ | Supported | Y | Y | N |
-| | | Prb | | | | |
-| | || (Number | | | | |
-| | || of | | | | |
-| | || bundled | | | | |
-| | || PRBs per | | | | |
-| | || beam | | | | |
-| | | forming | | | | |
-| | || weights) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || bfwI | Supported | Y | Y | N |
-| | || (beam | | | | |
-| | | forming | | | | |
-| | || weight | | | | |
-| | || in-phase | | | | |
-| | || value) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || bfwQ | Supported | Y | Y | N |
-| | || (beam | | | | |
-| | | forming | | | | |
-| | || weight | | | | |
-| | || quadra | | | | |
-| | | ture | | | | |
-| | || value) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || disable\ | Supported | Y | Y | N |
-| | || BFWs | | | | |
-| | || (disable | | | | |
-| | || beam | | | | |
-| | | forming | | | | |
-| | || weights) | | | | |
-| | +------------+------------+-----+-----+-----+
-| | || RAD | Supported | Y | Y | N |
-| | || (Reset | | | | |
-| | || After PRB | | | | |
-| | || Discon | | | | |
-| | | tinuity) | | | | |
-| | | | | | | |
-+------------+------------+------------+------------+-----+-----+-----+
-|| U-plane || data\ | Supported | Y | Y | Y |
-|| Packet || Direction | | | | |
-|| Format || (data | | | | |
-| || direction | | | | |
-| || (gNB | | | | |
-| || Tx/Rx)) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || payload\ | 001b | Y | Y | Y |
-| || Version | | | | |
-| || (payload | | | | |
-| || version) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || filter\ | Supported | Y | Y | Y |
-| || Index | | | | |
-| || (filter | | | | |
-| || index) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || frameId | Supported | Y | Y | Y |
-| || (frame | | | | |
-| || iden | | | | |
-| | tifier) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || subframeId | Supported | Y | Y | Y |
-| || (subframe | | | | |
-| || iden | | | | |
-| | tifier) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || slotId | Supported | Y | Y | Y |
-| || (slot | | | | |
-| || iden | | | | |
-| | tifier) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || symbolId | Supported | Y | Y | Y |
-| || (symbol | | | | |
-| || iden | | | | |
-| | tifier) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || sectionId | Supported | Y | Y | Y |
-| || (section | | | | |
-| || iden | | | | |
-| | tifier) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || rb | 0 | Y | Y | Y |
-| || (resource | | | | |
-| || block | | | | |
-| || indicator) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || symInc | 0 | Y | Y | Y |
-| || (symbol | | | | |
-| || number | | | | |
-| || increment | | | | |
-| || command) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || startPrbu | Supported | Y | Y | Y |
-| || (startingPRB | | | | |
-| || of user | | | | |
-| || plane | | | | |
-| || section) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || numPrbu | Supported | Y | Y | Y |
-| || (number of | | | | |
-| || PRBs per | | | | |
-| || user plane | | | | |
-| || section) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || udCompHdr | Supported | Y | Y | N |
-| || (user data | | | | |
-| || com | | | | |
-| | pression | | | | |
-| || header) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || reserved | 0 | Y | Y | Y |
-| || (reserved | | | | |
-| || for future | | | | |
-| || use) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || udCompParam | Supported | Y | Y | N |
-| || (user data | | | | |
-| || compre | | | | |
-| | ssion | | | | |
-| || parameter) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || iSample | 16 | Y | Y | Y |
-| || (in-phase | | | | |
-| | sample) | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || qSample | 16 | Y | Y | Y |
-| || ( | | | | |
-| | quadrature | | | | |
-| | sample) | | | | |
-| | | | | | |
-+------------+-------------------------+------------+-----+-----+-----+
-| S-plane || Topology | Supported | N | N | N |
-| || confi | | | | |
-| | guration: | | | | |
-| || C1 | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Topology | Supported | N | N | N |
-| || confi | | | | |
-| | guration: | | | | |
-| || C2 | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Topology | Supported | Y | Y | Y |
-| || confi | | | | |
-| | guration: | | | | |
-| || C3 | | | | |
-| +-------------------------+------------+-----+-----+-----+
-| || Topology | Supported | N | N | N |
-| || confi | | | | |
-| | guration: | | | | |
-| || C4 | | | | |
-| | | | | | |
-+ +------------+------------+------------+-----+-----+-----+
-| | PTP || Full | Supported | Y | Y | N |
-| | || Timing | | | | |
-| | || Support | | | | |
-| | || (G.8275.1)| | | | |
-| | | | | | | |
-+------------+------------+------------+------------+-----+-----+-----+
-| M-plane | | || Not | N | N | N |
-| | | || supported | | | |
-| | | | | | | |
-+------------+------------+------------+------------+-----+-----+-----+
+- **C**: Completed code implementation for O-RAN Library
+
+- **I**: Integrated into Intel FlexRAN PHY
+
+- **T**: Tested end to end with O-RU
+
+Table 8. Levels of Validation
+
++------------+------------+------------+-----------------+-----+-----+-----+
+| Category | Item | Status | C | I | T |
++============+============+============+=================+=====+=====+=====+
+| General || Radio | NR/LTE | N/A | N/A | N/A |
+| || access | | | | |
+| || technology | | | | |
+| || (LTE / NR) | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || Nominal || 15 | Y | Y | N |
+| || sub-carrier || /30/120KHz | | | |
+| || spacing | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| | FFT size || 512/1024 | Y | Y | N |
+| | || /2048/4096 | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || Channel || 5/10 | Y | Y | N |
+| || bandwidth || /20/100Mhz | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || Number of | 12 | Y | Y | N |
+| || Cells | | | | |
+| || (Component | | | | |
+| || Carriers) | | | | |
+| || | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || RU | A, B | Y | Y | N |
+| || category | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| | TDD Config || Supported | Y | Y | N |
+| | || /Flexible | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || FDD | Supported | Y | Y | N |
+| || Support | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || Tx/Rx | Supported | Y | Y | N |
+| || switching | | | | |
+| || based on | | | | |
+| || 'data | | | | |
+| || Direction' | | | | |
+| || field of | | | | |
+| || C-plane | | | | |
+| || message | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || IP version | N/A | N/A | N/A | N/A |
+| || for | | | | |
+| || Management | | | | |
+| || traffic at | | | | |
+| || fronthaul | | | | |
+| || network | | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+| PRACH || One Type 3 | Supported | Y | Y | N |
+| || message | | | | |
+| || for all | | | | |
+| || repeated | | | | |
+| || PRACH | | | | |
+| || preambles | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Type 3 | 1 | Y | Y | N |
+| || message | | | | |
+| || per | | | | |
+| || repeated | | | | |
+| || PRACH | | | | |
+| || preambles | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || timeOffset | Supported | Y | Y | N |
+| || including | | | | |
+| || cpLength | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| | Supported | Supported | Y | Y | N |
+| +-------------------------+-----------------+-----+-----+-----+
+| || PRACH | Supported | Y | Y | N |
+| || preamble | | | | |
+| || format/ | | | | |
+| || index | | | | |
+| || number | | | | |
+| || (number of | | | | |
+| || occasions) | | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+|| Delay || Network | Supported | Y | Y | N |
+|| management|| delay | | | | |
+| || determination | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || lls-CU | Supported | Y | Y | N |
+| || timing | | | | |
+| || advance | | | | |
+| || type | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Non-delay || Not | N | N | N |
+| || managed || supported | | | |
+| || U-plane | | | | |
+| || traffic | | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+|| C/U-plane || Transport | Ethernet | Y | Y | N |
+|| Transport || encapsulation | | | | |
+| || (Ethernet/IP) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Jumbo | Supported | Y | Y | N |
+| || frames | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Transport | eCPRI | Y | Y | N |
+| || header | | | | |
+| || (eCPRI/RoE) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || IP version | N/A | N/A | N/A | N/A |
+| || when | | | | |
+| || Transport | | | | |
+| || header is | | | | |
+| || IP/UDP | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || eCPRI || Not | N | N | N |
+| || Concatenation || supported | | | |
+| || when | | | | |
+| || Transport | | | | |
+| || header is | | | | |
+| || eCPRI | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || eAxC ID | 4 \* | Y | Y | N |
+| || CU_Port_ID | | | | |
+| || bitwidth | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || eAxC ID | 4 \* | Y | Y | N |
+| || BandSector_ID | | | | |
+| || bitwidth | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || eAxC ID | 4 \* | Y | Y | N |
+| || CC_ID | | | | |
+| || bitwidth | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || eAxC ID | 4 \* | Y | Y | N |
+| || RU_Port_ID | | | | |
+| || bitwidth | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| | Fragmentation | Supported | Y | Y | N |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Transport | N/A | N | N | N |
+| || prioritization | | | | |
+| || within | | | | |
+| || U-plane | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Separation | Supported | Y | Y | N |
+| || of | | | | |
+| || C/U-plane | | | | |
+| || and | | | | |
+| || M-plane | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Separation || VLAN ID | Y | Y | N |
+| || of C-plane || | | | |
+| || and || | | | |
+| || U-plane || | | | |
+| | || | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Max Number | 16 | Y | Y | N |
+| || of VLAN | | | | |
+| || per | | | | |
+| || physical | | | | |
+| || port | | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+|| Reception | Rx_on_time | Supported | Y | Y | N |
+|| Window | | | | | |
+|| Monitoring| | | | | |
+|| (Counters)| | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| | Rx_early | Supported | N | N | N |
+| +-------------------------+-----------------+-----+-----+-----+
+| | Rx_late | Supported | N | N | N |
+| +-------------------------+-----------------+-----+-----+-----+
+| | Rx_corrupt | Supported | N | N | N |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Rx_pkt_dupl | Supported | N | N | N |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Total_msgs_rcvd | Supported | Y | N | N |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+|| || RU || Index and | Y | Y | N |
+|| Beam-\ || beamforming || weights | | | |
+|| forming || type || | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Beamforming | C-plane | Y | N | N |
+| || control | | | | |
+| || method | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Number of || No res- | Y | Y | N |
+| || beams || strictions | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+|| IQ || U-plane | Supported | Y | Y | Y |
+|| compre || data | | | | |
+| ssion || compression | | | | |
+| || method | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || U-plane || BFP: | Y | Y | Y |
+| || data IQ || 8,9,12,14 | | | |
+| || bitwidth || bits | | | |
+| || (Before / || | | | |
+| || After || Modulation | | | |
+| || compression) || compression: | | | |
+| || || 1,2,3,4 bits | | | |
+| || || | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Static | Supported | N | N | N |
+| || configuration | | | | |
+| || of U-plane | | | | |
+| || IQ format | | | | |
+| || and | | | | |
+| || compression | | | | |
+| || header | | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+|| eCPRI || ecpriVersion | 001b | Y | Y | Y |
+|| Header || | | | | |
+|| Format || | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || ecpriReserved | Supported | Y | Y | Y |
+| +-------------------------+-----------------+-----+-----+-----+
+| || ecpriCon || Not | N | N | N |
+| | catenation || supported | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || ecpri\ | U-plane | Supported | Y | Y | Y |
+| || Message | | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | | C-plane | Supported | Y | Y | Y |
+| | +------------+-----------------+-----+-----+-----+
+| | || Delay | Supported | Y | Y | Y |
+| | || measure | | | | |
+| | | ment | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || ecpri | Supported | Y | Y | Y |
+| || Payload | | | | |
+| || (payload | | | | |
+| || size in | | | | |
+| || bytes) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || ecpriRtcid | Supported | Y | Y | Y |
+| || /ecpriPcid | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || ecpri | Supported | Y | Y | Y |
+| || Seqid: | | | | |
+| || Sequence | | | | |
+| || ID | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || ecpri\ | Supported | Y | Y | Y |
+| || Seqid: | | | | |
+| || E bit | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || ecpri\ || Not | N | N | N |
+| || Seqid: || supported | | | |
+| || Sub\ | | | | |
+| || sequence | | | | |
+| || ID | | | | |
+| | | | | | |
++------------+------------+------------+-----------------+-----+-----+-----+
+|| C-plane || Section || Not | N | N | N |
+|| Type || Type 0 || supported | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Section | Supported | Y | Y | Y |
+| || Type 1 | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Section | Supported | Y | Y | Y |
+| || Type 3 | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Section || Not | N | N | N |
+| || Type 5 || supported | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Section || Not | N | N | N |
+| || Type 6 || supported | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Section || Not | N | N | N |
+| || Type 7 || supported | | | |
+| | | | | | |
++------------+------------+------------+-----------------+-----+-----+-----+
+|| C-plane || *Coding*\ || data\ | Supported | Y | Y | N |
+|| Packet || *of Infor*|| Direction | | | | |
+|| Format | *mation* || (data | | | | |
+| || *Elements*|| direction | | | | |
+| || *Appli* || (gNB | | | | |
+| | *cation* || Tx/Rx)) | | | | |
+| || *Layer,*\ || | | | | |
+| || *Common* || | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || payload || 001b | Y | Y | N |
+| | | Version || | | | |
+| | || (payload || | | | |
+| | || version) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || filter | Supported | Y | Y | N |
+| | | Index | | | | |
+| | || (filter | | | | |
+| | || index) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || frameId | Supported | Y | Y | N |
+| | || (frame | | | | |
+| | || iden | | | | |
+| | | tifier) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || subframeId| Supported | Y | Y | N |
+| | || (subframe | | | | |
+| | || iden | | | | |
+| | | tifier) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || slotId | Supported | Y | Y | N |
+| | || (slot | | | | |
+| | || iden | | | | |
+| | | tifier) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || start | Supported | Y | Y | N |
+| | || Symbolid | | | | |
+| | || (start | | | | |
+| | || symbol | | | | |
+| | || iden | | | | |
+| | | tifier) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || number || up to the | Y | Y | N |
+| | || Ofsections|| maximum | | | |
+| | || (number of|| number of | | | |
+| | || sections) || PRBs | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || section || 1 and 3 | Y | Y | N |
+| | || Type || | | | |
+| | || (section || | | | |
+| | || type) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || udCompHdr | Supported | Y | Y | N |
+| | || (user data| | | | |
+| | || com | | | | |
+| | | pression | | | | |
+| | || header) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || number || Not | N | N | N |
+| | || OfUEs || supported | | | |
+| | || (number Of| | | | |
+| | || UEs) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || timeOffset| Supported | Y | Y | N |
+| | || (time | | | | |
+| | || offset) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || frame | mu=0,1,3 | Y | Y | N |
+| | || Structure | | | | |
+| | || (frame | | | | |
+| | || structure)| | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || cpLength | Supported | Y | Y | N |
+| | || (cyclic | | | | |
+| | || prefix | | | | |
+| | || length) | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || *Coding* || sectionId | Supported | Y | Y | N |
+| || *of Infor*|| (section | | | | |
+| | *mation* || iden | | | | |
+| || *Elements*| tifier) | | | | |
+| || *Ap* | | | | | |
+| | *plication*| | | | | |
+| || *Layer,* | | | | | |
+| || *Sections*| | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || rb | 0 | Y | Y | N |
+| | || (resource | | | | |
+| | || block | | | | |
+| | || indicator)| | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || symInc | 0 or 1 | Y | Y | N |
+| | || (symbol | | | | |
+| | || number | | | | |
+| | || increment | | | | |
+| | || command) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || startPrbc | Supported | Y | Y | N |
+| | || (starting | | | | |
+| | || PRB of | | | | |
+| | || control | | | | |
+| | || section) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || reMask | Supported | Y | Y | N |
+| | || (resource | | | | |
+| | || element | | | | |
+| | || mask) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || numPrbc | Supported | Y | Y | N |
+| | || (number of| | | | |
+| | || contiguous| | | | |
+| | || PRBs per | | | | |
+| | || control | | | | |
+| | || section) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || numSymbol | Supported | Y | Y | N |
+| | || (number of| | | | |
+| | || symbols) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || ef | Supported | Y | Y | N |
+| | || (extension| | | | |
+| | || flag) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || beamId | Support | Y | Y | N |
+| | || (beam | | | | |
+| | || iden | | | | |
+| | | tifier) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || ueId (UE || Not | N | N | N |
+| | || iden || supported | | | |
+| | | tifier) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || freqOffset| Supported | Y | Y | N |
+| | || (frequency| | | | |
+| | || offset) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || regulari || Not | N | N | N |
+| | | zation || supported | | | |
+| | || Factor || | | | |
+| | || (regulari | | | | |
+| | | zation | | | | |
+| | || Factor) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || ciIsample,|| Not | N | N | N |
+| | || ciQsample || supported | | | |
+| | || (channel || | | | |
+| | || infor | | | | |
+| | | mation | | | | |
+| | || I and Q | | | | |
+| | || values) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || laaMsgType|| Not | N | N | N |
+| | || (LAA || supported | | | |
+| | || message || | | | |
+| | || type) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || laaMsgLen || Not | N | N | N |
+| | || (LAA || supported | | | |
+| | || message | | | | |
+| | || length) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | | lbtHandle || Not | N | N | N |
+| | | || supported | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtDefer || Not | N | N | N |
+| | || Factor || supported | | | |
+| | || (listen || | | | |
+| | || before || | | | |
+| | || talk || | | | |
+| | || defer || | | | |
+| | || factor) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtBack || Not | N | N | N |
+| | || offCounter|| supported | | | |
+| | || (listen || | | | |
+| | || before || | | | |
+| | || talk || | | | |
+| | || backoff || | | | |
+| | || counter) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtOffset || Not | N | N | N |
+| | || (listen- || supported | | | |
+| | || before | | | | |
+| | || talk || | | | |
+| | || offset) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || MCOT || Not | N | N | N |
+| | || (maximum || supported | | | |
+| | || channel | | | | |
+| | || occupancy | | | | |
+| | || time) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtMode || Not | N | N | N |
+| | || (LBT Mode)|| supported | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbt || Not | N | N | N |
+| | | PdschRes || supported | | | |
+| | || (LBT PDSCH|| | | | |
+| | || Result) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || sfStatus || Not | N | N | N |
+| | || (subframe || supported | | | |
+| | || status) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtDrsRes || Not | N | N | N |
+| | || (LBT DRS || supported | | | |
+| | || Result) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || initial || Not | N | N | N |
+| | | PartialSF || supported | | | |
+| | || (Initial | | | | |
+| | | partial | | | | |
+| | | SF) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtBufErr || Not | N | N | N |
+| | || (LBT || supported | | | |
+| | | Buffer | | | | |
+| | || Error) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || sfnSf || Not | N | N | N |
+| | || (SFN/SF || supported | | | |
+| | | End) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbt || Not | N | N | N |
+| | || CWConfig_H|| supported | | | |
+| | || (HARQ | | | | |
+| | || Parameters| | | | |
+| | || for | | | | |
+| | || Congestion| | | | |
+| | || Window | | | | |
+| | || mana | | | | |
+| | | gement) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbt || Not | N | N | N |
+| | || CWConfig_T|| supported | | | |
+| | || (TB | | | | |
+| | | Parameters | | | | |
+| | || for | | | | |
+| | || Congestion| | | | |
+| | || Window | | | | |
+| | || mana | | | | |
+| | | gement) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtTr || Not | N | N | N |
+| | | afficClass || supported | | | |
+| | || (Traffic | | | | |
+| | || class | | | | |
+| | || priority | | | | |
+| | || for | | | | |
+| | || Congestion| | | | |
+| | || Window | | | | |
+| | || mana | | | | |
+| | | gement) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || lbtCWR_Rst|| Not | N | N | N |
+| | || (Noti || supported | | | |
+| | | cation | | | | |
+| | || about | | | | |
+| | || packet | | | | |
+| | || reception | | | | |
+| | || successful| | | | |
+| | || or not) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || reserved | 0 | N | N | N |
+| | || (reserved | | | | |
+| | || for future| | | | |
+| | || use) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || *Section* | | | | |
+| | || *Exten* | | | | |
+| | | *sion* | | | | |
+| | || *Commands*| | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || extType | Supported | Y | Y | N |
+| | || (extension| | | | |
+| | || type) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || ef | Supported | Y | Y | N |
+| | | (extension | | | | |
+| | || flag) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || extLen | Supported | Y | Y | N |
+| | || (extension| | | | |
+| | || length) | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || Coding of | | | | | |
+| || Infor | | | | | |
+| | mation | | | | | |
+| || Elements –| | | | | |
+| || Appli | | | | | |
+| | cation | | | | | |
+| || Layer, | | | | | |
+| || Section | | | | | |
+| || Exten | | | | | |
+| | sions | | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || | | | | | |
+| || *Ext*\ || bfw | Supported | Y | Y | N |
+| || *Type=1:* || CompHdr | | | | |
+| || *Beam* || (beam | | | | |
+| || *forming* | forming | | | | |
+| || *Weights* || weight | | | | |
+| || *Exten\* || compre | | | | |
+| | *sion* | ssion | | | | |
+| || *Type* || header) | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || | | | | |
+| || || bf | Supported | Y | Y | N |
+| || | wCompParam | | | | |
+| || || (beam | | | | |
+| || || forming | | | | |
+| || || weight | | | | |
+| || || compre | | | | |
+| || | ssion | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfwl | Supported | Y | Y | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || weight | | | | |
+| || || in-phase | | | | |
+| || || value) | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfwQ | Supported | Y | Y | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || weight | | | | |
+| || || quadrature| | | | |
+| || || value) | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || || bfaCompHdr| Supported | Y | N | N |
+| || *ExtType*\|| | | | | |
+| || *=2:* || (beam\ | | | | |
+| || *Beam* | forming | | | | |
+| | *forming* || attributes| | | | |
+| || *Attribu* || compre | | | | |
+| | *tes* | ssion | | | | |
+| || *Exten* || header) | | | | |
+| || *sion* | | | | | |
+| || *Type* | | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfAzPt | Supported | Y | N | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || azimuth | | | | |
+| || || pointing | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfZePt | Supported | Y | N | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || zenith | | | | |
+| || || pointing | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfAz3dd | Supported | Y | N | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || azimuth | | | | |
+| || || beamwidth | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfZe3dd | Supported | Y | N | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || zenith | | | | |
+| || || beamwidth | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfAzSl | Supported | Y | N | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || azimuth | | | | |
+| || || sidelobe | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || bfZeSl | Supported | Y | N | N |
+| || || (beam | | | | |
+| || | forming | | | | |
+| || || zenith | | | | |
+| || || sidelobe | | | | |
+| || || parameter)| | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || zero- | Supported | Y | N | N |
+| || | padding | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || || code\ | Supported | Y | N | N |
+| || *ExtType* || bookIndex | | | | |
+| || *=3:* || | | | | |
+| || *DL* || (precoder | | | | |
+| || *Preco* || codebook | | | | |
+| | *ding* || | | | | |
+| || *Exten* || used for | | | | |
+| | *sion* || trans | | | | |
+| || *Type* | mission | | | | |
+| | | | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || layerID | Supported | Y | N | N |
+| || || (Layer ID | | | | |
+| || || for DL | | | | |
+| || || trans | | | | |
+| || | mission) | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || txScheme | Supported | Y | N | N |
+| || || (trans | | | | |
+| || | mission | | | | |
+| || || scheme) | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || numLayers | Supported | Y | N | N |
+| || || (number of| | | | |
+| || || layers | | | | |
+| || || used for | | | | |
+| || || DL | | | | |
+| || || trans | | | | |
+| || | mission) | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| || || crsReMask | Supported | Y | N | N |
+| || || (CRS | | | | |
+| || || resource | | | | |
+| || || element | | | | |
+| || || mask) | | | | |
+| || +------------+-----------------+-----+-----+-----+
+| | || crs\ | Supported | Y | N | N |
+| | || SyumINum | | | | |
+| | || (CRS | | | | |
+| | || symbol | | | | |
+| | || number | | | | |
+| | || indi | | | | |
+| | | cation) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || crsShift | Supported | Y | N | N |
+| | || (crsShift | | | | |
+| | || used for | | | | |
+| | || DL | | | | |
+| | || trans | | | | |
+| | | mission) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || beamIdAP1 | Supported | Y | N | N |
+| | || (beam id | | | | |
+| | || to be used| | | | |
+| | || for | | | | |
+| | || antenna | | | | |
+| | || port 1) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || beamIdAP2 | Supported | Y | N | N |
+| | || (beam id | | | | |
+| | || to be used| | | | |
+| | || for | | | | |
+| | || antenna | | | | |
+| | || port 2) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || beamIdAP3 | Supported | Y | N | N |
+| | || (beam id | | | | |
+| | || to be used| | | | |
+| | || for | | | | |
+| | || antenna | | | | |
+| | || port 3) | | | | |
+| | | | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| | || csf || Supported | Y | Y | N |
+| || *ExtType*\|| (cons || | | | |
+| || *=4:* | tellation || | | | |
+| || *Modula* || shift | | | | |
+| | *tion* || flag) | | | | |
+| || *Compre* || | | | | |
+| | *ssion* || | | | | |
+| || *Parame* || | | | | |
+| | *ters* || | | | | |
+| || *Exten* || | | | | |
+| | *sion* | | | | | |
+| || *Type* || | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || mod || Supported | Y | Y | N |
+| | || CompScaler|| | | | |
+| | || ( || | | | |
+| | || modulation|| | | | |
+| | || compre || | | | |
+| | | ssion || | | | |
+| | || scaler || | | | |
+| | | value) || | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || || mcScale\ || Supported | Y | N | N |
+| || *ExtType*\|| ReMask || | | | |
+| || *=5:* || ( || | | | |
+| || *Modula* || modulation|| | | | |
+| | *tion* || compre || | | | |
+| || *Compre* | ssion || | | | |
+| | *ssion* || power || | | | |
+| || *Additio* || RE || | | | |
+| || *Parame* || mask) || | | | |
+| || *ters* | || | | | |
+| || *Exten* || | | | | |
+| | *sion* || | | | | |
+| || Type* | || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || csf || Supported | Y | N | N |
+| | || (cons || | | | |
+| | | tellation || | | | |
+| | || shift || | | | |
+| | || flag) || | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || mcScale\ | Supported | Y | N | N |
+| | || Offset | | | | |
+| | || (scaling | | | | |
+| | || value for | | | | |
+| | || modulation| | | | |
+| | || compre | | | | |
+| | | ssion) | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || *E* || rbgSize | Supported | Y | N | N |
+| | *xtType=6:*|| (resource | | | | |
+| || *Non-con* || block | | | | |
+| | *tiguous* || group | | | | |
+| || *PRB* || size) | | | | |
+| || *alloca* | | | | | |
+| | *tion in* | | | | | |
+| || *time and*| | | | | |
+| || *frequen* | | | | | |
+| | *cy domain*| | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || rbgMask | Supported | Y | N | N |
+| | || (resource | | | | |
+| | || block | | | | |
+| | || group bit | | | | |
+| | || mask) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || symbol\ | Supported | Y | N | N |
+| | || Mask | | | | |
+| | || (symbol | | | | |
+| | || bit mask) | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || *Ext* || beam | Supported | Y | N | N |
+| | *Type=10:* || GroupType | | | | |
+| || *Section* | | | | | |
+| || *des\* | | | | | |
+| | *cription* | | | | | |
+| || *for gro\*| | | | | |
+| | *up* | | | | | |
+| || *configu\*| | | | | |
+| | *ration of*| | | | | |
+| || *multiple*| | | | | |
+| || *ports* | | | | | |
+| | | | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | | numPortc | Supported | Y | N | N |
+| | | | | | | |
+| +------------+------------+-----------------+-----+-----+-----+
+| || *Ext* || b | Supported | Y | Y | N |
+| | *Type=11:* | fwCompHdr | | | | |
+| || *Flexible*|| (beam | | | | |
+| || *Beam* | forming | | | | |
+| | *forming* || weight | | | | |
+| || *Weights* || compre | | | | |
+| || *Exten* | ssion | | | | |
+| | *sion* | | | | | |
+| || *Type* || header) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || bfw | Supported | Y | Y | N |
+| | || CompParam | | | | |
+| | || for PRB | | | | |
+| | || bundle x | | | | |
+| | || (beam | | | | |
+| | | forming | | | | |
+| | || weight | | | | |
+| | || compre | | | | |
+| | | ssion | | | | |
+| | || parameter)| | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || numBund\ | Supported | Y | Y | N |
+| | | Prb | | | | |
+| | || (Number | | | | |
+| | || of | | | | |
+| | || bundled | | | | |
+| | || PRBs per | | | | |
+| | || beam | | | | |
+| | | forming | | | | |
+| | || weights) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || bfwI | Supported | Y | Y | N |
+| | || (beam | | | | |
+| | | forming | | | | |
+| | || weight | | | | |
+| | || in-phase | | | | |
+| | || value) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || bfwQ | Supported | Y | Y | N |
+| | || (beam | | | | |
+| | | forming | | | | |
+| | || weight | | | | |
+| | || quadra | | | | |
+| | | ture | | | | |
+| | || value) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || disable\ | Supported | Y | Y | N |
+| | || BFWs | | | | |
+| | || (disable | | | | |
+| | || beam | | | | |
+| | | forming | | | | |
+| | || weights) | | | | |
+| | +------------+-----------------+-----+-----+-----+
+| | || RAD | Supported | Y | Y | N |
+| | || (Reset | | | | |
+| | || After PRB | | | | |
+| | || Discon | | | | |
+| | | tinuity) | | | | |
+| | | | | | | |
++------------+------------+------------+-----------------+-----+-----+-----+
+|| U-plane || data\ | Supported | Y | Y | Y |
+|| Packet || Direction | | | | |
+|| Format || (data | | | | |
+| || direction | | | | |
+| || (gNB | | | | |
+| || Tx/Rx)) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || payload\ | 001b | Y | Y | Y |
+| || Version | | | | |
+| || (payload | | | | |
+| || version) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || filter\ | Supported | Y | Y | Y |
+| || Index | | | | |
+| || (filter | | | | |
+| || index) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || frameId | Supported | Y | Y | Y |
+| || (frame | | | | |
+| || iden | | | | |
+| | tifier) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || subframeId | Supported | Y | Y | Y |
+| || (subframe | | | | |
+| || iden | | | | |
+| | tifier) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || slotId | Supported | Y | Y | Y |
+| || (slot | | | | |
+| || iden | | | | |
+| | tifier) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || symbolId | Supported | Y | Y | Y |
+| || (symbol | | | | |
+| || iden | | | | |
+| | tifier) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || sectionId | Supported | Y | Y | Y |
+| || (section | | | | |
+| || iden | | | | |
+| | tifier) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || rb | 0 | Y | Y | Y |
+| || (resource | | | | |
+| || block | | | | |
+| || indicator) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || symInc | 0 | Y | Y | Y |
+| || (symbol | | | | |
+| || number | | | | |
+| || increment | | | | |
+| || command) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || startPrbu | Supported | Y | Y | Y |
+| || (startingPRB | | | | |
+| || of user | | | | |
+| || plane | | | | |
+| || section) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || numPrbu | Supported | Y | Y | Y |
+| || (number of | | | | |
+| || PRBs per | | | | |
+| || user plane | | | | |
+| || section) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || udCompHdr | Supported | Y | Y | N |
+| || (user data | | | | |
+| || com | | | | |
+| | pression | | | | |
+| || header) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || reserved | 0 | Y | Y | Y |
+| || (reserved | | | | |
+| || for future | | | | |
+| || use) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || udCompParam | Supported | Y | Y | N |
+| || (user data | | | | |
+| || compre | | | | |
+| | ssion | | | | |
+| || parameter) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || iSample | 16 | Y | Y | Y |
+| || (in-phase | | | | |
+| | sample) | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || qSample | 16 | Y | Y | Y |
+| || ( | | | | |
+| | quadrature | | | | |
+| | sample) | | | | |
+| | | | | | |
++------------+-------------------------+-----------------+-----+-----+-----+
+| S-plane || Topology | Supported | N | N | N |
+| || confi | | | | |
+| | guration: | | | | |
+| || C1 | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Topology | Supported | N | N | N |
+| || confi | | | | |
+| | guration: | | | | |
+| || C2 | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Topology | Supported | Y | Y | Y |
+| || confi | | | | |
+| | guration: | | | | |
+| || C3 | | | | |
+| +-------------------------+-----------------+-----+-----+-----+
+| || Topology | Supported | N | N | N |
+| || confi | | | | |
+| | guration: | | | | |
+| || C4 | | | | |
+| | | | | | |
++ +------------+------------+-----------------+-----+-----+-----+
+| | PTP || Full | Supported | Y | Y | N |
+| | || Timing | | | | |
+| | || Support | | | | |
+| | || (G.8275.1)| | | | |
+| | | | | | | |
++------------+------------+------------+-----------------+-----+-----+-----+
+| M-plane | | || Not | N | N | N |
+| | | || supported | | | |
+| | | | | | | |
++------------+------------+------------+-----------------+-----+-----+-----+
+
\* The bit width of each component in eAxC ID can be configurable.
functionality.
VLAN tag functionality is offloaded to NIC as per the configuration of
-VF (refer to Setup Configuration).
+VF (refer to *Appendix A, Setup Configuration*).
-The transport header is defined in the ORAN Fronthaul specification
-based on the eCPRI specification.
+The transport header is defined in the O-RAN Fronthaul specification
+based on the eCPRI specification, Refer to *Table 2*.
.. image:: images/eCPRI-Header-Field-Definitions.jpg
:width: 600
Figure 12. eCPRI Header Field Definitions
-Only ECPRI_IQ_DATA = 0x00 and ECPRI_RT_CONTROL_DATA= 0x02 message types
-are supported.
+Only ECPRI_IQ_DATA = 0x00 , ECPRI_RT_CONTROL_DATA= 0x02 and
+ECPRI_DELAY_MEASUREMENT message types are supported.
For one-way delay measurements the eCPRI Header Field Definitions are
the same as above until the ecpriPayload. The one-delay measurement
Figure 14. Bit Allocations of ecpriRtcid/ecpriPcid
For ecpriSeqid only, the support for a sequence number is implemented.
-The subsequent number is not supported.
+The following number is not supported.
+
+Comments in the source code can be used to see more information on the
+implementation specifics of handling this field.
U-plane
-------
O-RAN packet meant for traffic with compression enabled has the
Compression Header added after each Application Header. According to
-O-RAN Fronthaul's specification, the Compression Header is part of a
-repeated Section Application Header. In the O-RAN library implementation,
-the header is implemented as a separate structure, following the
+*O-RAN Fronthaul's specification* (Refer to *Table 2*), the Compression
+Header is part of a repeated Section Application Header. In the O-RAN library
+implementation,the header is implemented as a separate structure, following the
Application Section Header. As a result, the Compression Header is not
included in the O-RAN packet, if compression is not used.
Figure 15 shows the components of an ORAN packet.
-.. image:: images/xRAN-Packet-Components.jpg
+.. image:: images/O-RAN-Packet-Components.jpg
:width: 600
:alt: Figure 15. O-RAN Packet Components
The Common Radio Application Header is followed by the Application
Header that is repeated for each Data Section within the eCPRI message.
-The relevant section of O-RAN packet is shown in color.
+The relevant section of the O-RAN packet is shown in color.
.. image:: images/Data-Section-Application-Data-Header.jpg
:width: 600
A single section is used per one Ethernet packet with IQ samples
-startPrbu is equal to 0 and numPrbu is wqual to the number of RBs used:
+startPrbu is equal to 0 and numPrbu is equal to the number of RBs used:
- rb field is not used (value 0).
Data Payload
~~~~~~~~~~~~
-An O-RAN packet data payload contains a number of PRBs. Each PRB is built
-of 12 IQ samples. Flexible IQ bit width is supported. If compression is enabled udCompParam is included in the data payload. The data section is shown in colour.
+An O-RAN packet data payload contains several PRBs. Each PRB is built of
+12 IQ samples. Flexible IQ bit width is supported. If compression is
+enabled, udCompParam is included in the data payload. The data section
+is shown in color.
.. image:: images/Data-Payload.jpg
:width: 600
- :alt: Figure 17. Data Payload
+ :alt: Figure 18. Data Payload
-Figure 17. Data Payload
+Figure 18. Data Payload
C-plane
-------
C-Plane messages are encapsulated using a two-layered header approach.
The first layer consists of an eCPRI standard header, including
corresponding fields used to indicate the message type, while the second
-layer is an application layer including necessary fields for control and
-synchronization. Within the application layer, a “section” defines the characteristics of U-plane data to be transferred or received from a
-beam with one pattern id. In general, the transport header,application
+layer is an application layer, including necessary fields for control
+and synchronization. Within the application layer, a “section” defines
+the characteristics of U-plane data to be transferred or received from a
+beam with one pattern id. In general, the transport header, application
header, and sections are all intended to be aligned on 4-byte boundaries
and are transmitted in “network byte order” meaning the most significant
byte of a multi-byte parameter is transmitted first.
Section extensions are not supported in this release.
-The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h
+The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h,
and the fields are appropriately re-ordered in order to apply the
conversion of network byte order after setting values.
-The comments in source code of O-RAN lib can be used to see more information on
-implementation specifics of handling sections as well as particular fields.
-Additional changes may be needed on C-plane to perform IOT with O-RU depending on the scenario.
+The comments in the source code of O-RAN lib can be used to see more
+information on the implementation specifics of handling sections as well as
+particular fields. Additional changes may be needed on the C-plane to perform
+IOT with an O-RU depending on the scenario.
Ethernet Header
~~~~~~~~~~~~~~~
-Refer to Figure 11.
+Refer to *Figure 11*.
eCPRI Header
~~~~~~~~~~~~
-Refer to Figure 12.
+Refer to *Figure 12*.
This header is defined as the structure of xran_ecpri_hdr in
lib/api/xran_pkt.h.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The Radio Application Common Header is used for time reference. Its
-structure is shown in Figure 18.
+structure is shown in *Figure 19*.
.. image:: images/Radio-Application-Common-Header.jpg
:width: 600
This header is defined as the structure of
xran_cp_radioapp_common_header in lib/api/xran_pkt_cp.h.
-Please note that the payload version in this header is fixed to
-XRAN_PAYLOAD_VER (defined as 1) in this release.
+Note: The payload version in this header is fixed to XRAN_PAYLOAD_VER
+(defined as 1) in this release.
Section Type 0 Structure
~~~~~~~~~~~~~~~~~~~~~~~~
| xran_cp_radioapp_section1 |
+----------------------------------+
+Note: Even though the API function can support composing multiple sections in
+a C-Plane message, the current implementation is limited to composins a single
+section per C-Plane message.
+
Section Type 3 Structure
~~~~~~~~~~~~~~~~~~~~~~~~
.. image:: images/Section-Type-5-Structure.jpg
:width: 600
- :alt: Figure 23. Section Type 5 Structure
+ :alt: Figure 23. Section Type 5 Structure
-Figure 23. Section Type 5 Structure
+Figure 23. Section Type 5 Structure
Section Type 6 Structure
:local:
This section describes how to install and build the required components needed to build the FHI Library, WLS Library and the 5G FAPI TM modules.
+For the f release the ICC compiler is optional and support will be discontinued in future releases
+
+Download and Install oneAPI
+---------------------------
+Download and install the Intel® oneAPI Base Toolkit by issuing the following commands from yor Linux
+Console:
+
+wget https://registrationcenter-download.intel.com/akdlm/irc_nas/18673/l_BaseKit_p_2022.2.0.262_offline.sh
+
+sudo sh ./l_BaseKit_p_2022.2.0.262_offline.sh
+
+Then follow the instructions on the installer.
+Additional information available from
+
+https://www.intel.com/content/www/us/en/developer/tools/oneapi/base-toolkit-download.html?operatingsystem=linux&distributions=webdownload&options=offline
Install ICC and System Studio
-----------------------------
#cd /opt && mkdir intel && cp $BUILD_DIR/license.lic intel/license.lic
#tar -zxvf $BUILD_DIR/system_studio_2019_update_3_composer_edition_offline.tar.gz
-Edit system_studio_2029_update_3_composer_edition_offline/silent.cfg to accept the EULA file as below example::
+Edit system_studio_2019_update_3_composer_edition_offline/silent.cfg to accept the EULA file as below example::
ACCEPT_EULA=accept
PSET_INSTALL_DIR=opt/intel
#./install.sh -s silent.cfg
-Set env for ICC::
- Check for your installation path. The folloing is an example
+Set env for oneAPI or ICC:
+ Check for your installation path. The following is an example for ICC.
+
#source /opt/intel_2019/system_studio_2019/compiler_and_libraries_2019.3.206/linux/bin/iccvars.sh intel64
#export PATH=/opt/intel_2019/system_studio_2019/compiler_and_libraries_2019.3.206/linux/bin/:$PATH
-----------------------
- download DPDK::
- #wget http://static.dpdk.org/rel/dpdk-20.11.1.tar.x
- #tar -xf dpdk-20.11.1.tar.xz
+ #wget http://static.dpdk.org/rel/dpdk-20.11.3.tar.x
+ #tar -xf dpdk-20.11.3.tar.xz
#export RTE_TARGET=x86_64-native-linuxapp-icc
- #export RTE_SDK=Intallation_DIR/dpdk-20.11.1
+ #export RTE_SDK=Intallation_DIR/dpdk-20.11.3
- patch DPDK for O-RAN FHI lib, this patch is specific for O-RAN FHI to reduce the data transmission latency of Intel NIC. This may not be needed for some NICs, please refer to |br| O-RAN FHI Lib Introduction -> setup configuration -> A.2 prerequisites
- build DPDK
- This release uses DPDK version 20.11.1 plus patches so the build procedure for the DPDK is the following
-
- export RTE_TARGET=x86_64-native-linuxapp-icc
- export WIRELESS_SDK_TARGET_ISA=avx512
- export WIRELESS_SDK_TOOLCHAIN=icc
- export SDK_BUILD=build-${WIRELESS_DSK_TARGET_ISA}-icc
+ This release uses DPDK version 20.11.3 so the build procedure for the DPDK is the following
+
+ Setup compiler environment
- Then locate the shell script file compilervars.sh that goes into the system studio 2019 installation folder and invoke following the example below:
- source /opt/intel_2019/system_studio_2019/compilers_and_libraries_2019/linux/bin/compilervars.sh -arch intel64 -platform linux
+ if [ $oneapi -eq 1 ]; then
+ export RTE_TARGET=x86_64-native-linuxapp-icx
+ export WIRELESS_SDK_TOOLCHAIN=icx
+ export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
+ source /opt/intel/oneapi/setvars.sh
+ export PATH=$PATH:/opt/intel/oneapi/compiler/2022.0.1/linux/bin-llvm/
+ echo "Changing the toolchain to GCC 8.3.1 20190311 (Red Hat 8.3.1-3)"
+ source /opt/rh/devtoolset-8/enable
+
+ else
+ export RTE_TARGET=x86_64-native-linuxapp-icc
+ export WIRELESS_SDK_TOOLCHAIN=icc
+ export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
+ source /opt/intel/system_studio_2019/bin/iccvars.sh intel64 -platform linux
+
+ fi
+
The build procedure uses meson and ninja so if not present in your system please install before the next step
- set DPDK path
DPDK path is needed during build and run lib/app::
- #export RTE_SDK=Installation_DIR/dpdk-20.11.1
- #export DESTDIR=Installation_DIR/dpdk-20.11.1
+ #export RTE_SDK=Installation_DIR/dpdk-20.11.3
+ #export DESTDIR=Installation_DIR/dpdk-20.11.3
Install google test
Configure FEC card
--------------------
-For the E Maintenance Release either a SW FEC, or an FPGA FEC (Vista Creek N3000) or an ASIC FEC (Mount Bryce ACC100) can be used.
+For the F Release either a SW FEC, or an FPGA FEC (Vista Creek N3000) or an ASIC FEC (Mount Bryce ACC100) can be used.
The procedure to configure the HW based FECs is explained below.
Customize a setup environment shell script
customize this script to provide the paths to the tools and libraries that
are used building and running the code.
You can add for example the following entries based on your particular installation and the
-following illustration is just an example::
+following illustration is just an example (use icx for oneApi instead of icc)::
- export DIR_ROOT=/home/
- #set the L1 binary root DIR
- #set the phy root DIR
- export DIR_ROOT_PHY=$DIR_ROOT/phy
- #set the DPDK root DIR
-- #export DIR_ROOT_DPDK=/home/dpdk-20.11.1
+- #export DIR_ROOT_DPDK=/home/dpdk-20.11.3
- #set the GTEST root DIR
- #export DIR_ROOT_GTEST=/home/gtest/gtest-1.7.0
- export DIR_WIRELESS_TEST_5G=$DIR_ROOT_L1_BIN/testcase
'http://127.0.0.1.*',
'https://gerrit.o-ran-sc.org.*'
]
+language = 'en'
Intel® Ethernet 800 Series firmware/NVM versions. Support for eCPRI DDP
profile included starting from Columbiaville (CVL)release 2.4 or later.
This section is for general information purposes as the binaries provided
-for this FlexRan release in github.com are built with DPDK 20.11.1 and the
+for this FlexRan release in github.com are built with DPDK 20.11.3 and the
mix and match of binaries is not supported.
The required DPDK version contains the support of loading the specific
Wireless Edge DDP package.
- DPDK version— 21.02 (or later)
-- For FlexRAN oran_e_maintenance_release_v1.0, corresponding support of CVL 2.4 driver pack and DPDK 21.02 is “experimental” and subject to additional
- testing and potential changes.
+- For FlexRAN release oran_f_release_v1.0, corresponding support
+ of CVL 2.4 driver pack and DPDK 21.02 is “experimental” and subject
+ to additional testing and potential changes.
DDP Package Setup
=================
82:00.3 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01)
Use the **lspci** command to obtain the selected device serial
-number:::
+number::
# lspci -vv -s 06:00.0 \| grep -i Serial
Capabilities: [150 v1] Device Serial Number 35-11-a0-ff-ff-ca-05-68
-Or, fully parsed without punctuation:::
+Or, fully parsed without punctuation::
# lspci -vv -s 06:00.0 \|grep Serial \|awk '{print $7}'|sed s/-//g
3511a0ffffca0568
==================
Example of output of successful load of Wireless Edge Package to all
-devices:::
+devices::
# dmesg | grep -i "ddp \| safe"
[606960.921404] ice 0000:18:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101
[606965.017082] ice 0000:51:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
[606965.802115] ice 0000:51:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
[606966.576517] ice 0000:51:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
-
+ [606960.921404] ice 0000:18:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101
+ [606961.672999] ice 0000:18:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
+ [606962.439067] ice 0000:18:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
+ [606963.198305] ice 0000:18:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
+ [606964.252076] ice 0000:51:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101
+ [606965.017082] ice 0000:51:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
+ [606965.802115] ice 0000:51:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
+ [606966.576517] ice 0000:51:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101
If using only DPDK driver:
==========================
Verify using DPDK's **testpmd** application to indicate the status
-And version of the loaded DDP package.
+and version of the loaded DDP package.
Example of eCPRI config with dpdk-testpmd
-----------------------------------------
and requires that DPDK
be installed in the system since in the makefile it uses the RTE_SDK environment variable when
building the library. |br|
-The current release was tested using DPDK version 20.11 but it doesn't preclude the
+The current release was tested using DPDK version 20.11.3 but it doesn't preclude the
use of newer releases. |br|
Also the 5G FAPI TM currently uses the Intel Compiler that is defined as part of the ODULOW documentation.
ORAN 5G FAPI TM Release Notes
=============================
+Version FAPI TM oran_f_release_v1.0, June 2022
+----------------------------------------------
+
+* Support of oneAPI compiler
+
+* Support for additional features not properly defined in the SCF 5G FAPI 2.0 specs has been added by
+ means of vendor specific fields. (FlexRAN 22.11 compatible).
+
Version FAPI TM oran_e_maintenance_release_v1.0, Mar 2022
---------------------------------------------------------
O-RAN O-DU Low
==============
-**User Guide, March 2022**
+**User Guide, June 2022**
.. toctree::
:maxdepth: 2
* :ref:`search`
-Test Cases for the E Maintenance Release
-========================================
+Test Cases for the F Release
+============================
.. toctree::
:maxdepth: 2
Front Haul Interface Library Release Notes
==========================================
+
+Version FH oran_f_release_v1.0, June 2022
+-----------------------------------------
+
+* Update to DPDK 20.11.3
+* oneAPI compiler support
+* core optimizations for massive mimo scenarios
+
Version FH oran_e_maintenance_release_v1.0, March 2022
------------------------------------------------------
O-DU Low Project Release Notes
==========================================
+O-DU Low oran_f_release_v1.0. June 2022
+---------------------------------------
+
+* Enhanced features and optimizations in support of MMIMO and URLC.
+* Enhanced test coverage prior to the comunity release.
+* Incorporation of Bug Fixes for E2E connectivity from Commercial product.
+* Additional information at the component level release notes.
+* Support for oneAPI compiler.
+
O-DU Low oran_e_maintenance_release_v1.0, Mar 2022
--------------------------------------------------
:depth: 3
:local:
-This section describes the downlink, uplink and full duplex bit exact test cases that are present as part of the E Maintenance Release |br|
+This section describes the downlink, uplink and full duplex bit exact test cases that are present as part of the F Release |br|
release. All the test config files, IQ samples and reference Inputs are placed under the FlexRAN/testcase folder. These test config files are used for testmac.
-There are 3 kinds of tests: dl, ul, and fd. The following test cases are part of the E Maintenance Release and reside in the github repo mentioned earlier in this document.
+There are 3 kinds of tests: dl, ul, and fd. The following test cases are part of the F Release and reside in the github repo mentioned earlier in this document.
The following DL, UL and PRACH test cases are used for validation.
The wls library uses DPDK as the basis for the shared memory operations and requires that DPDK
be installed in the system since in the makefile it uses the RTE_SDK environment variable when
building the library. |br|
-The current release was tested using DPDK version 20.11.1 but it doesn't preclude the
-use of newer releases. Since the L1 binaries are built with DPDK 20.11.1 the ODULOW as a whole
+The current release was tested using DPDK version 20.11.3 but it doesn't preclude the
+use of newer releases. Since the L1 binaries are built with DPDK 20.11.3 the ODULOW as a whole
does has the limitation to use only this version of DPDK.
Also the library uses the Intel Compiler that is defined as part of the ODULOW documentation.
WLS Library Release Notes
=========================
+Version WLS oran_f_release_v1.0, June 2022
+------------------------------------------
+
+* Support for oneAPI compiler
+* Added flag in WLS_Put for LTE support
+
Version WLS oran_e_maintenance_release_v1.0, Mar 2022
-----------------------------------------------------
The O-RAN Library consists of multiple modules where different
functionality is encapsulated. The complete list of all \*.c and \*.h
-files as well as Makefile for O-RAN (aka FHI Lib) release is:
+files, as well as Makefile for O-RAN (aka FHI Lib)f release is:
├── app
│ ├── Makefile
+│ ├── ifft_in.txt
+
+│ ├── run_o_du.sh
+
+│ ├── run_o_ru.sh
+
│ ├── src
+│ │ ├── app_bbu_main.c
+
+│ │ ├── app_bbu_pool.c
+
+│ │ ├── app_bbu_pool.h
+
+│ │ ├── app_dl_bbu_pool_tasks.c
+
│ │ ├── app_io_fh_xran.c
│ │ ├── app_io_fh_xran.h
│ │ ├── app_profile_xran.h
+│ │ ├── app_ul_bbu_pool_tasks.c
+
+│ │ ├── aux_line.c
+
+│ │ ├── aux_line.h
+
│ │ ├── common.c
│ │ ├── common.h
│ │ ├── debug.h
+│ │ ├── ebbu_pool_cfg.c
+
+│ │ ├── ebbu_pool_cfg.h
+
│ │ ├── sample-app.c
│ │ └── xran_mlog_task_id.h
│ ├── cat_b
+│ ├── dss
+
│ ├── lte_a
│ ├── lte_b
│ │ ├── xran_cp_api.h
+│ │ ├── xran_ecpri_owd_measurements.h
+
│ │ ├── xran_fh_o_du.h
+│ │ ├── xran_fh_o_ru.h
+
│ │ ├── xran_lib_mlog_tasks_id.h
│ │ ├── xran_mlog_lnx.h
│ └── src
-│ ├── xran_app_frag.c
-
-│ ├── xran_app_frag.h
-
│ ├── xran_bfp_byte_packing_utils.hpp
│ ├── xran_bfp_cplane8.cpp
│ ├── xran_bfp_cplane16.cpp
- ├── xran_bfp_cplane16_snc.cpp
+│ ├── xran_bfp_cplane16_snc.cpp
│ ├── xran_bfp_cplane32.cpp
│ ├── xran_bfp_cplane64_snc.cpp
-│ ├── xran_bfp_cplane8.cpp
-
│ ├── xran_bfp_ref.cpp
│ ├── xran_bfp_uplane.cpp
│ ├── xran_dev.h
-│ ├── xran_ecpri_owd_measurements.h
-
│ ├── xran_frame_struct.c
│ ├── xran_frame_struct.h
│ └── xran_up_api.c
-├── Licenses.txt
-
-├── readme.md
-
└── test
├── common
└── test_xran
+ ├── c_plane_tests.cc
+
├── chain_tests.cc
├── compander_functional.cc
├── conf.json
-
- ├── c_plane_tests.cc
-
+
├── init_sys_functional.cc
├── Makefile
+ ├── mod_compression_unit_test.cc
+
├── prach_functional.cc
├── prach_performance.cc
├── unittests.cc
└── u_plane_functional.cc
+
+ ├── u_plane_performance.cc
General Introduction
--------------------
-The O-RAN Library functionality is broken down into two main sections:
+The O-RAN FHI Library functionality is broken down into two main sections:
- O-RAN specific packet handling (src)
-- Ethernet and supporting functionality (Ethernet)
+- Ethernet and supporting functionality (ethernet)
-External functions and structures are available via set of header files
-in the API folder.
+External functions and structures are available via a set of header
+files in the API folder.
This library depends on DPDK primitives to perform Ethernet networking
-in userspace, including initialization and control of Ethernet ports.
+in user space, including initialization and control of Ethernet ports.
Ethernet ports are expected to be SRIOV virtual functions (VF) but also
-can be physical functions (PF) as well.
+can be physical functions (PF) as well
This library is expected to be included in the project via
xran_fh_o_du.h, statically compiled and linked with the L1 application
as well as DPDK libraries. The O-RAN packet processing-specific
functionality is encapsulated into this library and not exposed to the
-rest of the 5G NR pipeline.
+rest of the 5G NR pipeline.
-This way, O-RAN specific changes are decoupled from the 5G NR L1
-pipeline. As a result, the design and implementation of the 5G L1
-pipeline code and O-RAN library can be done in parallel, provided the
-defined interface is not modified.
+This way, O-RAN specific changes are decoupled from the L1 pipeline. As a
+result, the design and implementation of the 5G L1 pipeline code and
+O-RAN FHI library can be done in parallel, provided the defined interface is
+not modified.
Ethernet consists of two modules:
A detailed description of functions and input/output arguments, as well
as key data structures, can be found in the Doxygen file for the FlexRAN
-5G NR release. In this document supplemental information is provided
-with respect to the overall design and implementation assumptions.
+5G NR release, Refer to Table 2. In this document, supplemental
+information is provided for the overall design and implementation
+assumptions.(Available only outside of the Community Version)
Initialization and Close
------------------------
14 symbols).
5.Call xran_open() to initialize PRACH configuration, initialize DPDK,
-and launch O-RAN timing thread.
+and launch xRAN timing thread,
6.Call xran_start() to start processing O-RAN packets for DL and UL.
After this is complete 5G L1 runs with O-RAN Front haul interface. During
run time for every TTI event, the corresponding call back is called. For
packet reception on UL direction, the corresponding call back is called.
-OTA time information such as frame id, subframe id and slot id can be
+OTA time information such as frame id, subframe id, and slot id can be
obtained as result synchronization of the L1 pipeline to GPS time is
performed.
To stop and close the interface, perform this sequence of steps:
-7.Call xran_stop() to stop the processing of DL and UL.
+1.Call xran_stop() to stop the processing of DL and UL
-8.Call xran_close() to remove usage of O-RAN resources.
+2.Call xran_close() to remove usage of xRAN resources
-9.Call xran_mm_destroy() to destroy memory management subsystem.
+3.Call xran_mm_destroy() to destroy memory management subsystem
After this session is complete, a restart of the full L1 application is
required. The current version of the library does not support multiple
folder /app/usecase/ contains set of examples for different Radio Access technology (LTE|5G NR), different category (A|B)
and list of numerologies (0,1,3) and list of bandwidths (5,10,20,100Mhz).
-Some configuration options are not used in the current release and are reserved
+Note: Some configuration options are not used in the f release and are reserved
for future use.
The following options are available:
**From an implementation perspective:**
-xran_init() performs init of the O-RAN library and interface according to
-struct xran_fh_init information as per the start of application
-configuration.:
+The xran_init() performs init of the O-RAN FHI library and interface
+according to struct xran_fh_init information as per the start of
+application configuration:
- Init DPDK with corresponding networking ports and core assignment
- Init DPDK timers and DPDK rings for internal packet processing
-- Instantiate ORAN FH thread doing
+- Instantiates ORAH FH thread doing
- Timing processing (xran_timing_source_thread())
- ETH PMD (process_dpdk_io())
- - IO O-RAN-PHY exchange (ring_processing_func())
+ - IO XRAN-PHY exchange (ring_processing_func())
**xran_open()** performs additional configuration as per run scenario:
~~~~~~~~~~~~~
Exchange of IQ samples, as well as C-plane specific information, is
-performed using a set of buffers allocated by O-RAN library from DPDK
+performed using a set of buffers allocated by xRAN library from DPDK
memory and shared with the l1 application. Buffers are allocated as a
-standard mbuf structure and DPDK pools are used to manage the allocation
-and free resources. Shared buffers are allocated at the init stage and
-are expected to be reused within 80 TTIs (10 ms).
+standard mbuf structure, and DPDK pools are used to manage the
+allocation and free resources. Shared buffers are allocated at the init
+stage and are expected to be reused within 80 TTIs (10 ms).
The O-RAN protocol requires U-plane IQ data to be transferred in network
byte order, and the L1 application handles IQ sample data in CPU byte
};
-For the Bronze release C-plane sections are expected to be provided by L1
-pipeline. If 100% of RBs always allocated single element of RB map
+C-plane sections are expected to be provided by the L1
+pipeline. If 100% of the RBs are used they are always allocated as a single element RB map, that
is expected to be allocated across all symbols. Dynamic RB allocation is
-performed base on C-plane configuration.
+performed based on C-plane configuration.
The O-RAN library will require that the content of the PRB map should be
sorted in increasing order of PRB first and then symbols.
From an implementation perspective, the O-RAN library uses a standard
mbuf primitive and allocates a pool of buffers for each sector. This
function is performed using rte_pktmbuf_pool_create(),
-rte_pktmbuf_alloc(), rte_pktmbuf_append() to allocate one buffer per
+rte_pktmbuf_alloc(), and rte_pktmbuf_append() to allocate one buffer per
symbol for the mmWave case. More information on mbuf and DPDK pools can
be found in the DPDK documentation.
};
-Doxygen file and xran_fh_o_du.h provide more details on the definition
-and usage of these structures.
+The Doxygen file and xran_fh_o_du.h provides more details on the
+definition and usage of these structures. Refer to *Table 2*, for
+FlexRAN 5G NR Reference Solution RefPHY (Doxygen).(Not available in
+the community version).
O-RAN Specific Functionality
----------------------------
xran_compression.h – interface to compression/decompression functions
-Doxygen files provide detailed information on functions and structures
-available.
+Source code comments can provide more details on functions and
+structures available.
.. _c-plane-1:
xran_cp_api.c and is used to prepare the content of C-plane packets
according to the given configuration. Users can enable/disable
generation of C-plane messages using enableCP field in struct
-xran_fh_init structure during init of ORAN front haul. The time of
-generation of C-plane message for DL and UL is done “Slot-based,” and
-timing can be controlled using O-DU settings according to Table 4.
+xran_fh_init structure during the initialization of O-RAN front haul.
+The time of generation of C-plane message for DL and UL is done
+“Slot-based,” and timing can be controlled using O-DU settings according
+to *Table 4*.
The C-plane module contains:
- initialization of C-plane database to keep track of allocation of
resources
-- code to prepare C-plane packet for TX (O-DU)
+- Code to prepare C-plane packet for TX (O-DU)
- eCPRI header
- append radio application header
- append control section header
- append control section
-- parser of C-plane packet for RX (O-RU emulation)
+- Parser of C-plane packet for RX (O-RU emulation)
- parses and checks Section 1 and Section 3 packet content
Sending and receiving packets is performed using O-RAN ethdi sublayer
functions.
+More information on function arguments and parameters can be found in
+the comments for the corresponding source code.
+
Creating a C-Plane Packet
^^^^^^^^^^^^^^^^^^^^^^^^^
-API and Data Structures
-'''''''''''''''''''''''
+1. API and Data Structures
A C-Plane message can be composed using the following API:::
dir is the direction of the C-Plane message to be generated. Available
parameters are defined as XRAN_DIR_UL and XRAN_DIR_DL.
-sectionType is the section type for C-Plane message to generate, as O-RAN
-specification defines all sections in a C-Plane message shall have the
-same section type. If different section types are required, they shall
-be sent with separate C-Plane messages. Available types of sections are
-defined as XRAN_CP_SECTIONTYPE_x. Please refer to the Table 5-2 Section
-Types in chapter 5.4 of ORAN specification.
+sectionType is the section type for C-Plane message to generate, as
+O-RAN specification defines all sections in a C-Plane message shall have
+the same section type. If different section types are required, they
+shall be sent with separate C-Plane messages. Available types of
+sections are defined as XRAN_CP_SECTIONTYPE_x. Refer to *Table* 2,
+*O-RAN Specification*, Table 5-2 Section Types.
numSections is the total number of sections to generate, i.e., the
number of the array in sections (struct xran_section_gen_info).
application and section header in the C-Plane message. It is defined as
the structure of xran_cp_header_params. Not all parameters in this
structure are used for the generation, and the required parameters are
-slightly different by the type of section, as described in Table 10.
+slightly different by the type of section, as described in Table 10 and
+References in the remarks column are corresponding Chapter numbers in
+the O-RAN *FrontHaul Working Group Control, User, and Synchronization
+Plane Specification* in *Table 2*.
Table 10. struct xran_cp_header_params – Common Radio Application Header
| || are | | | | | | | |
| || defined | | | | | | | |
| || as | | | | | | | |
-| || O-RAN\ | | | | | | | |
+| || X-RAN\ | | | | | | | |
| | _COMP | | | | | | | |
| || METHOD_x\| | | | | | | |
| || xxx | | | | | | | |
| || Length. | | | | | | | |
+----------+-----------+----------+---------+---+---+---+---+----------+
-**Only sections types 1 and 3 are supported in the current release.**
+**Note:**
+
+1.Only sections types 1 and 3 are supported in the current release.
+
+2.References in the remarks column are corresponding Chapter numbers in
+the *O-RAN Fronthaul Working Group Control, User, and
+Synchronization Plane Specification* in *Table 2*.
Sections are the pointer to the array of structure which has the
parameters for section(s) and it is defined as below:::
info is the structure to hold the information to generate section and it
is defined as the structure of xran_section_info. Like
xran_cp_header_params, all parameters are not required to generate
-section and Table 12 describes which |br|
-parameters are required for each
+section and *Table 12* describes which parameters are required for each
section.
Table 12. Parameters for Sections
| || de\ | | | | | | |
| | fined | | | | | | |
| || as | | | | | | |
-| || O-RA\| | | | | | |
+| || X-RA\| | | | | | |
| | N\ | | | | | | |
| || _RBI\| | | | | | |
| | ND\ | | | | | | |
| | ease. | | | | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
-**Only sections types 1 and 3 are supported in the current release.**
+Note:
+
+1.Only sections types 1 and 3 are supported in the current release.
-**The xran_section_info has more parameters – type, startSymId, iqWidth,
+2.References in the remarks column are corresponding Chapter numbers in
+the *O-RAN FrontHaul Working Group Control, User, and
+Synchronization Plane Specification* in *Table 2*.
+
+Note: xran_section_info has more parameters – type, startSymId, iqWidth,
compMeth. These are the same parameters as those of radio application
or section header but need to be copied into this structure again for
-the section data base.**
+the section data base.
exDataSize and exData are used to add section extensions for the
section.
};
For section extension type 1, the structure of xran_sectionext1_info is
-used. Please note that the O-RAN library will use bfwIQ (beamforming
-weight) as-is, i.e., O-RAN library will not perform the compression, so
-the user should provide proper data to bfwIQ.::
+used.
+
+Note: The O-RAN library will use beamforming weight (bfwIQ) as-is, i.e.,
+O-RAN library will not perform the compression, so the user should provide
+proper data to bfwIQ.::
struct xran_sectionext2_info {
For section extension type 2, the structure of xran_sectionext2_info is
used. Each parameter will be packed as specified bit width.::
+ struct xran_sectionext3_info {
+
+ uint8_t codebookIdx;
+
+ uint8_t layerId;
+
+ uint8_t numLayers;
+
+ uint8_t txScheme;
+
+ uint16_t crsReMask;
+
+ uint8_t crsShift;
+
+ uint8_t crsSymNum;
+
+ uint16_t numAntPort;
+
+ uint16_t beamIdAP1;
+
+ uint16_t beamIdAP2;
+
+ uint16_t beamIdAP3;
+
+ };
+
+For section extension type 3, the structure of xran_sectionext3_info is
+used.::
+
struct xran_sectionext4_info {
uint8_t csf;
};
For section extension type 5, the structure of xran_sectionext5_info is
-used. Please note that current implementation supports maximum two sets
-of additional parameters.::
+used.
+
+Note: Current implementation supports maximum two sets of additional parameters.::
struct xran_sectionext6_info {
};
- For section extension type 6, the structure of xran_sectionext6_info is
- used.
+For section extension type 6, the structure of xran_sectionext6_info is
+used.::
struct xran_sectionext10_info {
Detail Procedures in API
''''''''''''''''''''''''
-xran_prepare_ctrl_pkt() has several procedures to compose a C-Plane
+The xran_prepare_ctrl_pkt() has several procedures to compose a C-Plane
packet.
-1. Append transport header
+1. Append transport header:
- Reserve eCPRI header space in the packet buffer
2. Append radio application header:
-- xran_append_radioapp_header() checks the type of section through
- params->sectionType and determines proper function to append
- remaining header components.
+- The xran_append_radioapp_header() checks the type of section through params->sectionType and determines proper function to append remaining header components.
- Only section type 1 and 3 are supported, returns
XRAN_STATUS_INVALID_PARAM for other types.
header and size to calculate the total length in the transport
header.
-For section type 1, xran_prepare_section1_hdr() and sizeof(struct
-xran_cp_radioapp_section1_header)
+- For section type 1, xran_prepare_section1_hdr() and sizeof(struct xran_cp_radioapp_section1_header)
-For section type 3, xran_prepare_section3_hdr() and sizeof(struct
-xran_cp_radioapp_section3_header)
+- For section type 3, xran_prepare_section3_hdr() and sizeof(struct xran_cp_radioapp_section3_header)
-- Reserves the space of common radio application header and composes
- header by xran_prepare_radioapp_common_header().
+- Reserves the space of common radio application header and composes header by xran_prepare_radioapp_common_header().
-- The header is stored in network byte order.
+ The header is stored in network byte order.
- Appends remaining header components by the selected function above
-- The header is stored in network byte order
+ The header is stored in network byte order
-3. Append section header and section
+3. Append section header and section:
-- xran_append_control_section() determines proper size and function to
- append section header and contents.
+- The xran_append_control_section() determines proper size and function to append section header and contents.
- For section type 1, xran_prepare_section1() and sizeof(struct
xran_cp_radioapp_section1)
- Appends section extensions if it is set (ef=1)
-- xran_append_section_extensions() adds all configured extensions by
- its type.
+- The xran_append_section_extensions() adds all configured extensions by its type.
-- xran_prepare_sectionext_x() (x = 1,2,4,5) will be called by the
- type from xran_append_section_extensions() and these functions
- will create extension field.
+- The xran_prepare_sectionext_x() (x = 1,2,4,5) will be called by the type from and these functions will create extension field.
Example Usage of API
''''''''''''''''''''
The structure of xran_section_info is used to store/retrieve
information. This is the same structure used to generate a C-Plane
-message. Please refer to Section 5.4.2.1.1 for more details.
+message. Refer to Section *1, API and Data Structures* for more details.
The storage for section information is declared as a multi-dimensional
array and declared as a local static variable to limit direct access.
of the information (list), as shown below.
/*
-
\* This structure to store the section information of C-Plane
-
\* in order to generate and parse corresponding U-Plane \*/
struct xran_sectioninfo_db {
-
-uint32_t cur_index; /* Current index to store for this eAXC \*/
-
+uint32_t cur_index; /* Current index to store for this eAXC*/\
struct xran_section_info list[XRAN_MAX_NUM_SECTIONS]; /* The array of
section information \*/
Note. Since the context index is not managed by the library and APIs are
expecting it from the caller as a parameter, the caller shall
-consider a proper way to manage it to avoid corruption. The
+consider a proper method to manage it to avoid corruption. The
current reference implementation uses a slot and subframe index to
calculate the context index.
There are references to show the usage of APIs as below.
-- Initialization and release:
+- Initialization and release::
-- xran_cp_init_sectiondb(): xran_open() in lib/src/xran_main.c
+ xran_cp_init_sectiondb(): xran_open() in lib/src/xran_main.c
-- xran_cp_free_sectiondb(): xran_close() in lib/src/xran_main.c
+ xran_cp_free_sectiondb(): xran_close() in lib/src/xran_main.c
-- Store section information:
+- Store section information::
-- xran_cp_add_section_info(): send_cpmsg_dlul() and
- send_cpmsg_prach()in lib/src/xran_main.c
+ xran_cp_add_section_info(): send_cpmsg_dlul() and
+ send_cpmsg_prach()in lib/src/xran_main.c
-- Retrieve section information:
+- Retrieve section information::
-- xran_cp_iterate_section_info(): xran_process_tx_sym() in
- lib/src/xran_main.c
+ xran_cp_iterate_section_info(): xran_process_tx_sym() in
+ lib/src/xran_main.c
-- xran_cp_getsize_section_info(): xran_process_tx_sym() in
- lib/src/xran_main.c
+ xran_cp_getsize_section_info(): xran_process_tx_sym() in
+ lib/src/xran_main.c
-- Reset the storage for a new slot:
+- Reset the storage for a new slot::
-- xran_cp_reset_section_info(): tx_cp_dl_cb() and tx_cp_ul_cb() in
- lib/src/xran_main.c
+ xran_cp_reset_section_info(): tx_cp_dl_cb() and tx_cp_ul_cb() in
+ lib/src/xran_main.c
**Function for RU emulation and Debug**
'''''''''''''''''''''''''''''''''''''''
xran_parse_cp_pkt() is a function which can be utilized for RU emulation
-or debug. It is defined below:
-
-int xran_parse_cp_pkt(struct rte_mbuf \*mbuf,
-
-struct xran_cp_gen_params \*result,
+or debug. It is defined below::
-struct xran_recv_packet_info \*pkt_info);
+ int xran_parse_cp_pkt(struct rte_mbuf \*mbuf,
+ struct xran_cp_recv_params \*result,
+ struct xran_recv_packet_info \*pkt_info);
It parses a received C-Plane packet and retrieves the information from
its headers and sections.
The retrieved information is stored in the structures:
-struct xran_cp_gen_params: section information from received C-Plane
+struct xran_cp_recv_params: section information from received C-Plane
packet
-struct xran_recv_packet_info: transport layer header information (eCPRI
-header)
+struct xran_recv_packet_info: transport layer header information
+(eCPRI header)
These functions can be utilized to debug or RU emulation purposes.
that there is only one section per packet, and all IQ samples are
attached to it. Compression is not supported.
-A message is built in mbuf space given as a parameter. The library
+A message is built in the mbuf space given as a parameter. The library
builds eCPRI header filling structure fields by taking the IQ sample
size and populating a particular packet length and sequence number.
-With compression, supported IQ bit widths are 8,9,10,12,14.
+With block floating point compression, supported IQ bit widths are
+8,9,10,12,14. With modulation compression, supported IQ bit widths are
+defined according to modulation order as in section A.5 of O-RAN spec..
Implementation of a U-plane set of functions is defined in xran_up_api.c
and is used to prepare U-plane packet content according to the given
The time of generation of a U-plane message for DL and UL is
“symbol-based” and can be controlled using O-DU settings (O-RU),
-according to Table 4.
+according to *Table 4*.
+
+For more information on function arguments and parameters refer to
+corresponding source cod*\ e.
Supporting Code
---------------
where the system timer is synchronized to GPS time via PTP protocol
using the Linux PHP package. On the software side, a simple polling loop
is utilized to get time up to nanosecond precision and particular packet
-processing jobs are scheduled via the DPDK timer.
+processing jobs are scheduled via the DPDK timer.:::
-long poll_next_tick(int interval)
+ long poll_next_tick(int interval)
-{
+ {
-struct timespec start_time;
+ struct timespec start_time;
-struct timespec cur_time;
+ struct timespec cur_time;
-long target_time;
+ long target_time;
-long delta;
+ long delta;
-clock_gettime(CLOCK_REALTIME, &start_time);
+ clock_gettime(CLOCK_REALTIME, &start_time);
-target_time = (start_time.tv_sec \* NSEC_PER_SEC + start_time.tv_nsec +
-interval \* NSEC_PER_USEC) / (interval \* NSEC_PER_USEC) \* interval;
+ target_time = (start_time.tv_sec \* NSEC_PER_SEC + start_time.tv_nsec +
+ interval \* NSEC_PER_USEC) / (interval \* NSEC_PER_USEC) \* interval;
-while(1)
+ while(1)
-{
+ {
-clock_gettime(CLOCK_REALTIME, &cur_time);
+ clock_gettime(CLOCK_REALTIME, &cur_time);
-delta = (cur_time.tv_sec \* NSEC_PER_SEC + cur_time.tv_nsec) -
-target_time \* NSEC_PER_USEC;
+ delta = (cur_time.tv_sec \* NSEC_PER_SEC + cur_time.tv_nsec) -
+ target_time \* NSEC_PER_USEC;
-if(delta > 0 \|\| (delta < 0 && abs(delta) < THRESHOLD))
+ if(delta > 0 \|\| (delta < 0 && abs(delta) < THRESHOLD))
-{
+ {
-break;
+ break;
-}
+ }
-}
+ }
-return delta;
+ return delta;
-}
+ }
Polling is used to achieve the required precision of symbol time. For
example, in the mmWave scenario, the symbol time is 125µs/14=~8.9µs.
Small deterministic tasks can be executed within the polling interval
provided. It’s smaller than the symbol interval time.
+Current O-RAN library supports multiple O-RU of multiple numerologies,
+thus the sense of timing is based on the O-RU with highest numerology
+(smallest symbol time). It is required to configure the O-RU0 with
+highest numerology in the O-RAN configuration.
+
DPDK Timers
~~~~~~~~~~~
Jumbo Frames are used by default. Mbufs size is extended to support 9600
bytes packets.
-Mac address and VLAN tag are expected to be configured by Infrastructure
-software. See Appendix A.4.
+Configurable MTU size is supported starting from E release.
+
+MAC address and VLAN tag are expected to be configured by Infrastructure
+software. Refer to *A.4, Install and Configure Sample Application*.
From an implementation perspective, modules provide functions to handle:
- Send and Receive mbuf.
-O-RAN Ethdi
-~~~~~~~~~~~
+xRAN Ethdi
+~~~~~~~~~~
Ethdi provides functionality to work with the content of an Ethernet
-packet and dispatch processing to/from the O-RAN layer. Ethdi
+packet and dispatch processing to/from the xRAN layer. Ethdi
instantiates a main PMD driver thread and dispatches packets between the
ring and RX/TX using rte_eth_rx_burst() and rte_eth_tx_burst() DPDK
functions.
For received packets, it maintains a set of handlers for ethertype
-handlers and O-RAN layer register one O-RAN ethtype |br|
+handlers and xRAN layer register one O-RAN ethtype |br|
0xAEFE, resulting in
-packets with this ethertype being routed to the O-RAN processing
+packets with this ethertype being routed to the xRAN processing
function. This function checks the message type of the eCPRI header and
dispatches packet to either C-plane processing or U-plane processing.
-Initialization of memory pools, allocation and freeing of mbuf for
+Initialization of memory pools, allocation, and freeing of the mbuf for
Ethernet packets occur in this layer.
O-RAN One Way Delay Measurements
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The support for the eCPRI one- way delay measurements which are specified by
-the O-RAN to be used with the Measured Transport support per Section 2.3.3.3
-of the O-RAN-WG4.CUS.0-v4.00 specification and section 3.2.4.6 of the eCPRI_v2.0
-specification is implemented in the file xran_delay_measurement.c. Structure
-definitions used by the owd measurement functions are in the file xran_fh_o_du.h
-for common data and port specific variables and parameters.
-
-The implementation of this feature has been done under the assumption that the requestor
-is the O-DU and the recipient is the O-RU. All of the action_types per the eCPRI 2.0 have
-been implemented. In the current version the timestamps are obtained using the linux
-function clock_gettime using CLOCK_REALTIME as the clock_id argument.
-
-The implementation supports both the O-RU and the O-DU side in order to do the unit test
-in loopback mode.
-
-The one-delay measurements are enabled at configuration time and run right after the
-xran_start() function is executed. The total number of consecutive measurements per port
-should be a power of 2 and in order to minimize the system startup it is advisable that
-the number is 16 or below.
+The support for the eCPRI one- way delay measurements which are
+specified by the O-RAN to be used with the Measured Transport support
+per Section 2.3.3.3 of the O-RAN-WG4.CUS.0-v4.00 specification and
+section 3.2.4.6 of the eCPRI_v2.0 specification is implemented in the
+file xran_delay_measurement.c. Structure definitions used by the owd
+measurement functions are in the file xran_fh_o_du.h for common data and
+port specific variables and parameters.
+
+The implementation of this feature has been done under the assumption
+that the requestor is the O-DU and the recipient is the O-RU. All of the
+action_types per the eCPRI 2.0 have been implemented. In the current
+version the timestamps are obtained using the linux function
+clock_gettime using CLOCK_REALTIME as the clock_id argument.
+
+The implementation supports both the O-RU and the O-DU side in order to
+do the unit test in loopback mode.
+
+The one-delay measurements are enabled at configuration time and run
+right after the xran_start() function is executed. The total number of
+consecutive measurements per port should be a power of 2 and in order to
+minimize the system startup it is advisable that the number is 16 or
+below.
The following functions can be found in the xran_delay_measurement.c:
-xran_ecpri_one_way_delay_measurement_transmitter() which is invoked from the
-process_dpdk_io()function if the one-way delay measurements are enabled. This is
-the main function for the owd transmitter.
+xran_ecpri_one_way_delay_measurement_transmitter() which is invoked from
+the process_dpdk_io() function if the one-way delay measurements are
+enabled. This is the main function for the owd transmitter.
-xran_generate_delay_meas() is a general function used by the transmitter to send the appropriate
-messages based on actionType and filling up all the details for the ethernet and ecpri layers.
+xran_generate_delay_meas() is a general function used by the transmitter
+to send the appropriate messages based on actionType and filling up all
+the details for the ethernet and ecpri layers.
-Process_delay_meas() this function is invoked from the handle_ecpri_ethertype() function when
-the ecpri message type is ECPRI_DELAY_MEASUREMENT. This is the main owd receiver function.
+Process_delay_meas() this function is invoked from the
+handle_ecpri_ethertype() function when the ecpri message type is
+ECPRI_DELAY_MEASUREMENT. This is the main owd receiver function.
-From the Process_delay_meas() and depending on the message received we can execute one
-of the following functions
+From the Process_delay_meas() and depending on the message received we
+can execute one of the following functions
xran_process_delmeas_request() If we received a request message.
;******************************************************************************
;
-; Copyright (c) 2019 Intel.
+; Copyright (c) 2021 Intel.
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; Note:
; Schedule Policy [1: SCHED_FIFO 2: SCHED_RR]
[MAC2PHY_WORKER]
-core_id = 18
+core_id = 10
thread_sched_policy = 1
thread_priority = 89
[PHY2MAC_WORKER]
-core_id = 19
+core_id = 11
thread_sched_policy = 1
thread_priority = 89
[URLLC_WORKER]
-core_id = 19
+is_enabled = 1
+core_id = 12
thread_sched_policy = 1
thread_priority = 96
[WLS_CFG]
-device_name = wls_f0
+device_name = wls0
shmem_size = 2126512128
; Log level
; 0 - PA
; 1 - VA
dpdk_iova_mode = 0
-dpdk_memory_zone = gnb_f0
+dpdk_memory_zone = gnb0
###############################################################################
#
-# Copyright (c) 2019 Intel.
+# Copyright (c) 2021 Intel.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
echo start ORAN 5G FAPI
if [ "$1" = "-g" ]; then
shift
- #gdb-ia --args ./oran_5g_fapi $@
- gdb --args ./oran_5g_fapi $@
+ if [ "$RTE_TARGET" == "x86_64-native-linuxapp-icx"]; then
+ /opt/intel/oneapi/debugger/10.2.4/gdb/intel64/bin/gdb-oneapi --args ./oran_5g_fapi $@
+ else
+ /home/opt/intel/system_studio_2019/bin/gdb-ia --args ./oran_5g_fapi $@
+ fi
else
./oran_5g_fapi $@
fi
#!/bin/sh
###############################################################################
#
-# Copyright (c) 2019 Intel.
+# Copyright (c) 2021 Intel.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
###############################################################################
#
-# Copyright (c) 2019 Intel.
+# Copyright (c) 2021 Intel.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
##############################################################
# Tools configuration
##############################################################
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
CC := icc
CPP := icpc
AS := as
AR := ar
LD := icc
-OBJDUMP := objdump
-
-ifeq ($(SHELL),cmd.exe)
-MD := mkdir.exe -p
-RM := rm.exe -rf
+else ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ CC := icx
+ CPP := icx
+ AS := as
+ AR := ar
+ LD := icx
else
+ $(error "Please define WIRELESS_SDK_TOOLCHAIN environment variable")
+endif
+
+ifeq ($(WIRELESS_SDK_TARGET_ISA),sse)
+ TARGET_PROCESSOR := -xSSE4.2
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx2)
+ TARGET_PROCESSOR := -xCORE-AVX2
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx512)
+ TARGET_PROCESSOR := -xCORE-AVX512
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),snc)
+ TARGET_PROCESSOR := -xicelake-server
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),spr)
+ TARGET_PROCESSOR := -march=sapphirerapids
+endif
+
+ifeq ($(TARGET_PROCESSOR),)
+ $(error "Please define valid WIRELESS_SDK_TARGET_ISA environment variable $(WIRELESS_SDK_TARGET_ISA)")
+endif
+OBJDUMP := objdump
MD := mkdir -p
+CP := cp -f
RM := rm -rf
-endif
##############################################################
# TARGET
$(error "Please define RTE_SDK environment variable")
endif
-ifeq ($(MESON_BUILD),0)
-RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include
-else
-RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk)
-endif
+RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk)
##############################################################
# Projects folders
-I$(SRCDIR)/framework/wls/lib \
-I$(SRCDIR)/api/fapi2mac \
-I$(SRCDIR)/api/fapi2phy \
- -I$(FLEXRANDIR)/source/nr5g/api \
- -I$(FLEXRANDIR)/source/common \
+ -I$(FLEXRANDIR)/l1/source/nr5g/api \
+ -I$(FLEXRANDIR)/l1/source/common \
-I$(SRCDIR)/api/fapi2phy/p5 \
-I$(SRCDIR)/api/fapi2phy/p7 \
-I$(SRCDIR)/api/fapi2mac/p5 \
DEFS := $(addprefix -D,$(DEFS))
-CFLAGS := -g -Wall -Wextra -Wunused -wd9 -Wno-deprecated-declarations -Wimplicit-function-declaration -fasm-blocks -fstack-protector-strong -z,now, -z,relro -z noexecstack -Wformat -Wformat-security -Werror=format-security -fno-strict-overflow -fwrapv $(DEFS) $(INC)
+CFLAGS := -g -Wall -Wextra -Wunused -diag-disable9 -Wno-deprecated-declarations -Wimplicit-function-declaration -fasm-blocks -fstack-protector-strong -Wformat -Wformat-security -Werror=format-security -fwrapv -mssse3 $(DEFS) $(INC)
ifeq ($(PRINTDBG),)
CFLAGS := $(CFLAGS) -Werror
endif
-#RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
-ifeq ($(MESON_BUILD),0)
-RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
-else
-RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive
-endif
-LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls
+RTE_LIBS := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --static --libs libdpdk)
+LDFLAGS := -z now -z relro -z noexecstack -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls
LINUX_ORAN_5G_FAPI_SRC := \
$(SRCDIR)/nr5g_fapi.c \
$(SRCDIR)/utils/nr5g_fapi_snr_conversion.c \
$(SRCDIR)/framework/workers/nr5g_fapi_mac2phy_thread.c \
$(SRCDIR)/framework/workers/nr5g_fapi_phy2mac_thread.c \
- $(SRCDIR)/framework/workers/nr5g_fapi_urllc_thread.c \
+ $(SRCDIR)//framework/workers/nr5g_fapi_urllc_phy2mac_thread.c \
+ $(SRCDIR)//framework/workers/nr5g_fapi_urllc_mac2phy_thread.c \
$(SRCDIR)/framework/nr5g_fapi_framework.c \
$(SRCDIR)/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.c \
$(SRCDIR)/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.c \
$(SRCDIR)/api/fapi2phy/nr5g_fapi_fapi2phy_api.c \
$(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_add_remove_core_msg.c \
$(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_config_req.c \
+ $(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_param_resp.c \
$(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_start_req.c \
$(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_stop_req.c \
$(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_shutdown_req.c \
$(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_ul_iq_samples_req.c \
$(SRCDIR)/api/fapi2phy/p7/nr5g_fapi_proc_dl_tti_req.c \
$(SRCDIR)/api/fapi2phy/p7/nr5g_fapi_proc_ul_tti_req.c \
+ $(SRCDIR)/api/fapi2phy/p7/nr5g_fapi_proc_tti_req_common.c \
$(SRCDIR)/api/fapi2phy/p7/nr5g_fapi_proc_tx_data_req.c \
$(SRCDIR)/api/fapi2phy/p7/nr5g_fapi_proc_ul_dci_req.c
.PHONY: $(APP)
$(APP): $(DIRLIST) echo_options $(GEN_DEP) $(OBJS)
@echo [LD] $(APP)
- @$(CC) -o $(APP) $(OBJS) $(LDFLAGS) $(RTE_LIBS)
+ @$(CC) -o $(APP) $(OBJS) $(LDFLAGS) $(RTE_LIBS) -lstdc++ # stdc++ flag needed for RTE LIBS
# $(OBJDUMP) -d $(APP) > $(APP).asm
.PHONY : echo_options
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#define FAPI_MAX_NUM_TLVS_START 3 // Based on Timer Mode requirement.
#define FAPI_MAX_NUM_TLVS_SHUTDOWN 1 // Based on Timer Mode requirement.
#define FAPI_MAX_UCI_BIT_BYTE_LEN 256
+#define FAPI_RB_BITMAP_SIZE 36 // Based on 5G FAPI Table 3-38
enum ul_tti_pdu_type_e {
FAPI_PRACH_PDU_TYPE = 0,
FAPI_DL_TTI_PDU_TYPE_MAX
};
+ enum dl_resource_alloc_type_e { // Based on 5G FAPI Table 3-38
+ FAPI_DL_RESOURCE_ALLOC_TYPE_0 = 0,
+ FAPI_DL_RESOURCE_ALLOC_TYPE_1 = 1
+ };
+
+ enum ul_resource_alloc_type_e { // Based on 5G FAPI Table 3-38
+ FAPI_UL_RESOURCE_ALLOC_TYPE_0 = 0,
+ FAPI_UL_RESOURCE_ALLOC_TYPE_1 = 1
+ };
+
//------------------------------------------------------------------------------------------------------------
// Updated per 5G FAPI
typedef struct {
uint16_t dmrsPorts;
uint16_t rbStart;
uint16_t rbSize;
- uint8_t rbBitmap[36];
+ uint8_t rbBitmap[FAPI_RB_BITMAP_SIZE];
uint8_t vrbToPrbMapping;
uint8_t startSymbIndex;
uint8_t nrOfSymbols;
uint16_t dmrsPorts;
uint16_t nTpPuschId;
uint16_t tpPi2Bpsk;
- uint8_t rbBitmap[36];
+ uint8_t rbBitmap[FAPI_RB_BITMAP_SIZE];
uint16_t rbStart;
uint16_t rbSize;
uint8_t vrbToPrbMapping;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#define FAPI_MAX_NUM_SET_CORE_MASK ( 4 )
#define FAPI_MAX_MASK_OPTIONS ( 4 )
#define FAPI_NUM_SPLIT_OPTIONS ( 22 )
+#define FAPI_MAX_NUM_CELLS ( 32 )
+#define FAPI_MAX_GROUP_NUM ( 32 )
#endif
typedef struct {
fapi_start_req_vendor_msg_t start_req_vendor;
fapi_stop_req_vendor_msg_t stop_req_vendor;
fapi_vendor_p7_msg_t p7_req_vendor;
- } fapi_vendor_msg_t;
+ } fapi_vendor_msg_t; //TODO: union?
typedef struct {
fapi_msg_t header;
uint32_t eOption;
uint64_t nCoreMask[FAPI_MAX_MASK_OPTIONS][FAPI_MAX_NUM_SET_CORE_MASK];
uint32_t nMacOptions[FAPI_NUM_SPLIT_OPTIONS];
+ uint8_t nPuschInterOptions[FAPI_MAX_NUM_CELLS][FAPI_MAX_GROUP_NUM];
} fapi_vendor_ext_add_remove_core_info_t;
typedef struct {
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include <stdio.h>
#include "nr5g_fapi_internal.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_wls.h"
#include "nr5g_fapi_log.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_proc_error_ind.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef _NR5G_FAPI_FAP2MAC_P5_PROC_H_
#define _NR5G_FAPI_FAP2MAC_P5_PROC_H_
-#include "gnb_l1_l2_api.h"
+#include "common_mac_phy_api.h"
+#include "nr5g_mac_phy_api.h"
uint8_t nr5g_fapi_message_header(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
#ifdef DEBUG_MODE
uint8_t nr5g_fapi_dl_iq_samples_response(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
- PADD_REMOVE_BBU_CORES p_iapi_resp);
+ PADD_REMOVE_BBU_CORES_NR5G p_iapi_resp);
uint8_t nr5g_fapi_ul_iq_samples_response(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
- PADD_REMOVE_BBU_CORES p_iapi_resp);
+ PADD_REMOVE_BBU_CORES_NR5G p_iapi_resp);
uint8_t nr5g_fapi_message_header_for_ul_iq_samples(
uint8_t phy_id);
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
**/
uint8_t nr5g_fapi_dl_iq_samples_response(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
- PADD_REMOVE_BBU_CORES p_iapi_resp)
+ PADD_REMOVE_BBU_CORES_NR5G p_iapi_resp)
{
uint8_t phy_id;
fapi_vendor_ext_dl_iq_samples_res_t *p_fapi_resp;
NR5G_FAPI_LOG(INFO_LOG, ("[DL_IQ_SAMPLES.response][%d]", phy_id));
+ nr5g_fapi_clean(p_phy_instance);
return SUCCESS;
}
#endif
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
#include "nr5g_fapi_internal.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
p_stats->fapi_stats.fapi_stop_ind++;
NR5G_FAPI_LOG(INFO_LOG, ("[STOP.Indication][%d]", phy_id));
p_phy_instance->shutdown_retries = 0;
+ nr5g_fapi_clean(p_phy_instance);
#endif
} else {
/* PHY SHUTDOWN Failed. Retrigger Shutdown request for 3 tries before
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
**/
uint8_t nr5g_fapi_ul_iq_samples_response(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
- PADD_REMOVE_BBU_CORES p_iapi_resp)
+ PADD_REMOVE_BBU_CORES_NR5G p_iapi_resp)
{
uint8_t phy_id;
fapi_vendor_ext_ul_iq_samples_res_t *p_fapi_resp;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (c) 2021 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
-#include "fapi_vendor_extension.h"
-#include "gnb_l1_l2_api.h"
-#include "nr5g_fapi_common_types.h"
-#include "nr5g_fapi_fapi2phy_api.h"
-#include "nr5g_fapi_log.h"
-
-/**
- * @file
- * This file consist of implementation of FAPI VENDOR ADD_REMOVE_CORE message.
- *
- **/
-
-/** @ingroup group_source_api_p5_fapi2phy_proc
- *
- * @param[in] p_fapi_req Pointer to FAPI VENDOR ADD_REMOVE_CORE message structure.
- * @return Returns ::SUCCESS and ::FAILURE.
- *
- * @description
- * This is a timer mode specific message used to set options on bbupool cores.
- *
- */
-#ifdef DEBUG_MODE
-uint8_t nr5g_fapi_add_remove_core_message(
- bool is_urllc,
- fapi_vendor_ext_add_remove_core_msg_t * p_fapi_req)
-{
- uint32_t i, k;
- PMAC2PHY_QUEUE_EL p_list_elem;
- PADD_REMOVE_BBU_CORES p_add_remove_bbu_cores;
-
- /* Below print is for better logging on console in debug mode. */
- NR5G_FAPI_LOG(INFO_LOG, (""));
-
- if (NULL == p_fapi_req) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Invalid fapi message"));
- return FAILURE;
- }
-
- p_list_elem = nr5g_fapi_fapi2phy_create_api_list_elem(
- (uint8_t)MSG_TYPE_PHY_ADD_REMOVE_CORE, 1, (uint32_t) sizeof(ADD_REMOVE_BBU_CORES));
-
- if (!p_list_elem) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Unable to create "
- "list element. Out of memory!!!"));
- return FAILURE;
- }
-
- p_add_remove_bbu_cores = (PADD_REMOVE_BBU_CORES) (p_list_elem + 1);
- p_add_remove_bbu_cores->sMsgHdr.nMessageType = MSG_TYPE_PHY_ADD_REMOVE_CORE;
- p_add_remove_bbu_cores->sMsgHdr.nMessageLen = sizeof(ADD_REMOVE_BBU_CORES);
-
- for (i = 0; i < FAPI_MAX_NUM_SET_CORE_MASK; ++i)
- {
- for (k = 0; k < FAPI_MAX_MASK_OPTIONS; ++k)
- {
- p_add_remove_bbu_cores->nCoreMask[k][i] = p_fapi_req->add_remove_core_info.nCoreMask[k][i];
- }
- }
- for (i = 0; i < FAPI_NUM_SPLIT_OPTIONS; ++i)
- {
- p_add_remove_bbu_cores->nMacOptions[i] = p_fapi_req->add_remove_core_info.nMacOptions[i];
- }
- p_add_remove_bbu_cores->eOption = (BBUPOOL_CORE_OPERATION)p_fapi_req->add_remove_core_info.eOption;
-
- nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem);
-
- NR5G_FAPI_LOG(INFO_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE.message]"));
-
- return SUCCESS;
-}
-#endif
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h"
p_fapi_pdu_ind_info->handle = p_pusch_info->handle;
p_fapi_pdu_ind_info->rnti = p_rx_ulsch_pdu_data->nRNTI;
- p_fapi_pdu_ind_info->harqId = p_pusch_info->harq_process_id;
+ // upper nibble of pdu_length is passed in upper nibble in harqId (which only takes up to 4 bits)
+ // this way, pdu_length has 20-bits (up to 1048576)
+ p_fapi_pdu_ind_info->harqId = ((p_rx_ulsch_pdu_data->nPduLen & 0x000F0000) >> 12) | (p_pusch_info->harq_process_id & 0x0F);
p_fapi_pdu_ind_info->ul_cqi = p_pusch_info->ul_cqi;
p_fapi_pdu_ind_info->timingAdvance = p_pusch_info->timing_advance;
p_fapi_pdu_ind_info->rssi = 880;
- p_fapi_pdu_ind_info->pdu_length = p_rx_ulsch_pdu_data->nPduLen;
- if (p_fapi_pdu_ind_info->pdu_length > 0)
- {
+ p_fapi_pdu_ind_info->pdu_length = 0xFFFF & p_rx_ulsch_pdu_data->nPduLen;
p_fapi_pdu_ind_info->pduData = (void *)p_rx_ulsch_pdu_data->pPayload;
- }
p_stats->fapi_stats.fapi_rx_data_ind_pdus++;
}
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h"
*
*******************************************************************************/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include <stdio.h>
#include "nr5g_fapi_internal.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_wls.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_wls.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef NR5G_FAPI_FAPI2PHY_API_H
#define NR5G_FAPI_FAPI2PHY_API_H
-#include "gnb_l1_l2_api.h"
+#include "common_mac_phy_api.h"
#include <nr5g_fapi_std.h>
typedef struct _nr5g_fapi_fapi2phy_queue {
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef _NR5G_FAPI_FAP2PHY_P5_PROC_H_
#define _NR5G_FAPI_FAP2PHY_P5_PROC_H_
+uint8_t nr5g_fapi_param_response(
+ p_nr5g_fapi_phy_instance_t p_phy_instance);
+
uint8_t nr5g_fapi_config_request(
bool is_urllc,
p_nr5g_fapi_phy_instance_t p_phy_instance,
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef _NR5G_FAPI_FAP2PHY_P5_PVT_PROC_H_
#define _NR5G_FAPI_FAP2PHY_P5_PVT_PROC_H_
+#include "nr5g_mac_phy_api.h"
+
//x is 32 bit variable, y is length in bytes
#define GETVLFRM32B(x, y) ((x) & ((0xFFFFFFFF) >> (32 - (y << 3))))
*
*******************************************************************************/
+#include "nr5g_mac_phy_api.h"
#include "fapi_vendor_extension.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_common_types.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_log.h"
{
uint32_t i, k;
PMAC2PHY_QUEUE_EL p_list_elem;
+ PADD_REMOVE_BBU_CORES_NR5G p_add_remove_bbu_cores_nr5g;
PADD_REMOVE_BBU_CORES p_add_remove_bbu_cores;
/* Below print is for better logging on console in debug mode. */
}
p_list_elem = nr5g_fapi_fapi2phy_create_api_list_elem(
- (uint8_t)MSG_TYPE_PHY_ADD_REMOVE_CORE, 1, (uint32_t) sizeof(ADD_REMOVE_BBU_CORES));
+ (uint8_t)MSG_TYPE_PHY_ADD_REMOVE_CORE, 1, (uint32_t) sizeof(ADD_REMOVE_BBU_CORES_NR5G));
if (!p_list_elem) {
NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Unable to create "
return FAILURE;
}
- p_add_remove_bbu_cores = (PADD_REMOVE_BBU_CORES) (p_list_elem + 1);
- p_add_remove_bbu_cores->sMsgHdr.nMessageType = MSG_TYPE_PHY_ADD_REMOVE_CORE;
- p_add_remove_bbu_cores->sMsgHdr.nMessageLen = sizeof(ADD_REMOVE_BBU_CORES);
+ p_add_remove_bbu_cores_nr5g = (PADD_REMOVE_BBU_CORES_NR5G) (p_list_elem + 1);
+ p_add_remove_bbu_cores_nr5g->sMsgHdr.nMessageType = MSG_TYPE_PHY_ADD_REMOVE_CORE;
+ p_add_remove_bbu_cores_nr5g->sMsgHdr.nMessageLen = sizeof(ADD_REMOVE_BBU_CORES_NR5G);
+ p_add_remove_bbu_cores = &p_add_remove_bbu_cores_nr5g->sAddRemoveBbuCores;
for (i = 0; i < FAPI_MAX_NUM_SET_CORE_MASK; ++i)
{
for (k = 0; k < FAPI_MAX_MASK_OPTIONS; ++k)
{
p_add_remove_bbu_cores->nMacOptions[i] = p_fapi_req->add_remove_core_info.nMacOptions[i];
}
+ for(k = 0; k < FAPI_MAX_NUM_CELLS; ++k) {
+ for(i = 0; i < FAPI_MAX_GROUP_NUM; ++i) {
+ p_add_remove_bbu_cores->nPuschInterOptions[k][i] = p_fapi_req->add_remove_core_info.nPuschInterOptions[k][i];
+ }
+ }
p_add_remove_bbu_cores->eOption = (BBUPOOL_CORE_OPERATION)p_fapi_req->add_remove_core_info.eOption;
nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem);
/******************************************************************************
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
/***** Carrier Config *****/
case FAPI_DL_BANDWIDTH_TAG:
p_ia_config_req->nDLBandwidth =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_DL_FREQUENCY_TAG:
- p_ia_config_req->nDLAbsFrePointA = tlvs[i++].value;
+ p_ia_config_req->nDLAbsFrePointA = tlvs[i].value;
+ ++i;
break;
/* FAPI_DL_K0_TAG - NA */
case FAPI_NUM_TX_ANT_TAG:
p_ia_config_req->nNrOfTxAnt =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_UPLINK_BANDWIDTH_TAG:
p_ia_config_req->nULBandwidth =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_UPLINK_FREQUENCY_TAG:
- p_ia_config_req->nULAbsFrePointA = tlvs[i++].value;
+ p_ia_config_req->nULAbsFrePointA = tlvs[i].value;
+ ++i;
break;
/* FAPI_UL_K0_TAG - NA */
case FAPI_NUM_RX_ANT_TAG:
p_phy_instance->phy_config.n_nr_of_rx_ant =
p_ia_config_req->nNrOfRxAnt =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
/* FAPI_FREQUENCY_SHIFT_7P5_KHZ_TAG - NA */
case FAPI_PHY_CELL_ID_TAG:
p_phy_instance->phy_config.phy_cell_id =
p_ia_config_req->nPhyCellId =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_FRAME_DUPLEX_TYPE_TAG:
p_ia_config_req->nFrameDuplexType =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
/***** SSB Config *****/
p_ia_config_req->nSubcCommon =
p_ia_config_req->nSSBSubcSpacing =
p_phy_instance->phy_config.sub_c_common =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
/***** PRACH Config *****/
case FAPI_PRACH_SUBC_SPACING_TAG:
p_ia_config_req->nPrachSubcSpacing =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_RESTRICTED_SET_CONFIG_TAG:
p_ia_config_req->nPrachRestrictSet =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_NUM_PRACH_FD_OCCASIONS_TAG:
p_ia_config_req->nPrachFdm =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_PRACH_CONFIG_INDEX_TAG:
p_ia_config_req->nPrachConfIdx =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_PRACH_ROOT_SEQUENCE_INDEX_TAG:
p_ia_config_req->nPrachRootSeqIdx =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_K1_TAG:
p_ia_config_req->nPrachFreqStart =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_PRACH_ZERO_CORR_CONF_TAG:
p_ia_config_req->nPrachZeroCorrConf =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_SSB_PER_RACH_TAG:
p_ia_config_req->nPrachSsbRach =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
/***** SSB Table *****/
case FAPI_SSB_OFFSET_POINT_A_TAG:
p_ia_config_req->nSSBPrbOffset =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length) / (pow(2,
- p_ia_config_req->nSubcCommon));
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length) /
+ (pow(2, p_ia_config_req->nSubcCommon));
+ ++i;
break;
case FAPI_SSB_PERIOD_TAG:
p_ia_config_req->nSSBPeriod =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_SSB_SUBCARRIER_OFFSET_TAG:
p_ia_config_req->nSSBSubcOffset =
- (tlvs[i].value >> tlvs[i++].tl.length);
+ (tlvs[i].value >> tlvs[i].tl.length);
+ ++i;
break;
case FAPI_MIB_TAG:
case FAPI_DMRS_TYPE_A_POS_TAG:
p_ia_config_req->nDMRSTypeAPos =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
break;
case FAPI_SSB_MASK_TAG:
if (n_ssb_mask_idx < 2) {
p_ia_config_req->nSSBMask[n_ssb_mask_idx++] =
- tlvs[i++].value;
+ tlvs[i].value;
+ ++i;
}
break;
case FAPI_BEAM_ID_TAG:
- if (n_beamid_idx < MAX_NUM_ANT) {
+ if (n_beamid_idx < MAX_NUM_ANT_NR5G) {
p_ia_config_req->nBeamId[n_beamid_idx++] =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
+ ++i;
}
break;
case FAPI_TDD_PERIOD_TAG:
p_ia_config_req->nTddPeriod =
nr5g_fapi_calc_phy_tdd_period((uint8_t)
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length),
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length),
p_ia_config_req->nSubcCommon);
+ ++i;
break;
case FAPI_SLOT_CONFIG_TAG:
for (j = 0; j < p_ia_config_req->nTddPeriod; j++) {
p_sslot_Config = &p_ia_config_req->sSlotConfig[j];
- for (k = 0; k < MAX_NUM_OF_SYMBOL_PER_SLOT; k++) {
+ for (k = 0; k < MAX_NUM_OF_SYMBOL_PER_SLOT; k++, i++) {
p_sslot_Config->nSymbolType[k] =
- GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length);
+ GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length);
}
}
break;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2022 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @file
+ * This file consist of implementation of FAPI PARAM.response message.
+ *
+ **/
+
+#include "nr5g_fapi_framework.h"
+#include "nr5g_fapi_fapi2mac_api.h"
+#include "nr5g_fapi_fapi2mac_p5_proc.h"
+
+ /** @ingroup group_source_api_p5_fapi2mac_proc
+ *
+ * @param[in] p_phy_instance Pointer to PHY instance.
+ * @return Returns ::SUCCESS and ::FAILURE.
+ *
+ * @description
+ * This message allows PHY to report L2/L3 about PARAM.request's status.
+ *
+**/
+uint8_t nr5g_fapi_param_response(
+ p_nr5g_fapi_phy_instance_t p_phy_instance)
+{
+ fapi_param_resp_t *p_fapi_resp;
+ p_fapi_api_queue_elem_t p_list_elem;
+ nr5g_fapi_stats_t *p_stats;
+
+ // Create FAPI message header
+ nr5g_fapi_message_header_per_phy(p_phy_instance->phy_id, false);
+
+ p_stats = &p_phy_instance->stats;
+ p_stats->iapi_stats.iapi_param_res++;
+ p_list_elem =
+ nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_PARAM_RESPONSE, 1,
+ sizeof(fapi_param_resp_t));
+ if (!p_list_elem) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("[PARAM.response] Unable to create "
+ "list element. Out of memory!!!"));
+ return FAILURE;
+ }
+
+ p_fapi_resp = (fapi_param_resp_t *) (p_list_elem + 1);
+ p_fapi_resp->header.msg_id = FAPI_PARAM_RESPONSE;
+ p_fapi_resp->header.length = (uint16_t) sizeof(fapi_param_resp_t);
+ p_fapi_resp->error_code =
+ (p_phy_instance->state == FAPI_STATE_RUNNING) ? MSG_INVALID_STATE : MSG_OK;
+
+ /* TLV report is not supported in PHY */
+ p_fapi_resp->number_of_tlvs = 0;
+
+ // Add element to send list
+ nr5g_fapi_fapi2mac_add_api_to_list(p_phy_instance->phy_id, p_list_elem, false);
+
+ p_stats->fapi_stats.fapi_param_res++;
+ NR5G_FAPI_LOG(INFO_LOG, ("[PARAM.response][%d]", p_phy_instance->phy_id));
+ nr5g_fapi_fapi2mac_send_api_list(false);
+
+ return SUCCESS;
+}
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef _NR5G_FAPI_FAP2PHY_P7_PVT_PROC_H_
#define _NR5G_FAPI_FAP2PHY_P7_PVT_PROC_H_
+
+#include "nr5g_mac_phy_api.h"
+#include "fapi_interface.h"
+#include "fapi_vendor_extension.h"
+#include "nr5g_fapi_framework.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// DL/UL_TTI.req common
+uint8_t nr5g_fapi_calc_n_rbg_size(
+ uint16_t bwp_size);
+
+uint32_t nr5g_fapi_calc_rbg_index(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint16_t bwp_start,
+ uint16_t bwp_size,
+ uint32_t(*get_rbg_index_mask)(uint32_t nth_bit));
+
+uint16_t nr5g_fapi_get_rb_bits_for_rbg(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint32_t rbg_bit,
+ uint8_t rbg_size,
+ uint16_t rb_bitmap_mask);
+
// DL_TTI.req
uint8_t nr5g_fapi_dl_tti_req_to_phy_translation(
p_nr5g_fapi_phy_instance_t p_phy_instance,
uint16_t nr5g_fapi_calculate_nEpreRatioOfPDSCHToSSB(
uint8_t power_control_offset);
+uint32_t nr5g_fapi_calc_pdsch_rbg_index(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint16_t bwp_start,
+ uint16_t bwp_size);
+
void nr5g_fapi_fill_ssb_pdu(
p_nr5g_fapi_phy_instance_t p_phy_instance,
PBCHPDUStruct p_bch_pdu,
PCSIRSPDUStruct pCSIRSPdu);
// UL_TTI.req
-uint8_t nr5g_fapi_calc_n_rbg_size(
+uint32_t nr5g_fapi_calc_pusch_rbg_index(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint16_t bwp_start,
uint16_t bwp_size);
-uint32_t nr5g_fapi_calc_n_rbg_index_entry(
- uint8_t n_rbg_size,
- fapi_ul_pusch_pdu_t * p_pusch_pdu);
-
void nr5g_fapi_pusch_data_to_phy_ulsch_translation(
nr5g_fapi_pusch_info_t * p_pusch_info,
fapi_pusch_data_t * p_pusch_data,
fapi_vendor_msg_t * p_fapi_vendor_msg,
PTXRequestStruct p_phy_req);
+#ifdef __cplusplus
+}
+#endif
+
#endif //_NR5G_FAPI_FAP2PHY_P7_PVT_PROC_H_
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include <rte_memcpy.h>
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_dpdk.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
p_stats->iapi_stats.iapi_dl_tti_pdcch_pdus++;
}
+static uint32_t get_rbg_index_mask_from_MSB(uint32_t nth_bit) {
+ #define DLSCH_RBG_INDEX_MSB 0x80000000u
+ return DLSCH_RBG_INDEX_MSB >> nth_bit;
+}
+
+/** @ingroup group_source_api_p7_fapi2phy_proc
+ *
+ * @param[in] rb_bitmap Pointer to FAPI DL resource block bitmap.
+ * @param[in] rbg_size Size of resource block group.
+ *
+ * @return Returns IAPI nRBGIndex
+ *
+ * @description
+ * Maps rbBitmap into nRBGIndex bits for pdsch.
+ *
+**/
+uint32_t nr5g_fapi_calc_pdsch_rbg_index(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint16_t bwp_start,
+ uint16_t bwp_size
+ )
+{
+ return nr5g_fapi_calc_rbg_index(
+ rb_bitmap, bwp_start, bwp_size, get_rbg_index_mask_from_MSB);
+}
+
/** @ingroup group_nr5g_test_config
*
* @param[in] p_pdsch_pdu
fapi_dl_pdsch_pdu_t * p_pdsch_pdu,
PDLSCHPDUStruct p_dlsch_pdu)
{
- uint8_t idx, port_index = 0;
+ uint8_t resource_alloc_type, idx, port_index = 0u;
nr5g_fapi_stats_t *p_stats;
+ uint16_t bwp_start, bwp_size;
p_stats = &p_phy_instance->stats;
p_stats->fapi_stats.fapi_dl_tti_pdsch_pdus++;
- p_dlsch_pdu->nBWPSize = p_pdsch_pdu->bwpSize;
- p_dlsch_pdu->nBWPStart = p_pdsch_pdu->bwpStart;
+ bwp_size = p_dlsch_pdu->nBWPSize = p_pdsch_pdu->bwpSize;
+ bwp_start = p_dlsch_pdu->nBWPStart = p_pdsch_pdu->bwpStart;
p_dlsch_pdu->nSubcSpacing = p_pdsch_pdu->subCarrierSpacing;
p_dlsch_pdu->nCpType = p_pdsch_pdu->cyclicPrefix;
p_dlsch_pdu->nRNTI = p_pdsch_pdu->rnti;
}
// Resource Allocation Information
- if (FAILURE == NR5G_FAPI_MEMCPY(p_dlsch_pdu->nRBGIndex,
- sizeof(uint32_t) * MAX_DL_RBG_BIT_NUM,
- p_pdsch_pdu->rbBitmap, sizeof(uint32_t) * MAX_DL_RBG_BIT_NUM)) {
- NR5G_FAPI_LOG(ERROR_LOG, ("PDSCH: RNTI: %d Pdu Index: %d -- RB Bitmap"
- "cpy error.", p_pdsch_pdu->rnti, p_pdsch_pdu->pdu_index));
- }
+ resource_alloc_type =
p_dlsch_pdu->nResourceAllocType = p_pdsch_pdu->resourceAlloc;
+ if(FAPI_DL_RESOURCE_ALLOC_TYPE_0 == resource_alloc_type) {
+ p_dlsch_pdu->nRBGSize = nr5g_fapi_calc_n_rbg_size(bwp_size);
+ p_dlsch_pdu->nRBGIndex = nr5g_fapi_calc_pdsch_rbg_index(
+ p_pdsch_pdu->rbBitmap, bwp_start, bwp_size);
+ }
+
p_dlsch_pdu->nRBStart = p_pdsch_pdu->rbStart;
p_dlsch_pdu->nRBSize = p_pdsch_pdu->rbSize;
p_dlsch_pdu->nPMI = (p_pdsch_pdu->preCodingAndBeamforming.numPrgs > 0)
**/
uint16_t nr5g_fapi_calculate_nEpreRatioOfPDSCHToSSB(uint8_t power_control_offset)
{
- static const uint8_t MAPPING_SIZE = 24;
+ #define MAPPING_SIZE 24U
+
static const uint16_t power_control_offset_to_epre_ratio[MAPPING_SIZE] = {
// 0 1 2 3 4 5 6 7
1, 1, 1, 1000, 2000, 3000, 4000, 5000,
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2021 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+#include "nr5g_fapi_framework.h"
+#include "nr5g_fapi_fapi2phy_p7_pvt_proc.h"
+
+#define FAPI_EMPTY_RB_BITMAP_MASK (0u)
+#define FAPI_EMPTY_RBG_INDEX (0u)
+#define FAPI_MAX_RB_BIT_NUM (273u)
+
+static uint16_t nr5g_fapi_rb_bitmap_mask(
+ uint8_t rbg_size)
+{
+ switch (rbg_size) {
+ case 2:
+ return 0x3u;
+ case 4:
+ return 0xFu;
+ case 8:
+ return 0xFFu;
+ case 16:
+ return 0xFFFFu;
+ default:
+ return FAPI_EMPTY_RB_BITMAP_MASK;
+ }
+}
+
+uint16_t nr5g_fapi_get_rb_bits_for_rbg(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint32_t nth_rbg_bit,
+ uint8_t rbg_size,
+ uint16_t rb_bitmap_mask)
+{
+ uint16_t rb_bits = 0u;
+ const uint16_t rb_bits_bit_size = sizeof(rb_bits) * CHAR_BIT;
+ const uint16_t nth_rb_bit = nth_rbg_bit * rbg_size;
+ const uint32_t rb_byte_1 = ( nth_rb_bit / rb_bits_bit_size ) * sizeof(rb_bits);
+ const uint32_t rb_byte_2 = rb_byte_1 + 1u;
+ if (rb_byte_1 < FAPI_RB_BITMAP_SIZE)
+ {
+ rb_bits |= rb_bitmap[rb_byte_1];
+ }
+ if (rb_byte_2 < FAPI_RB_BITMAP_SIZE)
+ {
+ rb_bits |= (rb_bitmap[rb_byte_2] << CHAR_BIT);
+ }
+ const uint32_t local_rbg_idx = nth_rb_bit % rb_bits_bit_size;
+ return (rb_bits >> local_rbg_idx) & rb_bitmap_mask;
+}
+
+static bool nr5g_fapi_has_rbg_bits_in_rb_bitmap(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ const uint16_t rbg_bit,
+ const uint8_t rbg_size,
+ const uint16_t rb_bitmap_mask)
+{
+ const uint16_t rb_bits_for_rbg = nr5g_fapi_get_rb_bits_for_rbg(
+ rb_bitmap, rbg_bit, rbg_size, rb_bitmap_mask);
+ if (rb_bitmap_mask == rb_bits_for_rbg)
+ {
+ return true;
+ }
+ else if (FAPI_EMPTY_RB_BITMAP_MASK != rb_bits_for_rbg)
+ {
+ NR5G_FAPI_LOG(ERROR_LOG, ("rb_bits don not match rb_bitmap_mask."
+ " rbg_size %u rbg_bit=%u rb_bits_for_rbg=%#X rb_bitmap_mask=%#X",
+ rbg_size, rbg_bit, rb_bits_for_rbg, rb_bitmap_mask));
+ }
+ return false;
+}
+
+/** @ingroup group_source_api_p7_fapi2phy_proc
+ *
+ * @param[in] rb_bitmap Pointer to FAPI DL resource block bitmap.
+ * @param[in] bwp_start Value of bandwidth partition start.
+ * @param[in] bwp_size Value of bandwidth partition size.
+ * @param[in] rbg_size Value of resource block group size.
+ * @param[in] get_rbg_index_mask Function placing bit in rbgIndex (bit order).
+ *
+ * @return Returns IAPI nRBGIndex
+ *
+ * @description
+ * See TS 138 214 5.1.2.2.1/6.1.2.2.1 for more info.
+ * IAPI uses bit per Resource Block Group,
+ * FAPI uses bit per Virtual Resource Block.
+ * Therefore 1 nRBGIndex bit (IAPI), maps to nRBGSize bits (FAPI)
+ * Bitmaps mappings representation:
+ * IAPI: nRBGIndex = RBG-0................RBG-17 (for PDSCH MSB to LSB,
+ * for PUSCH LSB to MSB)
+ * FAPI RB-0...RB-272:
+ * FAPI rbBitmap[i] = RB-(7+i*8)...........RB-(0+i*8) (MSB to LSB)
+ *
+**/
+uint32_t nr5g_fapi_calc_rbg_index(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint16_t bwp_start,
+ uint16_t bwp_size,
+ uint32_t(*get_rbg_index_mask)(uint32_t nth_bit))
+{
+ const uint8_t rbg_size = nr5g_fapi_calc_n_rbg_size(bwp_size);
+ const uint16_t rb_bitmap_mask = nr5g_fapi_rb_bitmap_mask(rbg_size);
+ if (FAPI_EMPTY_RB_BITMAP_MASK == rb_bitmap_mask)
+ {
+ NR5G_FAPI_LOG(ERROR_LOG, ("Wrong rbg_size=%u. rbg_index set to 0.",
+ rbg_size));
+ return FAPI_EMPTY_RBG_INDEX;
+ }
+ if (bwp_start >= FAPI_MAX_RB_BIT_NUM)
+ {
+ NR5G_FAPI_LOG(ERROR_LOG, ("Wrong bwp_start=%u. rbg_index set to 0.",
+ bwp_start));
+ return FAPI_EMPTY_RBG_INDEX;
+ }
+
+ const uint16_t rbg_bit_begin = bwp_start / rbg_size;
+ const uint16_t rb_bit_end = fmin(FAPI_MAX_RB_BIT_NUM, bwp_start + bwp_size);
+ const uint16_t rbg_bit_last = ceil((double)rb_bit_end / rbg_size) - 1u;
+
+ const uint16_t start_offset = bwp_start % rbg_size;
+ uint16_t rb_bitmap_mask_1st_rbg =
+ rb_bitmap_mask & (rb_bitmap_mask << start_offset);
+ const uint16_t last_rbg_size =
+ (0u == rb_bit_end % rbg_size) ? rbg_size : rb_bit_end % rbg_size;
+ const uint16_t end_offset = rbg_size - last_rbg_size;
+ uint16_t rb_bitmap_mask_last_rbg = rb_bitmap_mask >> end_offset;
+ if (rbg_bit_begin == rbg_bit_last)
+ {
+ const uint16_t mask = rb_bitmap_mask_1st_rbg & rb_bitmap_mask_last_rbg;
+ rb_bitmap_mask_1st_rbg = mask;
+ rb_bitmap_mask_last_rbg = mask;
+ }
+
+ uint32_t result = 0u;
+ // fill 1st rbg
+ if (nr5g_fapi_has_rbg_bits_in_rb_bitmap(
+ rb_bitmap, rbg_bit_begin, rbg_size, rb_bitmap_mask_1st_rbg))
+ {
+ result |= get_rbg_index_mask(rbg_bit_begin);
+ }
+ // fill last rbg
+ if (nr5g_fapi_has_rbg_bits_in_rb_bitmap(
+ rb_bitmap, rbg_bit_last, rbg_size, rb_bitmap_mask_last_rbg))
+ {
+ result |= get_rbg_index_mask(rbg_bit_last);
+ }
+ // fill rest of rbgs
+ uint8_t rbg_bit;
+ for (rbg_bit = rbg_bit_begin + 1u; rbg_bit < rbg_bit_last; rbg_bit++)
+ {
+ if (nr5g_fapi_has_rbg_bits_in_rb_bitmap(
+ rb_bitmap, rbg_bit, rbg_size, rb_bitmap_mask))
+ {
+ result |= get_rbg_index_mask(rbg_bit);
+ }
+ }
+
+ return result;
+}
+
+ /** @ingroup group_source_api_p7_fapi2phy_proc
+ *
+ * @param[in] bwp_size Variable holding the Bandwidth part size.
+ *
+ * @return Returns ::RBG Size.
+ *
+ * @description
+ * This functions calculates and return RBG Size from Bandwidth part size
+ * provided.
+ *
+**/
+uint8_t nr5g_fapi_calc_n_rbg_size(
+ uint16_t bwp_size)
+{
+ uint8_t n_rbg_size = 0;
+ if (bwp_size >= 1 && bwp_size <= 36) {
+ n_rbg_size = 2;
+ } else if (bwp_size >= 37 && bwp_size <= 72) {
+ n_rbg_size = 4;
+ } else if (bwp_size >= 73 && bwp_size <= 144) {
+ n_rbg_size = 8;
+ } else if (bwp_size >= 145 && bwp_size <= 275) {
+ n_rbg_size = 16;
+ } else {
+ n_rbg_size = 0;
+ }
+ return n_rbg_size;
+}
\ No newline at end of file
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p7_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p7_proc.h"
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
**/
#include "nr5g_fapi_framework.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p7_proc.h"
return SUCCESS;
}
- /** @ingroup group_source_api_p7_fapi2phy_proc
- *
- * @param[in] bwp_size Variable holding the Bandwidth part size.
- *
- * @return Returns ::RBG Size.
- *
- * @description
- * This functions calculates and return RBG Size from Bandwidth part size provided.
- *
-**/
-uint8_t nr5g_fapi_calc_n_rbg_size(
- uint16_t bwp_size)
-{
- uint8_t n_rbg_size = 0;
- if (bwp_size >= 1 && bwp_size <= 36) {
- n_rbg_size = 2;
- } else if (bwp_size >= 37 && bwp_size <= 72) {
- n_rbg_size = 4;
- } else if (bwp_size >= 73 && bwp_size <= 144) {
- n_rbg_size = 8;
- } else if (bwp_size >= 145 && bwp_size <= 275) {
- n_rbg_size = 16;
- } else {
- n_rbg_size = 0;
- }
- return n_rbg_size;
+static uint32_t get_rbg_index_mask_from_LSB(uint32_t nth_bit) {
+ #define ULSCH_RBG_INDEX_LSB 0x1u
+ return ULSCH_RBG_INDEX_LSB << nth_bit;
}
/** @ingroup group_source_api_p7_fapi2phy_proc
*
- * @param[in] n_rbg_size Variable holding the RBG Size
- * @param[in] p_push_pdu Pointer to FAPI PUSCH Pdu
+ * @param[in] rb_bitmap Pointer to FAPI DL resource block bitmap.
+ * @param[in] rbg_size Size of resource block group.
*
- * @return Returns ::RBG Bitmap entry
+ * @return Returns IAPI nRBGIndex
*
* @description
- * This functions derives the RBG Bitmap entry for PUSCH Type-0 allocation.
+ * Maps rbBitmap into nRBGIndex bits for pusch.
*
**/
-uint32_t nr5g_fapi_calc_n_rbg_index_entry(
- uint8_t n_rbg_size,
- fapi_ul_pusch_pdu_t * p_pusch_pdu)
+uint32_t nr5g_fapi_calc_pusch_rbg_index(
+ const uint8_t rb_bitmap[FAPI_RB_BITMAP_SIZE],
+ uint16_t bwp_start,
+ uint16_t bwp_size
+ )
{
- uint8_t i, temp, num_bits = 0;
- uint32_t n_rbg_bitmap = 0;
- uint8_t rb_bitmap_entries, rb_bitmap;
-
- rb_bitmap_entries = ceil(n_rbg_size / 8);
- for (i = 0; i < rb_bitmap_entries; i++) {
- num_bits = 0;
- temp = 0;
- rb_bitmap = p_pusch_pdu->rbBitmap[i];
- while (num_bits < 8) {
- if (rb_bitmap & (1 << num_bits)) {
- temp |= (1 << (7 - num_bits));
- }
- num_bits++;
- }
- n_rbg_bitmap |= ((n_rbg_bitmap | temp) << (32 - (8 * (i + 1))));
- }
- return n_rbg_bitmap;
+ return nr5g_fapi_calc_rbg_index(
+ rb_bitmap, bwp_start, bwp_size, get_rbg_index_mask_from_LSB);
}
/** @ingroup group_source_api_p7_fapi2phy_proc
}
p_ul_data_chan->nTPPuschID = p_pusch_pdu->nTpPuschId;
p_ul_data_chan->nTpPi2BPSK = p_pusch_pdu->tpPi2Bpsk;
+
+ // Resource Allocation Information
+ p_ul_data_chan->nResourceAllocType = p_pusch_pdu->resourceAlloc;
+ if(FAPI_UL_RESOURCE_ALLOC_TYPE_0 == p_pusch_pdu->resourceAlloc) {
+ // TODO HS check correctness of supporting only config1
//Config-1 alone is supported
- n_rbg_size = p_ul_data_chan->nRBGSize = nr5g_fapi_calc_n_rbg_size(bwp_size);
+ n_rbg_size = p_ul_data_chan->nRBGSize =
+ nr5g_fapi_calc_n_rbg_size(bwp_size);
if (n_rbg_size > 0) {
p_ul_data_chan->nNrOfRBGs =
ceil((bwp_size + (bwp_start % n_rbg_size)) / n_rbg_size);
}
- //First entry would be sufficient as maximum no of RBG's is at max 18.
- p_ul_data_chan->nRBGIndex[0] =
- nr5g_fapi_calc_n_rbg_index_entry(n_rbg_size, p_pusch_pdu);
+ p_ul_data_chan->nRBGIndex = nr5g_fapi_calc_pusch_rbg_index(
+ p_pusch_pdu->rbBitmap, bwp_start, bwp_size);
+ }
p_ul_data_chan->nRBStart = p_pusch_pdu->rbStart;
p_ul_data_chan->nRBSize = p_pusch_pdu->rbSize;
p_ul_data_chan->nVRBtoPRB = p_pusch_pdu->vrbToPrbMapping;
- p_ul_data_chan->nResourceAllocType = p_pusch_pdu->resourceAlloc;
p_ul_data_chan->nStartSymbolIndex = p_pusch_pdu->startSymbIndex;
p_ul_data_chan->nNrOfSymbols = p_pusch_pdu->nrOfSymbols;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include "nr5g_fapi_fapi2mac_wls.h"
#include "nr5g_fapi_fapi2phy_wls.h"
#include "nr5g_fapi_fapi2phy_api.h"
-#include "gnb_l1_l2_api.h"
#include "rte_memzone.h"
#include "nr5g_fapi_memory.h"
}
}
#else
- pthread_join(p_cfg->mac2phy_thread_info.thread_id, NULL);
- pthread_join(p_cfg->phy2mac_thread_info.thread_id, NULL);
- pthread_join(p_cfg->urllc_thread_info.thread_id, NULL);
+ pthread_join(p_cfg->mac2phy_thread_params.thread_info.thread_id, NULL);
+ pthread_join(p_cfg->phy2mac_thread_params.thread_info.thread_id, NULL);
+ pthread_join(p_cfg->urllc_phy2mac_thread_params.thread_info.thread_id, NULL);
+ pthread_join(p_cfg->urllc_mac2phy_thread_params.thread_info.thread_id, NULL);
#endif
return SUCCESS;
}
return NULL;
}
+uint8_t nr5g_fapi_prepare_thread(
+ nr5g_fapi_thread_params_t* thread_params,
+ char* thread_name,
+ void* thread_fun(void*))
+{
+ struct sched_param param;
+ pthread_attr_t* p_thread_attr = &thread_params->thread_info.thread_attr;
+ pthread_attr_init(p_thread_attr);
+ if (!pthread_attr_getschedparam(p_thread_attr, ¶m)) {
+ param.sched_priority = thread_params->thread_worker.thread_priority;
+ pthread_attr_setschedparam(p_thread_attr, ¶m);
+ pthread_attr_setschedpolicy(p_thread_attr, SCHED_FIFO);
+ }
+
+ if (0 != pthread_create(&thread_params->thread_info.thread_id,
+ p_thread_attr, thread_fun, (void *)
+ nr5g_fapi_get_nr5g_fapi_phy_ctx())) {
+ printf("Error: Unable to create threads\n");
+ if (p_thread_attr)
+ pthread_attr_destroy(p_thread_attr);
+ return FAILURE;
+ }
+ pthread_setname_np(thread_params->thread_info.thread_id,
+ thread_name);
+
+ return SUCCESS;
+}
+
+uint8_t nr5g_fapi_initialise_sempahore(
+ nr5g_fapi_urllc_thread_params_t* urllc_thread_params)
+{
+ memset(&urllc_thread_params->urllc_sem_process, 0, sizeof(sem_t));
+ memset(&urllc_thread_params->urllc_sem_done, 0, sizeof(sem_t));
+
+ pthread_mutex_init(&urllc_thread_params->lock, NULL);
+ urllc_thread_params->p_urllc_list_elem = NULL;
+ if (0 != sem_init(&urllc_thread_params->urllc_sem_process, 0, 0)) {
+ printf("Error: Unable to init urllc_sem_process semaphore\n");
+ return FAILURE;
+ }
+ if (0 != sem_init(&urllc_thread_params->urllc_sem_done, 0, 1)) {
+ printf("Error: Unable to init urllc_sem_done semaphore\n");
+ return FAILURE;
+ }
+
+ return SUCCESS;
+}
+
+void nr5g_fapi_init_thread(uint8_t worker_core_id)
+{
+ cpu_set_t cpuset;
+ pthread_t thread = pthread_self();
+
+ CPU_ZERO(&cpuset);
+ CPU_SET(worker_core_id, &cpuset);
+ pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset);
+
+ usleep(1000);
+}
+
+void nr5g_fapi_urllc_thread_callback(
+ void *p_list_elem,
+ nr5g_fapi_urllc_thread_params_t* urllc_params)
+{
+ if (nr5g_fapi_get_nr5g_fapi_phy_ctx()->is_urllc_enabled){
+ sem_wait(&urllc_params->urllc_sem_done);
+ pthread_mutex_lock(&urllc_params->lock);
+ urllc_params->p_urllc_list_elem = p_list_elem;
+ pthread_mutex_unlock(&urllc_params->lock);
+ sem_post(&urllc_params->urllc_sem_process);
+ }
+ else {
+ NR5G_FAPI_LOG(ERROR_LOG, ("[URLLC] Threads are not running"));
+ }
+}
+
uint8_t nr5g_fapi_framework_init(
p_nr5g_fapi_cfg_t p_cfg)
{
p_nr5g_fapi_phy_ctx_t p_phy_ctx = nr5g_fapi_get_nr5g_fapi_phy_ctx();
- pthread_attr_t *p_mac2phy_attr, *p_phy2mac_attr, *p_urllc_attr;
- struct sched_param param;
nr5g_fapi_set_log_level(p_cfg->logger.level);
// Set up WLS
}
NR5G_FAPI_LOG(INFO_LOG, ("[FAPI_INT] WLS init Successful"));
- p_phy_ctx->phy2mac_worker_core_id = p_cfg->phy2mac_worker.core_id;
- p_phy_ctx->mac2phy_worker_core_id = p_cfg->mac2phy_worker.core_id;
- p_phy_ctx->urllc_worker_core_id = p_cfg->urllc_worker.core_id;
+ p_phy_ctx->phy2mac_worker_core_id = p_cfg->phy2mac_thread_params.thread_worker.core_id;
+ p_phy_ctx->mac2phy_worker_core_id = p_cfg->mac2phy_thread_params.thread_worker.core_id;
+ p_phy_ctx->urllc_phy2mac_worker_core_id = p_cfg->urllc_phy2mac_thread_params.thread_worker.core_id;
+ p_phy_ctx->urllc_mac2phy_worker_core_id = p_cfg->urllc_mac2phy_thread_params.thread_worker.core_id;
+ p_phy_ctx->is_urllc_enabled = p_cfg->is_urllc_enabled;
- memset(&p_phy_ctx->urllc_sem_process, 0, sizeof(sem_t));
- memset(&p_phy_ctx->urllc_sem_done, 0, sizeof(sem_t));
- if (0 != sem_init(&p_phy_ctx->urllc_sem_process, 0, 0)) {
- printf("Error: Unable to init urllc semaphore\n");
- return FAILURE;
- }
- if (0 != sem_init(&p_phy_ctx->urllc_sem_done, 0, 1)) {
- printf("Error: Unable to init urllc_sem_done semaphore\n");
+ if (nr5g_fapi_prepare_thread(&p_cfg->phy2mac_thread_params,
+ "nr5g_fapi_phy2mac_thread",
+ nr5g_fapi_phy2mac_thread_func) == FAILURE) {
return FAILURE;
}
- p_phy2mac_attr = &p_cfg->phy2mac_thread_info.thread_attr;
- pthread_attr_init(p_phy2mac_attr);
- if (!pthread_attr_getschedparam(p_phy2mac_attr, ¶m)) {
- param.sched_priority = p_cfg->phy2mac_worker.thread_priority;
- pthread_attr_setschedparam(p_phy2mac_attr, ¶m);
- pthread_attr_setschedpolicy(p_phy2mac_attr, SCHED_FIFO);
- }
- if (0 != pthread_create(&p_cfg->phy2mac_thread_info.thread_id,
- p_phy2mac_attr, nr5g_fapi_phy2mac_thread_func, (void *)
- p_phy_ctx)) {
- printf("Error: Unable to create threads\n");
- if (p_phy2mac_attr)
- pthread_attr_destroy(p_phy2mac_attr);
+ if (nr5g_fapi_prepare_thread(&p_cfg->mac2phy_thread_params,
+ "nr5g_fapi_mac2phy_thread",
+ nr5g_fapi_mac2phy_thread_func) == FAILURE) {
return FAILURE;
}
- pthread_setname_np(p_cfg->phy2mac_thread_info.thread_id,
- "nr5g_fapi_phy2mac_thread");
- p_mac2phy_attr = &p_cfg->mac2phy_thread_info.thread_attr;
- pthread_attr_init(p_mac2phy_attr);
- if (!pthread_attr_getschedparam(p_mac2phy_attr, ¶m)) {
- param.sched_priority = p_cfg->mac2phy_worker.thread_priority;
- pthread_attr_setschedparam(p_mac2phy_attr, ¶m);
- pthread_attr_setschedpolicy(p_mac2phy_attr, SCHED_FIFO);
+ if (p_cfg->is_urllc_enabled)
+ {
+ if (nr5g_fapi_initialise_sempahore(&p_phy_ctx->urllc_phy2mac_params) == FAILURE) {
+ return FAILURE;
}
- if (0 != pthread_create(&p_cfg->mac2phy_thread_info.thread_id,
- p_mac2phy_attr, nr5g_fapi_mac2phy_thread_func, (void *)
- p_phy_ctx)) {
- printf("Error: Unable to create threads\n");
- if (p_mac2phy_attr)
- pthread_attr_destroy(p_mac2phy_attr);
+ if (nr5g_fapi_initialise_sempahore(&p_phy_ctx->urllc_mac2phy_params) == FAILURE) {
return FAILURE;
}
- pthread_setname_np(p_cfg->mac2phy_thread_info.thread_id,
- "nr5g_fapi_mac2phy_thread");
- p_urllc_attr = &p_cfg->urllc_thread_info.thread_attr;
- pthread_attr_init(p_urllc_attr);
- if (!pthread_attr_getschedparam(p_urllc_attr, ¶m)) {
- param.sched_priority = p_cfg->urllc_worker.thread_sched_policy;
- pthread_attr_setschedparam(p_urllc_attr, ¶m);
- pthread_attr_setschedpolicy(p_urllc_attr, SCHED_FIFO);
+ if (nr5g_fapi_prepare_thread(&p_cfg->urllc_mac2phy_thread_params,
+ "nr5g_fapi_urllc_mac2phy_thread",
+ nr5g_fapi_urllc_mac2phy_thread_func) == FAILURE) {
+ return FAILURE;
}
- if (0 != pthread_create(&p_cfg->urllc_thread_info.thread_id,
- p_urllc_attr, nr5g_fapi_urllc_thread_func, (void *)
- p_phy_ctx)) {
- printf("Error: Unable to create threads\n");
- if (p_urllc_attr)
- pthread_attr_destroy(p_urllc_attr);
- sem_destroy(&p_phy_ctx->urllc_sem_process);
- sem_destroy(&p_phy_ctx->urllc_sem_done);
+
+ if (nr5g_fapi_prepare_thread(&p_cfg->urllc_phy2mac_thread_params,
+ "nr5g_fapi_urllc_phy2mac_thread",
+ nr5g_fapi_urllc_phy2mac_thread_func) == FAILURE) {
return FAILURE;
}
- pthread_setname_np(p_cfg->urllc_thread_info.thread_id,
- "nr5g_fapi_urllc_thread");
+ }
return SUCCESS;
}
+
+void nr5g_fapi_clean(
+ p_nr5g_fapi_phy_instance_t p_phy_instance)
+{
+ p_phy_instance->phy_config.n_nr_of_rx_ant = 0;
+ p_phy_instance->phy_config.phy_cell_id = 0;
+ p_phy_instance->phy_config.sub_c_common = 0;
+ p_phy_instance->phy_config.use_vendor_EpreXSSB = 0;
+ p_phy_instance->shutdown_test_type = 0;
+ p_phy_instance->phy_id = 0;
+ p_phy_instance->state = FAPI_STATE_IDLE ;
+
+ memset(p_phy_instance->ul_slot_info, 0, sizeof(nr5g_fapi_ul_slot_info_t));
+ wls_fapi_free_send_free_list_urllc();
+}
\ No newline at end of file
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include "nr5g_fapi_std.h"
#include "nr5g_fapi_common_types.h"
#include "nr5g_fapi_wls.h"
-#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_wls.h"
#include "nr5g_fapi_log.h"
-#include "nr5g_fapi_urllc_thread.h"
+#include "nr5g_fapi_framework.h"
static p_fapi_api_queue_elem_t p_fapi2mac_buffers;
+uint64_t *nr5g_fapi_fapi2mac_wls_get(
+ uint32_t * const msg_size,
+ uint16_t * const msg_type,
+ uint16_t * const flags);
+
+uint8_t nr5g_fapi_fapi2mac_wls_put(
+ const p_fapi_api_queue_elem_t p_msg,
+ uint32_t msg_size,
+ uint16_t msg_type,
+ uint16_t flags);
+
+uint8_t nr5g_fapi_fapi2mac_wls_send(
+ const p_fapi_api_queue_elem_t p_list_elem,
+ bool is_urllc);
+
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_fapi2mac_group
*
* @return 0 if SUCCESS
*
* @description
- * This function is called at WLS init and waits in an infinite for L1 to respond back with some information
+ * This function is called at WLS init and waits infinitely for L1 to respond back with some information
* needed by the L2
*
**/
* @return Number of blocks of APIs received
*
* @description
- * This functions waits in a infinite loop for L1 to send a list of APIs to MAC. This is called
- * during runtime when L2 sends a API to L1 and then waits for response back.
+ * This functions waits in an infinite loop for L1 to send a list of APIs to MAC. This is called
+ * during runtime when L2 sends API to L1 and then waits for a response back.
*
**/
//------------------------------------------------------------------------------
**/
//------------------------------------------------------------------------------
uint64_t *nr5g_fapi_fapi2mac_wls_get(
- uint32_t * msg_size,
- uint16_t * msg_type,
- uint16_t * flags)
+ uint32_t * const msg_size,
+ uint16_t * const msg_type,
+ uint16_t * const flags)
{
uint64_t *data = NULL;
WLS_HANDLE h_wls;
**/
//------------------------------------------------------------------------------
inline uint8_t nr5g_fapi_fapi2mac_wls_put(
- p_fapi_api_queue_elem_t p_msg,
+ const p_fapi_api_queue_elem_t p_msg,
uint32_t msg_size,
uint16_t msg_type,
uint16_t flags)
**/
//------------------------------------------------------------------------------
uint8_t nr5g_fapi_fapi2mac_wls_send(
- p_fapi_api_queue_elem_t p_list_elem,
+ const p_fapi_api_queue_elem_t p_list_elem,
bool is_urllc)
{
uint8_t ret = SUCCESS;
} while (num_elms && is_msg_present(flags));
if (p_urllc_qelm_list) {
- nr5g_fapi_urllc_thread_callback(NR5G_FAPI_URLLC_MSG_DIR_MAC2PHY, (void *) p_urllc_qelm_list);
+ nr5g_fapi_urllc_thread_callback((void *) p_urllc_qelm_list,
+ &nr5g_fapi_get_nr5g_fapi_phy_ctx()->urllc_mac2phy_params);
}
tick_total_wls_get_per_tti_dl += __rdtsc() - start_tick;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_wls_recv(
);
-uint8_t nr5g_fapi_fapi2mac_wls_ready(
- );
uint32_t nr5g_fapi_fapi2mac_wls_wait(
);
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* @defgroup nr5g_fapi_source_framework_wls_fapi2phy_group
**/
+#include "nr5g_mac_phy_api.h"
#include "nr5g_fapi_std.h"
#include "nr5g_fapi_common_types.h"
#include "nr5g_fapi_internal.h"
#include "nr5g_fapi_wls.h"
#include "nr5g_fapi_fapi2phy_wls.h"
#include "nr5g_fapi_log.h"
-#include "nr5g_fapi_urllc_thread.h"
+#include "nr5g_fapi_framework.h"
static uint32_t g_to_free_send_list_cnt[TO_FREE_SIZE] = { 0 };
static uint64_t g_to_free_send_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} };
static uint32_t g_to_free_send_list_cnt_urllc[TO_FREE_SIZE_URLLC] = { 0 };
static uint64_t g_to_free_send_list_urllc[TO_FREE_SIZE_URLLC][TOTAL_FREE_BLOCKS] = { {0L} };
+static uint32_t g_free_recv_idx = 0;
+static uint32_t g_free_send_idx = 0;
+static uint32_t g_free_send_idx_urllc = 0;
+
+uint64_t *nr5g_fapi_fapi2phy_wls_get(
+ uint32_t * const msg_size,
+ uint16_t * const msg_type,
+ uint16_t * const flags);
+
+uint8_t nr5g_fapi_fapi2phy_wls_put(
+ uint64_t p_msg,
+ uint32_t msg_size,
+ uint16_t msg_type,
+ uint16_t flags);
+
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
*
**/
//----------------------------------------------------------------------------------
inline uint64_t *nr5g_fapi_fapi2phy_wls_get(
- uint32_t * msg_size,
- uint16_t * msg_type,
- uint16_t * flags)
+ uint32_t * const msg_size,
+ uint16_t * const msg_type,
+ uint16_t * const flags)
{
uint64_t *data = NULL;
WLS_HANDLE h_wls;
return (!((flags & WLS_TF_FIN) || (flags == 0)));
}
+void nr5g_fapi_transfer_to_free_recv_list (
+ PMAC2PHY_QUEUE_EL p_qelm_list
+ /*uint32_t* free_recv_idx*/)
+{
+ wls_fapi_add_recv_apis_to_free(p_qelm_list, g_free_recv_idx);
+ (g_free_recv_idx)++;
+ if ((g_free_recv_idx) >= TO_FREE_SIZE) {
+ (g_free_recv_idx) = 0;
+ }
+ // Free few TTIs Later
+ wls_fapi_free_recv_free_list(g_free_recv_idx);
+
+ wls_fapi_add_blocks_to_ul();
+}
+
//----------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
*
uint32_t msg_size = 0;
uint32_t num_elms = 0;
uint64_t *p_msg = NULL;
- static uint32_t g_free_recv_idx = 0;
PMAC2PHY_QUEUE_EL p_qelm_list = NULL, p_urllc_qelm_list = NULL;
PMAC2PHY_QUEUE_EL p_qelm = NULL;
PMAC2PHY_QUEUE_EL p_tail_qelm = NULL, p_urllc_tail_qelm = NULL;
} while (num_elms && is_msg_present(flags));
if (p_urllc_qelm_list) {
- wls_fapi_add_recv_apis_to_free(p_urllc_qelm_list, g_free_recv_idx);
- g_free_recv_idx++;
- if (g_free_recv_idx >= TO_FREE_SIZE) {
- g_free_recv_idx = 0;
- }
- // Free 10 TTIs Later
- wls_fapi_free_recv_free_list(g_free_recv_idx);
-
- wls_fapi_add_blocks_to_ul();
- nr5g_fapi_urllc_thread_callback(NR5G_FAPI_URLLC_MSG_DIR_PHY2MAC, (void *) p_urllc_qelm_list);
+ nr5g_fapi_transfer_to_free_recv_list (p_urllc_qelm_list);
+ nr5g_fapi_urllc_thread_callback((void *) p_urllc_qelm_list,
+ &nr5g_fapi_get_nr5g_fapi_phy_ctx()->urllc_phy2mac_params);
}
if (p_qelm_list) {
- wls_fapi_add_recv_apis_to_free(p_qelm_list, g_free_recv_idx);
- g_free_recv_idx++;
- if (g_free_recv_idx >= TO_FREE_SIZE) {
- g_free_recv_idx = 0;
- }
- // Free 10 TTIs Later
- wls_fapi_free_recv_free_list(g_free_recv_idx);
-
- wls_fapi_add_blocks_to_ul();
+ nr5g_fapi_transfer_to_free_recv_list (p_qelm_list);
}
tick_total_wls_get_per_tti_ul += __rdtsc() - start_tick;
uint16_t flags_urllc = (is_urllc ? WLS_TF_URLLC : 0);
uint8_t ret = SUCCESS;
int n_zbc_blocks = 0, is_zbc = 0, count = 0;
- static uint32_t g_free_send_idx = 0;
- static uint32_t g_free_send_idx_urllc = 0;
p_curr_msg = (PMAC2PHY_QUEUE_EL) data;
is_urllc ? wls_fapi_add_send_apis_to_free_urllc(p_curr_msg, g_free_send_idx_urllc)
}
// Free some TTIs Later
- is_urllc ? wls_fapi_free_send_free_list_urllc(g_free_send_idx_urllc)
- : wls_fapi_free_send_free_list(g_free_send_idx);
+ is_urllc ? wls_fapi_free_send_free_list_urllc()
+ : wls_fapi_free_send_free_list();
}
if (pthread_mutex_unlock((pthread_mutex_t *) &
* free array
**/
//------------------------------------------------------------------------------
-void wls_fapi_free_send_free_list(
- uint32_t idx)
+void wls_fapi_free_send_free_list()
{
PMAC2PHY_QUEUE_EL pNextMsg = NULL;
L1L2MessageHdr *p_msg_header = NULL;
int count = 0, loc = 0;
- if (idx >= TO_FREE_SIZE) {
- NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx));
+ if (g_free_send_idx >= TO_FREE_SIZE) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, g_free_send_idx));
return;
}
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[idx][count];
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[g_free_send_idx][count];
while (pNextMsg) {
p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
loc = get_stats_location(p_msg_header->nMessageType);
wls_fapi_free_buffer(pNextMsg, loc);
- g_to_free_send_list[idx][count++] = 0L;
- if (g_to_free_send_list[idx][count])
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[idx][count];
+ g_to_free_send_list[g_free_send_idx][count++] = 0L;
+ if (g_to_free_send_list[g_free_send_idx][count])
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[g_free_send_idx][count];
else
pNextMsg = 0L;
}
NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count));
- g_to_free_send_list_cnt[idx] = 0;
+ g_to_free_send_list_cnt[g_free_send_idx] = 0;
return;
}
* free array. Used by urllc thread.
**/
//------------------------------------------------------------------------------
-void wls_fapi_free_send_free_list_urllc(
- uint32_t idx)
+void wls_fapi_free_send_free_list_urllc()
{
PMAC2PHY_QUEUE_EL pNextMsg = NULL;
L1L2MessageHdr *p_msg_header = NULL;
int count = 0, loc = 0;
- if (idx >= TO_FREE_SIZE_URLLC) {
- NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx));
+ if (g_free_send_idx_urllc >= TO_FREE_SIZE_URLLC) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, g_free_send_idx_urllc));
return;
}
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list_urllc[idx][count];
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list_urllc[g_free_send_idx_urllc][count];
while (pNextMsg) {
p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
loc = get_stats_location(p_msg_header->nMessageType);
wls_fapi_free_buffer(pNextMsg, loc);
- g_to_free_send_list_urllc[idx][count++] = 0L;
- if (g_to_free_send_list_urllc[idx][count])
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list_urllc[idx][count];
+ g_to_free_send_list_urllc[g_free_send_idx_urllc][count++] = 0L;
+ if (g_to_free_send_list_urllc[g_free_send_idx_urllc][count])
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list_urllc[g_free_send_idx_urllc][count];
else
pNextMsg = 0L;
}
NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count));
- g_to_free_send_list_cnt_urllc[idx] = 0;
+ g_to_free_send_list_cnt_urllc[g_free_send_idx_urllc] = 0;
return;
}
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef _NR5G_FAPI2PHY_WLS_H_
#define _NR5G_FAPI2PHY_WLS_H_
-#include "gnb_l1_l2_api.h"
+#include "common_mac_phy_api.h"
uint8_t nr5g_fapi_fapi2phy_is_valid_wls_ptr(
void *data);
bool is_urllc);
PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_wls_recv(
);
-inline uint32_t nr5g_fapi_fapi2phy_wls_wait(
+uint32_t nr5g_fapi_fapi2phy_wls_wait(
);
void wls_fapi_add_send_apis_to_free(
PMAC2PHY_QUEUE_EL pListElem,
uint32_t idx);
-void wls_fapi_free_send_free_list(
- uint32_t idx);
+void wls_fapi_free_send_free_list();
void wls_fapi_add_send_apis_to_free_urllc(
PMAC2PHY_QUEUE_EL pListElem,
uint32_t idx);
-void wls_fapi_free_send_free_list_urllc(
- uint32_t idx);
+void wls_fapi_free_send_free_list_urllc();
void wls_fapi_add_recv_apis_to_free(
PMAC2PHY_QUEUE_EL pListElem,
uint32_t idx);
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
return retval;
}
-//----------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
- *
- * @param void
- *
- * @return 0 if SUCCESS
- *
- * @description
- * This function is called at WLS init and waits in an infinite for L1 to respond back with some information
- * needed by the L2
- *
-**/
-//----------------------------------------------------------------------------------
-inline uint8_t nr5g_fapi_fapi2mac_wls_ready(
- )
-{
- int retval = 0;
- p_nr5g_fapi_wls_context_t p_wls = nr5g_fapi_wls_context();
-
- retval = WLS_Ready1(p_wls->h_wls[NR5G_FAPI2MAC_WLS_INST]);
-
- return retval;
-}
-
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_lib_group
*
uint32_t size)
{
uint8_t *d = ptr;
- int i;
+ uint32_t i;
for (i = 0; i < size; i++) {
if (!(i & 0xf))
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include "nr5g_fapi_std.h"
#include "nr5g_fapi_common_types.h"
#include "wls_lib.h"
-#include "gnb_l1_l2_api.h"
typedef void *WLS_HANDLE;
extern nr5g_fapi_wls_context_t g_wls_ctx;
-inline p_nr5g_fapi_wls_context_t nr5g_fapi_wls_context(
+p_nr5g_fapi_wls_context_t nr5g_fapi_wls_context(
);
-inline uint8_t nr5g_fapi_fapi2phy_wls_ready(
+uint8_t nr5g_fapi_fapi2phy_wls_ready(
);
-inline uint8_t nr5g_fapi_fapi2mac_wls_ready(
+uint8_t nr5g_fapi_fapi2mac_wls_ready(
);
uint8_t nr5g_fapi_wls_init(
);
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
void *nr5g_fapi_mac2phy_thread_func(
void *config)
{
- cpu_set_t cpuset;
- pthread_t thread;
p_fapi_api_queue_elem_t p_msg_list = NULL;
p_nr5g_fapi_phy_ctx_t p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config;
uint64_t start_tick;
"Core: %d\n", __func__, pthread_self(),
p_phy_ctx->mac2phy_worker_core_id));
- thread = p_phy_ctx->mac2phy_tid = pthread_self();
- CPU_ZERO(&cpuset);
- CPU_SET(p_phy_ctx->mac2phy_worker_core_id, &cpuset);
- pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset);
+ nr5g_fapi_init_thread(p_phy_ctx->mac2phy_worker_core_id);
- usleep(1000);
while (!p_phy_ctx->process_exit) {
p_msg_list = nr5g_fapi_fapi2mac_wls_recv();
if (p_msg_list)
break;
/* P5 Message Processing */
+
+ case FAPI_PARAM_REQUEST:
+ {
+ nr5g_fapi_param_response(p_phy_instance);
+ }
+
+ break;
+
case FAPI_CONFIG_REQUEST:
{
nr5g_fapi_config_request(is_urllc, p_phy_instance,
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
void *nr5g_fapi_phy2mac_thread_func(
void *config)
{
- cpu_set_t cpuset;
- pthread_t thread;
PMAC2PHY_QUEUE_EL p_msg_list = NULL;
p_nr5g_fapi_phy_ctx_t p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config;
"Core: %d\n", __func__, pthread_self(),
p_phy_ctx->phy2mac_worker_core_id));
- thread = p_phy_ctx->phy2mac_tid = pthread_self();
- CPU_ZERO(&cpuset);
- CPU_SET(p_phy_ctx->phy2mac_worker_core_id, &cpuset);
- pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset);
+ nr5g_fapi_init_thread(p_phy_ctx->phy2mac_worker_core_id);
nr5g_fapi_fapi2mac_init_api_list();
- usleep(1000);
while (!p_phy_ctx->process_exit) {
p_msg_list = nr5g_fapi_fapi2phy_wls_recv();
if (p_msg_list)
case MSG_TYPE_PHY_DL_IQ_SAMPLES:
{
nr5g_fapi_dl_iq_samples_response((p_nr5g_fapi_phy_ctx_t)
- config, (PADD_REMOVE_BBU_CORES) p_msg_header);
+ config, (PADD_REMOVE_BBU_CORES_NR5G) p_msg_header);
}
break;
case MSG_TYPE_PHY_UL_IQ_SAMPLES:
{
nr5g_fapi_ul_iq_samples_response((p_nr5g_fapi_phy_ctx_t)
- config, (PADD_REMOVE_BBU_CORES) p_msg_header);
+ config, (PADD_REMOVE_BBU_CORES_NR5G) p_msg_header);
}
break;
#endif
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#ifndef _NR5G_FAPI_PHY2MAC_THREAD_H_
#define _NR5G_FAPI_PHY2MAC_THREAD_H_
-#include "gnb_l1_l2_api.h"
+#include "common_mac_phy_api.h"
void nr5g_fapi_phy2mac_api_recv_handler(
bool is_urllc,
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2022 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+#include "nr5g_fapi_std.h"
+#include "nr5g_fapi_framework.h"
+#include "nr5g_fapi_phy2mac_thread.h"
+#include "nr5g_fapi_mac2phy_thread.h"
+#include "nr5g_fapi_fapi2mac_api.h"
+#include "nr5g_fapi_fapi2phy_api.h"
+
+void *nr5g_fapi_urllc_mac2phy_thread_func(
+ void *config)
+{
+ p_nr5g_fapi_phy_ctx_t p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config;
+ uint64_t start_tick;
+
+ NR5G_FAPI_LOG(INFO_LOG, ("[URLLC_MAC2PHY] Thread %s launched LWP:%ld on "
+ "Core: %d\n", __func__, pthread_self(),
+ p_phy_ctx->urllc_mac2phy_worker_core_id));
+
+ nr5g_fapi_init_thread(p_phy_ctx->urllc_mac2phy_worker_core_id);
+
+ while (!p_phy_ctx->process_exit) {
+ sem_wait(&p_phy_ctx->urllc_mac2phy_params.urllc_sem_process);
+ pthread_mutex_lock(&p_phy_ctx->urllc_mac2phy_params.lock);
+ if (p_phy_ctx->urllc_mac2phy_params.p_urllc_list_elem)
+ {
+ nr5g_fapi_mac2phy_api_recv_handler(true, config,
+ (p_fapi_api_queue_elem_t) p_phy_ctx->urllc_mac2phy_params.
+ p_urllc_list_elem);
+ start_tick = __rdtsc();
+ NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Send to PHY urllc.."));
+ nr5g_fapi_fapi2phy_send_api_list(true);
+ tick_total_wls_send_per_tti_dl += __rdtsc() - start_tick;
+
+ p_phy_ctx->urllc_mac2phy_params.p_urllc_list_elem = NULL;
+ }
+ pthread_mutex_unlock(&p_phy_ctx->urllc_mac2phy_params.lock);
+ sem_post(&p_phy_ctx->urllc_mac2phy_params.urllc_sem_done);
+ }
+
+ pthread_exit(NULL);
+}
\ No newline at end of file
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2022 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+#include "nr5g_fapi_std.h"
+#include "nr5g_fapi_framework.h"
+#include "nr5g_fapi_phy2mac_thread.h"
+#include "nr5g_fapi_mac2phy_thread.h"
+#include "nr5g_fapi_fapi2mac_api.h"
+#include "nr5g_fapi_fapi2phy_api.h"
+
+void *nr5g_fapi_urllc_phy2mac_thread_func(
+ void *config)
+{
+ p_nr5g_fapi_phy_ctx_t p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config;
+
+ NR5G_FAPI_LOG(INFO_LOG, ("[URLLC_PHY2MAC] Thread %s launched LWP:%ld on "
+ "Core: %d\n", __func__, pthread_self(),
+ p_phy_ctx->urllc_phy2mac_worker_core_id));
+
+ nr5g_fapi_init_thread(p_phy_ctx->urllc_phy2mac_worker_core_id);
+
+ while (!p_phy_ctx->process_exit) {
+ sem_wait(&p_phy_ctx->urllc_phy2mac_params.urllc_sem_process);
+ pthread_mutex_lock(&p_phy_ctx->urllc_phy2mac_params.lock);
+ if (p_phy_ctx->urllc_phy2mac_params.p_urllc_list_elem)
+ {
+ nr5g_fapi_phy2mac_api_recv_handler(true, config,
+ (PMAC2PHY_QUEUE_EL) p_phy_ctx->urllc_phy2mac_params.
+ p_urllc_list_elem);
+ nr5g_fapi_fapi2mac_send_api_list(true);
+
+ p_phy_ctx->urllc_phy2mac_params.p_urllc_list_elem = NULL;
+ }
+ pthread_mutex_unlock(&p_phy_ctx->urllc_phy2mac_params.lock);
+ sem_post(&p_phy_ctx->urllc_phy2mac_params.urllc_sem_done);
+ }
+
+ pthread_exit(NULL);
+}
\ No newline at end of file
void *p_list_elem)
{
p_nr5g_fapi_phy_ctx_t p_phy_ctx = nr5g_fapi_get_nr5g_fapi_phy_ctx();
+ if(0u != p_phy_ctx->urllc_tid)
+ {
sem_wait(&p_phy_ctx->urllc_sem_done);
pthread_mutex_lock(&lock);
p_urllc_list_elem = p_list_elem;
pthread_mutex_unlock(&lock);
sem_post(&p_phy_ctx->urllc_sem_process);
}
+ else
+ {
+ NR5G_FAPI_LOG(ERROR_LOG, ("[URLLC] Thread is not running"));
+ }
+}
void *nr5g_fapi_urllc_thread_func(
void *config)
{
switch (urllc_msg_dir) {
case NR5G_FAPI_URLLC_MSG_DIR_MAC2PHY:
- nr5g_fapi_mac2phy_api_recv_handler(true, config, (p_fapi_api_queue_elem_t) p_urllc_list_elem);
+ nr5g_fapi_mac2phy_api_recv_handler(true, config,
+ (p_fapi_api_queue_elem_t) p_urllc_list_elem);
start_tick = __rdtsc();
- NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Send to PHY urllc.."));
+ NR5G_FAPI_LOG(TRACE_LOG,
+ ("[MAC2PHY] Send to PHY urllc.."));
nr5g_fapi_fapi2phy_send_api_list(true);
tick_total_wls_send_per_tti_dl += __rdtsc() - start_tick;
break;
case NR5G_FAPI_URLLC_MSG_DIR_PHY2MAC:
- nr5g_fapi_phy2mac_api_recv_handler(true, config, (PMAC2PHY_QUEUE_EL) p_urllc_list_elem);
+ nr5g_fapi_phy2mac_api_recv_handler(true, config,
+ (PMAC2PHY_QUEUE_EL) p_urllc_list_elem);
nr5g_fapi_fapi2mac_send_api_list(true);
break;
default:
- NR5G_FAPI_LOG(ERROR_LOG, ("[URLLC]: Invalid URLLC message direction.\n"));
+ NR5G_FAPI_LOG(ERROR_LOG,
+ ("[URLLC]: Invalid URLLC message direction.\n"));
break;
}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (c) 2021 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-#ifndef _NR5G_FAPI_URLLC_THREAD_H_
-#define _NR5G_FAPI_URLLC_THREAD_H_
-
-#include "gnb_l1_l2_api.h"
-
-typedef enum nr5g_fapi_urllc_msg_dir_e {
- NR5G_FAPI_URLLC_MSG_DIR_MAC2PHY = 0,
- NR5G_FAPI_URLLC_MSG_DIR_PHY2MAC,
- NR5G_FAPI_URLLC_MSG_DIR_LAST
-} nr5g_fapi_urllc_msg_dir_t;
-
-void nr5g_fapi_urllc_thread_callback(
- nr5g_fapi_urllc_msg_dir_t msg_dir,
- void *p_list_elem);
-
-#endif
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
nr5g_fapi_log_types_t level;
} nr5g_fapi_config_log_cfg_t;
+typedef struct _nr5g_fapi_thread_params_t {
+ nr5g_fapi_config_worker_cfg_t thread_worker;
+ nr5g_fapi_thread_info_t thread_info;
+} nr5g_fapi_thread_params_t;
+
typedef struct _nr5g_fapi_cfg {
char *prgname;
- nr5g_fapi_config_worker_cfg_t mac2phy_worker;
- nr5g_fapi_config_worker_cfg_t phy2mac_worker;
- nr5g_fapi_config_worker_cfg_t urllc_worker;
+ nr5g_fapi_thread_params_t mac2phy_thread_params;
+ nr5g_fapi_thread_params_t phy2mac_thread_params;
+ nr5g_fapi_thread_params_t urllc_mac2phy_thread_params;
+ nr5g_fapi_thread_params_t urllc_phy2mac_thread_params;
+ bool is_urllc_enabled;
nr5g_fapi_config_wls_cfg_t wls;
nr5g_fapi_config_log_cfg_t logger;
- nr5g_fapi_thread_info_t mac2phy_thread_info;
- nr5g_fapi_thread_info_t phy2mac_thread_info;
- nr5g_fapi_thread_info_t urllc_thread_info;
nr5g_fapi_config_dpdk_cft_t dpdk;
} nr5g_fapi_cfg_t,
*p_nr5g_fapi_cfg_t;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
} nr5g_fapi_phy_instance_t,
*p_nr5g_fapi_phy_instance_t;
+typedef struct _nr5g_fapi_urllc_thread_params_t {
+ void *p_urllc_list_elem;
+ pthread_mutex_t lock;
+ sem_t urllc_sem_process;
+ sem_t urllc_sem_done;
+} nr5g_fapi_urllc_thread_params_t;
+
// Phy Context
typedef struct _nr5g_fapi_phy_context {
uint8_t num_phy_instance;
uint8_t mac2phy_worker_core_id;
uint8_t phy2mac_worker_core_id;
- uint8_t urllc_worker_core_id;
- pthread_t phy2mac_tid;
- pthread_t mac2phy_tid;
- pthread_t urllc_tid;
- sem_t urllc_sem_process;
- sem_t urllc_sem_done;
+ uint8_t urllc_mac2phy_worker_core_id;
+ uint8_t urllc_phy2mac_worker_core_id;
+ nr5g_fapi_urllc_thread_params_t urllc_mac2phy_params;
+ nr5g_fapi_urllc_thread_params_t urllc_phy2mac_params;
+ bool is_urllc_enabled;
volatile uint64_t process_exit;
nr5g_fapi_phy_instance_t phy_instance[FAPI_MAX_PHY_INSTANCES];
} nr5g_fapi_phy_ctx_t,
*p_nr5g_fapi_phy_ctx_t;
// Function Declarations
-inline p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx(
+p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx(
);
uint8_t nr5g_fapi_framework_init(
);
void *config);
void *nr5g_fapi_mac2phy_thread_func(
void *config);
-void *nr5g_fapi_urllc_thread_func(
+void *nr5g_fapi_urllc_mac2phy_thread_func(
+ void *config);
+void *nr5g_fapi_urllc_phy2mac_thread_func(
void *config);
nr5g_fapi_ul_slot_info_t *nr5g_fapi_get_ul_slot_info(
bool is_urllc,
uint16_t slot_no,
uint8_t symbol_no,
nr5g_fapi_ul_slot_info_t * p_ul_slot_info);
+void nr5g_fapi_init_thread(uint8_t worker_core_id);
+void nr5g_fapi_urllc_thread_callback(
+ void *p_list_elem,
+ nr5g_fapi_urllc_thread_params_t* urllc_params);
+void nr5g_fapi_clean(
+ p_nr5g_fapi_phy_instance_t p_phy_instance);
#endif // _NR5G_FAPI_FRAMEWORK_H_
/******************************************************************************
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#define NR5G_FAPI_STATS_FNAME "FapiStats.txt"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
typedef enum _nr5g_fapi_log_types_t {
NONE_LOG = 0,
INFO_LOG, // default
uint16_t nr5g_fapi_statistic_info_set_all(
);
+#ifdef __cplusplus
+}
+#endif
+
#endif // NR5G_FAPI_LOG_H_
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#define NR5G_FAPI_MEMSET(s, x, c, n) nr5g_fapi_memset_bound_check(s, x, c, n)
#define NR5G_FAPI_STRCPY(d, x, s, n) nr5g_fapi_strcpy_bound_check(d, x, s, n)
-inline uint8_t nr5g_fapi_memcpy_bound_check(
- void *d,
+#include <stdint.h>
+#include <stddef.h>
+
+uint8_t nr5g_fapi_memcpy_bound_check(
+ void * const d,
size_t x,
- const void *s,
+ const void * const s,
size_t n);
-inline uint8_t nr5g_fapi_memset_bound_check(
- void *s,
+uint8_t nr5g_fapi_memset_bound_check(
+ void * const s,
size_t x,
const int32_t c,
size_t n);
-inline uint8_t nr5g_fapi_strcpy_bound_check(
- char *d,
+uint8_t nr5g_fapi_strcpy_bound_check(
+ char * const d,
size_t x,
- const char *s,
+ const char * const s,
size_t n);
#endif // NR5G_FAPI_MEM_H_
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
nr5g_fapi_cmgr((void *)config);
nr5g_fapi_dpdk_wait(config);
- pthread_attr_destroy(&config->phy2mac_thread_info.thread_attr);
- pthread_attr_destroy(&config->mac2phy_thread_info.thread_attr);
- pthread_attr_destroy(&config->urllc_thread_info.thread_attr);
+ pthread_attr_destroy(&config->phy2mac_thread_params.thread_info.thread_attr);
+ pthread_attr_destroy(&config->mac2phy_thread_params.thread_info.thread_attr);
+ if (config->is_urllc_enabled)
+ {
+ pthread_attr_destroy(&config->urllc_phy2mac_thread_params.thread_info.thread_attr);
+ pthread_attr_destroy(&config->urllc_mac2phy_thread_params.thread_info.thread_attr);
+ }
+
free(config);
return 0;
}
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
size_t len,
FILE * fp);
+void nr5g_fapi_get_worker_info(
+ struct rte_cfgfile *cfg_file,
+ unsigned int num_cpus,
+ nr5g_fapi_thread_params_t * thread_params,
+ const char* worker_name)
+{
+ const char *entry;
+
+ entry = rte_cfgfile_get_entry(cfg_file, worker_name, "core_id");
+ if (entry) {
+ thread_params->thread_worker.core_id = (uint8_t) atoi(entry);
+ if (thread_params->thread_worker.core_id >= (uint8_t) num_cpus) {
+ printf("Core Id is not in the range 0 to %d: configured: %d\n",
+ num_cpus, thread_params->thread_worker.core_id);
+ exit(-1);
+ }
+ }
+
+ entry =
+ rte_cfgfile_get_entry(cfg_file, worker_name,
+ "thread_sched_policy");
+ if (entry) {
+ thread_params->thread_worker.thread_sched_policy = (uint8_t) atoi(entry);
+ if (thread_params->thread_worker.thread_sched_policy != SCHED_FIFO &&
+ thread_params->thread_worker.thread_sched_policy != SCHED_RR) {
+ printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO"
+ " 2: SCHED_RR]: configured: %d\n",
+ thread_params->thread_worker.thread_sched_policy);
+ exit(-1);
+ }
+ }
+
+ int min_prio =
+ sched_get_priority_min(thread_params->thread_worker.thread_sched_policy);
+ int max_prio =
+ sched_get_priority_max(thread_params->thread_worker.thread_sched_policy);
+ entry =
+ rte_cfgfile_get_entry(cfg_file, worker_name, "thread_priority");
+ if (entry) {
+ thread_params->thread_worker.thread_priority = (uint8_t) atoi(entry);
+ if (thread_params->thread_worker.thread_priority < min_prio &&
+ thread_params->thread_worker.thread_priority > max_prio) {
+ printf("Thread priority valid range is %d to %d: configured: %d\n",
+ min_prio, max_prio, thread_params->thread_worker.thread_priority);
+ exit(-1);
+ }
+ }
+}
+
p_nr5g_fapi_cfg_t nr5g_fapi_config_loader(
char *prgname,
const char *cfg_fname)
}
pclose(fp);
num_cpus = atoi(max_core);
- entry = rte_cfgfile_get_entry(cfg_file, "MAC2PHY_WORKER", "core_id");
- if (entry) {
- cfg->mac2phy_worker.core_id = (uint8_t) atoi(entry);
- if (cfg->mac2phy_worker.core_id >= (uint8_t) num_cpus) {
- printf("Core Id is not in the range 0 to %d: configured: %d\n",
- num_cpus, cfg->mac2phy_worker.core_id);
- exit(-1);
- }
- }
- entry =
- rte_cfgfile_get_entry(cfg_file, "MAC2PHY_WORKER",
- "thread_sched_policy");
- if (entry) {
- cfg->mac2phy_worker.thread_sched_policy = (uint8_t) atoi(entry);
- if (cfg->mac2phy_worker.thread_sched_policy != SCHED_FIFO &&
- cfg->mac2phy_worker.thread_sched_policy != SCHED_RR) {
- printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO"
- " 2: SCHED_RR]: configured: %d\n",
- cfg->mac2phy_worker.thread_sched_policy);
- exit(-1);
- }
+ cfg->is_urllc_enabled = TRUE;
+ entry = rte_cfgfile_get_entry(cfg_file, "URLLC", "is_enabled");
+ if (entry)
+ {
+ cfg->is_urllc_enabled = (bool)atoi(entry);
+ if (!cfg->is_urllc_enabled)
+ printf("URLLC disabled\n");
}
- int min_prio =
- sched_get_priority_min(cfg->mac2phy_worker.thread_sched_policy);
- int max_prio =
- sched_get_priority_max(cfg->mac2phy_worker.thread_sched_policy);
- entry =
- rte_cfgfile_get_entry(cfg_file, "MAC2PHY_WORKER", "thread_priority");
- if (entry) {
- cfg->mac2phy_worker.thread_priority = (uint8_t) atoi(entry);
- if (cfg->mac2phy_worker.thread_priority < min_prio &&
- cfg->mac2phy_worker.thread_priority > max_prio) {
- printf("Thread priority valid range is %d to %d: configured: %d\n",
- min_prio, max_prio, cfg->mac2phy_worker.thread_priority);
- exit(-1);
- }
- }
-
- entry = rte_cfgfile_get_entry(cfg_file, "PHY2MAC_WORKER", "core_id");
- if (entry) {
- cfg->phy2mac_worker.core_id = (uint8_t) atoi(entry);
- if (cfg->phy2mac_worker.core_id >= (uint8_t) num_cpus) {
- printf("Core Id is not in the range 0 to %d configured: %d\n",
- num_cpus, cfg->phy2mac_worker.core_id);
- exit(-1);
- }
- }
-
- entry =
- rte_cfgfile_get_entry(cfg_file, "PHY2MAC_WORKER",
- "thread_sched_policy");
- if (entry) {
- cfg->phy2mac_worker.thread_sched_policy = (uint8_t) atoi(entry);
- if (cfg->phy2mac_worker.thread_sched_policy != SCHED_FIFO &&
- cfg->phy2mac_worker.thread_sched_policy != SCHED_RR) {
- printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO"
- " 2: SCHED_RR] configured: %d\n",
- cfg->phy2mac_worker.thread_sched_policy);
- exit(-1);
- }
- }
-
- entry =
- rte_cfgfile_get_entry(cfg_file, "PHY2MAC_WORKER", "thread_priority");
- if (entry) {
- cfg->phy2mac_worker.thread_priority = (uint8_t) atoi(entry);
- if (cfg->phy2mac_worker.thread_priority < min_prio &&
- cfg->phy2mac_worker.thread_priority > max_prio) {
- printf("Thread priority valid range is %d to %d configured: %d\n",
- min_prio, max_prio, cfg->phy2mac_worker.thread_priority);
- exit(-1);
- }
- }
-
- entry = rte_cfgfile_get_entry(cfg_file, "URLLC_WORKER", "core_id");
- if (entry) {
- cfg->urllc_worker.core_id = (uint8_t) atoi(entry);
- if (cfg->urllc_worker.core_id >= (uint8_t) num_cpus) {
- printf("Core Id is not in the range 0 to %d configured: %d\n",
- num_cpus, cfg->urllc_worker.core_id);
- exit(-1);
- }
- }
-
- entry =
- rte_cfgfile_get_entry(cfg_file, "URLLC_WORKER", "thread_sched_policy");
- if (entry) {
- cfg->urllc_worker.thread_sched_policy = (uint8_t) atoi(entry);
- if (cfg->urllc_worker.thread_sched_policy != SCHED_FIFO &&
- cfg->urllc_worker.thread_sched_policy != SCHED_RR) {
- printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO"
- " 2: SCHED_RR] configured: %d\n",
- cfg->urllc_worker.thread_sched_policy);
- exit(-1);
- }
- }
-
- entry =
- rte_cfgfile_get_entry(cfg_file, "URLLC_WORKER", "thread_priority");
- if (entry) {
- cfg->urllc_worker.thread_priority = (uint8_t) atoi(entry);
- if (cfg->urllc_worker.thread_priority < min_prio &&
- cfg->urllc_worker.thread_priority > max_prio) {
- printf("Thread priority valid range is %d to %d configured: %d\n",
- min_prio, max_prio, cfg->urllc_worker.thread_priority);
- exit(-1);
- }
- }
+ nr5g_fapi_get_worker_info(cfg_file, num_cpus, &cfg->mac2phy_thread_params, "MAC2PHY_WORKER");
+ nr5g_fapi_get_worker_info(cfg_file, num_cpus, &cfg->phy2mac_thread_params, "PHY2MAC_WORKER");
+ nr5g_fapi_get_worker_info(cfg_file, num_cpus, &cfg->urllc_mac2phy_thread_params, "MAC2PHY_URLLC_WORKER");
+ nr5g_fapi_get_worker_info(cfg_file, num_cpus, &cfg->urllc_phy2mac_thread_params, "PHY2MAC_URLLC_WORKER");
entry = rte_cfgfile_get_entry(cfg_file, "WLS_CFG", "device_name");
if (entry) {
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
*
**/
+#include "nr5g_fapi_memory.h"
+
#include <rte_memcpy.h>
#include <string.h>
#include "nr5g_fapi_wls.h"
inline uint8_t nr5g_fapi_memcpy_bound_check(
- void *d,
+ void * const d,
size_t x,
- const void *s,
+ const void * const s,
size_t n)
{
// Memory block size and destination/source boundary check
}
inline uint8_t nr5g_fapi_memset_bound_check(
- void *s,
+ void * const s,
size_t x,
int32_t c,
size_t n)
}
inline uint8_t nr5g_fapi_strcpy_bound_check(
- char *d,
+ char * const d,
size_t x,
- const char *s,
+ const char * const s,
size_t n)
{
// Memory block size and destination/source boundary check
#include <math.h>
-#include "gnb_l1_l2_api.h"
+#include "nr5g_mac_phy_api.h"
uint8_t nr5g_fapi_convert_snr_iapi_to_fapi(const int16_t snr)
{
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2021 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
###############################################################################
#
-# Copyright (c) 2019 Intel.
+# Copyright (c) 2021 Intel.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
##############################################################
# Tools configuration
##############################################################
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
CC := icc
CPP := icpc
AS := as
AR := ar
LD := icc
+else ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ CC := icx
+ CPP := icpx
+ AS := as
+ AR := llvm-ar
+ LD := icx
+else
+ $(error "Please define WIRELESS_SDK_TOOLCHAIN environment variable")
+endif
OBJDUMP := objdump
ifeq ($(SHELL),cmd.exe)
RM := rm -rf
endif
-PROJECT_NAME := sample-app
PROJECT_TYPE := elf
PROJECT_DIR := $(XRAN_DIR)/app
-BUILDDIR := ./build
+ifeq ($(ORU),1)
+ PROJECT_NAME := sample-app-ru
+ BUILDDIR := build-oru
+else
+ PROJECT_NAME := sample-app
+ BUILDDIR := build
+endif
+
PROJECT_BINARY := $(BUILDDIR)/$(PROJECT_NAME)
ifeq ($(RTE_SDK),)
endif
RTE_TARGET ?= x86_64-native-linuxapp-gcc
-
RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk)
API_DIR := $(XRAN_DIR)/lib/api
endif
endif
+
+##############################################################
+# FRAMEWORK
+##############################################################
+ifeq ($(FWK), 1)
+FW_INC := $(DIR_WIRELESS_FW)/enhanced_bbupool/inc
+FW_LIBS := -L$(DIR_WIRELESS_FW)/enhanced_bbupool/build -Wl,--whole-archive -Wl,-lebbupool -Wl,--no-whole-archive
+endif
+
CC_SRC = $(SRC_DIR)/common.c \
$(SRC_DIR)/config.c \
$(SRC_DIR)/app_io_fh_xran.c \
$(SRC_DIR)/app_profile_xran.c \
$(SRC_DIR)/sample-app.c
+ifeq ($(FWK), 1)
+CC_SRC += $(SRC_DIR)/aux_cline.c \
+ $(SRC_DIR)/app_bbu_main.c \
+ $(SRC_DIR)/app_bbu_pool.c \
+ $(SRC_DIR)/ebbu_pool_cfg.c \
+ $(SRC_DIR)/app_dl_bbu_pool_tasks.c \
+ $(SRC_DIR)/app_ul_bbu_pool_tasks.c
+endif
+
CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \
-fdata-sections \
-ffunction-sections \
-g \
-Wall \
-Wimplicit-function-declaration \
- -g -O3 -wd1786 -mcmodel=large
+ -g -O3 -mcmodel=large
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
+CC_FLAGS += -wd1786 -xcore-avx512
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+CC_FLAGS += -xcore-avx512 -mintrinsic-promote -Wno-unused-function -Wno-intrinsic-promote -Wno-error
+endif
CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -no-prec-div \
-no-prec-div -fp-model fast=2\
-no-prec-sqrt -falign-functions=16 -fast-transcendentals \
-Werror -Wno-unused-variable -std=c++11 -mcmodel=large
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
+CPP_FLAGS += -xcore-avx512 -fp-model fast=2 -no-prec-div -no-prec-sqrt -fast-transcendentals -restrict
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+CPP_FLAGS += -fp-model fast -march=icelake-server -mintrinsic-promote -Wno-unused-function -Wno-intrinsic-promote -Wno-error
+endif
+
INC := -I$(API_DIR) -I$(RTE_INC) -I$(OWD_DIR)
DEF :=
DEF += -UMLOG_ENABLED
endif
+ifeq ($(FWK),1)
+ INC += -I$(FW_INC)
+ DEF += -DFWK_ENABLED
+else
+ DEF += -UFWK_ENABLED
+endif
+
+ifeq ($(ORU),1)
+ DEF += -DXRAN_O_RU_BUILD
+else
+ DEF += -UXRAN_O_RU_BUILD
+endif
+
+ifeq ($(ORU),1)
+ XRAN_LIB_DIR=$(XRAN_DIR)/lib/build-oru
+ LD_FLAGS += -L$(XRAN_LIB_DIR) -lxran-oru
+else
XRAN_LIB_DIR=$(XRAN_DIR)/lib/build
LD_FLAGS += -L$(XRAN_LIB_DIR) -lxran
+endif
RTE_LIBS = $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --static --libs libdpdk)
-
LD_FLAGS += $(RTE_LIBS)
ifeq ($(MLOG),1)
LD_FLAGS += -L$(MLOG_DIR)/bin -lmlog
endif
+ifeq ($(FWK),1)
+LD_FLAGS += ${FW_LIBS}
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+LD_FLAGS += -Wl,-lstdc++
+endif
+
AS_FLAGS :=
AR_FLAGS := rc
-PROJECT_OBJ_DIR := build/obj
+PROJECT_OBJ_DIR := $(BUILDDIR)/obj
CC_OBJS := $(patsubst %.c,%.o,$(CC_SRC))
CPP_OBJS := $(patsubst %.cpp,%.o,$(CPP_SRC))
release : all
$(PROJECT_BINARY): $(DIRLIST) echo_start_build $(GENERATE_DEPS) $(PRE_BUILD) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS)
+ @$(MD) $(BUILDDIR)
@echo "[LD] $@ "
@$(LD) -o $@ $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS) $(LD_FLAGS) -Wl,-L $(BUILDDIR) -lrt -lpthread
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.0
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.1
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.2
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.3
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.0
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.1
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.2
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.3
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.0
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.1
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.2
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.3
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.0
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.1
$RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.2
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.3
else
#VM
];
% total number of tests
-tests_total = 12
+tests_total = 15
tech_all = ... % 0 - NR 1- LTE
[
- 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1
+ 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 2, 2, 2
]
sub6_all = ...
[
- true, true, true, true, false, true, true, true, true, true, true, true
+ true, true, true, true, false, true, true, true, true, true, true, true, true, true, true
]
mu_all = ...
[
- 0, 0, 0, 1, 3, 1, 0, 0, 0, 0, 0, 0
+ 0, 0, 0, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
]
bw_all = ...
[
- 5, 10, 20, 100, 100, 100, 20, 10, 5, 20, 10, 5
+ 5, 10, 20, 100, 100, 100, 20, 10, 5, 20, 10, 5, 20, 10, 5
]
ant_num_all = ...
[
- 4, 4, 4, 4, 4, 8, 4, 4, 4, 8, 8, 8
+ 4, 4, 4, 4, 4, 8, 4, 4, 4, 8, 8, 8, 4, 4, 4
]
bfw_gen_all = ...
[
- false, false, false, false, false, true, false, false, false, true, true, true,
+ false, false, false, false, false, true, false, false, false, true, true, true, false, false, false
]
trx_all = ...
[
- 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32
+ 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32
]
path_to_usecase_all = ...
[
"./usecase/lte_b/mu0_20mhz/";
"./usecase/lte_b/mu0_10mhz/";
"./usecase/lte_b/mu0_5mhz/";
+ "./usecase/dss/mu0_20mhz/";
+ "./usecase/dss/mu0_10mhz/";
+ "./usecase/dss/mu0_5mhz/";
]
path_to_usecase_all = cellstr(path_to_usecase_all)
nSlots_all = ...
[
- 20,20,20,20,20,20,20,20,20,10,10,10
+ 20,20,20,20,20,20,20,20,20,10,10,10,20,20,20
]
%select mu and bw to generate test files
ulimit -c unlimited
echo 1 > /proc/sys/kernel/core_uses_pid
-./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg --num_eth_vfs 6 \
+./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg --num_eth_vfs 8 \
--vf_addr_o_xu_a "0000:51:01.0,0000:51:09.0" \
--vf_addr_o_xu_b "0000:51:11.0,0000:51:19.0" \
---vf_addr_o_xu_c "0000:18:01.0,0000:18:09.0"
+--vf_addr_o_xu_c "0000:18:01.0,0000:18:09.0" \
+--vf_addr_o_xu_d "0000:18:01.1,0000:18:09.1"
ulimit -c unlimited
echo 1 > /proc/sys/kernel/core_uses_pid
-./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg --num_eth_vfs 6 \
+./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg --num_eth_vfs 8 \
--vf_addr_o_xu_a "0000:17:01.0,0000:17:09.0" \
--vf_addr_o_xu_b "0000:17:11.0,0000:17:19.0" \
---vf_addr_o_xu_c "0000:65:01.0,0000:65:09.0"
+--vf_addr_o_xu_c "0000:65:01.0,0000:65:09.0" \
+--vf_addr_o_xu_d "0000:65:01.1,0000:65:09.1"
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This module provides implementation of BBU tasks for sample app
+ * @file app_bbu_main.c
+ * @ingroup xran
+ * @author Intel Corporation
+ *
+ **/
+
+#define _GNU_SOURCE
+#include <sched.h>
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <assert.h>
+#include <pthread.h>
+#include <time.h>
+
+
+#include "app_bbu_pool.h"
+#include "app_io_fh_xran.h"
+#include "xran_mlog_task_id.h"
+
+/**
+ * @file app_bbu_main.c
+ * @brief example pipeline code to use Enhanced BBUPool Framework
+*/
+
+uint32_t gRunCount = 0;
+volatile uint32_t nStopFlag = 1;
+int32_t gQueueCtxNum = 1;
+
+int32_t nSplitNumCell[EBBU_POOL_MAX_TEST_CELL];
+
+int32_t nTestCell = 0;
+int32_t nTestCore = 0;
+volatile uint64_t ttistart = 0;
+int32_t dl_ul_count, dl_count, ul_count;
+
+uint32_t gMaxSlotNum[MAX_PHY_INSTANCES];
+uint32_t gNumDLCtx[MAX_PHY_INSTANCES];
+uint32_t gNumULCtx[MAX_PHY_INSTANCES];
+uint32_t gNumDLBufferCtx[MAX_PHY_INSTANCES];
+uint32_t gNumULBufferCtx[MAX_PHY_INSTANCES];
+uint32_t gDLProcAdvance[MAX_PHY_INSTANCES];
+int32_t gULProcAdvance[MAX_PHY_INSTANCES];
+
+
+#define EX_FUNC_NUM 9
+int32_t exGenDlFunc[EX_FUNC_NUM] =
+{
+ DL_CONFIG,
+ DL_PDSCH_SCRM,
+};
+int32_t exGenUlFunc[EX_FUNC_NUM] =
+{
+ UL_CONFIG,
+ UL_IQ_DECOMP2,
+ UL_IQ_DECOMP6,
+ UL_IQ_DECOMP11,
+ UL_IQ_DECOMP13,
+ UL_PRACH,
+ UL_PUSCH_TB
+};
+
+int32_t exGenAllFunc[EX_FUNC_NUM] =
+{
+ DL_CONFIG,
+ UL_CONFIG,
+ DL_PDSCH_SCRM,
+ UL_IQ_DECOMP2,
+ UL_IQ_DECOMP6,
+ UL_IQ_DECOMP11,
+ UL_IQ_DECOMP13,
+ UL_PRACH,
+ UL_PUSCH_TB
+};
+
+peBbuPoolCfgVarsStruct pCfg;
+pthread_t tCtrlThread;
+eBbuPoolHandler pHandler = NULL;
+clock_t tStart, tEnd;
+uint32_t ttiCell[EBBU_POOL_MAX_TEST_CELL] = {0};
+uint64_t ttiCountCell[EBBU_POOL_MAX_TEST_CELL] = {0UL};
+uint32_t frameFormatCell[EBBU_POOL_MAX_TEST_CELL] = {0};
+uint64_t tTTI = 0;
+
+
+eBbuPoolHandler app_get_ebbu_pool_handler(void)
+{
+ return pHandler;
+}
+
+
+int32_t
+app_bbu_dl_tti_call_back(void * param)
+{
+ int32_t ret = 0;
+ uint64_t t1 = MLogTick();
+ int32_t iCell = 0;
+ int32_t nCtx[EBBU_POOL_MAX_TEST_CELL] = {0}, iExFunc = 0, eventId = 0;
+ int32_t *exGenFuncDl = NULL, *exGenFuncUl = NULL;
+ int32_t nFuncNumDl = 0, nFuncNumUl = 0;
+ uint8_t Numerlogy = app_io_xran_fh_config[0].frame_conf.nNumerology;
+ uint8_t nNrOfSlotInSf = 1<<Numerlogy;
+ int32_t sfIdx = app_io_xran_sfidx_get(nNrOfSlotInSf);
+ uint64_t t = MLogTick();
+ uint32_t mlogVars[10], mlogVarsCnt = 0;
+
+ exGenFuncDl = exGenDlFunc;
+ nFuncNumDl = 2;
+ exGenFuncUl = exGenUlFunc;
+ nFuncNumUl = 7;
+
+ mlogVars[mlogVarsCnt++] = 0x99999999;
+ mlogVars[mlogVarsCnt++] = sfIdx % gMaxSlotNum[0];
+ MLogAddVariables(mlogVarsCnt, mlogVars, t);
+
+ for(iCell = 0; iCell < nTestCell ; iCell ++)
+ {
+ //check is it a tti for this cell
+ if(sfIdx % ttiCell[iCell] == 0)
+ {
+ ttistart = MLogTick();
+ dl_ul_count = nTestCell;
+ dl_ul_count += nTestCell;
+ ttiCountCell[iCell] = sfIdx;
+ nCtx[iCell] = ttiCountCell[iCell] % MAX_TEST_CTX;
+
+ event_chain_reset(&gEventChain[iCell][nCtx[iCell]]);
+
+ //if(nD2USwitch[frameFormatCell[iCell]][ttiCountCell[iCell]%EBBU_POOL_TDD_PERIOD] & EBBU_POOL_TEST_DL)
+ {
+ //printf("\ncell %d dl", iCell);
+ for(iExFunc = 0; iExFunc < nFuncNumDl; iExFunc ++)
+ {
+ eventId = exGenFuncDl[iExFunc];
+ ret = test_func_gen(pHandler, iCell, ttiCountCell[iCell], eventId);
+ }
+ }
+
+ //if(nD2USwitch[frameFormatCell[iCell]][ttiCountCell[iCell]%EBBU_POOL_TDD_PERIOD] & EBBU_POOL_TEST_UL)
+ {
+ //printf("\ncell %d ul", iCell);
+ for(iExFunc = 0; iExFunc < nFuncNumUl; iExFunc ++)
+ {
+ eventId = exGenFuncUl[iExFunc];
+ ret = test_func_gen(pHandler, iCell, ttiCountCell[iCell], eventId);
+ }
+ }
+ }
+
+ if(EBBUPOOL_ERROR == ret)
+ {
+ printf("\nFail to send cell %d, sf %lu, tsc %llu", iCell, ttiCountCell[iCell], ebbu_pool_tick()/tTTI/2);
+ }
+ }
+ MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
+ return 0;
+}
+
+int32_t app_bbu_init(int argc, char *argv[], char cfgName[512], UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg[], uint64_t nActiveCoreMask[EBBUPOOL_MAX_CORE_MASK])
+{
+ tStart = clock();
+ uint32_t nFh_cell = 0;
+ int32_t i;
+
+ ebbu_pool_cfg_set_cfg_filename(argc, argv, cfgName);
+
+ ebbu_pool_cfg_init_from_xml();
+ pCfg = ebbu_pool_cfg_get_ctx();
+
+ nTestCell = pCfg->testCellNum;
+
+ for (i = 0; i < p_use_cfg->oXuNum; i++)
+ nFh_cell += p_o_xu_cfg[i]->numCC;
+
+ if (nFh_cell != nTestCell) {
+ rte_panic("WARNING: miss match between BBU Cells (%d) and O-RAN FH Cells (%d)", nTestCell, nFh_cell);
+ }
+
+ if(nTestCell > EBBU_POOL_MAX_TEST_CELL || nTestCell <= 0)
+ {
+ printf("Wrong cell num %d\n",nTestCell);
+ nTestCell = 0;
+ }
+ nTestCore = pCfg->testCoreNum;
+ if(nTestCore > EBBU_POOL_MAX_TEST_CORE || nTestCore <= 0)
+ {
+ printf("Wrong core num %d\n",nTestCore);
+ nTestCore = 0;
+ }
+
+ gRunCount = 0;
+
+ printf("Test cell %d, test total core num %d, test slots %d\n", nTestCell, nTestCore, gRunCount);
+
+ // Step 1: create Framework handler
+ ebbu_pool_create_handler(&pHandler, 1, pCfg->mainThreadCoreId);
+ if(NULL == pHandler)
+ {
+ printf("\nFail to init Framework!");
+ exit(-1);
+ }
+
+ // Step 2: create priority queues
+ // Assume 3 queues
+ uint32_t nPrioQueue = pCfg->queueNum;
+ uint32_t nQueueSize = pCfg->queueDepth;
+ uint32_t pPrioQueueSize[8] = {nQueueSize, nQueueSize, nQueueSize, nQueueSize,nQueueSize, nQueueSize, nQueueSize, nQueueSize};
+ QueueConfigStruct sQueueConfig;
+ sQueueConfig.pQueueDepth = pPrioQueueSize;
+ sQueueConfig.nPriQueueNum = nPrioQueue;
+ sQueueConfig.nPriQueueCtxNum = pCfg->ququeCtxNum;
+ sQueueConfig.nPriQueueCtxMaxFetch = pCfg->ququeCtxNum;
+
+ ebbu_pool_create_queues(pHandler, sQueueConfig);
+
+ ebbu_pool_queue_ctx_set_threshold(pHandler, 2*nTestCell);
+
+ // Step 3: create one report for Framework
+ ReportCfg sReport;
+ sReport.nEventHoldNum = 2000;
+ sReport.pHandler = (void *)pHandler;
+ ebbu_pool_create_report(sReport);
+
+ // Step 4: start control thread
+ // pthread_create(&tCtrlThread, NULL, controlThread, (void *)pHandler);
+
+ peBbuPoolCfgVarsStruct pCfg = ebbu_pool_cfg_get_ctx();
+ int32_t iCell = 0;
+ int32_t iCtx = 0;
+ uint32_t xran_timer = (1000/(1 << p_o_xu_cfg[0]->mu_number)); /* base on O-RU 0 */
+
+ printf("xran_timer for TTI [%d] us\n", xran_timer);
+ // Init base timing as per xran_timer
+ uint64_t tStart = ebbu_pool_tick();
+ usleep(xran_timer);
+ tTTI = ebbu_pool_tick() - tStart;
+
+ // cell specific TTI init
+ // create cell and create consumer thread
+ // set events num per cell
+ for(iCell = 0; iCell < nTestCell; iCell ++)
+ {
+ ttiCell[iCell] = pCfg->sTestCell[iCell].tti/xran_timer;
+ printf("\nttiCell[%d] %d", iCell, ttiCell[iCell]);
+
+ frameFormatCell[iCell] = pCfg->sTestCell[iCell].frameFormat;
+ if(frameFormatCell[iCell] >= EBBU_POOL_MAX_FRAME_FORMAT)
+ frameFormatCell[iCell] = 0;
+
+ for(iCtx = 0; iCtx < MAX_TEST_CTX; iCtx ++)
+ {
+ event_chain_gen(&gEventChain[iCell][iCtx]);
+ }
+ nSplitNumCell[iCell] = 1;//((pCfg->sTestCell[iCell].eventPerTti)-11)/18; //current event chain has 29 events, 19 of them can be split
+ printf("\nnSplitNumCell[%d] %d", iCell, nSplitNumCell[iCell]);
+ if(nSplitNumCell[iCell] > MAX_TEST_SPLIT_NUM)
+ nSplitNumCell[iCell] = MAX_TEST_SPLIT_NUM;
+
+ }
+ test_buffer_create();
+
+ // add consumer thread
+
+ /*int32_t corePool[EBBU_POOL_MAX_TEST_CORE] = {4,24,5,25,6,26,7,27,
+ 8,28,9,29,10,30,11,31,
+ 12,32,13,33,14,34,15,35,
+ 16,36,17,37,18,38,19,39,
+ 2,22,3,23};
+ */
+
+ int32_t iCore = 0;
+ uint64_t nMask0 = 0UL, nMask1 = 0UL;
+ uint32_t iCoreIdx = 0;
+ uint64_t nCoreMask[EBBUPOOL_MAX_CORE_MASK];
+
+ for(; iCore < nTestCore; iCore ++)
+ {
+ iCoreIdx = pCfg->testCoreList[iCore];
+ if(iCoreIdx < 64)
+ nMask0 |= 1UL << iCoreIdx;
+ else
+ nMask1 |= 1UL << iCoreIdx;
+
+ }
+ //printf("\nnStartMask %016lx\n", nStartMask);
+
+ nActiveCoreMask[0] = nCoreMask[0] = nMask0;
+ nActiveCoreMask[0] = nCoreMask[1] = nMask1;
+ nActiveCoreMask[0] = nCoreMask[2] = 0;
+ nActiveCoreMask[0] = nCoreMask[3] = 0;
+
+ ebbu_pool_consumer_set_thread_params(pHandler, 55, SCHED_FIFO, pCfg->sleepFlag);
+ ebbu_pool_consumer_set_thread_mask(pHandler, nCoreMask);
+
+ usleep(100000);
+
+ /* mMIMO with 64TRX */
+ for(iCell = 0; iCell < nTestCell; iCell ++) {
+
+ gDLProcAdvance[iCell] = DL_PROC_ADVANCE_MU1;
+ gULProcAdvance[iCell] = UL_PROC_ADVANCE_MU1;
+ gNumDLCtx[iCell] = 5;
+ gNumDLBufferCtx[iCell] = 3;
+ gNumULCtx[iCell] = 8;
+ gNumULBufferCtx[iCell] = 2;
+ gMaxSlotNum[iCell] = 10240 * (1 << p_o_xu_cfg[0]->mu_number);
+ }
+
+ return 0;
+}
+
+int32_t app_bbu_close(void)
+{
+ // Close Mlog Buffer and write to File
+ // if(pCfg->mlogEnable)
+ // MLogPrint(NULL);
+
+ // Step 5: release all the threads
+ ebbu_pool_release_threads(pHandler);
+
+ // Step 6: get report for Framework
+ int32_t testResult = ebbu_pool_status_report(pHandler);
+ // Save the test status, 0 means pass, other means fail
+ char resultString[8] = {'\0'};
+ if(testResult == 0)
+ sprintf(resultString, "PASS");
+ else
+ sprintf(resultString, "FAIL");
+
+ tEnd = clock();
+
+ char fResultName[64] = {"sample-app_bbu_pool_test_results.txt"};
+ FILE *pFile = fopen(fResultName, "a");
+ if(pFile != NULL)
+ {
+ fprintf(pFile, "sample-app test case\n");
+ fprintf(pFile, "Execution time: %.3f second\n", (double)(tEnd - tStart)/1000000);
+ fprintf(pFile, "Result: %s\n\n", resultString);
+ fclose(pFile);
+ }
+
+ // Step 7: release report for Framework
+ ebbu_pool_release_report(pHandler);
+
+ // Step 8: release all allocated queues
+ ebbu_pool_release_queues(pHandler);
+
+ // Step 9: release handler for Framework
+ ebbu_pool_release_handler(&pHandler);
+ printf("\n");
+
+ return 0;
+}
+
+void
+app_io_xran_fh_bbu_rx_callback(void *pCallbackTag, xran_status_t status)
+{
+ eBbuPoolHandler pHandler = app_get_ebbu_pool_handler();
+ uint64_t t1 = MLogTick();
+ uint32_t mlogVar[10];
+ uint32_t mlogVarCnt = 0;
+ int32_t nCellIdx;
+ int32_t nCcIdx;
+ int32_t sym, nSlotIdx, ntti;
+ uint64_t mlog_start;
+ struct xran_cb_tag *pTag = (struct xran_cb_tag *) pCallbackTag;
+ int32_t o_xu_id = pTag->oXuId;
+ struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
+ uint32_t xran_max_antenna_nr = RTE_MAX(pXranConf->neAxc, pXranConf->neAxcUl);
+ uint32_t ant_id, sym_id, idxElm;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
+
+ mlog_start = MLogTick();
+ nCcIdx = pTag->cellId;
+ nCellIdx = psXranIoIf->map_cell_id2port[o_xu_id][nCcIdx];
+ nSlotIdx = pTag->slotiId; ///((status >> 16) & 0xFFFF); /** TTI aka slotIdx */
+ sym = pTag->symbol & 0xFF; /* sym */
+ ntti = (nSlotIdx + XRAN_N_FE_BUF_LEN-1) % XRAN_N_FE_BUF_LEN;
+
+ {
+ mlogVar[mlogVarCnt++] = 0xbcbcbcbc;
+ mlogVar[mlogVarCnt++] = o_xu_id;
+ mlogVar[mlogVarCnt++] = nCellIdx;
+ mlogVar[mlogVarCnt++] = sym;
+ mlogVar[mlogVarCnt++] = nSlotIdx;
+ mlogVar[mlogVarCnt++] = ntti;
+ //mlogVar[mlogVarCnt++] = nSlotIdx % gNumSlotPerSfn[nCellIdx];
+ //mlogVar[mlogVarCnt++] = get_slot_type(nCellIdx, nSlotIdx, SLOT_TYPE_UL);
+
+ MLogAddVariables(mlogVarCnt, mlogVar, mlog_start);
+ }
+
+ if(psIoCtrl == NULL)
+ {
+ printf("psIoCtrl NULL! o_xu_id= %d\n", o_xu_id);
+ return;
+ }
+
+ if (sym == XRAN_ONE_FOURTHS_CB_SYM) {
+ // 1/4 of slot
+ test_func_gen(pHandler, nCellIdx, nSlotIdx, SYM2_WAKE_UP);
+ } else if (sym == XRAN_HALF_CB_SYM) {
+ // First Half
+ test_func_gen(pHandler, nCellIdx, nSlotIdx, SYM6_WAKE_UP);
+ } else if (sym == XRAN_THREE_FOURTHS_CB_SYM) {
+ // 2/4 of slot
+ test_func_gen(pHandler, nCellIdx, nSlotIdx, SYM11_WAKE_UP);
+ } else if (sym == XRAN_FULL_CB_SYM) {
+ // Second Half
+ test_func_gen(pHandler, nCellIdx, nSlotIdx, SYM13_WAKE_UP);
+ } else {
+ /* error */
+ MLogTask(PID_GNB_SYM_CB, t1, MLogTick());
+
+ rte_panic("app_io_xran_fh_bbu_rx_callback: sym\n");
+ return;
+ }
+
+ if(sym == XRAN_FULL_CB_SYM) //full slot callback only
+ {
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[ntti][nCcIdx][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL){
+ printf("(%d:%d:%d)pRbMap == NULL\n", nCcIdx, ntti, ant_id);
+ exit(-1);
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
+ pRbElm = &pRbMap->prbMap[idxElm];
+ pRbElm->nSecDesc[sym_id] = 0;
+ }
+ }
+ }
+ }
+
+ rte_pause();
+
+ MLogTask(PCID_GNB_FH_RX_DATA_CC0+nCellIdx, mlog_start, MLogTick());
+ return;
+}
+
+void
+app_io_xran_fh_bbu_rx_prach_callback(void *pCallbackTag, xran_status_t status)
+{
+ eBbuPoolHandler pHandler = app_get_ebbu_pool_handler();
+ int32_t nCellIdx, nCcIdx;
+ int32_t sym, nSlotIdx, ntti;
+ struct xran_cb_tag *pTag = (struct xran_cb_tag *) pCallbackTag;
+ int32_t o_xu_id = pTag->oXuId;
+ uint64_t mlog_start = MLogTick();
+ uint32_t mlogVar[10];
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
+ uint32_t mlogVarCnt = 0;
+
+ if(psIoCtrl == NULL || psXranIoIf == NULL)
+ {
+ printf("psIoCtrl NULL! o_xu_id= %d\n", o_xu_id);
+ return;
+ }
+
+ nCcIdx = pTag->cellId;
+ nCellIdx = psXranIoIf->map_cell_id2port[o_xu_id][nCcIdx];
+ nSlotIdx = pTag->slotiId; ///((status >> 16) & 0xFFFF); /** TTI aka slotIdx */
+ sym = pTag->symbol & 0xFF; /* sym */
+ ntti = (nSlotIdx + XRAN_N_FE_BUF_LEN-1) % XRAN_N_FE_BUF_LEN;
+
+ mlogVar[mlogVarCnt++] = 0xDDDDDDDD;
+ mlogVar[mlogVarCnt++] = o_xu_id;
+ mlogVar[mlogVarCnt++] = nCellIdx;
+ mlogVar[mlogVarCnt++] = sym;
+ mlogVar[mlogVarCnt++] = nSlotIdx;
+ mlogVar[mlogVarCnt++] = ntti;
+ MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
+ test_func_gen(pHandler, nCellIdx, nSlotIdx, PRACH_WAKE_UP);
+
+ MLogTask(PCID_GNB_FH_RX_PRACH_CC0+nCellIdx, mlog_start, MLogTick());
+}
+
+void
+app_io_xran_fh_bbu_rx_srs_callback(void *pCallbackTag, xran_status_t status)
+{
+ eBbuPoolHandler pHandler = app_get_ebbu_pool_handler();
+ int32_t nCellIdx;
+ int32_t nCcIdx;
+ int32_t sym, nSlotIdx, ntti;
+ struct xran_cb_tag *pTag = (struct xran_cb_tag *) pCallbackTag;
+ int32_t o_xu_id = pTag->oXuId;
+ struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
+ uint32_t xran_max_antenna_nr = RTE_MAX(pXranConf->neAxc, pXranConf->neAxcUl);
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(pXranConf->nAntElmTRx, xran_max_antenna_nr);
+ uint32_t ant_id, sym_id, idxElm;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
+ uint64_t mlog_start = MLogTick();
+ uint32_t mlogVar[10];
+ uint32_t mlogVarCnt = 0;
+
+ if(psIoCtrl == NULL || psXranIoIf == NULL)
+ {
+ printf("psIoCtrl NULL! o_xu_id= %d\n", o_xu_id);
+ return;
+ }
+ nCcIdx = pTag->cellId;
+ nCellIdx = psXranIoIf->map_cell_id2port[o_xu_id][nCcIdx];
+ nSlotIdx = pTag->slotiId; ///((status >> 16) & 0xFFFF); /** TTI aka slotIdx */
+ sym = pTag->symbol & 0xFF; /* sym */
+ ntti = (nSlotIdx + XRAN_N_FE_BUF_LEN-1) % XRAN_N_FE_BUF_LEN;
+
+ mlogVar[mlogVarCnt++] = 0xCCCCCCCC;
+ mlogVar[mlogVarCnt++] = o_xu_id;
+ mlogVar[mlogVarCnt++] = nCellIdx;
+ mlogVar[mlogVarCnt++] = sym;
+ mlogVar[mlogVarCnt++] = nSlotIdx;
+ mlogVar[mlogVarCnt++] = ntti;
+ MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
+ test_func_gen(pHandler, nCellIdx, nSlotIdx, SRS_WAKE_UP);
+
+ if(sym == XRAN_FULL_CB_SYM) //full slot callback only
+ {
+ for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++) {
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[ntti][nCcIdx][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL){
+ printf("(%d:%d:%d)pRbMap == NULL\n", nCcIdx, ntti, ant_id);
+ exit(-1);
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
+ pRbElm = &pRbMap->prbMap[idxElm];
+ pRbElm->nSecDesc[sym_id] = 0;
+ }
+ }
+ }
+ }
+ MLogTask(PCID_GNB_FH_RX_SRS_CC0+nCellIdx, mlog_start, MLogTick());
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This module provides implementation of BBU tasks for sample app
+ * @file app_bbu.c
+ * @ingroup xran
+ * @author Intel Corporation
+ *
+ **/
+
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <assert.h>
+#include <pthread.h>
+#include <immintrin.h>
+
+#include "app_bbu_pool.h"
+
+/**
+ * @file gnb_main_ebbu_pool.c
+ * @brief example pipeline code to use Enhanced BBUPool Framework
+*/
+
+extern int32_t gQueueCtxNum;
+extern int32_t nSplitNumCell[EBBU_POOL_MAX_TEST_CELL];
+
+int32_t test_func_A(void *pCookies);
+int32_t test_func_B(void *pCookies);
+int32_t test_func_C(void *pCookies);
+
+void test_pre_func_A(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara);
+void test_pre_func_B(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara);
+
+int32_t test_func_gen(eBbuPoolHandler pHandler, int32_t nCell, int32_t nSlot, int32_t eventId);
+
+int32_t simulate_traffic(void *pCookies, int32_t testCount);
+
+typedef enum
+{
+ CAT_A = 0, //directly execute
+ CAT_B, //highest priority
+ CAT_C, //first priority
+ CAT_D, //second priority
+ CAT_E, //third priority
+ CAT_F, //forth priority
+ CAT_G, //fifth priority
+ CAT_H, //sixth priority
+ CAT_I, //seventh priority
+ CAT_NUM
+} EventCatEnum;
+
+static int32_t eventSendDic[CAT_NUM] =
+{
+ EBBUPOOL_PRIO_EXECUTE,
+ EBBUPOOL_PRIO_HIGHEST,
+ EBBUPOOL_PRIO_ONE,
+ EBBUPOOL_PRIO_TWO,
+ EBBUPOOL_PRIO_THREE,
+ EBBUPOOL_PRIO_FOUR,
+ EBBUPOOL_PRIO_FIVE,
+ EBBUPOOL_PRIO_SIX,
+ EBBUPOOL_PRIO_SEVEN
+};
+
+EventConfigStruct testEventTable[MAX_TASK_NUM_G_NB] =
+{
+ /* Event ID*/ /* Event Name*/ /* pri */ /* event function */ /* pre event function */ /* nExtEvent */ /*prefetch flag */ /*core mask type */ /* core affinity 0~63 */ /* core affinity 64~127 */
+ { TTI_START, EVENT_NAME(TTI_START), CAT_B, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { SYM2_WAKE_UP, EVENT_NAME(SYM2_WAKE_UP), CAT_B, app_bbu_pool_task_sym2_wakeup, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { SYM6_WAKE_UP, EVENT_NAME(SYM6_WAKE_UP), CAT_B, app_bbu_pool_task_sym6_wakeup, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { SYM11_WAKE_UP, EVENT_NAME(SYM11_WAKE_UP), CAT_B, app_bbu_pool_task_sym11_wakeup, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { SYM13_WAKE_UP, EVENT_NAME(SYM13_WAKE_UP), CAT_B, app_bbu_pool_task_sym13_wakeup, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { PRACH_WAKE_UP, EVENT_NAME(PRACH_WAKE_UP), CAT_B, app_bbu_pool_task_prach_wakeup, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { SRS_WAKE_UP, EVENT_NAME(SRS_WAKE_UP), CAT_B, app_bbu_pool_task_srs_wakeup, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_CONFIG, EVENT_NAME(DL_CONFIG), CAT_B, app_bbu_pool_task_dl_config,app_bbu_pool_pre_task_dl_cfg, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_PDSCH_TB, EVENT_NAME(DL_PDSCH_TB), CAT_B, test_func_A, test_pre_func_B, 0, 0, 0, 0x000000ffffffffff, 0xfffffffffffffff},
+ { DL_PDSCH_SCRM, EVENT_NAME(DL_PDSCH_SCRM), CAT_C, test_func_A, NULL, 0, 0, 0, 0x000000ffffffffff, 0xfffffffffffffff},
+ { DL_PDSCH_SYM, EVENT_NAME(DL_PDSCH_SYM), CAT_C, test_func_B, test_pre_func_A, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_PDSCH_RS, EVENT_NAME(DL_PDSCH_RS), CAT_C, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_CTRL, EVENT_NAME(DL_CTRL), CAT_C, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_CONFIG, EVENT_NAME(UL_CONFIG), CAT_C, app_bbu_pool_task_ul_config,app_bbu_pool_pre_task_ul_cfg, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_IQ_DECOMP2, EVENT_NAME(UL_IQ_DECOMP2), CAT_D, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_IQ_DECOMP6, EVENT_NAME(UL_IQ_DECOMP6), CAT_D, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_IQ_DECOMP11, EVENT_NAME(UL_IQ_DECOMP11), CAT_D, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_IQ_DECOMP13, EVENT_NAME(UL_IQ_DECOMP13), CAT_D, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_CE0, EVENT_NAME(UL_PUSCH_CE0), CAT_D, test_func_B, test_pre_func_A, 0, 0, 0, 0x000000ffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_CE7, EVENT_NAME(UL_PUSCH_CE7), CAT_D, test_func_B, test_pre_func_A, 0, 0, 0, 0x000000ffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_EQL0, EVENT_NAME(UL_PUSCH_EQL0), CAT_D, test_func_B, test_pre_func_A, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_EQL7, EVENT_NAME(UL_PUSCH_EQL7), CAT_D, test_func_B, test_pre_func_A, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_LLR, EVENT_NAME(UL_PUSCH_LLR), CAT_C, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_DEC, EVENT_NAME(UL_PUSCH_DEC), CAT_C, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PUSCH_TB, EVENT_NAME(UL_PUSCH_TB), CAT_C, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PUCCH, EVENT_NAME(UL_PUCCH), CAT_E, test_func_A, test_pre_func_A, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_PRACH, EVENT_NAME(UL_PRACH), CAT_E, test_func_A, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_SRS_DECOMP, EVENT_NAME(UL_SRS_DECOMP), CAT_E, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_SRS_CE, EVENT_NAME(UL_SRS_CE), CAT_E, test_func_B, test_pre_func_B, 0, 0, 0, 0x000000ffffffffff, 0xfffffffffffffff},
+ { UL_SRS_POST, EVENT_NAME(UL_SRS_POST), CAT_E, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_POST, EVENT_NAME(DL_POST), CAT_B, app_bbu_pool_task_dl_post, app_bbu_pool_pre_task_dl_post, 0, 1, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_POST, EVENT_NAME(UL_POST), CAT_A, test_func_C, NULL, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_BEAM_GEN, EVENT_NAME(DL_BEAM_GEN), CAT_D, test_func_B, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { DL_BEAM_TX, EVENT_NAME(DL_BEAM_TX), CAT_D, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_BEAM_GEN, EVENT_NAME(UL_BEAM_GEN), CAT_D, test_func_B, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+ { UL_BEAM_TX, EVENT_NAME(UL_BEAM_TX), CAT_D, test_func_A, test_pre_func_B, 0, 0, 0, 0x00ffffffffffffff, 0xfffffffffffffff},
+};
+
+int32_t gNBNextTaskMap[MAX_TASK_NUM_G_NB][MAX_NEXT_TASK_NUM] =
+{
+ // TTI_START
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // SYM2_WAKE_UP
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // SYM6_WAKE_UP
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // SYM11_WAKE_UP
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // SYM13_WAKE_UP
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // PRACH_WAKE_UP
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // SRS_WAKE_UP
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_CONFIG
+ {DL_PDSCH_TB, DL_CTRL, DL_PDSCH_RS, DL_BEAM_GEN, -1, -1, -1, -1},
+
+ // DL_PDSCH_TB
+ {DL_PDSCH_SCRM, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_PDSCH_SCRM
+ {DL_PDSCH_SYM, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_PDSCH_SYM
+ {DL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_PDSCH_RS
+ {DL_PDSCH_SYM, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_CTRL
+ {DL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_CONFIG
+ {UL_IQ_DECOMP2, UL_IQ_DECOMP6, UL_IQ_DECOMP11, UL_IQ_DECOMP13, UL_PUCCH, UL_PRACH, UL_SRS_DECOMP, UL_BEAM_GEN},
+
+ // UL_IQ_DECOMP2
+ {UL_PUSCH_CE0, UL_PUSCH_CE7, -1, -1, -1, -1, -1, -1},
+
+ // UL_IQ_DECOMP6
+ {UL_PUSCH_EQL0, UL_PUSCH_EQL7, -1, -1, -1, -1, -1, -1},
+
+ // UL_IQ_DECOMP11
+ {UL_PUSCH_CE7, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_IQ_DECOMP13
+ {UL_PUSCH_EQL7, UL_PUCCH, UL_SRS_DECOMP, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_CE0
+ {UL_PUSCH_EQL0, UL_PUSCH_EQL7, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_CE7
+ {UL_PUSCH_EQL7, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_EQL0
+ {UL_PUSCH_LLR, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_EQL7
+ {UL_PUSCH_LLR, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_LLR
+ {UL_PUSCH_DEC, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_DEC
+ {UL_PUSCH_TB, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUSCH_TB
+ {UL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PUCCH
+ {UL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_PRACH
+ {UL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_SRS_DECOMP
+ {UL_SRS_CE, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_SRS_CE
+ {UL_SRS_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_SRS_POST
+ {UL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_POST
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_POST
+ {-1, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_BEAM_GEN
+ {DL_BEAM_TX, -1, -1, -1, -1, -1, -1, -1},
+
+ // DL_BEAM_TX
+ {DL_POST, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_BEAM_GEN
+ {UL_BEAM_TX, -1, -1, -1, -1, -1, -1, -1},
+
+ // UL_BEAM_TX
+ {UL_POST, -1, -1, -1, -1, -1, -1, -1},
+};
+
+__attribute__((aligned(IA_ALIGN))) EventCtrlStruct gEventCtrl[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX][MAX_TASK_NUM_G_NB][MAX_TEST_SPLIT_NUM];
+static __attribute__((aligned(IA_ALIGN))) EventStruct gEvent[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX][MAX_TASK_NUM_G_NB][MAX_TEST_SPLIT_NUM];
+__attribute__((aligned(IA_ALIGN))) EventChainDescStruct gEventChain[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX];
+static SampleSplitStruct gsSampleSplit[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX][MAX_TEST_SPLIT_NUM];
+
+static uint64_t dl_start_mlog[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX];
+static uint64_t ul_start_mlog[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX];
+extern volatile uint64_t ttistart;
+extern int32_t dl_ul_count, dl_count, ul_count;
+int32_t test_buffer_create()
+{
+ int32_t iCell, iCtx, iTask, iSplit;
+ for(iCell = 0; iCell < EBBU_POOL_MAX_TEST_CELL; iCell ++)
+ for(iCtx = 0; iCtx < MAX_TEST_CTX; iCtx ++)
+ for(iTask = 0; iTask < MAX_TASK_NUM_G_NB; iTask ++)
+ for(iSplit = 0; iSplit < MAX_TEST_SPLIT_NUM; iSplit ++)
+ gEventCtrl[iCell][iCtx][iTask][iSplit].dummy0 = (float *)_mm_malloc(sizeof(float), IA_ALIGN);
+ return 0;
+}
+
+int32_t event_chain_gen(EventChainDescStruct *psEventChain)
+{
+ /*Construct the next event chain by copying existing array */
+ psEventChain->eventChainDepth = MAX_TASK_NUM_G_NB;
+ memcpy((void *)psEventChain->nextEventChain, (void *)gNBNextTaskMap, sizeof(gNBNextTaskMap));
+ //printf("\nCopy gNBNextTaskMap with size %d", sizeof(gNBNextTaskMap));
+ memset((void *)&psEventChain->nextEventCount, 0 , sizeof(psEventChain->nextEventCount));
+ memset((void *)&psEventChain->preEventCount, 0 , sizeof(psEventChain->preEventCount));
+ memset((void *)&psEventChain->preEventStat, 0 , sizeof(psEventChain->preEventStat));
+
+ /*For each event, find all preceding dependent event */
+ int32_t iEvent = 0;
+ int32_t iNext = 0;
+
+ /* Set the external event Wakeup Dependencies (apart from Task Dependency) */
+ for(iEvent = 0; iEvent < MAX_TASK_NUM_G_NB; iEvent++)
+ {
+ psEventChain->preEventCountSave[iEvent] = testEventTable[iEvent].nWakeOnExtrernalEvent;
+ }
+
+ for(iEvent = 0; iEvent < MAX_TASK_NUM_G_NB; iEvent ++)
+ {
+ for(iNext = 0; iNext < MAX_NEXT_TASK_NUM; iNext ++)
+ {
+ if(psEventChain->nextEventChain[iEvent][iNext] != -1)
+ {
+ psEventChain->preEventCountSave[psEventChain->nextEventChain[iEvent][iNext]] ++;
+ psEventChain->nextEventCount[iEvent] ++;
+ }
+ }
+ }
+
+ /*
+ for(iEvent = 0; iEvent < MAX_TASK_NUM_G_NB; iEvent ++)
+ {
+ printf("\nEvent %d preEvent %d",iEvent,psEventChain->preEventCount[iEvent]);
+ }
+ */
+ return 0;
+}
+
+int32_t event_chain_reset(EventChainDescStruct *psEventChain)
+{
+ memset((void *)&psEventChain->preEventStat, 0 , sizeof(psEventChain->preEventStat));
+
+ /*For each event, find all preceding dependent event */
+ int32_t iEvent = 0;
+
+ /* Set the external event Wakeup Dependencies (apart from Task Dependency) */
+ for(iEvent = 0; iEvent < MAX_TASK_NUM_G_NB; iEvent++)
+ {
+ psEventChain->preEventCount[iEvent] = psEventChain->preEventCountSave[iEvent];
+ }
+ return 0;
+}
+
+static void set_event_info(EventCtrlStruct *pEvenCtrl, int32_t eventId,
+ int32_t iSplit, EventSendStruct *psEventSend)
+{
+ int32_t nCell = pEvenCtrl->nCellIdx;
+ int32_t nSlot = pEvenCtrl->nSlotIdx;
+ int32_t nCtx = nSlot % MAX_TEST_CTX;
+ int32_t nQueueCtxNum = nSlot % gQueueCtxNum;
+ EventStruct * pEvent = &gEvent[nCell][nCtx][eventId][iSplit];
+ pEvent->pEventFunc = testEventTable[eventId].pEventFunc;
+ pEvent->pEventArgs = pEvenCtrl;
+ pEvent->nEventId = eventId;
+ pEvent->nEventSentTime = ebbu_pool_tick();
+ pEvent->nEventSentTimeMlog = MLogTick();
+ pEvent->nEventAliveTime = 10000000;
+ pEvent->nCoreAffinityMask = _mm256_set_epi64x(0,0,testEventTable[eventId].nCoreMask1,testEventTable[eventId].nCoreMask0);
+ pEvent->nEventStatus = EBBUPOOL_EVENT_VALID;
+
+ psEventSend->eDisposFlag = EBBUPOOL_NON_DISPOSABLE;
+
+ psEventSend->ePrioCat = eventSendDic[testEventTable[eventId].nEventPrio];
+ psEventSend->nQueueCtx = 0;
+ if(gQueueCtxNum > 1)
+ psEventSend->nQueueCtx = nQueueCtxNum;
+
+ psEventSend->psEventStruct[0] = pEvent;
+ psEventSend->nEventNum = 1;
+
+ psEventSend->nPreFlag = testEventTable[eventId].nPrefetchFlag;
+
+ return;
+}
+
+static void set_split_event_info(EventCtrlStruct *pEvenCtrl, int32_t eventId,
+ int32_t nSplit, EventSendStruct *psEventSend)
+{
+ int32_t nCell = pEvenCtrl[0].nCellIdx;
+ int32_t nSlot = pEvenCtrl[0].nSlotIdx;
+ int32_t nCtx = nSlot % MAX_TEST_CTX;
+ int32_t nQueueCtxNum = nSlot % gQueueCtxNum;
+ int32_t iSplit = 0;
+ for(; iSplit < nSplit; iSplit ++)
+ {
+ EventStruct *pEvent = &gEvent[nCell][nCtx][eventId][iSplit];
+ pEvent->pEventFunc = testEventTable[eventId].pEventFunc;
+ pEvent->pEventArgs = &pEvenCtrl[iSplit];
+ pEvent->nEventId = eventId;
+ pEvent->nEventSentTime = ebbu_pool_tick();
+ pEvent->nEventSentTimeMlog = MLogTick();
+ pEvent->nEventAliveTime = 10000000;
+ pEvent->nCoreAffinityMask = _mm256_set_epi64x(0,0,testEventTable[eventId].nCoreMask1,testEventTable[eventId].nCoreMask0);
+ pEvent->nEventStatus = EBBUPOOL_EVENT_VALID;
+ psEventSend->psEventStruct[iSplit] = pEvent;
+ }
+ pEvenCtrl[0].tSendTime = MLogTick();
+ psEventSend->eDisposFlag = EBBUPOOL_DISPOSABLE;
+ psEventSend->ePrioCat = eventSendDic[testEventTable[eventId].nEventPrio];
+ psEventSend->nQueueCtx = 0;
+ if(gQueueCtxNum > 1)
+ psEventSend->nQueueCtx = nQueueCtxNum;
+ psEventSend->nEventNum = nSplit;
+ psEventSend->nPreFlag = testEventTable[eventId].nPrefetchFlag;
+
+ return;
+}
+
+int32_t next_event_unlock(void *pCookies)
+{
+ EventCtrlStruct *pEvenCtrl = (EventCtrlStruct *)pCookies;
+ eBbuPoolHandler pHandler = (eBbuPoolHandler)pEvenCtrl->pHandler;
+ int32_t nCell = pEvenCtrl->nCellIdx;
+ int32_t nSlot = pEvenCtrl->nSlotIdx;
+ int32_t nCtx = nSlot % MAX_TEST_CTX;
+ int32_t eventId = pEvenCtrl->nEventId;
+ EventChainDescStruct * pEventChain = &gEventChain[nCell][nCtx];
+
+ if(eventId == DL_POST||eventId == UL_POST)
+ ebbu_pool_queue_ctx_add(pHandler, nCtx);
+
+ /*Set and check the status of all next event */
+ /*Then decide whether to send next event or not */
+ int32_t iNext = 0;
+ int32_t nextEventId = 0;
+
+ for(iNext = 0; iNext < pEventChain->nextEventCount[eventId]; iNext++)
+ {
+ nextEventId = pEventChain->nextEventChain[eventId][iNext];
+ /*printf("\nnSlot %d event %d nextEventCount %d inext %d next %d next_pre_count %d next_pre_stat %d",
+ nSlotIdx, nTaskId, pEventChain->nextEventCount[nTaskId], iNext, nextEventId,
+ pEventChain->preEventCount[nextEventId], pEventChain->preEventStat[nextEventId]);
+ */
+
+ if(__atomic_add_fetch(&pEventChain->preEventStat[nextEventId], 1, __ATOMIC_ACQ_REL) ==
+ __atomic_load_n(&pEventChain->preEventCount[nextEventId], __ATOMIC_ACQUIRE))
+ {
+ test_func_gen(pHandler, nCell, nSlot, nextEventId);
+ }
+ }
+
+ return 0;
+}
+
+int32_t test_func_gen(eBbuPoolHandler pHandler, int32_t nCell, int32_t nSlot, int32_t eventId)
+{
+ int j;
+ if(eventId >= MAX_TASK_NUM_G_NB || nCell >= EBBU_POOL_MAX_TEST_CELL)
+ {
+ printf("\nError! Wrong eventId %d max %d nCell %d",eventId, MAX_TASK_NUM_G_NB, nCell);
+ exit(-1);
+ }
+
+ int32_t nCtx = nSlot % MAX_TEST_CTX;
+ int32_t iNext, iNextEventId, nSplitIdx;
+ EventChainDescStruct * pEventChain = &gEventChain[nCell][nCtx];
+ EventSendStruct sEventSend;
+ EventCtrlStruct *pEventCtrl;
+ TaskPreGen sPara;
+ int32_t nSplit = 1, ret = 0;
+
+ uint64_t t1 = MLogTick();
+
+ if(DL_CONFIG == eventId)
+ dl_start_mlog[nCell][nCtx] = t1;
+ else if(UL_CONFIG == eventId)
+ ul_start_mlog[nCell][nCtx] = t1;
+
+ // Klocwork check
+ for (j = 0; j < MAX_TEST_SPLIT_NUM; j++)
+ sPara.pTaskExePara[j] = (void *)&gsSampleSplit[nCell%EBBU_POOL_MAX_TEST_CELL][nSlot%MAX_TEST_CTX][j];
+
+ if (testEventTable[eventId].pPreEventFunc)
+ {
+ /* Run Pre Event and Find out how many split */
+ sPara.nTaskNum = 1;
+ testEventTable[eventId].pPreEventFunc(nSlot, nCell, &sPara);
+ nSplit = sPara.nTaskNum;
+ if(nSplit > 1)
+ {
+ /* Add the split to all the Nex Next Dependencies */
+ for(iNext = 0; iNext < pEventChain->nextEventCount[eventId]; iNext++)
+ {
+ iNextEventId = pEventChain->nextEventChain[eventId][iNext];
+ __atomic_add_fetch(&pEventChain->preEventCount[iNextEventId], nSplit - 1, __ATOMIC_ACQ_REL);
+ }
+ }
+ }
+
+ //send the splitted events together, save ebbupool internal overhead
+ for(nSplitIdx = 0; nSplitIdx < nSplit; nSplitIdx++)
+ {
+ pEventCtrl = &gEventCtrl[nCell][nCtx][eventId][nSplitIdx];
+ pEventCtrl->nEventId = eventId;
+ pEventCtrl->nSplitIdx = nSplitIdx;
+ pEventCtrl->nCellIdx = nCell;
+ pEventCtrl->nSlotIdx = nSlot;
+ pEventCtrl->pTaskPara = sPara.pTaskExePara[nSplitIdx];
+ pEventCtrl->pHandler = pHandler;
+ }
+
+ set_split_event_info(&gEventCtrl[nCell][nCtx][eventId][0], eventId, nSplit, &sEventSend);
+ ret = ebbu_pool_send_event(pHandler, sEventSend);
+
+ if(0 != ret)
+ printf("\nEvent %d gen failed!",eventId);
+
+ MLogTask(MAX_TASK_NUM_G_NB * nCell + eventId + 2000, t1, MLogTick());
+
+ return 0;
+}
+void test_pre_func_A(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara)
+{
+ // uint64_t t1 = MLogTick();
+ //printf("\nfunc pre A event %d",pEvenCtrl->nEventId);
+ // int32_t ret = 0;
+ //do some traffic
+ //ret = simulate_traffic(pCookies, 1000);
+
+ pPara->nTaskNum = nSplitNumCell[nCellIdx];
+ int32_t iSplit = 0;
+ for(iSplit = 0; iSplit < pPara->nTaskNum; iSplit ++)
+ {
+ pPara->pTaskExePara[iSplit] = (void *)&gsSampleSplit[nCellIdx%EBBU_POOL_MAX_TEST_CELL][nSubframe%MAX_TEST_CTX][iSplit];
+ }
+ return;
+ //MLogTask(MAX_TASK_NUM_G_NB * pInputPara->nCellIdx + pEvenCtrl->nEventId, t1, MLogTick());
+}
+
+
+void test_pre_func_B(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara)
+{
+ // uint64_t t1 = MLogTick();
+ //printf("\nfunc pre A event %d",pEvenCtrl->nEventId);
+ // int32_t ret = 0;
+
+ //do some traffic
+ //ret = simulate_traffic(pCookies, 1000);
+ int32_t iSplit = 0;
+ for(iSplit = 0; iSplit < pPara->nTaskNum; iSplit ++)
+ {
+ pPara->pTaskExePara[iSplit] = (void *)&gsSampleSplit[nCellIdx%EBBU_POOL_MAX_TEST_CELL][nSubframe%MAX_TEST_CTX][iSplit];
+ }
+ return;
+
+ pPara->nTaskNum = nSplitNumCell[nCellIdx];
+
+ //MLogTask(MAX_TASK_NUM_G_NB * pInputPara->nCellIdx + pEvenCtrl->nEventId, t1, MLogTick());
+}
+
+int32_t test_func_A(void *pCookies)
+{
+ EventCtrlStruct *pEvenCtrl = (EventCtrlStruct *)pCookies;
+
+ uint64_t t1 = MLogTick();
+#if 0
+ //printf("\nfunc A event %d",pEvenCtrl->nEventId);
+ if(DL_CONFIG == pEvenCtrl->nEventId)
+ {
+ app_bbu_pool_task_dl_config(pCookies);
+ MLogTask(pEvenCtrl->nCellIdx + 4000, pEvenCtrl->tSendTime, t1);
+ }
+
+ if(UL_CONFIG == pEvenCtrl->nEventId)
+ {
+ app_bbu_pool_task_ul_config(pCookies);
+ MLogTask(pEvenCtrl->nCellIdx + 5000, pEvenCtrl->tSendTime, t1);
+ }
+#endif
+ // int32_t ret = 0;
+
+ //do some traffic
+ //ret = simulate_traffic(pCookies, 3000);
+ //usleep(10);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+
+ MLogTask(MAX_TASK_NUM_G_NB * pEvenCtrl->nCellIdx + pEvenCtrl->nEventId, t1, MLogTick());
+ //printf("\nfunc a latency %llu",MLogTick()-t1);
+
+ return 0;
+
+}
+
+int32_t test_func_B(void *pCookies)
+{
+ EventCtrlStruct *pEvenCtrl = (EventCtrlStruct *)pCookies;
+
+ uint64_t t1 = MLogTick();
+ //printf("\nfunc B event %d",pEvenCtrl->nEventId);
+ // int32_t ret = 0;
+
+ //do some traffic
+ //ret = simulate_traffic(pCookies, 5000);
+ //usleep(10);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+
+ MLogTask(MAX_TASK_NUM_G_NB * pEvenCtrl->nCellIdx + pEvenCtrl->nEventId, t1, MLogTick());
+
+ return 0;
+}
+
+int32_t test_func_C(void *pCookies)
+{
+ EventCtrlStruct *pEvenCtrl = (EventCtrlStruct *)pCookies;
+
+ uint64_t t1 = MLogTick();
+ //printf("\nfunc B event %d",pEvenCtrl->nEventId);
+ int32_t ret = 0;
+
+ //do some traffic
+
+ MLogTask(MAX_TASK_NUM_G_NB * pEvenCtrl->nCellIdx + pEvenCtrl->nEventId, t1, MLogTick());
+
+ if(pEvenCtrl->nEventId == DL_POST || pEvenCtrl->nEventId == UL_POST)
+ {
+ if(__atomic_sub_fetch(&dl_ul_count, 1, __ATOMIC_ACQ_REL) == 0)
+ {
+ MLogTask(MAX_TASK_NUM_G_NB * pEvenCtrl->nCellIdx + 6000, ttistart, MLogTick());
+ }
+ }
+
+ MLogTask(77777, t1, MLogTick());
+ return ret;
+}
+
+#if 0
+int32_t simulate_traffic(void *pCookies, int32_t testCount)
+{
+ //printf("\ndo traffic!");
+ EventCtrlStruct *pEvenCtrl = (EventCtrlStruct *)pCookies;
+ __m256 sigma2 = _mm256_set1_ps(testCount/1234.5);
+ __m256 ftemp1, ftemp2;
+
+ int32_t m = testCount;
+ m = m/2;
+
+ while(m > 0)
+ {
+ ftemp1 = _mm256_rcp_ps(sigma2);
+ ftemp2 = _mm256_sub_ps(_mm256_set1_ps(0), sigma2);
+ ftemp2 = _mm256_fmadd_ps(ftemp1, sigma2, ftemp2);
+ sigma2 = _mm256_rcp_ps(ftemp2);
+ m --;
+ }
+
+ int32_t nfloat = 8; //256bits has eight 32bits
+ float *dummy = (float *)&sigma2;
+ *pEvenCtrl->dummy0 = 0;
+ for(m = 0; m < nfloat; m++)
+ *pEvenCtrl->dummy0 += dummy[m];
+
+ return 0;
+}
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief Header file to implementation of BBU
+ * @file app_bbu.h
+ * @ingroup xran
+ * @author Intel Corporation
+ *
+ **/
+
+#ifndef _APP_BBU_POOL_H_
+#define _APP_BBU_POOL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ebbu_pool_api.h"
+#include "ebbu_pool_cfg.h"
+
+#include "config.h"
+#include "xran_fh_o_du.h"
+#include "xran_mlog_lnx.h"
+
+#ifndef SUCCESS
+/** SUCCESS = 0 */
+#define SUCCESS 0
+#endif /* #ifndef SUCCESS */
+
+#ifndef FAILURE
+/** FAILURE = 1 */
+#define FAILURE 1
+#endif /* #ifndef FAILURE */
+
+#define MAX_NEXT_TASK_NUM 8
+#define MAX_TEST_CTX 4
+#define MAX_TEST_SPLIT_NUM 55 // then largest 1000 events per TTI by pre-defined event chain
+
+#define EVENT_NAME(EVENT_TYPE) #EVENT_TYPE
+
+#define MAX_PHY_INSTANCES ( 24 )
+#define MAX_NUM_OF_SF_5G_CTX ( 8 )
+
+/******Processing Latencies***/
+#define DL_PROC_ADVANCE_MU0 ( 1 )
+#define DL_PROC_ADVANCE_MU1 ( 2 )
+#define DL_PROC_ADVANCE_MU3 ( 2 )
+
+#define UL_PROC_ADVANCE_MU0 ( 1 )
+#define UL_PROC_ADVANCE_MU1 ( 1 )
+#define UL_PROC_ADVANCE_MU3 ( 1 )
+
+extern uint32_t gMaxSlotNum[MAX_PHY_INSTANCES];
+extern uint32_t gNumDLCtx[MAX_PHY_INSTANCES];
+extern uint32_t gNumULCtx[MAX_PHY_INSTANCES];
+extern uint32_t gNumDLBufferCtx[MAX_PHY_INSTANCES];
+extern uint32_t gNumULBufferCtx[MAX_PHY_INSTANCES];
+extern uint32_t gDLProcAdvance[MAX_PHY_INSTANCES];
+extern int32_t gULProcAdvance[MAX_PHY_INSTANCES];
+
+#define get_dl_sf_idx(nSlotNum, nCellIdx) ((nSlotNum + gDLProcAdvance[nCellIdx]) % gMaxSlotNum[nCellIdx])
+#define get_ul_sf_idx(nSlotNum, nCellIdx) ((nSlotNum + gULProcAdvance[nCellIdx]) % gMaxSlotNum[nCellIdx])
+#define get_dl_sf_ctx(nSlotNum, nCellIdx) (nSlotNum % gNumDLCtx[nCellIdx])
+#define get_ul_sf_ctx(nSlotNum, nCellIdx) (nSlotNum % gNumULCtx[nCellIdx])
+
+typedef enum
+{
+ TTI_START = 0, /* 0 First task that will schedule all the other tasks for all Cells */
+ SYM2_WAKE_UP, /* 1 Sym2 Arrival which will wake up UL Tasks for all cells */
+ SYM6_WAKE_UP, /* 2 Sym6 Arrival which will wake up UL Tasks for all cells */
+ SYM11_WAKE_UP, /* 3 Sym11 Arrival which will wake up UL Tasks for all cells */
+ SYM13_WAKE_UP, /* 4 Sym13 Arrival which will wake up UL Tasks for all cells */
+ PRACH_WAKE_UP, /* 5 PRACH Arrival which will wake up will wake up PRACH for all cells */
+ SRS_WAKE_UP, /* 6 (Massive MIMO) SRS Arrival which will wake up SRS Decompression for all cells */
+ DL_CONFIG, /* 7 */
+ DL_PDSCH_TB, /* 8 */
+ DL_PDSCH_SCRM, /* 9 */
+ DL_PDSCH_SYM, /* 10 */
+ DL_PDSCH_RS, /* 11 */
+ DL_CTRL, /* 12 */
+ UL_CONFIG, /* 13 */
+ UL_IQ_DECOMP2, /* 14 */
+ UL_IQ_DECOMP6, /* 15 */
+ UL_IQ_DECOMP11, /* 16 */
+ UL_IQ_DECOMP13, /* 17 */
+ UL_PUSCH_CE0, /* 18 */
+ UL_PUSCH_CE7, /* 19 */
+ UL_PUSCH_EQL0, /* 20 */
+ UL_PUSCH_EQL7, /* 21 */
+ UL_PUSCH_LLR, /* 22 */
+ UL_PUSCH_DEC, /* 23 */
+ UL_PUSCH_TB, /* 24 */
+ UL_PUCCH, /* 25 */
+ UL_PRACH, /* 26 */
+ UL_SRS_DECOMP, /* 27 */
+ UL_SRS_CE, /* 28 */
+ UL_SRS_POST, /* 29 */
+ DL_POST, /* 30 */
+ UL_POST, /* 31 */
+ DL_BEAM_GEN, /* 32 */
+ DL_BEAM_TX, /* 33 */
+ UL_BEAM_GEN, /* 34 */
+ UL_BEAM_TX, /* 35 */
+ MAX_TASK_NUM_G_NB /* 36 */
+} TaskTypeEnum;
+
+///defines the parameters that multi-tasks are generated.
+typedef struct
+{
+ /*! Indicate how many tasks of the generating type. 1 means that no task splitting. */
+ uint16_t nTaskNum;
+ /*! the parameter list for each splitted task */
+ void *pTaskExePara[MAX_TEST_SPLIT_NUM];
+} TaskPreGen;
+
+typedef enum
+{
+ RB_SPLIT = 0,
+ UE_GROUP_SPLIT = 1,
+ LAYER_SPLIT = 2,
+ UE_SPLIT = 3,
+ PORT_SPLIT = 4,
+ CE_RX_SPLIT = 5,
+ OFDM_SYMB_SPLIT = 6
+} TaskSplitType;
+
+typedef struct tSampleSplitStruct
+{
+ int16_t nGroupStart;
+ int16_t nGroupNum;
+ int16_t nUeStart;
+ int16_t nUeNum;
+ int16_t nSymbStart;
+ int16_t nSymbNum;
+ int16_t nLayerStart;
+ int16_t nLayerNum;
+ int16_t nSplitIndex;
+ TaskSplitType eSplitType;
+} SampleSplitStruct;
+
+typedef struct
+{
+ int32_t eventChainDepth;
+ int32_t nextEventChain[MAX_TASK_NUM_G_NB][MAX_NEXT_TASK_NUM];
+ int32_t nextEventCount[MAX_TASK_NUM_G_NB];
+ int32_t preEventCount[MAX_TASK_NUM_G_NB];
+ int32_t preEventCountSave[MAX_TASK_NUM_G_NB];
+ int32_t preEventStat[MAX_TASK_NUM_G_NB];
+} __attribute__((aligned(IA_ALIGN))) EventChainDescStruct;
+
+typedef void (*PreEventExeFunc) (uint32_t nSfIdx, uint16_t nCellIdx, TaskPreGen *pPara);
+
+typedef struct
+{
+ int32_t nEventId;
+ char sTaskName[32];
+ int32_t nEventPrio;
+ EventExeFunc pEventFunc;
+ PreEventExeFunc pPreEventFunc;
+ uint32_t nWakeOnExtrernalEvent;
+ uint32_t nPrefetchFlag;
+ uint32_t nCoreMaskType;
+ uint64_t nCoreMask0;
+ uint64_t nCoreMask1;
+ //uint64_t nCoreMask2;
+ //uint64_t nCoreMask3;
+ //uint64_t nCoreMask4;
+ //uint64_t nCoreMask5;
+ //uint64_t nCoreMask6;
+ //uint64_t nCoreMask7;
+} __attribute__((aligned(IA_ALIGN))) EventConfigStruct;
+
+typedef struct
+{
+ int32_t nEventId;
+ int32_t nSplitIdx;
+ int32_t nCellIdx;
+ int32_t nSlotIdx;
+ void *pTaskPara;
+ void *pHandler;
+ float *dummy0;
+ uint64_t tSendTime;
+ uint8_t nBuffer[240];
+} __attribute__((aligned(IA_ALIGN))) EventCtrlStruct;
+
+typedef struct
+{
+ int32_t nEventId;
+ int32_t nEventPrio;
+ EventExeFunc pEventFunc;
+} __attribute__((aligned(IA_ALIGN))) EventInfo;
+
+typedef struct
+{
+ int32_t nCellInd;
+ EventStruct *pEventStruct;
+ int16_t *pCEtp;
+ int16_t *pMIMOouttp;
+ int16_t *pWeighttp;
+} __attribute__((aligned(IA_ALIGN))) gNBCellStruct;
+
+extern EventChainDescStruct gEventChain[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX];
+extern EventCtrlStruct gEventCtrl[EBBU_POOL_MAX_TEST_CELL][MAX_TEST_CTX][MAX_TASK_NUM_G_NB][MAX_TEST_SPLIT_NUM];
+
+int32_t event_chain_gen(EventChainDescStruct *psEventChain);
+int32_t event_chain_reset(EventChainDescStruct *psEventChain);
+int32_t test_buffer_create();
+
+eBbuPoolHandler app_get_ebbu_pool_handler(void);
+
+int32_t app_bbu_init(int argc, char *argv[], char cfgName[512], UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg[],
+ uint64_t nActiveCoreMask[EBBUPOOL_MAX_CORE_MASK]);
+int32_t app_bbu_close(void);
+
+
+int32_t app_bbu_dl_tti_call_back(void * param);
+
+int32_t test_func_gen(eBbuPoolHandler pHandler, int32_t nCell, int32_t nSlot, int32_t eventId);
+int32_t next_event_unlock(void *pCookies);
+
+/** tasks */
+int32_t app_bbu_pool_task_dl_post(void *pCookies);
+void app_bbu_pool_pre_task_dl_post(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara);
+int32_t app_bbu_pool_task_dl_config(void *pCookies);
+void app_bbu_pool_pre_task_dl_cfg(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara);
+int32_t app_bbu_pool_task_ul_config(void * pCookies);
+void app_bbu_pool_pre_task_ul_cfg(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara);
+
+int32_t app_bbu_pool_task_sym2_wakeup(void *pCookies);
+int32_t app_bbu_pool_task_sym6_wakeup(void *pCookies);
+int32_t app_bbu_pool_task_sym11_wakeup(void *pCookies);
+int32_t app_bbu_pool_task_sym13_wakeup(void *pCookies);
+int32_t app_bbu_pool_task_prach_wakeup(void *pCookies);
+int32_t app_bbu_pool_task_srs_wakeup(void *pCookies);
+
+void app_io_xran_fh_bbu_rx_callback(void *pCallbackTag, xran_status_t status);
+void app_io_xran_fh_bbu_rx_bfw_callback(void *pCallbackTag, xran_status_t status);
+void app_io_xran_fh_bbu_rx_prach_callback(void *pCallbackTag, xran_status_t status);
+void app_io_xran_fh_bbu_rx_srs_callback(void *pCallbackTag, xran_status_t status);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*_APP_BBU_POOL_H_*/
\ No newline at end of file
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This module provides implementation of BBU tasks for sample app
+ * @file app_bbu.c
+ * @ingroup xran
+ * @author Intel Corporation
+ *
+ **/
+
+#include <unistd.h>
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <pthread.h>
+#include <immintrin.h>
+
+#include "common.h"
+#include "app_bbu_pool.h"
+#include "app_io_fh_xran.h"
+#include "xran_compression.h"
+#include "xran_cp_api.h"
+#include "xran_fh_o_du.h"
+#include "xran_mlog_task_id.h"
+
+extern RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM];
+static SampleSplitStruct gsDlPostSymbolTaskSplit[MAX_PHY_INSTANCES][MAX_NUM_OF_SF_5G_CTX][MAX_TEST_SPLIT_NUM];
+static SampleSplitStruct gsDlCfgAxCTaskSplit[MAX_PHY_INSTANCES][MAX_NUM_OF_SF_5G_CTX][MAX_TEST_SPLIT_NUM];
+
+void app_bbu_pool_pre_task_dl_post(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara)
+{
+ int32_t nSplitGroup = 0;
+ int32_t iTask = 0;
+ uint32_t nSfIdx = get_dl_sf_idx(nSubframe, nCellIdx);
+ uint32_t nCtxNum = get_dl_sf_ctx(nSfIdx, nCellIdx);
+ SampleSplitStruct *pTaskSplitPara;
+ int32_t nGroupNum = 0;
+ int32_t nSymbStart = 0, nSymbPerSplit = 0;
+ int32_t nTotalLayers = 0, nLayerStart = 0, nLayerPerSplit = 0;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config* pXranConf = NULL;
+ // struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ uint32_t nRuCcidx = 0;
+ int32_t xran_port = 0;
+
+ if(psXranIoIf == NULL)
+ rte_panic("psXranIoIf == NULL");
+
+ if(nCellIdx >= MAX_PHY_INSTANCES)
+ rte_panic("nCellIdx >= MAX_PHY_INSTANCES");
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return /*EBBUPOOL_CORRECT*/;
+ }
+
+ // psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ if(pXranConf == NULL)
+ rte_panic("pXranConf");
+
+ nTotalLayers = pXranConf->neAxc;
+ nSplitGroup = pXranConf->neAxc;
+
+ /* all symp per eAxC */
+ nSymbStart = 0;
+ // nTotalSymb = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ nSymbPerSplit = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+
+ nLayerPerSplit = nTotalLayers/nSplitGroup;
+
+ pPara->nTaskNum = nSplitGroup;
+ for (iTask = 0; iTask < (nSplitGroup-1) && iTask < (MAX_TEST_SPLIT_NUM-1); iTask ++)
+ {
+ pTaskSplitPara = &(gsDlPostSymbolTaskSplit[nCellIdx][nCtxNum][iTask]);
+ pTaskSplitPara->nSymbStart = nSymbStart;
+ pTaskSplitPara->nSymbNum = nSymbPerSplit;
+ pTaskSplitPara->eSplitType = LAYER_SPLIT;
+ pTaskSplitPara->nSplitIndex = iTask;
+ pTaskSplitPara->nGroupStart = 0;
+ pTaskSplitPara->nGroupNum = nGroupNum;
+ pTaskSplitPara->nLayerStart = nLayerStart;
+ pTaskSplitPara->nLayerNum = nLayerPerSplit;
+ pPara->pTaskExePara[iTask] = pTaskSplitPara;
+ //nSymbStart += nSymbPerSplit;
+ nLayerStart += nLayerPerSplit;
+ }
+
+ pTaskSplitPara = &(gsDlPostSymbolTaskSplit[nCellIdx][nCtxNum][iTask]);
+ pTaskSplitPara->nSymbStart = nSymbStart;
+ pTaskSplitPara->nSymbNum = nSymbPerSplit;
+ pTaskSplitPara->eSplitType = LAYER_SPLIT;
+ pTaskSplitPara->nSplitIndex = iTask;
+ pTaskSplitPara->nGroupStart = 0;
+ pTaskSplitPara->nGroupNum = nGroupNum;
+ pTaskSplitPara->nLayerStart = nLayerStart;
+ pTaskSplitPara->nLayerNum = nTotalLayers - nLayerStart;
+ pPara->pTaskExePara[iTask] = pTaskSplitPara;
+
+ return;
+}
+
+void app_bbu_pool_pre_task_dl_cfg(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara)
+{
+ int32_t nSplitGroup = 0;
+ int32_t iTask = 0;
+ uint32_t nSfIdx = get_dl_sf_idx(nSubframe, nCellIdx);
+ uint32_t nCtxNum = get_dl_sf_ctx(nSfIdx, nCellIdx);
+ SampleSplitStruct *pTaskSplitPara;
+ int32_t nGroupNum = 0;
+ int32_t nSymbStart = 0, nSymbPerSplit = 0;
+ int32_t nTotalLayers = 0, nLayerStart = 0, nLayerPerSplit = 0;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config* pXranConf = NULL;
+ // struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ uint32_t nRuCcidx = 0;
+ int32_t xran_port = 0;
+ uint32_t neAxc = 0;
+
+ if(psXranIoIf == NULL)
+ rte_panic("psXranIoIf == NULL");
+
+ if(nCellIdx >= MAX_PHY_INSTANCES)
+ rte_panic("nCellIdx >= MAX_PHY_INSTANCES");
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return /*EBBUPOOL_CORRECT*/;
+ }
+
+ // psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ if(pXranConf == NULL)
+ rte_panic("pXranConf");
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ if(pXranConf == NULL)
+ rte_panic("pXranConf");
+
+ if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_A){
+ neAxc = pXranConf->neAxc;
+ nSplitGroup = 1;
+ } else if (pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B) {
+ neAxc = pXranConf->neAxc;
+ nSplitGroup = neAxc;
+ } else
+ rte_panic("neAxc");
+
+ nTotalLayers = neAxc;
+
+ /* all symb per eAxC */
+ nSymbStart = 0;
+ nSymbPerSplit = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+
+ nLayerPerSplit = nTotalLayers/nSplitGroup;
+
+ pPara->nTaskNum = nSplitGroup;
+ for (iTask = 0; iTask < (nSplitGroup-1) && iTask < (MAX_TEST_SPLIT_NUM-1); iTask ++)
+ {
+ pTaskSplitPara = &(gsDlCfgAxCTaskSplit[nCellIdx][nCtxNum][iTask]);
+ pTaskSplitPara->nSymbStart = nSymbStart;
+ pTaskSplitPara->nSymbNum = nSymbPerSplit;
+ pTaskSplitPara->eSplitType = LAYER_SPLIT;
+ pTaskSplitPara->nSplitIndex = iTask;
+ pTaskSplitPara->nGroupStart = 0;
+ pTaskSplitPara->nGroupNum = nGroupNum;
+ pTaskSplitPara->nLayerStart = nLayerStart;
+ pTaskSplitPara->nLayerNum = nLayerPerSplit;
+ pPara->pTaskExePara[iTask] = pTaskSplitPara;
+ //nSymbStart += nSymbPerSplit;
+ nLayerStart += nLayerPerSplit;
+ }
+
+ pTaskSplitPara = &(gsDlCfgAxCTaskSplit[nCellIdx][nCtxNum][iTask]);
+ pTaskSplitPara->nSymbStart = nSymbStart;
+ pTaskSplitPara->nSymbNum = nSymbPerSplit;
+ pTaskSplitPara->eSplitType = LAYER_SPLIT;
+ pTaskSplitPara->nSplitIndex = iTask;
+ pTaskSplitPara->nGroupStart = 0;
+ pTaskSplitPara->nGroupNum = nGroupNum;
+ pTaskSplitPara->nLayerStart = nLayerStart;
+ pTaskSplitPara->nLayerNum = nTotalLayers - nLayerStart;
+ pPara->pTaskExePara[iTask] = pTaskSplitPara;
+
+ return;
+}
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup xran
+*
+* @param[in] pCookies task input parameter
+* @return 0 if SUCCESS
+*
+* @description
+* This function takes the DL Config from MAC and stores it into PHY Internal structures.
+* and initials the parameter of UL DCI.
+*
+**/
+//-------------------------------------------------------------------------------------------
+int32_t
+app_bbu_pool_task_dl_config(void *pCookies)
+{
+ EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint32_t nSfIdx = get_dl_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
+ uint32_t nCtxNum = get_dl_sf_ctx(nSfIdx, nCellIdx);
+ uint32_t mlogVariablesCnt, mlogVariables[50];
+ uint64_t mlog_start = MLogTick();
+ uint32_t nRuCcidx = 0;
+ int32_t xran_port = 0;
+ SampleSplitStruct *pTaskPara = (SampleSplitStruct*)pEventCtrl->pTaskPara;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config* pXranConf = NULL;
+ xran_status_t status;
+ struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ int32_t cc_id, ant_id, sym_id, tti;
+ int32_t flowId;
+ struct o_xu_buffers * p_iq = NULL;
+ int32_t nSymbMask = 0b11111111111111;
+ RuntimeConfig *p_o_xu_cfg = NULL;
+ uint16_t nLayerStart = 0, nLayer = 0;
+
+ if(psXranIoIf == NULL)
+ rte_panic("psXranIoIf == NULL");
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return EBBUPOOL_CORRECT;
+ }
+ psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ if(pXranConf == NULL)
+ rte_panic("pXranConf");
+
+ mlogVariablesCnt = 0;
+ mlogVariables[mlogVariablesCnt++] = 0xCCBBCCBB;
+ mlogVariables[mlogVariablesCnt++] = pEventCtrl->nSlotIdx;
+ mlogVariables[mlogVariablesCnt++] = 0;
+ mlogVariables[mlogVariablesCnt++] = nCellIdx;
+ mlogVariables[mlogVariablesCnt++] = nSfIdx;
+ mlogVariables[mlogVariablesCnt++] = nCtxNum;
+ mlogVariables[mlogVariablesCnt++] = xran_port;
+ mlogVariables[mlogVariablesCnt++] = nRuCcidx;
+
+ p_o_xu_cfg = p_startupConfiguration[xran_port];
+
+
+ mlog_start = MLogTick();
+
+ if(LAYER_SPLIT == pTaskPara->eSplitType) {
+ // iSplit = pTaskPara->nSplitIndex;
+ nLayerStart = pTaskPara->nLayerStart;
+ nLayer = pTaskPara->nLayerNum;
+ //printf("\nsf %d nSymbStart %d nSymb %d iSplit %d", nSfIdx, nSymbStart, nSymb, iSplit);
+ } else {
+ rte_panic("LAYER_SPLIT == pTaskPara->eSplitType");
+ }
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
+ }
+ tti = nSfIdx;
+ for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
+ if (cc_id >= XRAN_MAX_SECTOR_NR)
+ {
+ rte_panic("cell id %d exceeding max number", cc_id);
+ }
+ for(ant_id = nLayerStart; ant_id < (nLayerStart + nLayer); ant_id++) {
+ if(p_o_xu_cfg->appMode == APP_O_DU) {
+ flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
+ } else {
+ flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(((1 << sym_id) & nSymbMask)) {
+ if ((status = app_io_xran_iq_content_init_cp_tx(p_o_xu_cfg->appMode, pXranConf,
+ psXranIoIf, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_init_cp_tx");
+ }
+ }
+ }
+ }
+ }
+
+ xran_prepare_cp_dl_slot(xran_port, nSfIdx, nRuCcidx, /*psXranIoIf->num_cc_per_port[xran_port]*/ 1, nSymbMask, nLayerStart,
+ nLayer, 0, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+
+ if (mlogVariablesCnt)
+ MLogAddVariables((uint32_t)mlogVariablesCnt, (uint32_t *)mlogVariables, mlog_start);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PCID_GNB_DL_CFG_CC0+nCellIdx, mlog_start, MLogTick());
+
+ return EBBUPOOL_CORRECT;
+}
+
+int32_t
+app_io_xran_dl_pack_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
+ uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
+{
+ xran_status_t status;
+ uint32_t nSlotIdx = get_dl_sf_idx(nSfIdx, nCellIdx);
+ // struct xran_io_shared_ctrl * psBbuXranIo = NULL;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct o_xu_buffers * p_iq = NULL;
+ RuntimeConfig *p_o_xu_cfg = NULL;
+ int32_t flowId = 0;
+ struct xran_fh_config *pXranConf = NULL;
+ int32_t cc_id, ant_id, sym_id, tti;
+ struct xran_io_shared_ctrl *psIoCtrl = NULL;
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0)
+ {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+
+ if(psIoCtrl == NULL) {
+ printf("psIoCtrl == NULL\n");
+ return FAILURE;
+ }
+
+ p_o_xu_cfg = p_startupConfiguration[xran_port];
+ if(p_o_xu_cfg == NULL) {
+ printf("p_o_xu_cfg == NULL\n");
+ return FAILURE;
+ }
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+
+ tti = nSlotIdx;
+ for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
+ for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < pXranConf->neAxc; ant_id++) {
+ if(p_o_xu_cfg->appMode == APP_O_DU) {
+ flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
+ } else {
+ flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(((1 << sym_id) & nSymMask)) {
+ if ((status = app_io_xran_iq_content_init_up_tx(p_o_xu_cfg->appMode, pXranConf,
+ psXranIoIf, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_init_up_tx");
+ }
+ }
+ }
+ }
+ }
+
+ xran_prepare_up_dl_sym(xran_port, nSlotIdx, nRuCcidx, 1, nSymMask, nAntStart, nAntNum, nSymStart, nSymNum);
+ return SUCCESS;
+}
+
+int32_t
+app_io_xran_dl_post_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask, uint32_t nAntStart, uint32_t nAntNum)
+{
+ uint16_t phyInstance = nCellIdx;
+ // uint32_t Ntx_antennas;
+ uint16_t nOranCellIdx;
+
+ uint64_t tTotal = MLogTick();
+ // struct xran_io_shared_ctrl * psBbuXranIo = NULL;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ // struct xran_fh_config *pXranConf = NULL;
+
+ nSymMask = nSymMask + 0;
+
+ nOranCellIdx = nCellIdx;
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ // pXranConf = &app_io_xran_fh_config[xran_port];
+// Ntx_antennas = pXranConf->neAxc;
+
+ app_io_xran_dl_pack_func(nCellIdx, nSfIdx, nSymMask, nAntStart, nAntNum, 0, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+
+ MLogTask(PCID_GNB_DL_IQ_COMPRESS_CC0 + phyInstance, tTotal, MLogTick());
+
+ return SUCCESS;
+}
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_nr5g_source_phy_pdsch
+*
+* @param[in] pCookies task input parameter
+* @return 0 if SUCCESS
+*
+* @description
+* This function will reset phy dl buffers.
+*
+**/
+//-------------------------------------------------------------------------------------------
+int32_t app_bbu_pool_task_dl_post(void *pCookies)
+{
+ EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint32_t nSfIdx = get_dl_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
+ SampleSplitStruct *pTaskPara = (SampleSplitStruct*)pEventCtrl->pTaskPara;
+ uint16_t nSymbStart = 0, nSymb = 0, iOfdmSymb = 0, iSplit = 0;
+ uint32_t nSymMask = 0;
+ uint64_t mlog_start;
+ uint32_t mlogVar[10];
+ uint32_t mlogVarCnt = 0;
+ uint16_t nLayerStart = 0, nLayer = 0;
+ mlog_start = MLogTick();
+
+ if(LAYER_SPLIT == pTaskPara->eSplitType) {
+ nSymbStart = pTaskPara->nSymbStart;
+ nSymb = pTaskPara->nSymbNum;
+ iSplit = pTaskPara->nSplitIndex;
+ nLayerStart = pTaskPara->nLayerStart;
+ nLayer = pTaskPara->nLayerNum;
+ //printf("\nsf %d nSymbStart %d nSymb %d iSplit %d", nSfIdx, nSymbStart, nSymb, iSplit);
+ } else if(OFDM_SYMB_SPLIT == pTaskPara->eSplitType) {
+ nSymbStart = pTaskPara->nSymbStart;
+ nSymb = pTaskPara->nSymbNum;
+ iSplit = pTaskPara->nSplitIndex;
+ rte_panic("\nsf %d nSymbStart %d nSymb %d iSplit %d", nSfIdx, nSymbStart, nSymb, iSplit);
+ } else {
+ rte_panic("OFDM_SYMB_SPLIT == pTaskPara->eSplitType");
+ }
+
+ // This is the loop of real OFDM symbol index
+ for(iOfdmSymb = nSymbStart; iOfdmSymb < (nSymbStart + nSymb); iOfdmSymb ++)
+ nSymMask |= (1 << iOfdmSymb);
+
+ app_io_xran_dl_post_func(pEventCtrl->nCellIdx, pEventCtrl->nSlotIdx, /*0x3FFF*/ nSymMask, nLayerStart, nLayer);
+
+#if 1
+ {
+ mlogVar[mlogVarCnt++] = 0xefefefef;
+ mlogVar[mlogVarCnt++] = nCellIdx;
+ mlogVar[mlogVarCnt++] = nSfIdx;
+ mlogVar[mlogVarCnt++] = nSymbStart;
+ mlogVar[mlogVarCnt++] = nSymb;
+ mlogVar[mlogVarCnt++] = nLayerStart;
+ mlogVar[mlogVarCnt++] = nLayer;
+ mlogVar[mlogVarCnt++] = iSplit;
+ MLogAddVariables(mlogVarCnt, mlogVar, mlog_start);
+ }
+#endif
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+
+ MLogTask(PCID_GNB_DL_POST_CC0+nCellIdx, mlog_start, MLogTick());
+ return EBBUPOOL_CORRECT;
+}
+
#include "xran_mlog_lnx.h"
#include "xran_fh_o_du.h"
+#include "xran_fh_o_ru.h"
#include "xran_compression.h"
#include "xran_cp_api.h"
#include "xran_sync_api.h"
#include "xran_mlog_task_id.h"
#include "app_io_fh_xran.h"
-
+#ifdef FWK_ENABLED
+#include "app_bbu_pool.h"
+#endif
/* buffers size */
uint32_t nFpgaToSW_FTH_RxBufferLen;
uint32_t nFpgaToSW_PRACH_RxBufferLen;
void app_io_xran_fh_rx_prach_callback(void *pCallbackTag, int32_t status);
void app_io_xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status);
+#ifndef FWK_ENABLED
+void app_io_xran_fh_bbu_rx_callback(void *pCallbackTag, xran_status_t status);
+void app_io_xran_fh_bbu_rx_bfw_callback(void *pCallbackTag, xran_status_t status);
+void app_io_xran_fh_bbu_rx_prach_callback(void *pCallbackTag, xran_status_t status);
+void app_io_xran_fh_bbu_rx_srs_callback(void *pCallbackTag, xran_status_t status);
+#endif
+
+extern RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM];
+
struct bbu_xran_io_if *
app_io_xran_if_alloc(void)
{
uint32_t nSlotIdx;
uint64_t nSecond;
- uint32_t nXranTime = xran_get_slot_idx(0, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ /*uint32_t nXranTime = */xran_get_slot_idx(0, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf
+ nSubframeIdx*nNrOfSlotInSf
+ nSlotIdx;
uint64_t t1 = MLogTick();
uint32_t mlogVar[10];
uint32_t mlogVarCnt = 0;
- uint8_t Numerlogy = app_io_xran_fh_config[0].frame_conf.nNumerology;
- uint8_t nNrOfSlotInSf = 1<<Numerlogy;
- int32_t sfIdx = app_io_xran_sfidx_get(nNrOfSlotInSf);
+ //uint8_t Numerlogy = app_io_xran_fh_config[0].frame_conf.nNumerology;
+ //uint8_t nNrOfSlotInSf = 1<<Numerlogy;
+ //int32_t sfIdx = app_io_xran_sfidx_get(nNrOfSlotInSf);
int32_t nCellIdx;
- int32_t sym, nSlotIdx;
- uint64_t mlog_start, mlog_end;
+ int32_t sym, nSlotIdx, ntti;
+ uint64_t mlog_start;
struct xran_cb_tag *pTag = (struct xran_cb_tag *) pCallbackTag;
+ int32_t o_xu_id = pTag->oXuId;
+ struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
+ struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
+ uint32_t xran_max_antenna_nr = RTE_MAX(pXranConf->neAxc, pXranConf->neAxcUl);
+ //int32_t nSectorNum = pXranConf->nCC;
+ uint32_t ant_id, sym_id, idxElm;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
mlog_start = MLogTick();
nCellIdx = pTag->cellId;
nSlotIdx = pTag->slotiId; ///((status >> 16) & 0xFFFF); /** TTI aka slotIdx */
sym = pTag->symbol & 0xFF; /* sym */
+ ntti = (nSlotIdx + XRAN_N_FE_BUF_LEN -1) % XRAN_N_FE_BUF_LEN;
{
mlogVar[mlogVarCnt++] = 0xbcbcbcbc;
+ mlogVar[mlogVarCnt++] = o_xu_id;
mlogVar[mlogVarCnt++] = nCellIdx;
mlogVar[mlogVarCnt++] = sym;
mlogVar[mlogVarCnt++] = nSlotIdx;
+ mlogVar[mlogVarCnt++] = ntti;
//mlogVar[mlogVarCnt++] = nSlotIdx % gNumSlotPerSfn[nCellIdx];
//mlogVar[mlogVarCnt++] = get_slot_type(nCellIdx, nSlotIdx, SLOT_TYPE_UL);
MLogAddVariables(mlogVarCnt, mlogVar, mlog_start);
}
+ if(psIoCtrl == NULL)
+ {
+ printf("psIoCtrl NULL! o_xu_id= %d\n", o_xu_id);
+ return;
+ }
+
+ if (sym == XRAN_HALF_CB_SYM) {
+ // 1/4 of slot
+ } else if (sym == XRAN_HALF_CB_SYM) {
+ // First Half
+ } else if (sym == XRAN_THREE_FOURTHS_CB_SYM) {
+ // 2/4 of slot
+ } else if (sym == XRAN_FULL_CB_SYM) {
+ // Second Half
+ } else {
+ /* error */
+ MLogTask(PID_GNB_SYM_CB, t1, MLogTick());
+ return;
+ }
+
+ if(sym == XRAN_FULL_CB_SYM) //full slot callback only
+ {
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[ntti][nCellIdx][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL){
+ printf("(%d:%d:%d)pRbMap == NULL\n", nCellIdx, ntti, ant_id);
+ exit(-1);
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
+ pRbElm = &pRbMap->prbMap[idxElm];
+ pRbElm->nSecDesc[sym_id] = 0;
+ }
+ }
+ }
+ }
+
rte_pause();
MLogTask(PID_GNB_SYM_CB, t1, MLogTick());
void
app_io_xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status)
+{
+ uint64_t t1 = MLogTick();
+ uint32_t mlogVar[10];
+ uint32_t mlogVarCnt = 0;
+ //uint8_t Numerlogy = app_io_xran_fh_config[0].frame_conf.nNumerology;
+ //uint8_t nNrOfSlotInSf = 1<<Numerlogy;
+ //int32_t sfIdx = app_io_xran_sfidx_get(nNrOfSlotInSf);
+ int32_t nCellIdx;
+ int32_t sym, nSlotIdx, ntti;
+ struct xran_cb_tag *pTag = (struct xran_cb_tag *) pCallbackTag;
+ int32_t o_xu_id = pTag->oXuId;
+ struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
+ struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
+ uint32_t xran_max_antenna_nr = RTE_MAX(pXranConf->neAxc, pXranConf->neAxcUl);
+ //int32_t nSectorNum = pXranConf->nCC;
+ uint32_t ant_id, sym_id, idxElm;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(pXranConf->nAntElmTRx, xran_max_antenna_nr);
+
+ nCellIdx = pTag->cellId;
+ nSlotIdx = pTag->slotiId; ///((status >> 16) & 0xFFFF); /** TTI aka slotIdx */
+ sym = pTag->symbol & 0xFF; /* sym */
+ ntti = (nSlotIdx + XRAN_N_FE_BUF_LEN-1) % XRAN_N_FE_BUF_LEN;
+
+ {
+ mlogVar[mlogVarCnt++] = 0xCCCCCCCC;
+ mlogVar[mlogVarCnt++] = o_xu_id;
+ mlogVar[mlogVarCnt++] = nCellIdx;
+ mlogVar[mlogVarCnt++] = sym;
+ mlogVar[mlogVarCnt++] = nSlotIdx;
+ mlogVar[mlogVarCnt++] = ntti;
+ MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
+ }
+
+ if(psIoCtrl == NULL)
+ {
+ printf("psIoCtrl NULL! o_xu_id= %d\n", o_xu_id);
+ return;
+ }
+
+ if(sym == XRAN_FULL_CB_SYM) { //full slot callback only
+ for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++) {
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[ntti][nCellIdx][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL){
+ printf("(%d:%d:%d)pRbMap == NULL\n", nCellIdx, ntti, ant_id);
+ exit(-1);
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
+ pRbElm = &pRbMap->prbMap[idxElm];
+ pRbElm->nSecDesc[sym_id] = 0;
+ }
+ }
+ }
+ }
+ MLogTask(PID_GNB_SRS_CB, t1, MLogTick());
+}
+
+void
+app_io_xran_fh_rx_bfw_callback(void *pCallbackTag, xran_status_t status)
{
uint64_t t1 = MLogTick();
uint32_t mlogVar[10];
MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
rte_pause();
- MLogTask(PID_GNB_SRS_CB, t1, MLogTick());
+ MLogTask(PID_GNB_BFW_CB, t1, MLogTick());
}
-
int32_t
app_io_xran_dl_tti_call_back(void * param)
{
return 0;
}
+uint32_t
+NEXT_POW2 ( uint32_t x )
+{
+ uint32_t value = 1 ;
+ while ( value <= x)
+ value = value << 1;
+
+ return value ;
+}
+
int32_t
-app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg)
+app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg, struct xran_fh_init* p_xran_fh_init)
{
xran_status_t status;
struct bbu_xran_io_if *psBbuIo = app_io_xran_if_get();
struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
int32_t nSectorNum;
- int32_t i, j, k, m, z;
+ int32_t i, j, k = 0, z;
void *ptr;
void *mb;
+ void *ring;
uint32_t *u32dptr;
- uint16_t *u16dptr;
- uint8_t *u8dptr;
uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
uint32_t xran_max_sections_per_slot = RTE_MAX(p_o_xu_cfg->max_sections_per_slot, XRAN_MIN_SECTIONS_PER_SLOT);
- uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm)*(xran_max_sections_per_slot - 1);
+ uint32_t xran_max_prb = app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number,p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA);
+ uint32_t numPrbElm = xran_get_num_prb_elm(p_o_xu_cfg->p_PrbMapDl, p_o_xu_cfg->mtu);
+ uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm)*(numPrbElm);
+ uint32_t xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
SWXRANInterfaceTypeEnum eInterfaceType;
struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
struct xran_buffer_list *pFthRxSrsPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
+ struct xran_buffer_list *pFthRxCpPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
+ struct xran_buffer_list *pFthTxCpPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
+
if(psBbuIo == NULL)
rte_panic("psBbuIo == NULL\n");
nSectorIndex[nSectorNum] = nSectorNum;
}
+ nSectorNum = p_o_xu_cfg->numCC;
+
+ if(o_xu_id == 0) {
+ psBbuIo->num_o_ru = p_use_cfg->oXuNum;
+ psBbuIo->bbu_offload = p_xran_fh_init->io_cfg.bbu_offload;
+ }
+
+ psIoCtrl->byteOrder = XRAN_NE_BE_BYTE_ORDER;
+ psIoCtrl->iqOrder = XRAN_I_Q_ORDER;
+
+ for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
+ {
+ nSectorIndex[nSectorNum] = nSectorNum;
+ }
+
+ if(p_use_cfg->oXuNum > 1 && p_use_cfg->oXuNum <= XRAN_PORTS_NUM) {
+ nSectorNum = p_o_xu_cfg->numCC;
+ psBbuIo->num_cc_per_port[o_xu_id] = p_o_xu_cfg->numCC;
+ printf("port %d has %d CCs\n",o_xu_id, psBbuIo->num_cc_per_port[o_xu_id]);
+ for(i = 0; i < XRAN_MAX_SECTOR_NR && i < nSectorNum; i++) {
+ psBbuIo->map_cell_id2port[o_xu_id][i] = (o_xu_id*nSectorNum)+i;
+ printf("port %d cc_id %d is phy id %d\n", o_xu_id, i, psBbuIo->map_cell_id2port[o_xu_id][i]);
+ }
+ }
+ else {
+ nSectorNum = p_o_xu_cfg->numCC;;
+ psBbuIo->num_cc_per_port[o_xu_id] = nSectorNum;
+ printf("port %d has %d CCs\n",o_xu_id, psBbuIo->num_cc_per_port[o_xu_id]);
+ for(i = 0; i < XRAN_MAX_SECTOR_NR && i < nSectorNum; i++) {
+ psBbuIo->map_cell_id2port[o_xu_id][i] = i;
+ printf("port %d cc_id %d is phy id %d\n", o_xu_id, i, psBbuIo->map_cell_id2port[o_xu_id][i]);
+ }
+ }
+
nSectorNum = p_o_xu_cfg->numCC;
printf ("XRAN front haul xran_mm_init \n");
status = xran_mm_init (app_io_xran_handle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);
psBbuIo->nInstanceNum[o_xu_id] = p_o_xu_cfg->numCC;
if (o_xu_id < XRAN_PORTS_NUM) {
- status = xran_sector_get_instances (o_xu_id, app_io_xran_handle, psBbuIo->nInstanceNum[o_xu_id], &psBbuIo->nInstanceHandle[o_xu_id][0]);
+ status = xran_sector_get_instances (o_xu_id, app_io_xran_handle,
+ psBbuIo->nInstanceNum[o_xu_id],
+ &psBbuIo->nInstanceHandle[o_xu_id][0]);
if (status != XRAN_STATUS_SUCCESS) {
- printf ("get sector instance failed %d for XRAN nInstanceNum[%d] %d\n",k, psBbuIo->nInstanceNum[o_xu_id], o_xu_id);
+ printf ("get sector instance failed for XRAN nInstanceNum[%d] %d\n",psBbuIo->nInstanceNum[o_xu_id], o_xu_id);
exit(-1);
}
for (i = 0; i < psBbuIo->nInstanceNum[o_xu_id]; i++) {
- printf("%s [%d]: CC %d handle %p\n", __FUNCTION__, k, i, psBbuIo->nInstanceHandle[o_xu_id][i]);
+ printf("%s: CC %d handle %p\n", __FUNCTION__, i, psBbuIo->nInstanceHandle[o_xu_id][i]);
}
} else {
printf ("Failed at XRAN front haul xran_mm_init \n");
eInterfaceType = XRANFTHTX_OUT;
printf("nSectorIndex[%d] = %d\n",i, nSectorIndex[i]);
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, nSW_ToFpga_FTH_TxBufferLen);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init , status %d\n", status);
}
// ptr_temp[2] = z; // Ant
// ptr_temp[3] = k; // sym
}
+ if(psBbuIo->bbu_offload){
+ status = xran_bm_allocate_ring(psBbuIo->nInstanceHandle[o_xu_id][i], "TXO", i, j, z, k, &ring);
+ if(XRAN_STATUS_SUCCESS != status){
+ rte_panic("Failed at xran_bm_allocate_ring , status %d\n",status);
+ }
+ psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pRing = (void *)ring;
}
}
}
-
- /* C-plane DL */
- eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*xran_max_sections_per_slot*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc));
- if(XRAN_STATUS_SUCCESS != status) {
- rte_panic("Failed at xran_bm_init , status %d\n", status);
}
+ /* C-plane DL */
printf("size_of_prb_map %d\n", size_of_prb_map);
eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map);
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, size_of_prb_map);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init , status %d\n", status);
}
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulTxPrbMapBuffers[j][i][z];
- {
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map;
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
if(ptr){
- void *sd_ptr;
- void *sd_mb;
- int32_t elm_id;
struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
+ memset(p_rb_map, 0, size_of_prb_map);
if (p_o_xu_cfg->appMode == APP_O_DU) {
if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
- memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map);
+ if(p_o_xu_cfg->RunSlotPrbMapBySymbolEnable){
+ xran_init_PrbMap_by_symbol_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], ptr, p_o_xu_cfg->mtu, xran_max_prb);
+ }
+ else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], ptr, p_o_xu_cfg->mtu);
+ }
} else {
- memcpy(ptr, p_o_xu_cfg->p_PrbMapDl, size_of_prb_map);
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_PrbMapDl, ptr, p_o_xu_cfg->mtu);
}
} else {
if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
- memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], size_of_prb_map);
- } else {
- memcpy(ptr, p_o_xu_cfg->p_PrbMapUl, size_of_prb_map);
- }
- }
-
- for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
- struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
- for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
- for(m = 0; m < XRAN_MAX_FRAGMENT; m++){
- status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT],&sd_ptr, &sd_mb);
- if(XRAN_STATUS_SUCCESS != status){
- rte_panic("SD Failed at DESC_OUT xran_bm_allocate_buffer , m %d k %d elm_id %d\n",m,k, elm_id);
- }
- pPrbElem->p_sec_desc[k][m] = sd_ptr;
- memset(sd_ptr,0,sizeof(struct xran_section_desc));
+ if(p_o_xu_cfg->RunSlotPrbMapBySymbolEnable){
+ xran_init_PrbMap_by_symbol_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], ptr, p_o_xu_cfg->mtu, xran_max_prb);
}
+ else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], ptr, p_o_xu_cfg->mtu);
}
+ } else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_PrbMapUl, ptr, p_o_xu_cfg->mtu);
}
}
}
for(i = 0; i<nSectorNum; i++)
{
eInterfaceType = XRANFTHRX_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
+ status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, nSW_ToFpga_FTH_TxBufferLen);
if(XRAN_STATUS_SUCCESS != status)
{
printf("Failed at xran_bm_init, status %d\n", status);
psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb;
if(ptr){
u32dptr = (uint32_t*)(ptr);
- uint8_t *ptr_temp = (uint8_t *)ptr;
+ //uint8_t *ptr_temp = (uint8_t *)ptr;
memset(u32dptr, 0x0, nFpgaToSW_FTH_RxBufferLen);
// ptr_temp[0] = j; // TTI
// ptr_temp[1] = i; // Sec
}
/* C-plane */
- eInterfaceType = XRANFTHTX_SEC_DESC_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*xran_max_sections_per_slot*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc));
- if(XRAN_STATUS_SUCCESS != status) {
- rte_panic("Failed at xran_bm_init , status %d\n", status);
- }
eInterfaceType = XRANFTHRX_PRB_MAP_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map);
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, size_of_prb_map);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulRxPrbMapBuffers[j][i][z];
- {
+
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
if(ptr){
- void *sd_ptr;
- void *sd_mb;
- int32_t elm_id;
struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
+ memset(p_rb_map, 0, size_of_prb_map);
if (p_o_xu_cfg->appMode == APP_O_DU) {
if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
- memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], size_of_prb_map);
+ if(p_o_xu_cfg->RunSlotPrbMapBySymbolEnable){
+ xran_init_PrbMap_by_symbol_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], ptr, p_o_xu_cfg->mtu, xran_max_prb);
+ }
+ else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], ptr, p_o_xu_cfg->mtu);
+ }
} else {
- memcpy(ptr, p_o_xu_cfg->p_PrbMapUl, size_of_prb_map);
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_PrbMapUl, ptr, p_o_xu_cfg->mtu);
}
} else {
if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
+ if(p_o_xu_cfg->RunSlotPrbMapBySymbolEnable){
+ xran_init_PrbMap_by_symbol_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], ptr, p_o_xu_cfg->mtu, xran_max_prb);
+ }
+ else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], ptr, p_o_xu_cfg->mtu);
+ }
+ } else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_PrbMapDl, ptr, p_o_xu_cfg->mtu);
+ }
+ }
+ }
+ }
+ }
+
+ if(p_o_xu_cfg->appMode == APP_O_RU){
+ /* C-plane Rx */
+ eInterfaceType = XRANCP_PRB_MAP_IN_RX;
+ status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
+ XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map);
+ if(XRAN_STATUS_SUCCESS != status) {
+ rte_panic("Failed at xran_bm_init, status %d\n", status);
+ }
+
+ for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
+ for(z = 0; z < xran_max_antenna_nr; z++){
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulCpRxPrbMapBbuIoBufCtrl[j][i][z];
+
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
+ status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb);
+ if(XRAN_STATUS_SUCCESS != status) {
+ rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
+ }
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
+
+ if(ptr){
+ struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
+ memset(p_rb_map, 0, size_of_prb_map);
+
+ if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map);
} else {
memcpy(ptr, p_o_xu_cfg->p_PrbMapDl, size_of_prb_map);
}
}
+ }
+ }
- for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
- struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
- for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
- for(m = 0; m < XRAN_MAX_FRAGMENT; m++){
- status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN],&sd_ptr, &sd_mb);
+
+/* C-plane Tx */
+ eInterfaceType = XRANCP_PRB_MAP_IN_TX;
+ status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, size_of_prb_map);
if(XRAN_STATUS_SUCCESS != status){
- rte_panic("SD Failed at DESC_IN xran_bm_allocate_buffer , m %d k %d\n",m,k);
- }
- pPrbElem->p_sec_desc[k][m] = sd_ptr;
- memset(sd_ptr,0,sizeof(struct xran_section_desc));
+ rte_panic("Failed at xran_bm_init, status %d\n", status);
}
+
+ for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
+ for(z = 0; z < xran_max_antenna_nr; z++){
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulCpTxPrbMapBbuIoBufCtrl[j][i][z];
+
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
+ status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb);
+ if(XRAN_STATUS_SUCCESS != status) {
+ rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
}
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
+ if(ptr){
+ struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
+ memset(p_rb_map, 0, size_of_prb_map);
+
+ if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
+ memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map);
+ } else {
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_PrbMapDl, ptr, p_o_xu_cfg->mtu);
}
}
}
for(i = 0; i<nSectorNum; i++)
{
eInterfaceType = XRANFTHRACH_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],&psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, PRACH_PLAYBACK_BUFFER_BYTES);
+ status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],&psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_antenna_nr_prach*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, PRACH_PLAYBACK_BUFFER_BYTES);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
{
- for(z = 0; z < xran_max_antenna_nr; z++){
+ for(z = 0; z < xran_max_antenna_nr_prach; z++){
psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
- psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr; // ant number.
+ psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr_prach; // ant number.
psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHPrachRxBuffers[j][i][z][0];
psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHPrachRxBuffersDecomp[j][i][z][0];
for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
for(i = 0; i<nSectorNum && xran_max_ant_array_elm_nr; i++) {
eInterfaceType = XRANSRS_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],&psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT)-1, nSW_ToFpga_FTH_TxBufferLen);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
/* SRS C-plane */
- eInterfaceType = XRANSRS_SEC_DESC_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*xran_max_sections_per_slot*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc));
- if(XRAN_STATUS_SUCCESS != status) {
- rte_panic("Failed at xran_bm_init , status %d\n", status);
- }
eInterfaceType = XRANSRS_PRB_MAP_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map);
+ NEXT_POW2(XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT)-1, size_of_prb_map);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHSrsRxPrbMapBuffers[j][i][z];
- {
+
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map;
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
if(ptr) {
- void *sd_ptr;
- void *sd_mb;
- int32_t elm_id;
struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
+ memset(p_rb_map, 0, size_of_prb_map);
if (p_o_xu_cfg->appMode == APP_O_DU) {
if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
if(p_o_xu_cfg->RunSlotPrbMapEnabled) {
memcpy(ptr, p_o_xu_cfg->p_RunSrsSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map);
} else {
- memcpy(ptr, p_o_xu_cfg->p_PrbMapSrs, size_of_prb_map);
+ //memcpy(ptr, p_o_xu_cfg->p_PrbMapSrs, size_of_prb_map);
+ xran_init_PrbMap_from_cfg(p_o_xu_cfg->p_PrbMapSrs, ptr, p_o_xu_cfg->mtu);
}
}
-
- for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
- struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
- for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
- for(m = 0; m < XRAN_MAX_FRAGMENT; m++){
- status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][XRANSRS_SEC_DESC_IN],&sd_ptr, &sd_mb);
- if(XRAN_STATUS_SUCCESS != status){
- rte_panic("SD Failed at SRS_SEC_DESC_IN xran_bm_allocate_buffer , m %d k %d\n",m,k);
- }
- pPrbElem->p_sec_desc[k][m] = sd_ptr;
- memset(sd_ptr,0,sizeof(struct xran_section_desc));
- }
- }
- }
- }
}
}
}
pFthRxPrbMapBuffer[i][z][j] = NULL;
pFthRxRachBuffer[i][z][j] = NULL;
pFthRxRachBufferDecomp[i][z][j] = NULL;
+ pFthRxCpPrbMapBuffer[i][z][j] = NULL;
+ pFthTxCpPrbMapBuffer[i][z][j] = NULL;
}
for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
pFthRxSrsBuffer[i][z][j] = NULL;
pFthRxPrbMapBuffer[i][z][j] = &(psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxRachBuffer[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxRachBufferDecomp[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList);
+ pFthRxCpPrbMapBuffer[i][z][j] = &(psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
+ pFthTxCpPrbMapBuffer[i][z][j] = &(psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
}
for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR && xran_max_ant_array_elm_nr; z++){
/* add pusch callback */
for (i = 0; i<nSectorNum; i++)
{
+ psBbuIo->RxCbTag[o_xu_id][i].oXuId = o_xu_id;
psBbuIo->RxCbTag[o_xu_id][i].cellId = i;
psBbuIo->RxCbTag[o_xu_id][i].symbol = 0;
psBbuIo->RxCbTag[o_xu_id][i].slotiId = 0;
+ if(psBbuIo->bbu_offload)
+ xran_5g_fronthault_config (psBbuIo->nInstanceHandle[o_xu_id][i],
+ pFthTxBuffer[i],
+ pFthTxPrbMapBuffer[i],
+ pFthRxBuffer[i],
+ pFthRxPrbMapBuffer[i],
+ app_io_xran_fh_bbu_rx_callback, &psBbuIo->RxCbTag[o_xu_id][i]);
+ else
xran_5g_fronthault_config (psBbuIo->nInstanceHandle[o_xu_id][i],
pFthTxBuffer[i],
pFthTxPrbMapBuffer[i],
pFthRxPrbMapBuffer[i],
app_io_xran_fh_rx_callback, &psBbuIo->RxCbTag[o_xu_id][i]);
}
+ /* add BFWs callback here */
+ for (i = 0; i<nSectorNum; i++) {
+ psBbuIo->BfwCbTag[o_xu_id][i].cellId = o_xu_id;
+ psBbuIo->BfwCbTag[o_xu_id][i].cellId = i;
+ psBbuIo->BfwCbTag[o_xu_id][i].symbol = 0;
+ psBbuIo->BfwCbTag[o_xu_id][i].slotiId = 0;
+#if 0
+ if(psBbuIo->bbu_offload)
+ xran_5g_bfw_config(psBbuIo->nInstanceHandle[o_xu_id][i],
+ pFthRxCpPrbMapBuffer[i],
+ pFthTxCpPrbMapBuffer[i],
+ app_io_xran_fh_bbu_rx_bfw_callback,&psBbuIo->BfwCbTag[o_xu_id][i]);
+ else
+#endif
+ xran_5g_bfw_config(psBbuIo->nInstanceHandle[o_xu_id][i],
+ pFthRxCpPrbMapBuffer[i],
+ pFthTxCpPrbMapBuffer[i],
+ app_io_xran_fh_rx_bfw_callback,&psBbuIo->BfwCbTag[o_xu_id][i]);
+ }
/* add prach callback here */
for (i = 0; i<nSectorNum; i++)
{
+ psBbuIo->PrachCbTag[o_xu_id][i].oXuId = o_xu_id;
psBbuIo->PrachCbTag[o_xu_id][i].cellId = i;
psBbuIo->PrachCbTag[o_xu_id][i].symbol = 0;
psBbuIo->PrachCbTag[o_xu_id][i].slotiId = 0;
+ if(psBbuIo->bbu_offload)
+ xran_5g_prach_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxRachBuffer[i],pFthRxRachBufferDecomp[i],
+ app_io_xran_fh_bbu_rx_prach_callback,&psBbuIo->PrachCbTag[o_xu_id][i]);
+ else
xran_5g_prach_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxRachBuffer[i],pFthRxRachBufferDecomp[i],
app_io_xran_fh_rx_prach_callback,&psBbuIo->PrachCbTag[o_xu_id][i]);
}
/* add SRS callback here */
for (i = 0; i<nSectorNum && xran_max_ant_array_elm_nr; i++) {
+ psBbuIo->SrsCbTag[o_xu_id][i].oXuId = o_xu_id;
psBbuIo->SrsCbTag[o_xu_id][i].cellId = i;
psBbuIo->SrsCbTag[o_xu_id][i].symbol = 0;
psBbuIo->SrsCbTag[o_xu_id][i].slotiId = 0;
+ if(psBbuIo->bbu_offload)
+ xran_5g_srs_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxSrsBuffer[i], pFthRxSrsPrbMapBuffer[i],
+ app_io_xran_fh_bbu_rx_srs_callback,&psBbuIo->SrsCbTag[o_xu_id][i]);
+ else
xran_5g_srs_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxSrsBuffer[i], pFthRxSrsPrbMapBuffer[i],
app_io_xran_fh_rx_srs_callback,&psBbuIo->SrsCbTag[o_xu_id][i]);
}
}
int32_t
-app_io_xran_ext_type11_populate(struct xran_prb_elm* p_pRbMapElm, int16_t *p_tx_dl_bfw_buffer, uint32_t mtu)
+app_io_xran_ext_type1_populate(struct xran_prb_elm* p_pRbMapElm, char *p_bfw_buffer, uint32_t mtu, uint16_t* numSetBFW_total)
+{
+ xran_status_t status = XRAN_STATUS_SUCCESS;
+
+ int16_t ext_len;
+ int16_t ext_sec_total = 0;
+ int8_t * ext_buf = NULL;
+ int8_t * ext_buf_start = NULL;
+
+ ext_len = p_pRbMapElm->bf_weight.maxExtBufSize = mtu; /* MAX_RX_LEN; */ /* Maximum space of external buffer */
+ if (p_pRbMapElm->bf_weight.p_ext_start)
+ ext_buf = (int8_t *)p_pRbMapElm->bf_weight.p_ext_start;
+ else
+ ext_buf = (int8_t *)xran_malloc(p_pRbMapElm->bf_weight.maxExtBufSize);
+
+ if(ext_buf == NULL)
+ rte_panic("xran_malloc return NULL [sz %d]\n", p_pRbMapElm->bf_weight.maxExtBufSize);
+
+ if(ext_buf) {
+ ext_buf_start = ext_buf;
+ ext_buf += (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header));
+
+ ext_len -= (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header));
+
+ ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
+ ext_len,
+ (int16_t *) (p_bfw_buffer + (*numSetBFW_total*p_pRbMapElm->bf_weight.nAntElmTRx)*4),
+ p_pRbMapElm);
+ if(ext_sec_total > 0) {
+ p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start;
+ p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
+ p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
+ } else
+ rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
+ } else {
+ rte_panic("xran_malloc return NULL\n");
+ }
+
+ return status;
+}
+
+int32_t
+app_io_xran_ext_type11_populate(struct xran_prb_elm* p_pRbMapElm, char *p_tx_dl_bfw_buffer, uint32_t mtu)
{
xran_status_t status = XRAN_STATUS_SUCCESS;
int32_t n_max_set_bfw;
p_pRbMapElm->bf_weight.maxExtBufSize = mtu; /* MAX_RX_LEN; */ /* Maximum space of external buffer */
+ if (p_pRbMapElm->bf_weight.p_ext_start)
+ extbuf = (uint8_t *)p_pRbMapElm->bf_weight.p_ext_start;
+ else
extbuf = (uint8_t*)xran_malloc(p_pRbMapElm->bf_weight.maxExtBufSize);
if(extbuf == NULL)
- rte_panic("xran_malloc return NULL\n");
+ rte_panic("xran_malloc return NULL [sz %d]\n", p_pRbMapElm->bf_weight.maxExtBufSize);
/* Check BFWs can be fit with MTU size */
n_max_set_bfw = xran_cp_estimate_max_set_bfws(p_pRbMapElm->bf_weight.nAntElmTRx,
pRbMap->prbMap[0].nRBSize = nRBs;
pRbMap->prbMap[0].nStartSymb = 0;
pRbMap->prbMap[0].numSymb = 14;
- pRbMap->prbMap[0].p_sec_desc[sym_id][0]->iq_buffer_offset = 0;
- pRbMap->prbMap[0].p_sec_desc[sym_id][0]->iq_buffer_len = nRBs *4L;
+ pRbMap->prbMap[0].sec_desc[sym_id][0].iq_buffer_offset = 0;
+ pRbMap->prbMap[0].sec_desc[sym_id][0].iq_buffer_len = nRBs *4L;
pRbMap->prbMap[0].nBeamIndex = 0;
pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
int32_t
app_io_xran_iq_content_init_cp_tx(uint8_t appMode, struct xran_fh_config *pXranConf,
struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
- int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId)
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t target_tti, int32_t flowId)
{
int32_t status = 0;
struct xran_prb_map* pRbMap = NULL;
+ char* dl_bfw_pos = NULL;
+
+ int32_t tti_dst = target_tti % XRAN_N_FE_BUF_LEN;
+ int32_t tti_src = target_tti % p_iq->numSlots;
+ int32_t tx_dl_bfw_buffer_position = tti_src * (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4;
+ uint16_t numSetBFW_total = 0;
if(p_iq->p_tx_play_buffer[flowId]) {
- pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ cc_id = cc_id % XRAN_MAX_SECTOR_NR;
+ ant_id = ant_id % XRAN_MAX_ANTENNA_NR;
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti_dst][cc_id][ant_id].sBufferList.pBuffers->pData;
+ dl_bfw_pos = ((char*)p_iq->p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position;
if(pRbMap) {
if (pXranConf->DynamicSectionEna == 0) {
- app_io_xran_iq_content_init_cp_rb_map(pRbMap, XRAN_DIR_DL, cc_id, ant_id, sym_id, tti, pXranConf->nDLRBs);
+ if(pRbMap->nPrbElm != 1 )
+ app_io_xran_iq_content_init_cp_rb_map(pRbMap, XRAN_DIR_DL, cc_id, ant_id, sym_id, tti_dst, pXranConf->nDLRBs);
} else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
&& appMode == APP_O_DU
&& sym_id == 0) { /* BFWs are per slot */
int32_t idxElm = 0;
- char* dl_bfw_pos = ((char*)p_iq->p_tx_dl_bfw_buffer[flowId]) + p_iq->tx_dl_bfw_buffer_position[flowId];
struct xran_prb_elm* p_pRbMapElm = NULL;
for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx;
if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update) {
- if(p_pRbMapElm->bf_weight.numBundPrb == 0) {
- /* No bundled PRB, using extension 1 */
- int16_t ext_len = 9600;
- int16_t ext_sec_total = 0;
- int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
- int8_t * ext_buf_start = ext_buf;
- if(ext_buf) {
- ext_buf += (RTE_PKTMBUF_HEADROOM +
- sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_section1_header) +
- sizeof(struct xran_cp_radioapp_section1));
-
- ext_len -= (RTE_PKTMBUF_HEADROOM +
- sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_section1_header) +
- sizeof(struct xran_cp_radioapp_section1));
-
- ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
- ext_len,
- (int16_t *) (dl_bfw_pos + (p_pRbMapElm->nRBStart*p_pRbMapElm->bf_weight.nAntElmTRx)*4),
- p_pRbMapElm->nRBSize,
- p_pRbMapElm->bf_weight.nAntElmTRx,
- p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
- if(ext_sec_total > 0) {
- p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start;
- p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
- p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
- } else
- rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
+ if(p_pRbMapElm->bf_weight.extType == 1) {
+ app_io_xran_ext_type1_populate(p_pRbMapElm, dl_bfw_pos, app_io_xran_fh_init.mtu, &numSetBFW_total);
} else {
- rte_panic("xran_malloc return NULL\n");
- }
- } else {
- app_io_xran_ext_type11_populate(p_pRbMapElm, p_iq->p_tx_dl_bfw_buffer[flowId], app_io_xran_fh_init.mtu);
+ app_io_xran_ext_type11_populate(p_pRbMapElm, dl_bfw_pos, app_io_xran_fh_init.mtu);
}
}
+ numSetBFW_total += p_pRbMapElm->bf_weight.numSetBFWs;
}
}
} else {
- printf("DL pRbMap ==NULL\n");
+ printf("DL pRbMap ==NULL [%d][%d][%d]\n", tti_dst, cc_id, ant_id);
exit(-1);
}
-
- if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B && appMode == APP_O_DU && sym_id == 0) {
- p_iq->tx_dl_bfw_buffer_position[flowId] += (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4;
- if(p_iq->tx_dl_bfw_buffer_position[flowId] >= p_iq->tx_dl_bfw_buffer_size[flowId])
- p_iq->tx_dl_bfw_buffer_position[flowId] = 0;
- }
} else {
//printf("flowId %d\n", flowId);
}
int32_t
app_io_xran_iq_content_init_cp_rx(uint8_t appMode, struct xran_fh_config *pXranConf,
struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
- int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId)
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t target_tti, int32_t flowId)
{
- int32_t status = 0;
struct xran_prb_map* pRbMap = NULL;
- char *pos = NULL;
- void *ptr = NULL;
+ char* ul_bfw_pos = NULL;
+
+ int32_t tti_dst = target_tti % XRAN_N_FE_BUF_LEN;
+ int32_t tti_src = target_tti % p_iq->numSlots;
+ int32_t tx_ul_bfw_buffer_position = tti_src * (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4;
+
+ uint16_t numSetBFW_total = 0;
- pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ cc_id = cc_id % XRAN_MAX_SECTOR_NR;
+ ant_id = ant_id % XRAN_MAX_ANTENNA_NR;
+
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti_dst][cc_id][ant_id].sBufferList.pBuffers->pData;
+ ul_bfw_pos = ((char*)p_iq->p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position;
if(pRbMap) {
if (pXranConf->DynamicSectionEna == 0) {
- app_io_xran_iq_content_init_cp_rb_map(pRbMap, XRAN_DIR_UL, cc_id, ant_id, sym_id, tti, pXranConf->nULRBs);
+ if(pRbMap->nPrbElm != 1 )
+ app_io_xran_iq_content_init_cp_rb_map(pRbMap, XRAN_DIR_UL, cc_id, ant_id, sym_id, tti_dst, pXranConf->nULRBs);
} else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
&& appMode == APP_O_DU
&& sym_id == 0) {
int32_t idxElm = 0;
- char * ul_bfw_pos = ((char*)p_iq->p_tx_ul_bfw_buffer[flowId]) + p_iq->tx_ul_bfw_buffer_position[flowId];
struct xran_prb_elm* p_pRbMapElm = NULL;
for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx;
if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update) {
- if(p_pRbMapElm->bf_weight.numBundPrb == 0) {
- /* No bundled PRB, using extension 1 */
-
- int16_t ext_len = 9600;
- int16_t ext_sec_total = 0;
- int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
- int8_t * ext_buf_start = ext_buf;
- int32_t idRb = 0;
- int16_t *ptr = NULL;
- int32_t i;
- if(ext_buf) {
- ext_buf += (RTE_PKTMBUF_HEADROOM +
- sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_section1_header) +
- sizeof(struct xran_cp_radioapp_section1));
-
- ext_len -= (RTE_PKTMBUF_HEADROOM +
- sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_section1_header) +
- sizeof(struct xran_cp_radioapp_section1));
-
- ptr = (int16_t*)(ul_bfw_pos +(p_pRbMapElm->nRBStart*p_pRbMapElm->bf_weight.nAntElmTRx)*4);
- ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
- ext_len,
- (int16_t *) (ul_bfw_pos + (p_pRbMapElm->nRBStart*p_pRbMapElm->bf_weight.nAntElmTRx)*4),
- p_pRbMapElm->nRBSize,
- p_pRbMapElm->bf_weight.nAntElmTRx,
- p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
- if(ext_sec_total > 0) {
- p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start;
- p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
- p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
+ if(p_pRbMapElm->bf_weight.extType == 1) {
+ app_io_xran_ext_type1_populate(p_pRbMapElm, ul_bfw_pos, app_io_xran_fh_init.mtu, &numSetBFW_total);
} else {
- rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
- }
- } else {
- rte_panic("xran_malloc return NULL\n");
- }
- } else {
- app_io_xran_ext_type11_populate(p_pRbMapElm, p_iq->p_tx_ul_bfw_buffer[flowId], app_io_xran_fh_init.mtu);
- }
- }
+ app_io_xran_ext_type11_populate(p_pRbMapElm, ul_bfw_pos, app_io_xran_fh_init.mtu);
}
+ } /* if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update) */
+ numSetBFW_total += p_pRbMapElm->bf_weight.numSetBFWs;
+ } /* for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) */
}
- p_iq->tx_ul_bfw_buffer_position[flowId] += (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4;
- if(p_iq->tx_ul_bfw_buffer_position[flowId] >= p_iq->tx_ul_bfw_buffer_size[flowId])
- p_iq->tx_ul_bfw_buffer_position[flowId] = 0;
} else {
rte_panic("DL pRbMap ==NULL\n");
}
int32_t
app_io_xran_iq_content_init_up_tx(uint8_t appMode, struct xran_fh_config *pXranConf,
struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
- int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId)
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t target_tti, int32_t flowId)
{
char *pos = NULL;
void *ptr = NULL;
struct xran_prb_map* pRbMap = NULL;
enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC;
+ int32_t tti_dst = target_tti % XRAN_N_FE_BUF_LEN;
+ int32_t tti_src = target_tti % p_iq->numSlots;
+ int32_t tx_play_buffer_position = tti_src * (XRAN_NUM_OF_SYMBOL_PER_SLOT*pXranConf->nDLRBs*N_SC_PER_PRB*4) + (sym_id * pXranConf->nDLRBs*N_SC_PER_PRB*4);
+
if (pXranConf != NULL)
{
staticEn = pXranConf->ru_conf.xranCompHdrType;
- pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
- pos = ((char*)p_iq->p_tx_play_buffer[flowId]) + p_iq->tx_play_buffer_position[flowId];
- ptr = psIoCtrl->sFrontHaulTxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti_dst][cc_id][ant_id].sBufferList.pBuffers->pData;
+ pos = ((char*)p_iq->p_tx_play_buffer[flowId]) + tx_play_buffer_position;
+ ptr = psIoCtrl->sFrontHaulTxBbuIoBufCtrl[tti_dst][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
if(ptr && pos) {
int32_t idxElm = 0;
uint8_t *dst = (uint8_t *)u8dptr;
uint8_t *src = (uint8_t *)pos;
+ uint16_t num_sections, idx, comp_method;
+ uint16_t prb_per_section;
struct xran_prb_elm* p_prbMapElm = &pRbMap->prbMap[idxElm];
dst = xran_add_hdr_offset(dst, ((staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE));
for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
struct xran_section_desc *p_sec_desc = NULL;
p_prbMapElm = &pRbMap->prbMap[idxElm];
- p_sec_desc = p_prbMapElm->p_sec_desc[sym_id][0];
+ p_sec_desc = &p_prbMapElm->sec_desc[sym_id][0];
+
+ if(p_prbMapElm->bf_weight.extType == 1)
+ {
+ num_sections = p_prbMapElm->bf_weight.numSetBFWs;
+ prb_per_section = p_prbMapElm->bf_weight.numBundPrb;
+ }
+ else
+ {
+ num_sections = 1;
+ prb_per_section = p_prbMapElm->UP_nRBSize;
+ }
if(p_sec_desc == NULL) {
rte_panic ("p_sec_desc == NULL\n");
continue;
}
- src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L);
+ src = (uint8_t *)(pos + p_prbMapElm->UP_nRBStart*N_SC_PER_PRB*4L);
+ p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr);
+ p_sec_desc->iq_buffer_len = 0;
+
+ for(idx=0; idx < num_sections ; idx++)
+ {
+ //printf("\nidx %hu u8dptr %p dst %p",idx,u8dptr,dst);
+
+ if((idx+1)*prb_per_section > p_prbMapElm->UP_nRBSize){
+ prb_per_section = (p_prbMapElm->UP_nRBSize - idx*prb_per_section);
+ }
if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) {
- payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
+ payload_len = prb_per_section*N_SC_PER_PRB*4L;
memcpy(dst, src, payload_len);
} else if ((p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT) || (p_prbMapElm->compMethod == XRAN_COMPMETHOD_MODULATION)) {
memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
bfp_com_req.data_in = (int16_t*)src;
- bfp_com_req.numRBs = p_prbMapElm->nRBSize;
- bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
+ bfp_com_req.numRBs = prb_per_section;
+ bfp_com_req.len = prb_per_section*N_SC_PER_PRB*4L;
bfp_com_req.compMethod = p_prbMapElm->compMethod;
bfp_com_req.iqWidth = p_prbMapElm->iqWidth;
bfp_com_req.ScaleFactor= p_prbMapElm->ScaleFactor;
exit(-1);
}
+ if(num_sections != 1)
+ src += prb_per_section*N_SC_PER_PRB*4L;
+
/* update RB map for given element */
- p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr);
- p_sec_desc->iq_buffer_len = payload_len;
+ //p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr);
+ p_sec_desc->iq_buffer_len += payload_len;
/* add headroom for ORAN headers between IQs for chunk of RBs*/
dst += payload_len;
+ if(idx+1 == num_sections) /* Create space for (eth + eCPRI + radio app + section + comp) headers required by next prbElement */
+ {
dst = xran_add_hdr_offset(dst, ((staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE));
}
+ else
+ {
+ /* Create space for section/compression header in current prbElement */
+ //TODO: Check if alignment required for this case
+ dst += sizeof(struct data_section_hdr);
+ p_sec_desc->iq_buffer_len += sizeof(struct data_section_hdr);
- p_iq->tx_play_buffer_position[flowId] += pXranConf->nDLRBs*N_SC_PER_PRB*4;
- if(p_iq->tx_play_buffer_position[flowId] >= p_iq->tx_play_buffer_size[flowId])
- p_iq->tx_play_buffer_position[flowId] = 0;
- } else {
- rte_panic("ptr ==NULL\n");
+ comp_method = ((staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE);
+
+ if( comp_method != XRAN_COMPMETHOD_NONE)
+ {
+ dst += sizeof (struct data_section_compression_hdr);
+ p_sec_desc->iq_buffer_len += sizeof(struct data_section_compression_hdr);
}
}
-
+ } /*for num_section */
+ } /* for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) */
+ } /* if(ptr && pos) */
+ else {
+ rte_panic("ptr ==NULL\n");
+ }
+ } /* if (pXranConf != NULL) */
return 0;
}
ptr = psIoCtrl->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
if(ptr && pos) {
- int32_t compMethod = pXranConf->ru_conf.compMeth;
+ int32_t compMethod = pXranConf->ru_conf.compMeth_PRACH;
if(compMethod == XRAN_COMPMETHOD_NONE) {
u32dptr = (uint32_t*)(ptr);
comp_req.len = RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, p_iq->tx_prach_play_buffer_size[flowId]);
comp_req.numRBs = comp_req.len / 12 / 4; /* 12RE, 4bytes */
comp_req.compMethod = compMethod;
- comp_req.iqWidth = pXranConf->ru_conf.iqWidth;
+ comp_req.iqWidth = pXranConf->ru_conf.iqWidth_PRACH;
comp_req.ScaleFactor = 0; /* TODO */
comp_req.reMask = 0xfff; /* TODO */
for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
struct xran_section_desc *p_sec_desc = NULL;
p_prbMapElm = &pRbMap->prbMap[idxElm];
- p_sec_desc = p_prbMapElm->p_sec_desc[sym_id][0];
+ p_sec_desc = &p_prbMapElm->sec_desc[sym_id][0];
if(p_sec_desc == NULL){
rte_panic ("p_sec_desc == NULL\n");
continue;
}
- src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L);
+ src = (uint8_t *)(pos + p_prbMapElm->UP_nRBStart*N_SC_PER_PRB*4L);
if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) {
- payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
+ payload_len = p_prbMapElm->UP_nRBSize*N_SC_PER_PRB*4L;
memcpy(dst, src, payload_len);
} else if (p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT
memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
bfp_com_req.data_in = (int16_t*)src;
- bfp_com_req.numRBs = p_prbMapElm->nRBSize;
- bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
+ bfp_com_req.numRBs = p_prbMapElm->UP_nRBSize;
+ bfp_com_req.len = p_prbMapElm->UP_nRBSize*N_SC_PER_PRB*4L;
bfp_com_req.compMethod = p_prbMapElm->compMethod;
bfp_com_req.iqWidth = p_prbMapElm->iqWidth;
bfp_com_req.ScaleFactor= p_prbMapElm->ScaleFactor;
int32_t cc_id, ant_id, sym_id, tti;
int32_t flowId;
- uint8_t frame_id = 0;
- uint8_t subframe_id = 0;
- uint8_t slot_id = 0;
- uint8_t sym = 0;
-
- void *ptr;
- uint32_t *u32dptr;
- uint16_t *u16dptr;
- uint8_t *u8dptr;
+ //uint8_t frame_id = 0;
+ //uint8_t subframe_id = 0;
+ //uint8_t slot_id = 0;
+ //uint8_t sym = 0;
struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
- struct xran_fh_init *pXranInit = &app_io_xran_fh_init;
+ //struct xran_fh_init *pXranInit = &app_io_xran_fh_init;
struct o_xu_buffers * p_iq = NULL;
uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
-
- char *pos = NULL;
- struct xran_prb_map *pRbMap = NULL;
+ uint32_t xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
if(psBbuIo == NULL){
rte_panic("psBbuIo == NULL\n");
/* prach TX for RU only */
if(p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enablePrach) {
- for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+ for(ant_id = 0; ant_id < xran_max_antenna_nr_prach; ant_id++) {
for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
- flowId = p_o_xu_cfg->numAxc*cc_id + ant_id;
+ flowId = xran_max_antenna_nr_prach * cc_id + ant_id;
if ((status = app_io_xran_iq_content_init_up_prach(p_o_xu_cfg->appMode, pXranConf,
psBbuIo, psIoCtrl, p_iq,
cc_id, ant_id, sym_id, tti, flowId)) != 0) {
- rte_panic("app_io_xran_iq_content_init_cp_tx");
+ rte_panic("app_io_xran_iq_content_init_up_prach");
}
}
}
if ((status = app_io_xran_iq_content_init_up_srs(p_o_xu_cfg->appMode, pXranConf,
psBbuIo, psIoCtrl, p_iq,
cc_id, ant_id, sym_id, tti, flowId)) != 0){
- rte_panic("app_io_xran_iq_content_init_cp_tx");
+ rte_panic("app_io_xran_iq_content_init_up_srs");
}
}
}
void app_io_xran_if_stop(void)
{
xran_status_t status = 0;
- SWXRANInterfaceTypeEnum eInterfaceType;
status += xran_mm_destroy(app_io_xran_handle)*2;
}
int32_t
-app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg)
+app_io_xran_iq_content_get_up_prach(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t target_tti, int32_t flowId)
{
- struct bbu_xran_io_if *psBbuIo = app_io_xran_if_get();
- struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
- xran_status_t status;
- int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
- int32_t nSectorNum;
- int32_t cc_id, ant_id, sym_id, tti;
- int32_t flowId;
-
- uint8_t frame_id = 0;
- uint8_t subframe_id = 0;
- uint8_t slot_id = 0;
- uint8_t sym = 0;
- uint16_t idxDesc = 0;
-
- void *ptr;
- uint32_t *u32dptr;
- uint16_t *u16dptr;
- uint8_t *u8dptr;
+ xran_status_t status = 0;
+ int32_t prach_len = 0;
+ void *ptr = NULL;
+ char *pos = NULL;
- struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
+ int32_t tti_src = target_tti % XRAN_N_FE_BUF_LEN;
+ int32_t tti_dst = target_tti % p_iq->numSlots;
+ int32_t prach_log_buffer_position;
- uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
- uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
+ prach_len = (3 * pXranConf->ru_conf.iqWidth_PRACH) * pXranConf->prach_conf.numPrbc; /* 12RE*2pairs/8bits (12*2/8=3)*/
+ prach_log_buffer_position = tti_dst * (XRAN_NUM_OF_SYMBOL_PER_SLOT*prach_len) + (sym_id * prach_len);
- char *pos = NULL;
- struct o_xu_buffers *p_iq = NULL;
+ if(p_iq->p_prach_log_buffer[flowId]) {
+ pos = ((char*)p_iq->p_prach_log_buffer[flowId]) + prach_log_buffer_position;
+ ptr = psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[tti_src][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
+ if(ptr) {
+ int32_t compMethod = pXranConf->ru_conf.compMeth_PRACH;
+ if(compMethod == XRAN_COMPMETHOD_NONE) {
+ memcpy(pos, (uint32_t *)(ptr), prach_len);
+ } else {
+ struct xranlib_decompress_request decomp_req;
+ struct xranlib_decompress_response decomp_rsp;
+ int32_t parm_size;
+
+ memset(&decomp_req, 0, sizeof(struct xranlib_decompress_request));
+ memset(&decomp_rsp, 0, sizeof(struct xranlib_decompress_response));
+
+ switch(compMethod) {
+ case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
+ case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
+ default:
+ parm_size = 0;
+ }
- if(psBbuIo == NULL)
- rte_panic("psBbuIo == NULL\n");
+ decomp_req.data_in = (int8_t *)ptr;
+ decomp_req.numRBs = pXranConf->prach_conf.numPrbc;
+ decomp_req.len = (3 * pXranConf->ru_conf.iqWidth_PRACH + parm_size) * pXranConf->prach_conf.numPrbc; /* 12RE*2pairs/8bits (12*2/8=3)*/
+ decomp_req.compMethod = compMethod;
+ decomp_req.iqWidth = pXranConf->ru_conf.iqWidth_PRACH;
+ decomp_req.ScaleFactor = 0; /* TODO */
+ decomp_req.reMask = 0xfff; /* TODO */
- if(psIoCtrl == NULL)
- rte_panic("psIoCtrl == NULL\n");
+ decomp_rsp.data_out = (int16_t *)pos;
+ decomp_rsp.len = 0;
- for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) {
- nSectorIndex[nSectorNum] = nSectorNum;
+ xranlib_decompress(&decomp_req, &decomp_rsp);
}
+ }
+ } /* if(p_iq->p_prach_log_buffer[flowId]) */
- nSectorNum = p_o_xu_cfg->numCC;
- printf ("app_io_xran_iq_content_get\n");
-
- if(p_o_xu_cfg->p_buff) {
- p_iq = p_o_xu_cfg->p_buff;
- } else {
- printf("Error p_o_xu_cfg->p_buff\n");
- exit(-1);
+ return status;
}
- for(cc_id = 0; cc_id <nSectorNum; cc_id++) {
- for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti++) {
- for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+int32_t
+app_io_xran_iq_content_get_up_srs(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t target_tti, int32_t flowId)
+{
+ xran_status_t status = 0;
int32_t idxElm = 0;
struct xran_prb_map *pRbMap = NULL;
struct xran_prb_elm *pRbElm = NULL;
struct xran_section_desc *p_sec_desc = NULL;
- int32_t prach_len = 0;
- pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ void *ptr = NULL;
+ char *pos = NULL;
+ uint32_t *u32dptr;
+
+ int32_t tti_src = target_tti % XRAN_N_FE_BUF_LEN;
+ int32_t tti_dst = target_tti % p_iq->numSlots;
+ int32_t srs_log_buffer_position = tti_dst * (XRAN_NUM_OF_SYMBOL_PER_SLOT*pXranConf->nULRBs*N_SC_PER_PRB*4) + (sym_id * pXranConf->nULRBs*N_SC_PER_PRB*4);
+
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[tti_src][cc_id][ant_id].sBufferList.pBuffers->pData;
if(pRbMap == NULL){
- printf("pRbMap == NULL\n");
- exit(-1);
+ rte_panic("pRbMap == NULL\n");
}
- if(p_o_xu_cfg->appMode == APP_O_RU)
- flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
- else
- flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
- for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(p_iq->p_srs_log_buffer[flowId]) {
pRbElm = &pRbMap->prbMap[0];
- if(pRbMap->nPrbElm == 1){
- if(p_iq->p_rx_log_buffer[flowId]) {
- pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + p_iq->rx_log_buffer_position[flowId];
- uint32_t one_rb_size = (((pRbElm->iqWidth == 0) || (pRbElm->iqWidth == 16)) ? (N_SC_PER_PRB*2*2) : (3 * pRbElm->iqWidth + 1));
- if (app_io_xran_fh_init.mtu < pRbElm->nRBSize * one_rb_size)
- {
- ptr = psIoCtrl->sFrontHaulRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
+ /*if(pRbMap->nPrbElm == 1) {
+ if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb) {
+ pos = ((char*)p_iq->p_srs_log_buffer[flowId]) + p_iq->srs_log_buffer_position[flowId];
+ ptr = psIoCtrl->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
if(ptr){
int32_t payload_len = 0;
u32dptr = (uint32_t*)(ptr);
memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
-
switch(pRbElm->compMethod) {
case XRAN_COMPMETHOD_BLKFLOAT:
parm_size = 1;
bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size) * pRbElm->nRBSize;
bfp_decom_req.compMethod = pRbElm->compMethod;
bfp_decom_req.iqWidth = pRbElm->iqWidth;
- bfp_decom_req.reMask = pRbElm->reMask;
- bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor;
bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
bfp_decom_rsp.len = 0;
memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L);
}
}else {
- printf("%s:%d [%d][%d][%d][%d]ptr ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id);
+ printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id);
}
}
- else
- {
- p_sec_desc = pRbElm->p_sec_desc[sym_id][0];
- if(p_iq->p_rx_log_buffer[flowId] && p_sec_desc){
+ } else*/ {
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
+ pRbElm = &pRbMap->prbMap[idxElm];
+ p_sec_desc = &pRbElm->sec_desc[sym_id][0];
+ if(p_iq->p_srs_log_buffer[flowId] && p_sec_desc) {
if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){
- pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + p_iq->rx_log_buffer_position[flowId];
+ pos = ((char*)p_iq->p_srs_log_buffer[flowId]) + srs_log_buffer_position;
ptr = p_sec_desc->pData;
if(ptr){
- int32_t payload_len = 0;
u32dptr = (uint32_t*)(ptr);
if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){
struct xranlib_decompress_request bfp_decom_req;
bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*pRbElm->nRBSize;
bfp_decom_req.compMethod = pRbElm->compMethod;
bfp_decom_req.iqWidth = pRbElm->iqWidth;
- bfp_decom_req.reMask = pRbElm->reMask;
- bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor;
bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
bfp_decom_rsp.len = 0;
xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp);
- payload_len = bfp_decom_rsp.len;
-
- }
- else {
+ } else {
memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4);
}
}
- else {
- printf("%s:%d [%d][%d][%d][%d]ptr ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id);
}
+ } else {
+ printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", target_tti, sym_id, ant_id,flowId);
}
}
- else
- printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", tti, sym_id, ant_id,flowId);
}
}
- } else {
+
+ return status;
+}
+
+int32_t
+app_io_xran_iq_content_get_up_rx(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t target_tti, int32_t flowId)
+{
+ xran_status_t status = 0;
+ int32_t idxElm = 0;
+ int32_t idxSection = 0;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
+ struct xran_prb_elm *pRbElmRx = NULL;
+ struct xran_section_desc *p_sec_desc = NULL;
+
+ uint16_t idxDesc = 0;
+
+ void *ptr = NULL;
+ char *pos = NULL;
+ uint32_t *u32dptr;
+ struct data_section_hdr* data_hdr;
+ uint16_t num_prbu = 0, start_prbu = 0, prb_idx;
+ char *src;
+ const int16_t data_size = sizeof(struct data_section_hdr);
+ const int16_t compr_size = sizeof(struct data_section_compression_hdr);
+
+ int32_t tti_src = target_tti % XRAN_N_FE_BUF_LEN;
+ int32_t tti_dst = target_tti % p_iq->numSlots;
+ int32_t rx_log_buffer_position = tti_dst * (XRAN_NUM_OF_SYMBOL_PER_SLOT*pXranConf->nULRBs*N_SC_PER_PRB*4) + (sym_id * pXranConf->nULRBs*N_SC_PER_PRB*4);
+
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti_src][cc_id][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL) {
+ printf("pRbMap == NULL\n");
+ exit(-1);
+ }
+
+ if(0 == pXranConf->RunSlotPrbMapBySymbolEnable)
+ {
for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
pRbElm = &pRbMap->prbMap[idxElm];
- p_sec_desc = pRbElm->p_sec_desc[sym_id][0];
+ for (idxDesc = 0; idxDesc < XRAN_MAX_FRAGMENT; idxDesc++) {
+ p_sec_desc = &pRbElm->sec_desc[sym_id][idxDesc];
if(p_iq->p_rx_log_buffer[flowId] && p_sec_desc){
if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){
- pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + p_iq->rx_log_buffer_position[flowId];
+ if (!p_sec_desc->pCtrl)
+ continue;
+ pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + rx_log_buffer_position;
ptr = p_sec_desc->pData;
- if(ptr){
- int32_t payload_len = 0;
- u32dptr = (uint32_t*)(ptr);
+ src = (char *)ptr;
+ data_hdr = (struct data_section_hdr *)src;
+ num_prbu = p_sec_desc->num_prbu;
+ start_prbu = p_sec_desc->start_prbu;
+ prb_idx = start_prbu;
+ while(prb_idx < (pRbElm->UP_nRBStart + pRbElm->UP_nRBSize) && num_prbu != 0){
+ if(src){
+ u32dptr = (uint32_t*)(src);
if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){
struct xranlib_decompress_request bfp_decom_req;
struct xranlib_decompress_response bfp_decom_rsp;
- int32_t parm_size;
+ int32_t parm_size = 0;
memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
}
bfp_decom_req.data_in = (int8_t *)u32dptr;
- bfp_decom_req.numRBs = pRbElm->nRBSize;
- bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*pRbElm->nRBSize;
+ bfp_decom_req.numRBs = num_prbu;
+ bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*num_prbu;
bfp_decom_req.compMethod = pRbElm->compMethod;
bfp_decom_req.iqWidth = pRbElm->iqWidth;
bfp_decom_req.reMask = pRbElm->reMask;
bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor;
- bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
+ bfp_decom_rsp.data_out = (int16_t *)(pos + start_prbu*N_SC_PER_PRB*4);
bfp_decom_rsp.len = 0;
xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp);
- payload_len = bfp_decom_rsp.len;
+ src += (3 * pRbElm->iqWidth + parm_size)*num_prbu;
} else {
- memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4);
+ memcpy(pos + start_prbu*N_SC_PER_PRB*4 , u32dptr, num_prbu*N_SC_PER_PRB*4);
+ src += num_prbu*N_SC_PER_PRB*4;
}
}
else {
- // printf("%s:%d [%d][%d][%d][%d]ptr ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id);
- }
+ // printf("%s:%d [%d][%d][%d][%d]src ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id);
}
+ data_hdr = (struct data_section_hdr *)src;
+ if(pRbElm->bf_weight.extType == 1 && data_hdr != NULL)
+ {
+ data_hdr->fields.all_bits = rte_be_to_cpu_32(data_hdr->fields.all_bits);
+ num_prbu = data_hdr->fields.num_prbu;
+ start_prbu = data_hdr->fields.start_prbu;
+ prb_idx += num_prbu;
+ src += data_size;
+ if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE && pXranConf->ru_conf.xranCompHdrType == XRAN_COMP_HDR_TYPE_DYNAMIC)
+ src += compr_size;
}
else
- printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", tti, sym_id, ant_id,flowId);
- }
+ break;
}
- p_iq->rx_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
-
- if(p_iq->rx_log_buffer_position[flowId] >= p_iq->rx_log_buffer_size[flowId])
- p_iq->rx_log_buffer_position[flowId] = 0;
}
-
-
- flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
- prach_len = (3 * pXranConf->ru_conf.iqWidth_PRACH) * pXranConf->prach_conf.numPrbc; /* 12RE*2pairs/8bits (12*2/8=3)*/
- for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
-
- if(p_iq->p_prach_log_buffer[flowId]) {
- pos = ((char*)p_iq->p_prach_log_buffer[flowId]) + p_iq->prach_log_buffer_position[flowId];
- ptr = psIoCtrl->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
- if(ptr) {
- int32_t compMethod = pXranConf->ru_conf.compMeth_PRACH;
-
- if(compMethod == XRAN_COMPMETHOD_NONE) {
- memcpy(pos, (uint32_t *)(ptr), prach_len);
- }
- else {
- struct xranlib_decompress_request decomp_req;
- struct xranlib_decompress_response decomp_rsp;
- int32_t parm_size;
-
- memset(&decomp_req, 0, sizeof(struct xranlib_decompress_request));
- memset(&decomp_rsp, 0, sizeof(struct xranlib_decompress_response));
-
- switch(compMethod) {
- case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
- case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
- default:
- parm_size = 0;
}
-
- decomp_req.data_in = (int8_t *)ptr;
- decomp_req.numRBs = pXranConf->prach_conf.numPrbc;
- decomp_req.len = (3 * pXranConf->ru_conf.iqWidth_PRACH + parm_size) * pXranConf->prach_conf.numPrbc; /* 12RE*2pairs/8bits (12*2/8=3)*/
- decomp_req.compMethod = compMethod;
- decomp_req.iqWidth = pXranConf->ru_conf.iqWidth_PRACH;
- decomp_req.ScaleFactor = 0; /* TODO */
- decomp_req.reMask = 0xfff; /* TODO */
-
- decomp_rsp.data_out = (int16_t *)pos;
- decomp_rsp.len = 0;
-
- xranlib_decompress(&decomp_req, &decomp_rsp);
+ else
+ printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", target_tti, sym_id, ant_id,flowId);
}
}
-
- p_iq->prach_log_buffer_position[flowId] += prach_len;
-
- if(p_iq->prach_log_buffer_position[flowId] >= p_iq->prach_log_buffer_size[flowId])
- p_iq->prach_log_buffer_position[flowId] = 0;
- } /* if(p_iq->p_prach_log_buffer[flowId]) */
- } /* for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) */
- } /* for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) */
-
- /* SRS RX for O-DU only */
- if(p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) {
- for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++) {
- int32_t idxElm = 0;
- struct xran_prb_map *pRbMap = NULL;
- struct xran_prb_elm *pRbElm = NULL;
- struct xran_section_desc *p_sec_desc = NULL;
- pRbMap = (struct xran_prb_map *) psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
- if(pRbMap == NULL) {
- printf("pRbMap == NULL\n");
- exit(-1);
}
- flowId = p_o_xu_cfg->antElmTRx*cc_id + ant_id;
- if(p_iq->p_srs_log_buffer[flowId]) {
- for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) {
- pRbElm = &pRbMap->prbMap[0];
- /*if(pRbMap->nPrbElm == 1) {
+ else
+ {
+ for(idxSection = 0; idxSection < pRbMap->nPrbElm; idxSection++ ) {
+ pRbElmRx = &pRbMap->prbMap[idxSection];
+ for (idxDesc = 0; idxDesc < XRAN_MAX_FRAGMENT; idxDesc++) {
+ p_sec_desc = &pRbElmRx->sec_desc[sym_id][idxDesc];
+ if(p_iq->p_rx_log_buffer[flowId] && p_sec_desc){
+ if(!p_sec_desc->pCtrl)
+ continue;
+ for(idxElm = idxSection; idxElm < pRbMap->nPrbElm; idxElm++ )
+ {
+ pRbElm = &pRbMap->prbMap[idxElm];
if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb) {
- pos = ((char*)p_iq->p_srs_log_buffer[flowId]) + p_iq->srs_log_buffer_position[flowId];
- ptr = psIoCtrl->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
- if(ptr){
- int32_t payload_len = 0;
- u32dptr = (uint32_t*)(ptr);
+ pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + rx_log_buffer_position;
+ ptr = p_sec_desc->pData;
+ src = (char *)ptr;
+ data_hdr = (struct data_section_hdr *)src;
+ num_prbu = p_sec_desc->num_prbu;
+ start_prbu = p_sec_desc->start_prbu;
+ prb_idx = start_prbu;
+ while(prb_idx < (pRbElm->UP_nRBStart + pRbElm->UP_nRBSize) && num_prbu != 0){
+ // while(prb_idx < (pRbElm->nRBStart + pRbElm->nRBSize) && num_prbu != 0){
+ if(src){
+ u32dptr = (uint32_t*)(src);
if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){
struct xranlib_decompress_request bfp_decom_req;
struct xranlib_decompress_response bfp_decom_rsp;
- int32_t parm_size;
+ int32_t parm_size = 0;
memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
}
bfp_decom_req.data_in = (int8_t *)u32dptr;
- bfp_decom_req.numRBs = pRbElm->nRBSize;
- bfp_decom_req.len = (3* pRbElm->iqWidth + parm_size)*pRbElm->nRBSize;
+ bfp_decom_req.numRBs = num_prbu;
+ bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*num_prbu;
bfp_decom_req.compMethod = pRbElm->compMethod;
bfp_decom_req.iqWidth = pRbElm->iqWidth;
+ bfp_decom_req.reMask = pRbElm->reMask;
+ bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor;
- bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
+ bfp_decom_rsp.data_out = (int16_t *)(pos + start_prbu*N_SC_PER_PRB*4);
bfp_decom_rsp.len = 0;
xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp);
- payload_len = bfp_decom_rsp.len;
+ src += (3 * pRbElm->iqWidth + parm_size)*num_prbu;
} else {
- u32dptr = (uint32_t*)(ptr);
- memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L);
+ memcpy(pos + start_prbu*N_SC_PER_PRB*4 , u32dptr, num_prbu*N_SC_PER_PRB*4);
+ src += num_prbu*N_SC_PER_PRB*4;
+ }
+ }
+ else {
+ // printf("%s:%d [%d][%d][%d][%d]src ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id);
+ }
+ data_hdr = (struct data_section_hdr *)src;
+ if(pRbElm->bf_weight.extType == 1 && data_hdr != NULL)
+ {
+ data_hdr->fields.all_bits = rte_be_to_cpu_32(data_hdr->fields.all_bits);
+ num_prbu = data_hdr->fields.num_prbu;
+ start_prbu = data_hdr->fields.start_prbu;
+ prb_idx += num_prbu;
+ src += data_size;
+ if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE && pXranConf->ru_conf.xranCompHdrType == XRAN_COMP_HDR_TYPE_DYNAMIC)
+ src += compr_size;
+ }
+ else
+ break;
+ }
+ // break;
+ }
+ }
+ }
+ else
+ printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", target_tti, sym_id, ant_id,flowId);
+ }
+ }
+ }
+ return status;
+}
+
+
+
+int32_t
+app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg)
+{
+ struct bbu_xran_io_if *psBbuIo = app_io_xran_if_get();
+ struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id);
+ xran_status_t status;
+ int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
+ int32_t nSectorNum;
+ int32_t cc_id, ant_id, sym_id, tti;
+ int32_t flowId;
+ struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id];
+ char *pos = NULL;
+
+ uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
+ uint32_t xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
+
+ struct o_xu_buffers *p_iq = NULL;
+
+ if(psBbuIo == NULL)
+ rte_panic("psBbuIo == NULL\n");
+
+ if(psIoCtrl == NULL)
+ rte_panic("psIoCtrl == NULL\n");
+
+ for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) {
+ nSectorIndex[nSectorNum] = nSectorNum;
}
+
+ nSectorNum = p_o_xu_cfg->numCC;
+ printf ("app_io_xran_iq_content_get\n");
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
}else {
- printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id);
+ printf("Error p_o_xu_cfg->p_buff\n");
+ exit(-1);
}
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
}
- } else*/ {
+
+ if(psBbuIo->bbu_offload == 0) {
+ for(cc_id = 0; cc_id <nSectorNum; cc_id++) {
+ for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti++) {
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+ if(p_o_xu_cfg->appMode == APP_O_RU)
+ flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
+ else
+ flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
+
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if ((status = app_io_xran_iq_content_get_up_rx(p_o_xu_cfg->appMode, pXranConf,
+ psBbuIo, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_get_up_rx");
+ }
+ }
+ if(p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enablePrach && (ant_id < xran_max_antenna_nr_prach)) {
+ flowId = xran_max_antenna_nr_prach * cc_id + ant_id;
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if ((status = app_io_xran_iq_content_get_up_prach(p_o_xu_cfg->appMode, pXranConf,
+ psBbuIo, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_get_up_prach");
+ }
+ }
+ }
+ } /* for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) */
+
+ /* SRS RX for O-DU only */
+ if(p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) {
+ for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++) {
+ flowId = p_o_xu_cfg->antElmTRx*cc_id + ant_id;
+ for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) {
+ if ((status = app_io_xran_iq_content_get_up_srs(p_o_xu_cfg->appMode, pXranConf,
+ psBbuIo, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_get_up_srs");
+ }
+ }
+ }
+ }
+
+ /* CP - DL for O-RU only */
+ if(p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->xranCat == 1 && p_o_xu_cfg->extType == 1) {
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+ uint16_t idxElm = 0;
+ int i = 0, len;
+ uint8_t *src_buf;
+ char *src = NULL;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
+ int8_t *iq_data = NULL;
+ uint16_t N = pXranConf->nAntElmTRx;
+ uint8_t parm_size;
+ int32_t tti_dst = tti % p_iq->numSlots ;
+ int32_t tx_dl_bfw_buffer_position = tti_dst * (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4;
+ uint16_t iq_size;
+ struct xran_cp_radioapp_section_ext1 * ext1;
+ uint8_t bfwIqWidth;
+ uint8_t total_ext1_len = 0;
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL) {
+ printf("pRbMap == NULL\n");
+ exit(-1);
+ }
+ flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
+ pos = (char*)p_iq->p_tx_dl_bfw_log_buffer[flowId] + tx_dl_bfw_buffer_position;
for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
pRbElm = &pRbMap->prbMap[idxElm];
- p_sec_desc = pRbElm->p_sec_desc[sym_id][0];
- if(p_iq->p_srs_log_buffer[flowId] && p_sec_desc) {
- if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb) {
- pos = ((char*)p_iq->p_srs_log_buffer[flowId]) + p_iq->srs_log_buffer_position[flowId];
- ptr = p_sec_desc->pData;
- if(ptr) {
- int32_t payload_len = 0;
- u32dptr = (uint32_t*)(ptr);
- if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE) {
- struct xranlib_decompress_request bfp_decom_req;
- struct xranlib_decompress_response bfp_decom_rsp;
- int32_t parm_size;
-
- memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
- memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
- switch(pRbElm->compMethod) {
- case XRAN_COMPMETHOD_BLKFLOAT:
+ bfwIqWidth = pRbElm->bf_weight.bfwIqWidth;
+ if(p_iq->p_tx_dl_bfw_log_buffer[flowId]) {
+ src = (char *)pRbElm->bf_weight.p_ext_section;
+ if(!pRbElm->bf_weight.p_ext_start)
+ continue;
+
+ for(i = 0; i < (pRbElm->bf_weight.numSetBFWs); i++) {
+ if(src){
+ src_buf = (uint8_t *)src;
+ ext1 = (struct xran_cp_radioapp_section_ext1 *)src_buf;
+ src_buf += sizeof(struct xran_cp_radioapp_section_ext1);
+ if(src_buf == NULL)
+ break;
+
+ iq_data = (int8_t *)(src_buf);
+ total_ext1_len = ext1->extLen * XRAN_SECTIONEXT_ALIGN;
+ if (pRbElm->bf_weight.bfwCompMeth == XRAN_COMPMETHOD_NONE){
+ iq_size = N * bfwIqWidth * 2; // total in bits
+ parm_size = iq_size>>3; // total in bytes (/8)
+ if(iq_size%8) parm_size++; // round up
+ len = parm_size;
+ memcpy(pos,iq_data,len);
+ }
+ else {
+ switch(pRbElm->bf_weight.bfwCompMeth) {
+ case XRAN_BFWCOMPMETHOD_BLKFLOAT:
parm_size = 1;
break;
- case XRAN_COMPMETHOD_MODULATION:
- parm_size = 0;
+
+ case XRAN_BFWCOMPMETHOD_BLKSCALE:
+ parm_size = 1;
+ break;
+
+ case XRAN_BFWCOMPMETHOD_ULAW:
+ parm_size = 1;
+ break;
+
+ case XRAN_BFWCOMPMETHOD_BEAMSPACE:
+ parm_size = N>>3; if(N%8) parm_size++; parm_size *= 8;
break;
+
default:
parm_size = 0;
}
+ len = parm_size;
+ /* Get BF weights */
+ iq_size = N * bfwIqWidth * 2; // total in bits
+ parm_size = iq_size>>3; // total in bytes (/8)
+ if(iq_size%8) parm_size++; // round up
+ len += parm_size;
+ struct xranlib_decompress_request bfp_decom_req;
+ struct xranlib_decompress_response bfp_decom_rsp;
- bfp_decom_req.data_in = (int8_t *)u32dptr;
- bfp_decom_req.numRBs = pRbElm->nRBSize;
- bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*pRbElm->nRBSize;
- bfp_decom_req.compMethod = pRbElm->compMethod;
- bfp_decom_req.iqWidth = pRbElm->iqWidth;
-
- bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
- bfp_decom_rsp.len = 0;
+ memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
+ memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
- xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp);
- payload_len = bfp_decom_rsp.len;
+ bfp_decom_req.data_in = (int8_t*)iq_data;
+ bfp_decom_req.numRBs = 1;
+ bfp_decom_req.numDataElements = N*2;
+ bfp_decom_req.len = len;
+ bfp_decom_req.compMethod = pRbElm->bf_weight.bfwCompMeth;
+ bfp_decom_req.iqWidth = bfwIqWidth;
- } else {
- memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4);
+ bfp_decom_rsp.data_out = (int16_t *)(pos);
+ bfp_decom_rsp.len = 0;
+ xranlib_decompress_bfw(&bfp_decom_req, &bfp_decom_rsp);
}
+ pos += N*4;
}
+ src += (total_ext1_len + sizeof(struct xran_cp_radioapp_section1));
}
- } else {
- printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", tti, sym_id, ant_id,flowId);
}
}
- }
- p_iq->srs_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
- if(p_iq->srs_log_buffer_position[flowId] >= p_iq->srs_log_buffer_size[flowId])
- p_iq->srs_log_buffer_position[flowId] = 0;
+ } /* for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) */
+ } /* if(p_o_xu_cfg->appMode == APP_O_RU) */
+
+
+ /* CP - UL for O-RU only */
+ if(p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->xranCat == 1 && p_o_xu_cfg->extType == 1) {
+ for(ant_id = 0; ant_id < p_o_xu_cfg->numUlAxc; ant_id++) {
+ uint16_t idxElm = 0;
+ int i = 0, len;
+ uint8_t *src_buf;
+ char *src = NULL;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_elm *pRbElm = NULL;
+ int8_t *iq_data = NULL;
+ uint16_t N = pXranConf->nAntElmTRx;
+ uint8_t parm_size;
+ uint16_t iq_size;
+ struct xran_cp_radioapp_section_ext1 * ext1;
+ uint8_t bfwIqWidth;
+ uint8_t total_ext1_len = 0;
+ int32_t tti_dst = tti % p_iq->numSlots;
+ int32_t tx_ul_bfw_buffer_position = tti_dst * (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4;
+ pRbMap = (struct xran_prb_map *) psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap == NULL) {
+ printf("pRbMap == NULL\n");
+ exit(-1);
+ }
+ flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
+ pos = ((char*)p_iq->p_tx_ul_bfw_log_buffer[flowId]) + tx_ul_bfw_buffer_position;
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
+ pRbElm = &pRbMap->prbMap[idxElm];
+ bfwIqWidth = pRbElm->bf_weight.bfwIqWidth;
+ if(p_iq->p_tx_ul_bfw_log_buffer[flowId]) {
+ src = (char *)pRbElm->bf_weight.p_ext_section;
+ if(!pRbElm->bf_weight.p_ext_start)
+ continue;
+
+ for(i = 0; i < (pRbElm->bf_weight.numSetBFWs); i++) {
+ if(src){
+ src_buf = (uint8_t *)src;
+ ext1 = (struct xran_cp_radioapp_section_ext1 *)src_buf;
+ src_buf += sizeof(struct xran_cp_radioapp_section_ext1);
+ if(src_buf == NULL)
+ break;
+
+ iq_data = (int8_t *)(src_buf);
+ total_ext1_len = ext1->extLen * XRAN_SECTIONEXT_ALIGN;
+ if (pRbElm->bf_weight.bfwCompMeth == XRAN_COMPMETHOD_NONE){
+ iq_size = N * bfwIqWidth * 2; // total in bits
+ parm_size = iq_size>>3; // total in bytes (/8)
+ if(iq_size%8) parm_size++; // round up
+ len = parm_size;
+ memcpy(pos,iq_data,len);
}
+ else {
+ switch(pRbElm->bf_weight.bfwCompMeth) {
+ case XRAN_BFWCOMPMETHOD_BLKFLOAT:
+ parm_size = 1;
+ break;
+
+ case XRAN_BFWCOMPMETHOD_BLKSCALE:
+ parm_size = 1;
+ break;
+
+ case XRAN_BFWCOMPMETHOD_ULAW:
+ parm_size = 1;
+ break;
+
+ case XRAN_BFWCOMPMETHOD_BEAMSPACE:
+ parm_size = N>>3; if(N%8) parm_size++; parm_size *= 8;
+ break;
+
+ default:
+ parm_size = 0;
}
+ len = parm_size;
+ /* Get BF weights */
+ iq_size = N * bfwIqWidth * 2; // total in bits
+ parm_size = iq_size>>3; // total in bytes (/8)
+ if(iq_size%8) parm_size++; // round up
+ len += parm_size;
+ struct xranlib_decompress_request bfp_decom_req;
+ struct xranlib_decompress_response bfp_decom_rsp;
+
+ memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
+ memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
+
+ bfp_decom_req.data_in = (int8_t*)iq_data;
+ bfp_decom_req.numRBs = 1;
+ bfp_decom_req.numDataElements = N*2;
+ bfp_decom_req.len = len;
+ bfp_decom_req.compMethod = pRbElm->bf_weight.bfwCompMeth;
+ bfp_decom_req.iqWidth = bfwIqWidth;
+
+ bfp_decom_rsp.data_out = (int16_t *)(pos);
+ bfp_decom_rsp.len = 0;
+ xranlib_decompress_bfw(&bfp_decom_req, &bfp_decom_rsp);
}
+ pos += N*4;
}
+ src += (total_ext1_len + sizeof(struct xran_cp_radioapp_section1));
}
}
-
+ }
+ } /* for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) */
+ } /* if(p_o_xu_cfg->appMode == APP_O_RU) */
+ } /*for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti++)*/
+ } /*for(cc_id = 0; cc_id <nSectorNum; cc_id++)*/
+ }
return 0;
}
p_xran_fh_cfg->prach_conf.nPrachFreqStart = 0;
p_xran_fh_cfg->prach_conf.nPrachFilterIdx = XRAN_FILTERINDEX_PRACH_ABC;
p_xran_fh_cfg->prach_conf.nPrachConfIdx = p_o_xu_cfg->prachConfigIndex;
+ p_xran_fh_cfg->prach_conf.nPrachConfIdxLTE = p_o_xu_cfg->prachConfigIndexLTE; //will be used in case of dss only
p_xran_fh_cfg->prach_conf.nPrachFreqOffset = -792;
- p_xran_fh_cfg->srs_conf.symbMask = p_o_xu_cfg->srsSymMask;
+ p_xran_fh_cfg->srs_conf.symbMask = p_o_xu_cfg->srsSymMask; // deprecated
+
+ if(p_o_xu_cfg->numAxc > XRAN_MAX_PRACH_ANT_NUM)
+ p_xran_fh_cfg->srs_conf.eAxC_offset = p_o_xu_cfg->numAxc + XRAN_MAX_PRACH_ANT_NUM; /* PUSCH, PRACH, SRS */
+ else
p_xran_fh_cfg->srs_conf.eAxC_offset = 2 * p_o_xu_cfg->numAxc; /* PUSCH, PRACH, SRS */
+ p_xran_fh_cfg->srs_conf.slot = p_o_xu_cfg->srsSlot;
+ p_xran_fh_cfg->srs_conf.ndm_offset = p_o_xu_cfg->srsNdmOffset;
+ p_xran_fh_cfg->srs_conf.ndm_txduration = p_o_xu_cfg->srsNdmTxDuration;
p_xran_fh_cfg->ru_conf.xranTech = p_o_xu_cfg->xranTech;
p_xran_fh_cfg->ru_conf.xranCompHdrType = p_o_xu_cfg->CompHdrType;
p_xran_fh_cfg->ru_conf.xranCat = p_o_xu_cfg->xranCat;
+
+ if (p_xran_fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_A)
+ p_xran_fh_cfg->neAxcUl = p_xran_fh_cfg->neAxc;
+
p_xran_fh_cfg->ru_conf.iqWidth = p_o_xu_cfg->p_PrbMapDl->prbMap[0].iqWidth;
if (p_o_xu_cfg->compression == 0)
if (p_o_xu_cfg->prachCompMethod == 0)
p_o_xu_cfg->prachiqWidth = 16;
p_xran_fh_cfg->ru_conf.iqWidth_PRACH = p_o_xu_cfg->prachiqWidth;
-
p_xran_fh_cfg->ru_conf.fftSize = 0;
while (p_o_xu_cfg->nULFftSize >>= 1)
p_xran_fh_cfg->max_sections_per_slot = RTE_MAX(p_o_xu_cfg->max_sections_per_slot, XRAN_MIN_SECTIONS_PER_SLOT);
p_xran_fh_cfg->max_sections_per_symbol = RTE_MAX(p_o_xu_cfg->max_sections_per_symbol, XRAN_MIN_SECTIONS_PER_SLOT);
+ p_xran_fh_cfg->RunSlotPrbMapBySymbolEnable = p_o_xu_cfg->RunSlotPrbMapBySymbolEnable;
printf("Max Sections: %d per symb %d per slot\n", p_xran_fh_cfg->max_sections_per_slot, p_xran_fh_cfg->max_sections_per_symbol);
if(p_o_xu_cfg->maxFrameId)
p_xran_fh_cfg->cp_vlan_tag = p_o_xu_cfg->cp_vlan_tag;
p_xran_fh_cfg->up_vlan_tag = p_o_xu_cfg->up_vlan_tag;
+ p_xran_fh_cfg->dssEnable = p_o_xu_cfg->dssEnable;
+ p_xran_fh_cfg->dssPeriod = p_o_xu_cfg->dssPeriod;
+ for(i=0; i<p_o_xu_cfg->dssPeriod; i++) {
+ p_xran_fh_cfg->technology[i] = p_o_xu_cfg->technology[i];
+ }
+
return ret;
}
p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].measId = p_use_cfg->owdmMeasId;
p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].owdm_enable = p_use_cfg->owdmEnable;
p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].owdm_PlLength = p_use_cfg->owdmPlLength;
+ p_xran_fh_init->dlCpProcBurst = p_use_cfg->dlCpProcBurst;
} else {
printf("set O-RU\n");
p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].owdm_PlLength = p_use_cfg->owdmPlLength;
}
+ if(p_use_cfg->bbu_offload) {
+ if (p_xran_fh_init->io_cfg.id == 0) { /* O-DU */
+ p_xran_fh_init->io_cfg.bbu_offload = 1;
+ p_xran_fh_init->dlCpProcBurst = 1;
+ } else {
+ p_xran_fh_init->io_cfg.bbu_offload = 0;
+ }
+ } else {
+ p_xran_fh_init->io_cfg.bbu_offload = 0;
+ }
+
+ if (p_xran_fh_init->io_cfg.bbu_offload == 0 && XRAN_N_FE_BUF_LEN < 20)
+ rte_panic("Sample application with out BBU requires XRAN_N_FE_BUF_LEN to be at least 20 TTIs\n");
+
p_xran_fh_init->io_cfg.io_sleep = p_use_cfg->io_sleep;
p_xran_fh_init->io_cfg.dpdkMemorySize = p_use_cfg->dpdk_mem_sz;
p_xran_fh_init->io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
p_xran_fh_init->io_cfg.nEthLinePerPort = p_use_cfg->EthLinesNumber;
p_xran_fh_init->io_cfg.nEthLineSpeed = p_use_cfg->EthLinkSpeed;
+ if(p_use_cfg->mlogxrandisable == 1)
+ p_xran_fh_init->mlogxranenable = 0;
+ else
+ p_xran_fh_init->mlogxranenable = 1;
+
app_io_xran_eAxCid_conf_set(&p_xran_fh_init->eAxCId_conf, p_o_xu_cfg);
i = 0;
printf("nSW_ToFpga_FTH_TxBufferLen %d\n", nSW_ToFpga_FTH_TxBufferLen);
return 0;
}
+
+int32_t
+app_io_xran_map_cellid_to_port(struct bbu_xran_io_if * p_xran_io, uint32_t cell_id, uint32_t *ret_cc_id)
+{
+ int32_t port_id;
+ int32_t cc_id;
+
+ if(p_xran_io) {
+ if(cell_id < XRAN_PORTS_NUM*XRAN_MAX_SECTOR_NR) {
+ for (port_id = 0 ; port_id < XRAN_PORTS_NUM && port_id < p_xran_io->num_o_ru; port_id++) {
+ for(cc_id = 0; cc_id < XRAN_MAX_SECTOR_NR && cc_id < p_xran_io->num_cc_per_port[port_id]; cc_id++)
+ if(cell_id == (uint32_t)p_xran_io->map_cell_id2port[port_id][cc_id]) {
+ if(ret_cc_id) {
+ *ret_cc_id = cc_id;
+ return port_id;
+ }
+ }
+ }
+ }
+ }
+
+ printf("%s error [cell_id %d]\n", __FUNCTION__, cell_id);
+ return -1;
+}
+
+#ifndef FWK_ENABLED
+void
+app_io_xran_fh_bbu_rx_callback(void *pCallbackTag, xran_status_t status)
+{
+ app_io_xran_fh_rx_callback(pCallbackTag, status);
+}
+
+void
+app_io_xran_fh_bbu_rx_bfw_callback(void *pCallbackTag, xran_status_t status)
+{
+ app_io_xran_fh_rx_bfw_callback(pCallbackTag, status);
+}
+
+void
+app_io_xran_fh_bbu_rx_prach_callback(void *pCallbackTag, xran_status_t status)
+{
+ app_io_xran_fh_rx_prach_callback(pCallbackTag, status);
+}
+
+void
+app_io_xran_fh_bbu_rx_srs_callback(void *pCallbackTag, xran_status_t status)
+{
+ app_io_xran_fh_rx_srs_callback(pCallbackTag, status);
+}
+#endif
XRANFTHRACH_IN,
XRANSRS_IN,
XRANSRS_PRB_MAP_IN,
+ XRANCP_PRB_MAP_IN_RX,
+ XRANCP_PRB_MAP_IN_TX,
XRANSRS_SEC_DESC_IN,
MAX_SW_XRAN_INTERFACE_NUM
} SWXRANInterfaceTypeEnum;
};
struct xran_io_shared_ctrl {
+ enum xran_input_byte_order byteOrder; /* Order of bytes in int16_t in buffer. Big or little endian */
+ enum xran_input_i_q_order iqOrder; /* order of IQs in the buffer */
+
/* io struct */
struct xran_io_buf_ctrl sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_io_buf_ctrl sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
struct xran_io_buf_ctrl sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
+ struct xran_io_buf_ctrl sFHCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ struct xran_io_buf_ctrl sFHCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
/* buffers lists */
struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ struct xran_flat_buffer sFrontHaulCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ struct xran_flat_buffer sFrontHaulCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
/* Cat B SRS buffers */
struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
+
+ // struct xran_flat_buffer sFHCpRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
};
struct bbu_xran_io_if {
uint16_t nInstanceNum[XRAN_PORTS_NUM]; /**< instance is equivalent to CC */
uint16_t DynamicSectionEna;
+ uint16_t DynamicSectionEnaUL;
uint32_t nPhaseCompFlag;
+ uint32_t xranModCompEna;
+ uint32_t xranCompMethod;
+ uint32_t iqWidth;
+ uint32_t mtu;
+
+ int32_t bbu_offload; /**< enable packet handling on BBU cores */
int32_t num_o_ru;
int32_t num_cc_per_port[XRAN_PORTS_NUM];
struct xran_cb_tag RxCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
struct xran_cb_tag PrachCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
struct xran_cb_tag SrsCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
+ struct xran_cb_tag BfwCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
};
struct bbu_xran_io_if* app_io_xran_if_alloc(void);
struct xran_io_shared_ctrl * app_io_xran_if_ctrl_get(uint32_t o_xu_id);
int32_t app_io_xran_sfidx_get(uint8_t nNrOfSlotInSf);
-int32_t app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg);
+int32_t app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg, struct xran_fh_init* p_xran_fh_init);
int32_t app_io_xran_iq_content_init(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg);
int32_t app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg);
int32_t app_io_xran_eAxCid_conf_set(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg);
int32_t app_io_xran_fh_init_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init);
int32_t app_io_xran_buffers_max_sz_set (RuntimeConfig* p_o_xu_cfg);
+int32_t app_io_xran_dl_post_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask, uint32_t nAntStart, uint32_t nAntNum);
+
int32_t app_io_xran_dl_tti_call_back(void * param);
int32_t app_io_xran_ul_half_slot_call_back(void * param);
int32_t app_io_xran_ul_full_slot_call_back(void * param);
int32_t app_io_xran_ul_custom_sym_call_back(void * param, struct xran_sense_of_time* time);
+int32_t app_io_xran_map_cellid_to_port(struct bbu_xran_io_if * p_xran_io, uint32_t cell_id, uint32_t *ret_cc_id);
+
+int32_t app_io_xran_iq_content_init_cp_tx(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_init_cp_rx(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_init_up_tx(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_init_up_prach(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_init_up_srs(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_get_up_rx(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_get_up_prach(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
+int32_t app_io_xran_iq_content_get_up_srs(uint8_t appMode, struct xran_fh_config *pXranConf,
+ struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
+ int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
+
void app_io_xran_if_stop(void);
#ifdef __cplusplus
MLogGetStats(PID_TTI_TIMER, &tti.cnt, &tti.max, &tti.min, &tti.avg);
if (tti.cnt != 0) {
- sprintf(stats_file, "%s-%s-%s\0", XRAN_REPORT_FILE, (puConf->appMode == APP_O_DU)? "o-du" : "o-ru", usecase);
+ sprintf(stats_file, "%s-%s-%s", XRAN_REPORT_FILE, (puConf->appMode == APP_O_DU)? "o-du" : "o-ru", usecase);
printf("xran report file: %s\n", stats_file);
ret = xran_init_mlog_stats(stats_file, mlog_times_p->ticks_per_usec);
if (ret != 0)
--- /dev/null
+ /******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This module provides implementation of BBU tasks for sample app
+ * @file app_bbu.c
+ * @ingroup xran
+ * @author Intel Corporation
+ *
+ **/
+
+
+/*******************************************************************************
+ * Include public/global header files
+ *******************************************************************************/
+#include <unistd.h>
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <pthread.h>
+#include <immintrin.h>
+
+#include "common.h"
+#include "app_bbu_pool.h"
+#include "app_io_fh_xran.h"
+#include "xran_compression.h"
+#include "xran_cp_api.h"
+#include "xran_fh_o_du.h"
+#include "xran_mlog_task_id.h"
+
+extern RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM];
+static SampleSplitStruct gsUlCfgAxCTaskSplit[MAX_PHY_INSTANCES][MAX_NUM_OF_SF_5G_CTX][MAX_TEST_SPLIT_NUM];
+
+void app_bbu_pool_pre_task_ul_cfg(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara)
+{
+ int32_t nSplitGroup = 0;
+ int32_t iTask = 0;
+ uint32_t nSfIdx = get_dl_sf_idx(nSubframe, nCellIdx);
+ uint32_t nCtxNum = get_dl_sf_ctx(nSfIdx, nCellIdx);
+ SampleSplitStruct *pTaskSplitPara;
+ int32_t nGroupNum = 0;
+ int32_t nSymbStart = 0, nSymbPerSplit = 0;
+ int32_t nTotalLayers = 0, nLayerStart = 0, nLayerPerSplit = 0;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config* pXranConf = NULL;
+ // struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ uint32_t nRuCcidx = 0;
+ int32_t xran_port = 0;
+ uint32_t neAxc = 0;
+
+ if(psXranIoIf == NULL)
+ rte_panic("psXranIoIf == NULL");
+
+ if(nCellIdx >= MAX_PHY_INSTANCES)
+ rte_panic("nCellIdx >= MAX_PHY_INSTANCES");
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return /*EBBUPOOL_CORRECT*/;
+ }
+
+ // psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ if(pXranConf == NULL)
+ rte_panic("pXranConf");
+
+ if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_A) {
+ neAxc = pXranConf->neAxc;
+ nSplitGroup = 1;
+ } else if (pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B) {
+ neAxc = pXranConf->neAxcUl;
+ nSplitGroup = neAxc;
+ } else
+ rte_panic("neAxc");
+
+ nTotalLayers = neAxc;
+
+ /* all symb per eAxC */
+ nSymbStart = 0;
+ // nTotalSymb = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ nSymbPerSplit = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+
+ nLayerPerSplit = nTotalLayers/nSplitGroup;
+
+ pPara->nTaskNum = nSplitGroup;
+ for (iTask = 0; iTask < (nSplitGroup-1) && iTask < (MAX_TEST_SPLIT_NUM-1); iTask ++)
+ {
+ pTaskSplitPara = &(gsUlCfgAxCTaskSplit[nCellIdx][nCtxNum][iTask]);
+ pTaskSplitPara->nSymbStart = nSymbStart;
+ pTaskSplitPara->nSymbNum = nSymbPerSplit;
+ pTaskSplitPara->eSplitType = LAYER_SPLIT;
+ pTaskSplitPara->nSplitIndex = iTask;
+ pTaskSplitPara->nGroupStart = 0;
+ pTaskSplitPara->nGroupNum = nGroupNum;
+ pTaskSplitPara->nLayerStart = nLayerStart;
+ pTaskSplitPara->nLayerNum = nLayerPerSplit;
+ pPara->pTaskExePara[iTask] = pTaskSplitPara;
+ //nSymbStart += nSymbPerSplit;
+ nLayerStart += nLayerPerSplit;
+ }
+
+ pTaskSplitPara = &(gsUlCfgAxCTaskSplit[nCellIdx][nCtxNum][iTask]);
+ pTaskSplitPara->nSymbStart = nSymbStart;
+ pTaskSplitPara->nSymbNum = nSymbPerSplit;
+ pTaskSplitPara->eSplitType = LAYER_SPLIT;
+ pTaskSplitPara->nSplitIndex = iTask;
+ pTaskSplitPara->nGroupStart = 0;
+ pTaskSplitPara->nGroupNum = nGroupNum;
+ pTaskSplitPara->nLayerStart = nLayerStart;
+ pTaskSplitPara->nLayerNum = nTotalLayers - nLayerStart;
+ pPara->pTaskExePara[iTask] = pTaskSplitPara;
+
+ return;
+}
+
+/*! \brief Task function for UL configuration in PHY.
+ \param [in] pCookies Task input parameter.
+ \return BBU pool state
+*/
+int32_t app_bbu_pool_task_ul_config(void * pCookies)
+{
+ EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint32_t nSfIdx = get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
+ uint32_t nCtxNum = get_ul_sf_ctx(nSfIdx, nCellIdx);
+ uint64_t mlog_start = MLogTick();// nTtiStartTime = gTtiStartTime;
+ uint32_t mlogVariablesCnt, mlogVariables[50];
+ uint32_t nRuCcidx = 0;
+ int32_t xran_port = 0;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ struct xran_fh_config* pXranConf = NULL;
+ // uint32_t neAxc = 0;
+ xran_status_t status;
+ struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ int32_t cc_id, ant_id, sym_id, tti;
+ int32_t flowId;
+ struct o_xu_buffers * p_iq = NULL;
+ int32_t nSymbMask = 0b11111111111111;
+ RuntimeConfig *p_o_xu_cfg = NULL;
+ SampleSplitStruct *pTaskPara = (SampleSplitStruct*)pEventCtrl->pTaskPara;
+ uint16_t nLayerStart = 0, nLayer = 0;//, iSplit =0;
+
+ if(psXranIoIf == NULL)
+ rte_panic("psXranIoIf == NULL");
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return EBBUPOOL_CORRECT;
+ }
+ psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+ if(psIoCtrl == NULL)
+ rte_panic("psIoCtrl");
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ if(pXranConf == NULL)
+ rte_panic("pXranConf");
+
+#if 0
+ if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_A)
+ neAxc = pXranConf->neAxc;
+ else if (pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B)
+ neAxc = pXranConf->neAxcUl;
+ else
+ rte_panic("neAxc");
+#endif
+ mlogVariablesCnt = 0;
+ mlogVariables[mlogVariablesCnt++] = 0xCCEECCEE;
+ mlogVariables[mlogVariablesCnt++] = pEventCtrl->nSlotIdx;
+ mlogVariables[mlogVariablesCnt++] = 0;
+ mlogVariables[mlogVariablesCnt++] = nCellIdx;
+ mlogVariables[mlogVariablesCnt++] = nSfIdx;
+ mlogVariables[mlogVariablesCnt++] = nCtxNum;
+ mlogVariables[mlogVariablesCnt++] = xran_port;
+ mlogVariables[mlogVariablesCnt++] = nRuCcidx;
+
+ p_o_xu_cfg = p_startupConfiguration[xran_port];
+ if(p_o_xu_cfg == NULL)
+ rte_panic("p_o_xu_cfg");
+
+ if(LAYER_SPLIT == pTaskPara->eSplitType) {
+ // iSplit = pTaskPara->nSplitIndex;
+ nLayerStart = pTaskPara->nLayerStart;
+ nLayer = pTaskPara->nLayerNum;
+ //printf("\nsf %d nSymbStart %d nSymb %d iSplit %d", nSfIdx, nSymbStart, nSymb, iSplit);
+ } else {
+ rte_panic("LAYER_SPLIT == pTaskPara->eSplitType");
+ }
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
+ }
+ tti = nSfIdx;
+ for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
+ if (cc_id >= XRAN_MAX_SECTOR_NR)
+ {
+ rte_panic("cell id %d exceeding max number", cc_id);
+ }
+ for(ant_id = nLayerStart; ant_id < (nLayerStart + nLayer); ant_id++) {
+ if(p_o_xu_cfg->appMode == APP_O_DU) {
+ flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
+ } else {
+ flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(((1 << sym_id) & nSymbMask)) {
+ if ((status = app_io_xran_iq_content_init_cp_rx(p_o_xu_cfg->appMode, pXranConf,
+ psXranIoIf, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_init_cp_rx");
+ }
+ }
+ }
+ }
+ }
+
+ xran_prepare_cp_ul_slot(xran_port, nSfIdx, nRuCcidx, /*psXranIoIf->num_cc_per_port[xran_port]*/ 1, nSymbMask, nLayerStart,
+ nLayer, 0, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+
+ if (mlogVariablesCnt)
+ MLogAddVariables((uint32_t)mlogVariablesCnt, (uint32_t *)mlogVariables, mlog_start);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PCID_GNB_UL_CFG_CC0+nCellIdx, mlog_start, MLogTick());
+
+ return EBBUPOOL_CORRECT;
+}
+
+int32_t
+app_io_xran_ul_decomp_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
+ uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
+{
+ xran_status_t status;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct o_xu_buffers * p_iq = NULL;
+ RuntimeConfig *p_o_xu_cfg = NULL;
+ int32_t flowId = 0;
+ struct xran_fh_config *pXranConf = NULL;
+ int32_t cc_id, ant_id, sym_id, tti;
+ struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ uint32_t xran_max_antenna_nr;
+ // uint32_t xran_max_ant_array_elm_nr;
+ // uint32_t xran_max_antenna_nr_prach;
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+
+ if(psIoCtrl == NULL) {
+ printf("psIoCtrl == NULL\n");
+ return FAILURE;
+ }
+
+ p_o_xu_cfg = p_startupConfiguration[xran_port];
+ if(p_o_xu_cfg == NULL) {
+ printf("p_o_xu_cfg == NULL\n");
+ return FAILURE;
+ }
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+
+ xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
+ // xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
+ // xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
+
+ tti = nSfIdx;
+ for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
+ for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < xran_max_antenna_nr; ant_id++) {
+ if(p_o_xu_cfg->appMode == APP_O_DU) {
+ flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
+ } else {
+ flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
+ }
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(((1 << sym_id) & nSymMask)) {
+ if ((status = app_io_xran_iq_content_get_up_rx(p_o_xu_cfg->appMode, pXranConf,
+ psXranIoIf, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_get_up_rx");
+ }
+ }
+ }
+ }
+ }
+
+ return SUCCESS;
+}
+
+int32_t
+app_io_xran_prach_decomp_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
+ uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
+{
+ xran_status_t status;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct o_xu_buffers * p_iq = NULL;
+ RuntimeConfig *p_o_xu_cfg = NULL;
+ int32_t flowId = 0;
+ struct xran_fh_config *pXranConf = NULL;
+ int32_t cc_id, ant_id, sym_id, tti;
+ struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ uint32_t xran_max_antenna_nr;
+ // uint32_t xran_max_ant_array_elm_nr;
+ uint32_t xran_max_antenna_nr_prach;
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+
+ if(psIoCtrl == NULL) {
+ printf("psIoCtrl == NULL\n");
+ return FAILURE;
+ }
+
+ p_o_xu_cfg = p_startupConfiguration[xran_port];
+ if(p_o_xu_cfg == NULL) {
+ printf("p_o_xu_cfg == NULL\n");
+ return FAILURE;
+ }
+
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+
+ xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
+ // xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
+ xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
+
+ tti = nSfIdx;
+ for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
+ for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < xran_max_antenna_nr_prach; ant_id++) {
+ flowId = xran_max_antenna_nr_prach * cc_id + ant_id;
+
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(((1 << sym_id) & nSymMask)) {
+ if ((status = app_io_xran_iq_content_get_up_prach(p_o_xu_cfg->appMode, pXranConf,
+ psXranIoIf, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_get_up_prach");
+ }
+ }
+ }
+
+ }
+ }
+
+ return SUCCESS;
+}
+
+int32_t
+app_io_xran_srs_decomp_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
+ uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
+{
+ xran_status_t status;
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct o_xu_buffers * p_iq = NULL;
+ RuntimeConfig *p_o_xu_cfg = NULL;
+ int32_t flowId = 0;
+ struct xran_fh_config *pXranConf = NULL;
+ int32_t cc_id, ant_id, sym_id, tti;
+ struct xran_io_shared_ctrl *psIoCtrl = NULL;
+ uint32_t xran_max_antenna_nr;
+ uint32_t xran_max_ant_array_elm_nr;
+
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
+
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
+
+ if(psIoCtrl == NULL) {
+ printf("psIoCtrl == NULL\n");
+ return FAILURE;
+ }
+
+ p_o_xu_cfg = p_startupConfiguration[xran_port];
+ if(p_o_xu_cfg == NULL) {
+ printf("p_o_xu_cfg == NULL\n");
+ return FAILURE;
+ }
+
+ if(p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs){
+ if(p_o_xu_cfg->p_buff) {
+ p_iq = p_o_xu_cfg->p_buff;
+ } else {
+ rte_panic("Error p_o_xu_cfg->p_buff\n");
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+
+ xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
+ xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
+
+ tti = nSfIdx;
+ for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
+ for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < xran_max_ant_array_elm_nr; ant_id++) {
+ flowId = pXranConf->nAntElmTRx*cc_id + ant_id;
+ for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
+ if(((1 << sym_id) & nSymMask)) {
+ if ((status = app_io_xran_iq_content_get_up_srs(p_o_xu_cfg->appMode, pXranConf,
+ psXranIoIf, psIoCtrl, p_iq,
+ cc_id, ant_id, sym_id, tti, flowId)) != 0) {
+ rte_panic("app_io_xran_iq_content_get_up_srs");
+ }
+ }
+ }
+ }
+ }
+ }
+ return SUCCESS;
+}
+
+
+int32_t
+app_bbu_pool_task_symX_wakeup(void *pCookies, uint32_t nSym)
+{
+ EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint32_t nSfIdx = pEventCtrl->nSlotIdx;/*get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);*/
+
+ uint32_t nSymbMask = 0;
+ uint32_t nSymStart = 0;
+ // uint32_t nSymNum = 0;
+
+ uint32_t Nrx_antennas;
+ uint16_t nOranCellIdx;
+
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct xran_fh_config *pXranConf = NULL;
+
+ nOranCellIdx = nCellIdx;
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ Nrx_antennas = pXranConf->neAxcUl;
+
+ if(Nrx_antennas == 0)
+ rte_panic("[p %d cell %d] Nrx_antennas == 0\n", xran_port, nCellIdx);
+
+ nSymStart = 0;
+ // nSymNum = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+
+ switch(nSym)
+ {
+ case 2: /* [0,1,2] */
+ nSymbMask = 0x7;
+ break;
+ case 6: /* [3,4,5,6] */
+ nSymbMask = 0x78;
+ break;
+ case 11: /* [7,8,9,10,11] */
+ nSymbMask = 0xF80;
+ break;
+ case 13: /* [12,13] */
+ nSymbMask = 0x3000;
+ break;
+ default:
+ rte_panic("nSym %d\n", nSym);
+ }
+
+
+ if (nSym == 13) /* w/a to run copy to IQ buffer as single short */
+ {
+ nSymbMask = 0b11111111111111;
+ app_io_xran_ul_decomp_func(nCellIdx, nSfIdx, nSymbMask, 0, Nrx_antennas, nSymStart, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+ }
+
+ return EBBUPOOL_CORRECT;
+}
+
+int32_t
+app_bbu_pool_task_sym2_wakeup(void *pCookies)
+{
+ int32_t ret = 0;
+ // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ // uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint64_t mlog_start = MLogTick();
+
+ ret = app_bbu_pool_task_symX_wakeup(pCookies, 2);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PID_GNB_SYM2_WAKEUP, mlog_start, MLogTick());
+
+ return ret;
+}
+
+int32_t
+app_bbu_pool_task_sym6_wakeup(void *pCookies)
+{
+ int32_t ret = 0;
+ // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint64_t mlog_start = MLogTick();
+
+ ret = app_bbu_pool_task_symX_wakeup(pCookies, 6);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PID_GNB_SYM6_WAKEUP, mlog_start, MLogTick());
+ return ret;
+}
+
+int32_t
+app_bbu_pool_task_sym11_wakeup(void *pCookies)
+{
+ int32_t ret = 0;
+ // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint64_t mlog_start = MLogTick();
+
+ ret = app_bbu_pool_task_symX_wakeup(pCookies, 11);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PID_GNB_SYM11_WAKEUP, mlog_start, MLogTick());
+ return ret;
+}
+
+int32_t
+app_bbu_pool_task_sym13_wakeup(void *pCookies)
+{
+ int32_t ret = 0;
+ // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint64_t mlog_start = MLogTick();
+
+ ret = app_bbu_pool_task_symX_wakeup(pCookies, 13);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PID_GNB_SYM13_WAKEUP, mlog_start, MLogTick());
+ return ret;
+}
+
+int32_t
+app_bbu_pool_task_prach_wakeup(void *pCookies)
+{
+ EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint32_t nSfIdx = pEventCtrl->nSlotIdx;// get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
+
+ uint32_t nSymbMask = 0;
+ uint32_t nSymStart = 0;
+ // uint32_t nSymNum = 0;
+
+ uint32_t Nrx_antennas;
+ uint16_t nOranCellIdx;
+
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct xran_fh_config *pXranConf = NULL;
+ uint64_t mlog_start = MLogTick();
+ nOranCellIdx = nCellIdx;
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ Nrx_antennas = RTE_MIN(pXranConf->neAxcUl, XRAN_MAX_PRACH_ANT_NUM);
+
+ if(Nrx_antennas == 0)
+ rte_panic("Nrx_antennas == 0\n");
+
+ nSymStart = 0;
+ // nSymNum = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ nSymbMask = 0b11111111111111;
+
+ app_io_xran_prach_decomp_func(nCellIdx, nSfIdx, nSymbMask, 0, Nrx_antennas, nSymStart, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PID_GNB_PRACH_WAKEUP, mlog_start, MLogTick());
+ return EBBUPOOL_CORRECT;
+}
+
+int32_t
+app_bbu_pool_task_srs_wakeup(void *pCookies)
+{
+ int32_t ret = 0;
+ EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
+ uint16_t nCellIdx = pEventCtrl->nCellIdx;
+ uint32_t nSfIdx = pEventCtrl->nSlotIdx;// get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
+
+ uint32_t nSymbMask = 0;
+ uint32_t nSymStart = 0;
+ // uint32_t nSymNum = 0;
+
+ uint32_t Nrx_antennas;
+ uint16_t nOranCellIdx;
+
+ struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
+
+ int32_t xran_port = 0;
+ uint32_t nRuCcidx = 0;
+ struct xran_fh_config *pXranConf = NULL;
+ uint64_t mlog_start = MLogTick();
+ nOranCellIdx = nCellIdx;
+ xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
+ if(xran_port < 0) {
+ printf("incorrect xran_port\n");
+ return FAILURE;
+ }
+
+ pXranConf = &app_io_xran_fh_config[xran_port];
+ Nrx_antennas = pXranConf->nAntElmTRx;
+
+ nSymStart = 0;
+ // nSymNum = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ nSymbMask = 0b11111111111111;
+
+ ret = app_io_xran_srs_decomp_func(nCellIdx, nSfIdx, nSymbMask, 0, Nrx_antennas, nSymStart, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+ //unlock the next task
+ next_event_unlock(pCookies);
+ MLogTask(PID_GNB_SRS_WAKEUP, mlog_start, MLogTick());
+ return ret;
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file has utilities to parse the parameters passed in through the command
+ * line and configure the application based on these parameters
+ * @file aux_cline.c
+ * @ingroup xran
+ * @author Intel Corporation
+ **/
+
+
+#include "aux_cline.h"
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <limits.h>
+#include <pthread.h>
+
+
+typedef struct _CLINE_KEY_TABLE_
+{
+ char *name;
+ char *value;
+} CLINE_KEY_TABLE;
+
+
+#define CLINE_MAXKEYS (256)
+#define CLINE_MAX_STRING_LENGTH (128)
+#define CLINE_MAXKEYSIZE (2048)
+
+static CLINE_KEY_TABLE PhyAppKeys[CLINE_MAXKEYS];
+static uint32_t pPhyCfgNumEntries = 0;
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param void
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * Initialize Cline Interface
+ *
+**/
+//-------------------------------------------------------------------------------------------
+int cline_init(void)
+{
+ uint32_t i;
+ pPhyCfgNumEntries = 0;
+ for (i = 0; i < CLINE_MAXKEYS; i++)
+ {
+ PhyAppKeys[i].name = NULL;
+ PhyAppKeys[i].value = NULL;
+ }
+
+ return AUX_SUCCESS;
+}
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *name String to search for
+ * @param[out] *value Pointer to location where number needs to be stored
+ * @param[in] deflt Default value to put into the value field if string is not found
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This funtion searchs for a string from the phycfg.xml file and returns the number that
+ * was associated in file
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_set_int(const char *name, int *value, int deflt)
+{
+ uint32_t i;
+
+ for (i = 0; i < pPhyCfgNumEntries; i++)
+ {
+ if (PhyAppKeys[i].name)
+ {
+ if (strcasecmp(name, PhyAppKeys[i].name) == 0)
+ {
+ char *p1 = PhyAppKeys[i].value;
+ if (strstr(p1, "0x") || strstr(p1, "0X"))
+ {
+ uint64_t core;
+ if (cline_covert_hex_2_dec(p1, &core) != AUX_SUCCESS)
+ {
+ printf("cline_set_int Failed (%s)\n", p1);
+ return AUX_FAILURE;
+ }
+ *value = (int)core;
+ }
+ else
+ {
+ *value = (int)strtol(PhyAppKeys[i].value, NULL, 0);
+ if ((*value == 0 && errno == EINVAL) || (*value == INT_MAX && errno == ERANGE))
+ {
+ *value = deflt;
+ return AUX_FAILURE;
+ }
+ }
+ break;
+ }
+ }
+ else
+ {
+ // End of list reached
+ *value = deflt;
+ printf("incomming setting in XML: param \"%s\" is not found!\n", name);
+ return AUX_FAILURE;
+ }
+ }
+
+ return AUX_SUCCESS;
+}
+
+
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *name String to search for
+ * @param[out] *value Pointer to location where number needs to be stored
+ * @param[in] deflt Default value to put into the value field if string is not found
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This funtion searchs for a string from the phycfg.xml file and returns the number that
+ * was associated in file
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_set_uint64(const char *name, uint64_t *value, uint64_t deflt)
+{
+ uint32_t i;
+
+ for (i = 0; i < pPhyCfgNumEntries; i++)
+ {
+ if (PhyAppKeys[i].name)
+ {
+ if (strcasecmp(name, PhyAppKeys[i].name) == 0)
+ {
+ if (strstr(PhyAppKeys[i].value, "0x") || strstr(PhyAppKeys[i].value, "0X"))
+ {
+ if (cline_covert_hex_2_dec(PhyAppKeys[i].value, value) != AUX_SUCCESS)
+ {
+ printf("cline_covert_hex_2_dec Failed (%s)\n", PhyAppKeys[i].value);
+ return AUX_FAILURE;
+ }
+ }
+ else
+ {
+ *value = strtoull(PhyAppKeys[i].value, NULL, 0);
+ }
+ if ((*value == 0 && errno == EINVAL) || (*value == LONG_MAX && errno == ERANGE))
+ {
+ *value = deflt;
+ return AUX_FAILURE;
+ }
+ break;
+ }
+ }
+ else
+ {
+ // End of list reached
+ *value = deflt;
+ printf("incomming setting in XML: param \"%s\" is not found!\n", name);
+ return AUX_FAILURE;
+ }
+ }
+
+ return AUX_SUCCESS;
+}
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *pStr String to search for
+ * @param[out] *pDst Pointer to location where number needs to be stored
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This funtion takes a char string as input and converts it to a unit61_t
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_covert_hex_2_dec(char *pStr, uint64_t *pDst)
+{
+ char nibble;
+ int32_t i;
+ uint32_t len;
+ uint64_t value = 0, mult = 1, nibble_val = 0;
+
+ // Skip over "0x"
+ pStr += 2;
+
+ len = strlen(pStr);
+ if (len > 16)
+ {
+ printf("String Length is invalid: %p [%d]\n", pStr, len);
+ }
+
+ for (i = len - 1; i >= 0; i--)
+ {
+ nibble = pStr[i];
+ if ((nibble >= '0') && (nibble <= '9'))
+ {
+ nibble_val = nibble - '0';
+ }
+ else if ((nibble >= 'A') && (nibble <= 'F'))
+ {
+ nibble_val = nibble - 'A' + 10;
+ }
+ else if ((nibble >= 'a') && (nibble <= 'f'))
+ {
+ nibble_val = nibble - 'a' + 10;
+ }
+ else
+ {
+ printf("String is invalid: %p[%d] %c\n", pStr, i, nibble);
+ return AUX_FAILURE;
+ }
+
+ value += (nibble_val * mult);
+
+ mult = mult * 16;
+ }
+
+ *pDst = value;
+
+ return AUX_SUCCESS;
+}
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *name String to search for
+ * @param[out] *core Pointer to location where core id needs to be stored
+ * @param[out] *priority Pointer to location where priority needs to be stored
+ * @param[out] *policy Pointer to location where policy needs to be stored
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This funtion searchs for a string from the phycfg.xml file stores all thread related info into
+ * output locations
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_set_thread_info(const char *name, uint64_t *core, int *priority, int *policy)
+{
+#ifndef TEST_APP
+ uint32_t i;
+ int sched;
+ char *p1, *p2, *p3;
+
+ for (i = 0; i < pPhyCfgNumEntries; i++)
+ {
+ if (PhyAppKeys[i].name)
+ {
+ if (strcasecmp(name, PhyAppKeys[i].name) == 0)
+ {
+ p1 = (char*)PhyAppKeys[i].value;
+ p2 = strstr(p1, ",");
+ if (p2)
+ {
+ *p2 = '\0';
+ p2++;
+ p3 = strstr(p2, ",");
+ if (p3)
+ {
+ *p3 = '\0';
+ p3++;
+
+ if (strstr(p1, "0x") || strstr(p1, "0X"))
+ {
+ if (cline_covert_hex_2_dec(p1, core) != AUX_SUCCESS)
+ {
+ printf("cline_covert_hex_2_dec Failed (%s)\n", p1);
+ return AUX_FAILURE;
+ }
+ }
+ else
+ {
+ *core = strtoull(p1, NULL, 0);
+ }
+ *priority = strtol(p2, NULL, 0);
+ sched = strtol(p3, NULL, 0);
+
+ *policy = (sched ? SCHED_RR : SCHED_FIFO);
+
+ //print_info_log("%s %ld %d %d\n", name, *core, *priority, *policy);
+
+ return AUX_SUCCESS;
+ }
+ else
+ {
+ printf("p3 is null %s\n", p2);
+ }
+ }
+ else
+ {
+ printf("p2 is null %s\n", p1);
+ }
+
+ printf("%s FAIL1\n", name);
+ return AUX_FAILURE;
+ }
+ }
+ else
+ {
+ // End of list reached
+ printf("incomming setting in XML: param \"%s\" is not found!\n", name);
+
+ printf("cline_set_thread_info: %s FAIL2\n", name);
+ return AUX_FAILURE;
+ }
+ }
+
+ printf("cline_set_thread_info: %s FAIL3\n", name);
+ return AUX_FAILURE;
+#else
+ return AUX_SUCCESS;
+#endif
+}
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *name String to search for
+ * @param[in] maxLen Max lenth of output array
+ * @param[out] *dataOut Pointer to the data array filled by each int element of the input string
+ * @param[out] *outLen Filled length of the array
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This funtion searchs for a string from the phycfg.xml file stores all int value to output array
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_set_int_array(const char *name, int maxLen, int *dataOut, int *outLen)
+{
+ uint32_t i;
+ char *p1, *p2;
+ *outLen = 0;
+
+ for (i = 0; i < pPhyCfgNumEntries; i++)
+ {
+ if (PhyAppKeys[i].name)
+ {
+ if (strcasecmp(name, PhyAppKeys[i].name) == 0)
+ {
+ p1 = (char*)PhyAppKeys[i].value;
+ while(*outLen < maxLen)
+ {
+ p2 = strstr(p1, ",");
+ if(p2)
+ {
+ *p2 = '\0';
+ p2 ++;
+ dataOut[*outLen] = strtol(p1, NULL, 0);
+ //printf("\ngranularity %d in idx %d",dataOut[*outLen],*outLen);
+ p1 = p2;
+ *outLen += 1;
+ }
+ else
+ {
+ dataOut[*outLen] = strtol(p1, NULL, 0);
+ //printf("\ngranularity %d in idx %d",dataOut[*outLen],*outLen);
+ *outLen += 1;
+ break;
+ }
+ }
+ return AUX_SUCCESS;
+ }
+ }
+ }
+
+ //printf("cline_set_int_array: Could not find %s\n", name);
+
+ return AUX_SUCCESS;
+}
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *name String to search for
+ * @param[out] *value Pointer to location where string needs to be stored
+ * @param[in] deflt Default value to put into the value field if string is not found
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This funtion searchs for a string from the phycfg.xml file and returns the string that
+ * was associated in file
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_set_str(const char *name, char *value, const char *deflt)
+{
+ uint32_t i;
+
+ for (i = 0; i < CLINE_MAXKEYS; i++)
+ {
+ if (PhyAppKeys[i].name)
+ {
+ if (strcasecmp(name, PhyAppKeys[i].name) == 0)
+ {
+ strcpy(value, PhyAppKeys[i].value);
+ break;
+ }
+ }
+ else
+ {
+ // End of list reached
+ strcpy(value, deflt);
+ return AUX_FAILURE;
+ }
+ }
+
+ return AUX_SUCCESS;
+}
+
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] *pString Pointer to string that needs to be parsed
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This function takes a line from phycfg.xml and parses it and if valid fields are found,
+ * stores the xml tag and the value associated with the tag into a global structure.
+ *
+**/
+//-------------------------------------------------------------------------------------------
+int cline_parse_line(char *pString)
+{
+ char *stringLocal, *ptr1, *ptr2, *ptr3;
+// char stringName[CLINE_MAX_STRING_LENGTH] = "", stringValue[CLINE_MAX_STRING_LENGTH] = "";
+ char *stringName, *stringValue;
+
+ stringLocal = NULL;
+ stringName = NULL;
+ stringValue = NULL;
+ ptr1 = ptr2 = ptr3 = NULL;
+ uint32_t strLen = strlen(pString);
+ if (strLen)
+ {
+ stringLocal = (char *)malloc(strLen + 1);
+ if (stringLocal == NULL)
+ {
+ printf("Cannot allocate stringLocal of size %d\n", (strLen + 1));
+ return AUX_FAILURE;
+ }
+ }
+
+ // Dont Destroy Original String
+ if (stringLocal)
+ strcpy(stringLocal, pString);
+
+ if (stringLocal)
+ {
+ if (strlen(stringLocal) <= 2) // Probably line feed
+ {
+ if (stringLocal)
+ free(stringLocal);
+ return AUX_SUCCESS;
+ }
+ }
+ ptr1 = stringLocal;
+
+ // Locate Starting
+ if (ptr1)
+ ptr2 = strstr(ptr1, "<");
+ if (ptr2 == NULL)
+ {
+ if (stringLocal)
+ free(stringLocal);
+ printf("no begin at parameters string");
+ return AUX_FAILURE;
+ }
+
+ // See if this is a comment
+ if (ptr2)
+ ptr3 = strstr(ptr2, "!--");
+ if (ptr3 != NULL)
+ {
+ if (stringLocal)
+ free(stringLocal);
+ return AUX_SUCCESS;
+ }
+
+ // Locate Ending
+ if (ptr2)
+ ptr3 = strstr(ptr2, ">");
+ if (ptr3 == NULL)
+ {
+ if (stringLocal)
+ free(stringLocal);
+ printf("no ending at parameters string");
+ return AUX_FAILURE;
+ }
+
+ // Copy string
+ if (ptr3)
+ *ptr3 = '\0';
+ if (ptr2)
+ strLen = strlen(ptr2 + 1);
+ if (strLen)
+ {
+ stringName = (char *)malloc(strLen + 1);
+ if (stringName == NULL)
+ {
+ if (stringLocal)
+ free(stringLocal);
+ printf("Cannot allocate stringName of size %d\n", (strLen + 1));
+ return AUX_FAILURE;
+ }
+ else
+ {
+ if (ptr2)
+ strcpy(stringName, ptr2 + 1);
+ }
+ }
+
+ ptr1 = ptr3+1;
+
+ // Locate Starting
+ if (ptr1)
+ ptr2 = strstr(ptr1, "<");
+ if (ptr2 != NULL)
+ {
+ // Locate Ending
+ if (ptr2)
+ ptr3 = strstr(ptr2, ">");
+ if (ptr3 == NULL)
+ {
+ if (stringName)
+ free(stringName);
+ if (stringLocal)
+ free(stringLocal);
+ printf("no ending at parameters string");
+ return AUX_FAILURE;
+ }
+
+ // Copy string
+ strLen = 0;
+ if (ptr2)
+ *ptr2 = '\0';
+ if (ptr1)
+ strLen = strlen(ptr1);
+ if (strLen)
+ {
+ stringValue = (char *)malloc(strLen + 1);
+ if (stringValue == NULL)
+ {
+ if (stringName)
+ free(stringName);
+ if (stringLocal)
+ free(stringLocal);
+ printf("Cannot allocate stringValue of size %d\n", (strLen + 1));
+ return AUX_FAILURE;
+ }
+ if (ptr1)
+ strcpy(stringValue, ptr1);
+ }
+
+#ifdef WIN32
+ printf("Found String: %s with Value: %s\n", stringName, stringValue);
+#endif
+ {
+ uint32_t len = 0;
+
+ if (stringName)
+ {
+ len = strlen(stringName);
+ if (len)
+ {
+ PhyAppKeys[pPhyCfgNumEntries].name = (char *) malloc(len+1);
+ if (PhyAppKeys[pPhyCfgNumEntries].name == NULL)
+ {
+ if (stringName)
+ free(stringName);
+ if (stringLocal)
+ free(stringLocal);
+ if (stringValue)
+ free(stringValue);
+ printf("Cannot allocate PhyAppKeys[pPhyCfgNumEntries].name of size %d\n", (strLen + 1));
+ return AUX_FAILURE;
+ }
+ if (stringName)
+ strcpy(PhyAppKeys[pPhyCfgNumEntries].name, stringName);
+ }
+ }
+
+ len = 0;
+ if (stringValue)
+ {
+ len = strlen(stringValue);
+ if (len)
+ {
+ PhyAppKeys[pPhyCfgNumEntries].value = (char *)malloc(len + 1);
+ if (PhyAppKeys[pPhyCfgNumEntries].value == NULL)
+ {
+ if (stringName)
+ free(stringName);
+ if (stringLocal)
+ free(stringLocal);
+ if (stringValue)
+ free(stringValue);
+ printf("Cannot allocate PhyAppKeys[pPhyCfgNumEntries].value of size %d\n", (strLen + 1));
+ return AUX_FAILURE;
+ }
+ if (stringValue)
+ strcpy(PhyAppKeys[pPhyCfgNumEntries].value, stringValue);
+ }
+ }
+ }
+ pPhyCfgNumEntries++;
+ }
+
+ if(stringLocal)
+ free(stringLocal);
+ if (stringName)
+ free(stringName);
+ if (stringValue)
+ free(stringValue);
+
+ return AUX_SUCCESS;
+}
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param void
+ *
+ * @return void
+ *
+ * @description
+ * This function prints all the tags and values found in the phycfg.xml file after parsing
+ *
+**/
+//-------------------------------------------------------------------------------------------
+void cline_print_info(void)
+{
+#ifndef TEST_APP
+ uint32_t i;
+
+ for (i = 0; i < pPhyCfgNumEntries; i++)
+ {
+ if (PhyAppKeys[i].name)
+ {
+ printf(" --%s=%s\n", PhyAppKeys[i].name, PhyAppKeys[i].value);
+ }
+ }
+ printf("\n");
+#endif
+ return;
+}
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_source_auxlib_cline
+ *
+ * @param[in] argc Number of command line params
+ * @param[in] *argv[] Array of command line params
+ * @param[in] pString String to search for
+ * @param[out] *pDest Location where to store the payload
+ *
+ * @return 0 if AUX_SUCCESS
+ *
+ * @description
+ * This function looks for a string passed in from the command line and returns the immediate
+ * next parameter passed after this.
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t cline_get_string(int argc, char *argv[], char* pString, char *pDest)
+{
+ uint32_t ret = AUX_FAILURE;
+ int i = 1, length = (int)strlen(pString);
+ char *filename = NULL;
+
+ //print_info_log("Searching for string: %s. Length of string: %d\n", pString, length);
+ while (i < argc)
+ {
+ if (strstr(argv[i], pString) != NULL)
+ {
+ filename = strstr(argv[i], pString);
+ filename += (length + 1);
+
+ //print_info_log("Found %s: Val = %s\n", pString, filename);
+ strcpy(pDest, filename);
+
+ ret = AUX_SUCCESS;
+ break;
+ }
+
+ i++;
+ }
+
+ return ret;
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file has utilities to parse the parameters passed in through the command
+ * line and configure the application based on these parameters
+ * @file aux_cline.h
+ * @ingroup xran
+ * @author Intel Corporation
+ **/
+
+#ifndef _AUX_CLINE_H_
+#define _AUX_CLINE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define AUX_SUCCESS 0
+#define AUX_FAILURE 1
+
+int cline_init (void);
+uint32_t cline_set_int(const char *name, int *value, int deflt);
+uint32_t cline_set_uint64(const char *name, uint64_t *value, uint64_t deflt);
+uint32_t cline_covert_hex_2_dec(char *pStr, uint64_t *pDst);
+uint32_t cline_set_thread_info(const char *name, uint64_t *core, int *priority, int *sched);
+uint32_t cline_set_int_array(const char *name, int maxLen, int *dataOut, int *outLen);
+uint32_t cline_set_str(const char *name, char *value, const char *deflt);
+int cline_parse_line(char *pString);
+void cline_print_info(void);
+uint32_t cline_get_string(int argc, char *argv[], char* pString, char *pDest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_AUX_CLINE_H_*/
+
{{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
};
-uint32_t gMaxSlotNum;
-uint32_t gNumDLCtx;
-uint32_t gNumULCtx;
-uint32_t gDLResetAdvance;
-uint32_t gDLProcAdvance;
-uint32_t gULProcAdvance;
+uint32_t gLocMaxSlotNum;
static uint16_t g_NumSlotTDDLoop[XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP };
static uint16_t g_NumDLSymSp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
int32_t app_xran_slot_limit(int32_t nSfIdx)
{
while (nSfIdx < 0) {
- nSfIdx += gMaxSlotNum;
+ nSfIdx += gLocMaxSlotNum;
}
- while (nSfIdx >= gMaxSlotNum) {
- nSfIdx -= gMaxSlotNum;
+ while (nSfIdx >= gLocMaxSlotNum) {
+ nSfIdx -= gLocMaxSlotNum;
}
return nSfIdx;
#include <rte_common.h>
#include <rte_mbuf.h>
-#define VERSIONX "oran_e_maintenance_release_v1.0"
+#define VERSIONX "oran_f_release_v1.0"
#define APP_O_DU 0
#define APP_O_RU 1
int iq_srs_buffer_size_ul;
+ int numSlots; /**< number of slots in IQ vector */
+
int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
- int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
- int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
- int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
int16_t *p_srs_log_buffer[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int32_t srs_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
- int32_t srs_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED_CAT_B];
int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-DU) */
int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
- int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
+
+ int16_t *p_tx_dl_bfw_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
+ int32_t tx_dl_bfw_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-DU) */
int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
- int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
+
+ int16_t *p_tx_ul_bfw_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
+ int32_t tx_ul_bfw_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
/* beamforming weights for UL (O-RU) */
int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
#define KEY_FILE_ULBFWUE "UlBfwUe"
#define KEY_FILE_O_XU_CFG "oXuCfgFile"
+#define KEY_FILE_O_XU_BBU_CFG "oXuBbuCfgFile"
#define KEY_O_XU_PCIE_BUS "PciBusAddoXu"
#define KEY_O_XU_REM_MAC "oXuRem"
+#define KEY_DL_CP_BURST "dlCpProcBurst"
+#define KEY_XRAN_MLOG_DIS "xranMlogDisable"
#define KEY_FILE_ULSRS "antSrsC"
#define KEY_FILE_SLOT_TX "SlotNumTx"
#define KEY_FILE_SLOT_RX "SlotNumRx"
-#define KEY_PRACH_ENABLE "rachEanble"
-#define KEY_SRS_ENABLE "srsEanble"
+#define KEY_PRACH_ENABLE "rachEnable"
+#define KEY_SRS_ENABLE "srsEnable"
#define KEY_PUSCH_MASK_ENABLE "puschMaskEnable"
#define KEY_PUSCH_MASK_SLOT "puschMaskSlot"
#define KEY_PRACH_CFGIDX "prachConfigIndex"
+#define KEY_PRACH_CFGIDX_LTE "prachConfigIndexLTE"
#define KEY_SRS_SYM_IDX "srsSym"
+#define KEY_SRS_SLOT "srsSlot"
+#define KEY_SRS_NDM_OFFSET "srsNdmOffset"
+#define KEY_SRS_NDM_TXDUR "srsNdmTxDuration"
#define KEY_MAX_FRAME_ID "maxFrameId"
#define KEY_DEBUG_STOP_CNT "debugStopCount"
#define KEY_BBDEV_MODE "bbdevMode"
#define KEY_DYNA_SEC_ENA "DynamicSectionEna"
+#define EXT_TYPE "extType"
#define KEY_ALPHA "Gps_Alpha"
#define KEY_BETA "Gps_Beta"
#define KEY_PRBELEM_SRS "PrbElemSrs"
#define KEY_MAX_SEC_SYM "max_sections_per_symbol"
#define KEY_MAX_SEC_SLOT "max_sections_per_slot"
+#define KEY_PRBMAP_BY_SYMB "RunSlotPrbMapBySymbolEna"
+#define KEY_DSS_ENABLE "dssEnable"
+#define KEY_DSS_PERIOD "dssPeriod"
+#define KEY_TECHNOLOGY "technology"
typedef int (*fillConfigStruct_fn)(void* cbPram, const char *key, const char *value);
struct slot_cfg_to_pars {
*
* @todo Initialize missing parameters.
*/
-static void init_config(RuntimeConfig* config)
-{
- memset(config , 0, sizeof(RuntimeConfig));
-}
+//static void init_config(RuntimeConfig* config)
+//{
+// memset(config , 0, sizeof(RuntimeConfig));
+//}
static int32_t
parseFileViaCb (char *filename, fillConfigStruct_fn cbFn, void* cbParm);
static int fillConfigStruct(RuntimeConfig *config, const char *key, const char *value)
{
- int32_t parse_res = 0;
static uint32_t section_idx_dl = 0;
static uint32_t section_idx_ul = 0;
static uint32_t section_idx_srs = 0;
} else if (strcmp(key, KEY_SRS_ENABLE) == 0) {
config->enableSrs = atoi(value);
printf("Srs enable: %d\n",config->enableSrs);
+ } else if (strcmp(key, KEY_SRS_SYM_IDX) == 0) {
+ config->srsSymMask = atoi(value);
+ printf("Srs symbol [0-13]: %d\n",config->srsSymMask);
+ } else if (strcmp(key, KEY_SRS_SLOT) == 0) {
+ config->srsSlot = atoi(value);
+ printf("Srs slot: %d\n",config->srsSlot);
+ } else if (strcmp(key, KEY_SRS_NDM_OFFSET) == 0) {
+ config->srsNdmOffset = atoi(value);
+ printf("Srs NDM Offset: %d\n",config->srsNdmOffset);
+ } else if (strcmp(key, KEY_SRS_NDM_TXDUR) == 0) {
+ config->srsNdmTxDuration = atoi(value);
+ printf("Srs NDM TX duration: %d\n",config->srsNdmTxDuration);
} else if (strcmp(key, KEY_PUSCH_MASK_ENABLE) == 0) {
config->puschMaskEnable = atoi(value);
printf("PUSCH mask enable: %d\n",config->puschMaskEnable);
} else if (strcmp(key, KEY_PRACH_CFGIDX) == 0) {
config->prachConfigIndex = atoi(value);
printf("Prach config index: %d\n",config->prachConfigIndex);
- } else if (strcmp(key, KEY_SRS_SYM_IDX) == 0) {
- config->srsSymMask = atoi(value);
- printf("Srs symbol [0-13]: %d\n",config->srsSymMask);
+ } else if (strcmp(key, KEY_PRACH_CFGIDX_LTE) == 0) {
+ config->prachConfigIndexLTE = atoi(value);
+ printf("Prach config index LTE for DSS: %d\n",config->prachConfigIndexLTE);
} else if (strncmp(key, KEY_FILE_PRACH_AxC, strlen(KEY_FILE_PRACH_AxC)) == 0) {
unsigned int ant_num = 0;
sscanf(key,"antPrachC%02u",&ant_num);
} else if (strcmp(key, KEY_DYNA_SEC_ENA) == 0) {
config->DynamicSectionEna = atoi(value);
printf("DynamicSectionEna: %d\n",config->DynamicSectionEna);
+ } else if (strcmp(key, EXT_TYPE) == 0) {
+ config->extType = atoi(value);
+ printf("ExtType: %d\n",config->extType);
} else if (strcmp(key, KEY_ALPHA) == 0) {
config->GPS_Alpha = atoi(value);
printf("GPS_Alpha: %d\n",config->GPS_Alpha);
}
else{
struct xran_prb_elm *pPrbElem = &config->p_PrbMapUl->prbMap[section_idx_ul];
- sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
+ sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
(uint8_t*)&pPrbElem->bf_weight.numBundPrb,
(uint8_t*)&pPrbElem->bf_weight.numSetBFWs,
(uint8_t*)&pPrbElem->bf_weight.RAD,
(uint8_t*)&pPrbElem->bf_weight.disableBFWs,
(uint8_t*)&pPrbElem->bf_weight.bfwIqWidth,
- (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth);
+ (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth,
+ (uint8_t*)&pPrbElem->bf_weight.extType);
printf(KEY_EXTBFW_UL"%d: ", section_idx_ul);
- printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n",
- pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth);
+ printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d, extType %d\n",
+ pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth, pPrbElem->bf_weight.extType);
}
}else if (strcmp(key, KEY_NPRBELEM_DL ) == 0) {
config->p_PrbMapDl->nPrbElm = atoi(value);
}
else{
struct xran_prb_elm *pPrbElem = &config->p_PrbMapDl->prbMap[section_idx_dl];
- sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
+ sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
(uint8_t*)&pPrbElem->bf_weight.numBundPrb,
(uint8_t*)&pPrbElem->bf_weight.numSetBFWs,
(uint8_t*)&pPrbElem->bf_weight.RAD,
(uint8_t*)&pPrbElem->bf_weight.disableBFWs,
(uint8_t*)&pPrbElem->bf_weight.bfwIqWidth,
- (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth);
+ (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth,
+ (uint8_t*)&pPrbElem->bf_weight.extType);
printf(KEY_EXTBFW_DL"%d: ", section_idx_dl);
- printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n",
- pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth);
+ printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d, extType %d\n",
+ pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth, pPrbElem->bf_weight.extType);
}
} else if (strcmp(key, KEY_NPRBELEM_SRS ) == 0) {
config->p_PrbMapSrs->nPrbElm = atoi(value);
printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n",
pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType);
}
+ } else if (strcmp(key, KEY_PRBMAP_BY_SYMB ) == 0) {
+ config->RunSlotPrbMapBySymbolEnable = atoi(value);
+ printf("RunSlotPrbMapBySymbolEnable: %d\n",config->RunSlotPrbMapBySymbolEnable);
+ } else if (strcmp(key, KEY_DSS_ENABLE ) == 0) {
+ config->dssEnable = atoi(value);
+ printf("dssEnable: %d\n",config->dssEnable);
+ } else if (strcmp(key, KEY_DSS_PERIOD ) == 0) {
+ config->dssPeriod = atoi(value);
+ printf("dssPeriod: %d\n",config->dssPeriod);
+ } else if (strcmp(key, KEY_TECHNOLOGY ) == 0) {
+ int i = 0;
+ sscanf(value, "%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx",
+ (uint8_t *)&config->technology[0],
+ (uint8_t *)&config->technology[1],
+ (uint8_t *)&config->technology[2],
+ (uint8_t *)&config->technology[3],
+ (uint8_t *)&config->technology[4],
+ (uint8_t *)&config->technology[5],
+ (uint8_t *)&config->technology[6],
+ (uint8_t *)&config->technology[7],
+ (uint8_t *)&config->technology[8],
+ (uint8_t *)&config->technology[9],
+ (uint8_t *)&config->technology[10],
+ (uint8_t *)&config->technology[11],
+ (uint8_t *)&config->technology[12],
+ (uint8_t *)&config->technology[13],
+ (uint8_t *)&config->technology[14]);
+ printf("technology:");
+ for( i=0; i<config->dssPeriod; i++) {
+ printf("%d ",config->technology[i]);
+ }
+ printf("\n");
}else {
printf("Unsupported configuration key [%s]\n", key);
return -1;
}
-
return 0;
}
static int
fillUsecaseStruct(UsecaseConfig *config, const char *key, const char *value)
{
- int32_t parse_res = 0;
if (strcmp(key, KEY_APP_MODE) == 0){
config->appMode = atoi(value);
printf("appMode %d \n", config->appMode);
strncpy(&config->o_xu_cfg_file[o_xu_id][0], value, strlen(value));
printf("oXuCfgFile%d: %s\n",o_xu_id, config->o_xu_cfg_file[o_xu_id]);
}
+ } else if (strncmp(key, KEY_FILE_O_XU_BBU_CFG, strlen(KEY_FILE_O_XU_BBU_CFG)) == 0) {
+ strncpy(&config->o_xu_bbu_cfg_file[0], value, strlen(value));
+ printf("oXuBbuCfgFile: %s\n", config->o_xu_bbu_cfg_file);
} else if (strncmp(key, KEY_OWDM_INIT_EN, strlen(KEY_OWDM_INIT_EN)) == 0) {
config->owdmInitEn = atoi(value);
printf("owdmInitEn %d\n", config->owdmInitEn);
config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[4],
config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[5]);
}
+ }
+ else if (strncmp(key, KEY_DL_CP_BURST, strlen(KEY_DL_CP_BURST)) == 0) {
+ config->dlCpProcBurst = atoi(value);
+ printf("dlCpProcBurst %d\n", config->dlCpProcBurst);
+ } else if (strncmp(key, KEY_XRAN_MLOG_DIS, strlen(KEY_XRAN_MLOG_DIS)) == 0) {
+ config->mlogxrandisable = atoi(value);
+ printf("xranMlogDisable %d\n", config->mlogxrandisable);
} else {
printf("Unsupported configuration key [%s]\n", key);
return -1;
printf("section_idx %d of bfw exceeds nPrbElemUl\n",section_idx);
}else{
struct xran_prb_elm *pPrbElem = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx];
- sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
+ sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
(uint8_t*)&pPrbElem->bf_weight.numBundPrb,
(uint8_t*)&pPrbElem->bf_weight.numSetBFWs,
(uint8_t*)&pPrbElem->bf_weight.RAD,
(uint8_t*)&pPrbElem->bf_weight.disableBFWs,
(uint8_t*)&pPrbElem->bf_weight.bfwIqWidth,
- (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth);
+ (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth,
+ (uint8_t*)&pPrbElem->bf_weight.extType);
printf(KEY_EXTBFW_UL"%d: ", section_idx);
- printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n",
- pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth);
+ printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d, extType %d\n",
+ pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth, pPrbElem->bf_weight.extType);
}
}else if (strcmp(key, KEY_NPRBELEM_DL ) == 0) {
config->p_SlotPrbMap[direction][slot_idx]->nPrbElm = atoi(value);
}
else{
struct xran_prb_elm *pPrbElem = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx];
- sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
+ sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu",
(uint8_t*)&pPrbElem->bf_weight.numBundPrb,
(uint8_t*)&pPrbElem->bf_weight.numSetBFWs,
(uint8_t*)&pPrbElem->bf_weight.RAD,
(uint8_t*)&pPrbElem->bf_weight.disableBFWs,
(uint8_t*)&pPrbElem->bf_weight.bfwIqWidth,
- (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth);
+ (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth,
+ (uint8_t*)&pPrbElem->bf_weight.extType);
printf(KEY_EXTBFW_DL"%d: ",section_idx);
- printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n",
- pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth);
+ printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d, extType %d\n",
+ pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth, pPrbElem->bf_weight.extType);
}
} else {
printf("Unsupported configuration key [%s]\n", key);
struct xran_prb_map*
config_malloc_prb_map(void)
{
- uint32_t size = sizeof(struct xran_prb_map) + (XRAN_MAX_SECTIONS_PER_SLOT -1) * sizeof(struct xran_prb_elm);
+ //uint32_t size = sizeof(struct xran_prb_map) + (XRAN_MAX_SECTIONS_PER_SLOT -1) * sizeof(struct xran_prb_elm);
+ uint32_t size = sizeof(struct xran_prb_map) + (8) * sizeof(struct xran_prb_elm);
void *ret = NULL;
ret = malloc(size);
int32_t
config_init(RuntimeConfig *p_o_xu_cfg)
{
- int32_t i, j, k, z;
+ int32_t i, j;
memset(p_o_xu_cfg, 0, sizeof(RuntimeConfig));
p_o_xu_cfg->p_PrbMapDl = config_malloc_prb_map();
}
}
+#if 0
for (i = 0; i < XRAN_DIR_MAX; i++) {
for (j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
for (k = 0; k < XRAN_MAX_SECTOR_NR; k++) {
}
}
}
+#endif
return 0;
}
+int32_t
+config_init2(RuntimeConfig *p_o_xu_cfg)
+{
+ int32_t i, j, k, z;
+ for (i = 0; i < XRAN_DIR_MAX; i++) {
+ for (j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
+ for (k = 0; k < p_o_xu_cfg->numCC; k++) {
+ for (z = 0; z < p_o_xu_cfg->numAxc; z++) {
+ p_o_xu_cfg->p_RunSlotPrbMap[i][j][k][z] = config_malloc_prb_map();
+ p_o_xu_cfg->p_RunSrsSlotPrbMap[i][j][k][z] = config_malloc_prb_map();
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
int
-parseConfigFile(char *filename, RuntimeConfig *config)
+parseConfigFile(const char *filename, RuntimeConfig *config)
{
char inputLine[MAX_LINE_SIZE] = {0};
int inputLen = 0;
}
}
- if (inputLine[strlen(inputLine)-1] == '\n')
- inputLine[strlen(inputLine)-1] == '\0';
lineNum++;
inputLen = strlen(inputLine);
}
int32_t
-parseSlotConfigFile(char *dir, RuntimeConfig *config)
+parseSlotConfigFile(const char *dir, RuntimeConfig *config)
{
int32_t ret = 0;
char filename[512];
size_t len;
int32_t slot_idx = 0;
- int32_t cc_idx = 0;
- int32_t ant_idx = 0;
int32_t direction = 0;
struct slot_cfg_to_pars slot_cfg_param;
}
}
- if (inputLine[strlen(inputLine)-1] == '\n')
- inputLine[strlen(inputLine)-1] == '\0';
lineNum++;
inputLen = strlen(inputLine);
return 0;
}
-int parseUsecaseFile(char *filename, UsecaseConfig *usecase_cfg)
+int parseUsecaseFile(const char *filename, UsecaseConfig *usecase_cfg)
{
char inputLine[MAX_LINE_SIZE] = {0};
int inputLen = 0;
}
}
- if (inputLine[strlen(inputLine)-1] == '\n')
- inputLine[strlen(inputLine)-1] == '\0';
lineNum++;
inputLen = strlen(inputLine);
Set by SIB2, prach-FreqOffset in E-UTRA. */
uint8_t prachConfigIndex;/**< TS36.211 - Table 5.7.1-2 : PRACH Configuration Index */
+ uint8_t prachConfigIndexLTE;/**< PRACH Configuration Index for LTE in dss case*/
uint8_t iqswap; /**< do swap of IQ before send to ETH */
uint8_t nebyteorderswap; /**< do swap of byte order from host byte order to network byte order. ETH */
uint8_t compression; /**< enable use case with compression */
uint16_t totalBfWeights; /**< The total number of beamforming weights on RU */
uint8_t enableSrs; /**< enable SRS (valid for Cat B only) */
- uint16_t srsSymMask; /**< SRS symbol mask [014] within S/U slot [0-13] def is 13 */
+ uint16_t srsSymMask; /* deprecated */
+ uint16_t srsSlot; /**< SRS slot within TDD period (special slot), for O-RU emulation */
+ uint8_t srsNdmOffset; /**< tti offset to delay the transmission of NDM SRS UP, for O-RU emulation */
+ uint16_t srsNdmTxDuration; /**< symbol duration for NDM SRS UP transmisson, for O-RU emulation */
uint8_t puschMaskEnable; /**< enable PUSCH mask, which means not tranfer PUSCH in some UL slot */
uint8_t puschMaskSlot; /**< PUSCH channel will not tranfer in slot module Frame */
+ uint8_t extType;
uint16_t maxFrameId; /**< max value of frame id */
struct xran_prb_map* p_PrbMapUl;
struct xran_prb_map* p_PrbMapSrs;
+ uint8_t dssEnable; /**< enable DSS (extension-9) */
+ uint8_t dssPeriod; /**< DSS pattern period for LTE/NR */
+ uint8_t technology[XRAN_MAX_DSS_PERIODICITY]; /**< technology array represents slot is LTE(0)/NR(1) */
+
uint16_t SlotPrbCCmask[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTIONS_PER_SLOT];
uint64_t SlotPrbAntCMask[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTIONS_PER_SLOT];
struct xran_prb_map* p_SlotPrbMap[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN];
uint16_t max_sections_per_slot;
uint16_t max_sections_per_symbol;
+ int32_t RunSlotPrbMapBySymbolEnable;
} RuntimeConfig;
/** use case configuration */
char o_xu_cfg_file [XRAN_PORTS_NUM][512]; /**< file with config for each O-XU */
char o_xu_pcie_bus_addr[XRAN_PORTS_NUM][XRAN_VF_MAX][512]; /**< VFs used for each O-RU|O-DU */
- char prefix_name[256];
+ char o_xu_bbu_cfg_file[512]; /**< file with config for each O-XU */
+
+ char prefix_name[256];
+ uint8_t dlCpProcBurst; /**< When set to 1, dl cp processing will be done on single symbol. When set to 0, DL CP processing
+ will be spread across all allowed symbols and multiple cores to reduce burstiness */
+ int32_t bbu_offload; /**< enable packet handling on BBU cores */
+ int32_t mlogxrandisable; /**< set to 1 to disable mlog 0 - default mlog enabled */
} UsecaseConfig;
/**
*
* @param filename The name of the configuration file to be parsed.
* @param config The configuration structure to be filled with parsed data. */
-int parseConfigFile(char *filename, RuntimeConfig *config);
+int parseConfigFile(const char *filename, RuntimeConfig *config);
/**
* Parse application use case file.
*
* @param filename The name of the use case file to be parsed.
* @param config The configuration structure to be filled with parsed data. */
-int parseUsecaseFile(char *filename, UsecaseConfig *config);
+int parseUsecaseFile(const char *filename, UsecaseConfig *config);
/**
* Parse slot config file.
*
* @param dir folder name.
* @param config The configuration structure to be filled with parsed data. */
-int32_t parseSlotConfigFile(char *dir, RuntimeConfig *config);
+int32_t parseSlotConfigFile(const char *dir, RuntimeConfig *config);
int32_t config_init(RuntimeConfig *p_o_xu_cfg);
+int32_t config_init2(RuntimeConfig *p_o_xu_cfg);
struct xran_prb_map* config_malloc_prb_map(void);
#endif /* _SAMPLEAPP__CONFIG_H_ */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file consists of parameters that are to be read from ebbu_pool_cfg.xml
+ * to configure the application at system initialization
+ * @file ebbu_pool_cfg.h
+ * @ingroup xran
+ * @author Intel Corporation
+ **/
+
+
+#include "ebbu_pool_cfg.h"
+
+#include <sys/param.h>
+#include <stdio.h>
+#include <string.h>
+
+static eBbuPoolCfgVarsStruct geBbuPoolCfgVars;
+char eBbuPoolCfgFileName[512];
+
+uint32_t nD2USwitch[EBBU_POOL_MAX_FRAME_FORMAT][EBBU_POOL_TDD_PERIOD] =
+{
+ {0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3}, //FDD
+ {0x1, 0x1, 0x1, 0x3, 0x2, 0x1, 0x1, 0x1, 0x3, 0x2}, //DDDSU
+ {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2} //DDDDDDDSUU
+};
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_test_ebbu_pool
+ *
+ * @param void
+ *
+ * @return eBBUPool Config Local Context Structure Pointer
+ *
+ * @description
+ * Returns the eBBUPool Config Local Context Structure Pointer
+ *
+**/
+//-------------------------------------------------------------------------------------------
+peBbuPoolCfgVarsStruct ebbu_pool_cfg_get_ctx(void)
+{
+ return &geBbuPoolCfgVars;
+}
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_test_ebbu_pool
+ *
+ * @param void
+ *
+ * @return void
+ *
+ * @description
+ * Initialize the geBbuPoolCfgVars. This is called at application bootup
+ *
+**/
+//-------------------------------------------------------------------------------------------
+void ebbu_pool_cfg_init_vars(void)
+{
+ memset(&geBbuPoolCfgVars, 0, sizeof(eBbuPoolCfgVarsStruct));
+}
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_test_ebbu_pool
+ *
+ * @param[in] *pCfgFile Pointer to FILE descriptor to read from
+ *
+ * @return 0 if SUCCESS
+ *
+ * @description
+ * This function parses the XML file that was opened and reads all the tags and associated
+ * values and stores them
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t ebbu_pool_cfg_parse_xml(FILE *pCfgFile)
+{
+ // peBbuPoolCfgVarsStruct geBbuPoolCfgVars = ebbu_pool_cfg_get_ctx();
+ uint32_t lineNum = 0, retCode;
+ char string[1024];
+
+ while(!feof(pCfgFile))
+ {
+ fgets(string, 1024, pCfgFile);
+ lineNum++;
+ retCode = cline_parse_line(string);
+
+ if (retCode != EBBU_POOL_CFG_ERRORCODE__SUCCESS)
+ {
+ printf("Something wrong in file %s ErrorCode[%d] at line[%d]: %s\n", eBbuPoolCfgFileName, (int) retCode, (int)lineNum, string);
+ return EBBU_POOL_CFG_ERRORCODE__FAIL;
+ }
+ }
+
+ return EBBU_POOL_CFG_ERRORCODE__SUCCESS;
+}
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_test_ebbu_pool
+ *
+ * @param void
+ *
+ * @return 0 if SUCCESS
+ *
+ * @description
+ * This function searches for tags from xml and applies the values to the eBBUPool test
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t ebbu_pool_cfg_apply(void)
+{
+ printf("ebbu_pool_cfg_apply\n");
+ peBbuPoolCfgVarsStruct geBbuPoolCfgVars = ebbu_pool_cfg_get_ctx();
+ int rc = EBBU_POOL_CFG_ERRORCODE__SUCCESS;
+ int32_t coreNum, cellNum, iCell;
+ uint32_t cellFrameCfg[EBBU_POOL_MAX_TEST_CELL], cellTtiCfg[EBBU_POOL_MAX_TEST_CELL], cellEventCfg[EBBU_POOL_MAX_TEST_CELL];
+
+ cline_print_info();
+
+ //----------------------------------------------------
+ // eBbuPool general config
+ //----------------------------------------------------
+ rc |= cline_set_int((const char *) "eBbuPoolMainThreadCore", (int *) &geBbuPoolCfgVars->mainThreadCoreId, 0);
+ rc |= cline_set_int((const char *) "eBbuPoolConsumerSleep", (int *) &geBbuPoolCfgVars->sleepFlag, 1);
+
+ //----------------------------------------------------
+ // Queue config
+ //----------------------------------------------------
+ rc |= cline_set_int((const char *) "QueueDepth", (int *) &geBbuPoolCfgVars->queueDepth, 1024);
+ rc |= cline_set_int((const char *) "QueueNum", (int *) &geBbuPoolCfgVars->queueNum, 3);
+ rc |= cline_set_int((const char *) "QueuCtxNum", (int *) &geBbuPoolCfgVars->ququeCtxNum, 1);
+
+ //----------------------------------------------------
+ // Test Config
+ //----------------------------------------------------
+ rc |= cline_set_int((const char *) "TimerThreadCore", (int *) &geBbuPoolCfgVars->timerCoreId, 0);
+ rc |= cline_set_int((const char *) "CtrlThreadNum", (int *) &geBbuPoolCfgVars->ctrlThreadNum, 0);
+ rc |= cline_set_int_array((const char *) "CtrlThreadCoreList", EBBU_POOL_MAX_CTRL_THREAD,(int *) &geBbuPoolCfgVars->ctrlThreadCoreId[0], &coreNum);
+ rc |= cline_set_int((const char *) "TestCellNum", (int *) &geBbuPoolCfgVars->testCellNum, 0);
+ rc |= cline_set_int((const char *) "TestCoreNum", (int *) &geBbuPoolCfgVars->testCoreNum, 0);
+ rc |= cline_set_int_array((const char *) "TestCoreList", EBBU_POOL_MAX_TEST_CORE, (int *) &geBbuPoolCfgVars->testCoreList[0], &coreNum);
+ rc |= cline_set_int_array((const char *) "TestCellFrameFormat", EBBU_POOL_MAX_TEST_CELL, (int *) &cellFrameCfg[0], &cellNum);
+ rc |= cline_set_int_array((const char *) "TestCellTti", EBBU_POOL_MAX_TEST_CELL, (int *) &cellTtiCfg[0], &cellNum);
+ rc |= cline_set_int_array((const char *) "TestCellEventNum", EBBU_POOL_MAX_TEST_CELL, (int *) &cellEventCfg[0], &cellNum);
+ rc |= cline_set_int((const char *) "MlogEnable", (int *) &geBbuPoolCfgVars->mlogEnable, 0);
+
+ if(cellNum > geBbuPoolCfgVars->testCellNum)
+ cellNum = geBbuPoolCfgVars->testCellNum;
+
+ for(iCell = 0; iCell < cellNum; iCell ++)
+ {
+ geBbuPoolCfgVars->sTestCell[iCell].frameFormat = cellFrameCfg[iCell];
+ geBbuPoolCfgVars->sTestCell[iCell].tti = cellTtiCfg[iCell];
+ geBbuPoolCfgVars->sTestCell[iCell].eventPerTti = cellEventCfg[iCell];
+ }
+
+
+ printf("eBbuPool config completely read: %x\n", rc);
+
+ printf("\n");
+
+ return rc;
+}
+
+
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_test_ebbu_pool
+ *
+ * @param void
+ *
+ * @return 0 if SUCCESS
+ *
+ * @description
+ * This function is called from main() and initializes the EBBU_POOL_CFG layer. It reads the xml
+ * file and configures the application based on xml tags and values from file.
+ *
+**/
+//-------------------------------------------------------------------------------------------
+uint32_t ebbu_pool_cfg_init_from_xml(void)
+{
+ // peBbuPoolCfgVarsStruct geBbuPoolCfgVars = ebbu_pool_cfg_get_ctx();
+ FILE *pCfgFile;
+ pCfgFile = fopen(eBbuPoolCfgFileName, "r");
+
+ ebbu_pool_cfg_init_vars();
+
+ cline_init();
+
+ if (pCfgFile == NULL)
+ {
+ printf("ERROR: %s file is not found in directory\n", eBbuPoolCfgFileName);
+ printf(" Please contact Intel to get the correct config file\n");
+ return EBBU_POOL_CFG_ERRORCODE__FAIL;
+ }
+
+ if (ebbu_pool_cfg_parse_xml(pCfgFile) != EBBU_POOL_CFG_ERRORCODE__SUCCESS)
+ {
+ printf("Could not Parse the XML File.\n");
+ fclose(pCfgFile);
+ return EBBU_POOL_CFG_ERRORCODE__FAIL;
+ }
+ printf("PhyCfg XML file parsed\n");
+
+ if (ebbu_pool_cfg_apply() != EBBU_POOL_CFG_ERRORCODE__SUCCESS)
+ {
+ printf("Could not Apply the settings from XML File.\n");
+ fclose(pCfgFile);
+ return EBBU_POOL_CFG_ERRORCODE__FAIL;
+ }
+
+ fclose(pCfgFile);
+ return EBBU_POOL_CFG_ERRORCODE__SUCCESS;
+}
+
+
+//-------------------------------------------------------------------------------------------
+/** @ingroup group_test_ebbu_pool
+ *
+ * @param[in] argc Number of command line arguments
+ * @param[in] *argv[] Array of command line arguments
+ *
+ * @return void
+ *
+ * @description
+ * This function parses the command line parameters entered while running the eBbuPool test application
+ * and searches for string "cfgfile" and takes the immediate next field and uses it as the
+ * xml file name. If it is not found, it uses default file name "bbdev_cfg.xml" and tries to open
+ * this.
+ *
+**/
+//-------------------------------------------------------------------------------------------
+void ebbu_pool_cfg_set_cfg_filename(int argc, char *argv[], char filename[512])
+{
+ // peBbuPoolCfgVarsStruct geBbuPoolCfgVars = ebbu_pool_cfg_get_ctx();
+#if 0
+ uint32_t ret;
+ ret = cline_get_string(argc, argv, "cfgfile", eBbuPoolCfgFileName);
+
+ if (ret != AUX_SUCCESS)
+ {
+ printf("ebbu_pool_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: %s\n", EBBU_POOL_FILE_NAME);
+ strcpy(eBbuPoolCfgFileName, EBBU_POOL_FILE_NAME);
+ }
+ strcpy(filename, eBbuPoolCfgFileName);
+#else
+ strncpy(eBbuPoolCfgFileName, filename, MIN(strnlen(filename, 511),511) );
+ eBbuPoolCfgFileName[511] = '\0';
+ printf("eBbuPoolCfgFileName %s\n", eBbuPoolCfgFileName);
+#endif
+ return;
+}
+
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file consists of parameters that are to be read from ebbu_pool_cfg.xml
+ * to configure the application at system initialization
+ * @file ebbu_pool_cfg.h
+ * @ingroup xran
+ * @author Intel Corporation
+**/
+
+#ifndef _EBBUPOOLCFG_H_
+#define _EBBUPOOLCFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ebbu_pool_api.h"
+#include "aux_cline.h"
+
+#define EBBU_POOL_FILE_NAME "config_file/ebbu_pool_cfg_basic.xml"
+
+#define EBBU_POOL_CFG_ERRORCODE__SUCCESS ( 0 )
+#define EBBU_POOL_CFG_ERRORCODE__FAIL ( 1 )
+#define EBBU_POOL_CFG_ERRORCODE__VER_MISMATCH ( 2 )
+
+#define EBBU_POOL_MAX_TEST_CELL 40
+#define EBBU_POOL_MAX_TEST_CORE 256
+#define EBBU_POOL_MAX_CTRL_THREAD 8
+
+
+#define EBBU_POOL_MAX_FRAME_FORMAT 3
+#define EBBU_POOL_TDD_PERIOD 10
+#define EBBU_POOL_TEST_DL 1
+#define EBBU_POOL_TEST_UL 2
+
+extern uint32_t nD2USwitch[EBBU_POOL_MAX_FRAME_FORMAT][EBBU_POOL_TDD_PERIOD];
+
+typedef struct
+{
+ uint32_t frameFormat; //FDD or TDD:DDDSU, DDDDDDDSUU
+ uint32_t tti; //micro-second
+ uint32_t eventPerTti;
+}eBbuPoolTestCellStruc;
+
+typedef struct
+{
+ //eBbuPool general config
+ uint32_t mainThreadCoreId;
+ uint32_t sleepFlag;
+
+ //Queus config
+ uint32_t queueDepth;
+ uint32_t queueNum;
+ uint32_t ququeCtxNum;
+
+ //Test config
+ uint32_t timerCoreId;
+ uint32_t ctrlThreadNum;
+ uint32_t ctrlThreadCoreId[EBBU_POOL_MAX_CTRL_THREAD];
+ uint32_t testCellNum;
+ eBbuPoolTestCellStruc sTestCell[EBBU_POOL_MAX_TEST_CELL];
+ uint32_t testCoreNum;
+ uint32_t testCoreList[EBBU_POOL_MAX_TEST_CORE];
+
+ //Misc
+ uint32_t mlogEnable;
+} eBbuPoolCfgVarsStruct, *peBbuPoolCfgVarsStruct;
+
+peBbuPoolCfgVarsStruct ebbu_pool_cfg_get_ctx(void);
+uint32_t ebbu_pool_cfg_init_from_xml(void);
+void ebbu_pool_cfg_set_cfg_filename(int argc, char *argv[], char filename[512]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _EBBUPOOLCFG_H_ */
+
#include "xran_mlog_task_id.h"
#include "app_io_fh_xran.h"
#include "app_profile_xran.h"
+#ifdef FWK_ENABLED
+#include "app_bbu_pool.h"
+#endif
#include "xran_ecpri_owd_measurements.h"
#define MAX_BBU_POOL_CORE_MASK (4)
static enum app_state state;
static uint64_t ticks_per_usec;
-static volatile uint64_t timer_last_irq_tick = 0;
-static uint64_t tsc_resolution_hz = 0;
UsecaseConfig* p_usecaseConfiguration = {NULL};
-RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM] = {NULL,NULL,NULL,NULL};
+RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM] = {NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL};
struct app_sym_cb_ctx cb_sym_ctx[XRAN_CB_SYM_MAX];
-long old_rx_counter[XRAN_PORTS_NUM] = {0,0,0,0};
-long old_tx_counter[XRAN_PORTS_NUM] = {0,0,0,0};
+long old_rx_counter[XRAN_PORTS_NUM] = {0,0,0,0,0,0,0,0};
+long old_tx_counter[XRAN_PORTS_NUM] = {0,0,0,0,0,0,0,0};
static void
app_print_menu()
char sysversion[100];
char *compilation_date = __DATE__;
char *compilation_time = __TIME__;
-
- uint32_t nLen;
+ char compiler[100];
snprintf(sysversion, 99, "Version: %s", VERSIONX);
- nLen = strlen(sysversion);
+
+#if defined(__clang__)
+ snprintf(compiler, 99, "family clang: %s", __clang_version__);
+#elif defined(__ICC) || defined(__INTEL_COMPILER)
+ snprintf(compiler, 99, "family icc: version %d", __INTEL_COMPILER);
+#elif defined(__INTEL_LLVM_COMPILER)
+ snprintf(compiler, 99, "family icx: version %d", __INTEL_LLVM_COMPILER);
+#elif defined(__GNUC__) || defined(__GNUG__)
+ snprintf(compiler, 99, "family gcc: version %d.%d.%d", __GNUC__, __GNUC_MINOR__,__GNUC_PATCHLEVEL__);
+#endif
printf("\n\n");
printf("===========================================================================================================\n");
printf("%s\n", sysversion);
printf("build-date: %s\n", compilation_date);
printf("build-time: %s\n", compilation_time);
+ printf("build-with: %s\n", compiler);
}
static void
static int32_t
app_parse_cmdline_args(int argc, char ** argv, struct sample_app_params* params)
{
- int32_t ret = 0;
int32_t c = 0;
int32_t vf_cnt = 0;
- int32_t *pInt;
int32_t cnt = 0;
size_t optlen = 0;
char *saveptr = NULL;
char *token = NULL;
- int32_t port = 4;
+ int32_t port = 8;
static struct option long_options[] = {
{"cfgfile", required_argument, 0, 'z'},
{"vf_addr_o_xu_b", required_argument, 0, 'b'},
{"vf_addr_o_xu_c", required_argument, 0, 'c'},
{"vf_addr_o_xu_d", required_argument, 0, 'd'},
+ {"vf_addr_o_xu_e", required_argument, 0, 'e'},
+ {"vf_addr_o_xu_f", required_argument, 0, 'F'},
+ {"vf_addr_o_xu_g", required_argument, 0, 'g'},
+ {"vf_addr_o_xu_h", required_argument, 0, 'H'},
{"help", no_argument, 0, 'h'},
{0, 0, 0, 0}
};
//int this_option_optind = optind ? optind : 1;
int option_index = 0;
- c = getopt_long(argc, argv, "a:b:c:d:f:h:p:u:v", long_options, &option_index);
+ c = getopt_long(argc, argv, "a:b:c:d:e:f:F:g:h:H:p:u:v", long_options, &option_index);
if (c == -1)
break;
cnt += 1;
- pInt = NULL;
- port = 4;
+ port = 8;
switch (c) {
case 'f':
port -= 1;
case 'd':
port -= 1;
+ case 'e':
+ port -= 1;
+ case 'F':
+ port -= 1;
+ case 'g':
+ port -= 1;
+ case 'H':
+ port -= 1;
vf_cnt = 0;
optlen = strlen(optarg) + 1;
printf("%s:%d: port %d %s [len %ld]\n",__FUNCTION__, __LINE__, port, optarg, optlen);
int32_t vf_num = 0;
int32_t o_xu_id = 0;
char filename[512];
+ char bbu_filename[512];
char *dir;
size_t len;
exit(-1);
}
- if (p_o_xu_cfg) {
- int32_t i;
- RuntimeConfig* p_o_xu_cfg_loc = p_o_xu_cfg;
- for (i = 0; i < XRAN_PORTS_NUM; i++) {
- config_init(p_o_xu_cfg_loc);
- p_o_xu_cfg_loc++;
- }
- } else {
- printf("p_o_xu_cfg error.\n");
- exit(-1);
- }
+ p_use_cfg->dlCpProcBurst = 1;
if (p_args) {
if (p_args->usecase_file) { /* use case for multiple O-RUs */
printf("app_parse_all_cfgs: Name of p_args->usecase_file, %s is too long. Maximum is 511 characters!!\n", p_args->usecase_file);
return -1;
} else {
- strncpy(filename, p_args->usecase_file, len);
+ strncpy(filename, p_args->usecase_file, RTE_MIN (512,len));
}
if (parseUsecaseFile(filename, p_use_cfg) != 0) {
printf("Use case config file error.\n");
return -1;
}
+ if (p_o_xu_cfg) {
+ int32_t i;
+ RuntimeConfig* p_o_xu_cfg_loc = p_o_xu_cfg;
+ for (i = 0; i < p_use_cfg->oXuNum; i++) {
+ config_init(p_o_xu_cfg_loc);
+ p_o_xu_cfg_loc++;
+ }
+ } else {
+ printf("p_o_xu_cfg error.\n");
+ exit(-1);
+ }
/* use cmdline pcie address */
for (o_xu_id = 0; o_xu_id < p_use_cfg->oXuNum && o_xu_id < XRAN_PORTS_NUM; o_xu_id++) {
for (vf_num = 0; vf_num < XRAN_VF_MAX && p_args->num_vfs ; vf_num++) {
- strncpy(&p_use_cfg->o_xu_pcie_bus_addr[o_xu_id][vf_num][0], &p_args->vf_pcie_addr[o_xu_id][vf_num][0], strlen(&p_args->vf_pcie_addr[o_xu_id][vf_num][0]));
+ strncpy(&p_use_cfg->o_xu_pcie_bus_addr[o_xu_id][vf_num][0], &p_args->vf_pcie_addr[o_xu_id][vf_num][0], RTE_MIN (512,strlen(&p_args->vf_pcie_addr[o_xu_id][vf_num][0])));
}
}
+
+
dir = dirname(p_args->usecase_file);
+ if(strlen(p_use_cfg->o_xu_bbu_cfg_file)){
+ memset(bbu_filename, 0, sizeof(bbu_filename));
+ printf("dir (%s)\n",dir);
+ len = strlen(dir) + 1;
+ if (len > 511){
+ printf("app_parse_all_cfgs: Name of directory, %s, xu_id = %d is too long. Maximum is 511 characters!!\n", dir, o_xu_id);
+ return -1;
+ } else {
+ strncpy(bbu_filename, dir, RTE_MIN(512,len));
+ }
+ strncat(bbu_filename, "/", 1);
+ len +=1;
+ len = (sizeof(bbu_filename)) - len;
+ if (len > strlen(p_use_cfg->o_xu_bbu_cfg_file)) {
+ strncat(bbu_filename, p_use_cfg->o_xu_bbu_cfg_file, RTE_MIN (len, strlen(p_use_cfg->o_xu_bbu_cfg_file)));
+ } else {
+ printf("File name error\n");
+ return -1;
+ }
+ strncpy(p_use_cfg->o_xu_bbu_cfg_file, bbu_filename, RTE_MIN (512, strlen(bbu_filename)));
+ printf("bbu_cfg_file (%s)\n",p_use_cfg->o_xu_bbu_cfg_file);
+#ifdef FWK_ENABLED
+ p_use_cfg->bbu_offload = 1;
+#else
+ p_use_cfg->bbu_offload = 0;
+#endif
+ } else {
+ printf("bbu_cfg_file is not provided\n");
+ p_use_cfg->bbu_offload = 0;
+ }
+
for (o_xu_id = 0; o_xu_id < p_use_cfg->oXuNum && o_xu_id < XRAN_PORTS_NUM; o_xu_id++) {
memset(filename, 0, sizeof(filename));
printf("dir (%s)\n",dir);
printf("app_parse_all_cfgs: Name of directory, %s, xu_id = %d is too long. Maximum is 511 characters!!\n", dir, o_xu_id);
return -1;
} else {
- strncpy(filename, dir, len);
+ strncpy(filename, dir, RTE_MIN (512,len));
}
strncat(filename, "/", 1);
len +=1;
return -1;
}
p_o_xu_cfg->o_xu_id = o_xu_id;
+ config_init2(p_o_xu_cfg);
if (p_o_xu_cfg->SlotNum_fileEnabled) {
if (parseSlotConfigFile(dir, p_o_xu_cfg) != 0) {
printf("parseSlotConfigFiles\n");
return -1;
}
}
+
p_o_xu_cfg++;
}
} else {
p_iq = p_o_xu_cfg->p_buff;
printf("IQ files size is %d slots\n", p_o_xu_cfg->numSlots);
+ //printf("numSlots=%u\n", p_o_xu_cfg->numSlots);
+ //getchar();
p_iq->iq_playback_buffer_size_dl = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number,
p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA) *4L);
p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA) *4L);
- /* 10 * [14*32*273*2*2] = 4892160 bytes */
+ /* 10 * [273*32*2*2] = 349440 bytes */
p_iq->iq_bfw_buffer_size_dl = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * p_o_xu_cfg->antElmTRx *
app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number,
p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA) *4L);
- /* 10 * [14*32*273*2*2] = 4892160 bytes */
- p_iq->iq_bfw_buffer_size_ul = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT *
+ /* 10 * [273*32*2*2] = 349440 bytes */
+ p_iq->iq_bfw_buffer_size_ul = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * p_o_xu_cfg->antElmTRx *
app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number,
p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA) *4L);
app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number,
p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA)*4L);
+ p_iq->numSlots = p_o_xu_cfg->numSlots;
+
for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) {
p_iq->p_tx_play_buffer[i] = (int16_t*)malloc(p_iq->iq_playback_buffer_size_dl);
p_iq->tx_play_buffer_size[i] = (int32_t)p_iq->iq_playback_buffer_size_dl;
if (p_iq->p_tx_play_buffer[i] == NULL)
exit(-1);
+
p_iq->tx_play_buffer_size[i] = sys_load_file_to_buff(p_o_xu_cfg->ant_file[i],
"DL IFFT IN IQ Samples in binary format",
(uint8_t*)p_iq->p_tx_play_buffer[i],
p_iq->tx_play_buffer_size[i],
1);
- p_iq->tx_play_buffer_position[i] = 0;
}
if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) {
(uint8_t*) p_iq->p_tx_dl_bfw_buffer[i],
p_iq->tx_dl_bfw_buffer_size[i],
1);
- p_iq->tx_dl_bfw_buffer_position[i] = 0;
}
}
(uint8_t*) p_iq->p_tx_ul_bfw_buffer[i],
p_iq->tx_ul_bfw_buffer_size[i],
1);
- p_iq->tx_ul_bfw_buffer_position[i] = 0;
}
}
if (p_iq->p_rx_log_buffer[i] == NULL)
exit(-1);
- p_iq->rx_log_buffer_position[i] = 0;
-
memset(p_iq->p_rx_log_buffer[i], 0, p_iq->rx_log_buffer_size[i]);
}
exit(-1);
memset(p_iq->p_prach_log_buffer[i], 0, p_iq->prach_log_buffer_size[i]);
- p_iq->prach_log_buffer_position[i] = 0;
}
/* log of SRS */
exit(-1);
memset(p_iq->p_srs_log_buffer[i], 0, p_iq->iq_srs_buffer_size_ul);
- p_iq->srs_log_buffer_position[i] = 0;
+ }
+ }
+
+ /* log of BFWs */
+ if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) {
+ for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) {
+
+ p_iq->p_tx_dl_bfw_log_buffer[i] = (int16_t*)malloc(p_iq->iq_bfw_buffer_size_dl);
+ p_iq->tx_dl_bfw_log_buffer_size[i] = (int32_t)p_iq->iq_bfw_buffer_size_dl;
+
+ if (p_iq->p_tx_dl_bfw_log_buffer[i] == NULL)
+ exit(-1);
+
+ memset(p_iq->p_tx_dl_bfw_log_buffer[i], 0, p_iq->iq_bfw_buffer_size_dl);
+ }
+ }
+
+ if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) {
+ for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) {
+
+ p_iq->p_tx_ul_bfw_log_buffer[i] = (int16_t*)malloc(p_iq->iq_bfw_buffer_size_ul);
+ p_iq->tx_ul_bfw_log_buffer_size[i] = (int32_t)p_iq->iq_bfw_buffer_size_ul;
+
+ if (p_iq->p_tx_ul_bfw_log_buffer[i] == NULL)
+ exit(-1);
+
+ memset(p_iq->p_tx_ul_bfw_log_buffer[i], 0, p_iq->iq_bfw_buffer_size_ul);
}
}
(uint8_t*) p_iq->p_rx_log_buffer[i],
p_iq->rx_log_buffer_size[i]/sizeof(short),
sizeof(short));
+
+ if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) {
+ snprintf(filename, sizeof(filename),"./logs/%s%d-dl_bfw_log_ue%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i);
+ sys_save_buf_to_file_txt(filename,
+ "DL Beamformig weights IQ Samples in human readable format",
+ (uint8_t*) p_iq->p_tx_dl_bfw_log_buffer[i],
+ p_iq->tx_dl_bfw_log_buffer_size[i],
+ 1);
+
+ snprintf(filename, sizeof(filename),"./logs/%s%d-dl_bfw_log_ue%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"),p_o_xu_cfg->o_xu_id, i);
+ sys_save_buf_to_file(filename,
+ "DL Beamformig weightsIQ Samples in binary format",
+ (uint8_t*) p_iq->p_tx_dl_bfw_log_buffer[i],
+ p_iq->tx_dl_bfw_log_buffer_size[i]/sizeof(short),
+ sizeof(short));
+
+ }
+ if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) {
+ snprintf(filename, sizeof(filename),"./logs/%s%d-ul_bfw_log_ue%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i);
+ sys_save_buf_to_file_txt(filename,
+ "DL Beamformig weights IQ Samples in human readable format",
+ (uint8_t*) p_iq->p_tx_ul_bfw_log_buffer[i],
+ p_iq->tx_ul_bfw_log_buffer_size[i],
+ 1);
+
+ snprintf(filename, sizeof(filename),"./logs/%s%d-ul_bfw_log_ue%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"),p_o_xu_cfg->o_xu_id, i);
+ sys_save_buf_to_file(filename,
+ "DL Beamformig weightsIQ Samples in binary format",
+ (uint8_t*) p_iq->p_tx_ul_bfw_log_buffer[i],
+ p_iq->tx_ul_bfw_log_buffer_size[i]/sizeof(short),
+ sizeof(short));
+ }
+
}
if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) {
else
return -1;
- if (result = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset))
+ if ((result = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset)))
{
printf("pthread_setaffinity_np failed: coreId = 2, result = %d\n",result);
}
int main(int argc, char *argv[])
{
- int i;
- int j, len;
int32_t o_xu_id = 0;
- int lcore_id = 0;
char filename[256];
int32_t xret = 0;
struct stat st = {0};
uint32_t filenameLength = strlen(argv[1]);
enum xran_if_state xran_curr_if_state = XRAN_INIT;
struct sample_app_params arg_params;
-
+ uint64_t nActiveCoreMask[MAX_BBU_POOL_CORE_MASK] = {0};
uint64_t nTotalTime;
uint64_t nUsedTime;
uint32_t nCoresUsed;
uint32_t nCoreUsedNum[64];
- float nUsedPercent;
+ //float nUsedPercent;
app_version_print();
app_timer_set_tsc_freq_from_clock();
printf("app_parse_all_cfgs failed %d\n", xret);
exit(-1);
}
+#ifdef FWK_ENABLED
+ if(p_usecaseConfiguration->bbu_offload) {
+ if(p_startupConfiguration[0]->appMode == APP_O_DU) {
+ if ((xret = app_bbu_init(argc, argv, p_usecaseConfiguration->o_xu_bbu_cfg_file, p_usecaseConfiguration, p_startupConfiguration,
+ nActiveCoreMask)) < 0) {
+ printf("app_bbu_init failed %d\n", xret);
+ }
+ uint32_t i;
+ uint64_t nMask = 1;
+ /* use only 1 worker for BBU offload */
+ for (i = 0; i < 64; i++)
+ {
+ if(p_usecaseConfiguration->io_core < 64) {
+ if (nMask & p_usecaseConfiguration->io_worker) {
+ p_usecaseConfiguration->io_worker = nMask;
+ p_usecaseConfiguration->io_worker_64_127 = 0;
+ break;
+ }
+ }
+ if(p_usecaseConfiguration->io_core >= 64) {
+ if (nMask & p_usecaseConfiguration->io_worker_64_127) {
+ p_usecaseConfiguration->io_worker_64_127 = nMask;
+ p_usecaseConfiguration->io_worker = 0;
+ break;
+ }
+ }
+ nMask = nMask << 1;
+ }
+ }
+ }
+#endif
if ((xret = app_set_main_core(p_usecaseConfiguration)) < 0) {
printf("app_set_main_core failed %d\n", xret);
exit(-1);
/* one init for all O-XU */
app_io_xran_fh_init_init(p_usecaseConfiguration, p_startupConfiguration[0], &app_io_xran_fh_init);
-
xret = xran_init(argc, argv, &app_io_xran_fh_init, argv[0], &app_io_xran_handle);
if (xret != XRAN_STATUS_SUCCESS) {
printf("xran_init failed %d\n", xret);
mkdir("./logs", 0777);
}
+ snprintf(filename, sizeof(filename),"mlog-%s", p_usecaseConfiguration->appMode == 0 ? "o-du" : "o-ru");
+
+ /* Init mlog */
+ unsigned int mlogSubframes = 128;
+ unsigned int mlogCores = 32;
+ unsigned int mlogSize = 10000;
+
+ // Open Mlog Buffers and initalize variables
+ MLogOpen(mlogSubframes, mlogCores, mlogSize, 0, filename);
+ MLogSetMask(0);
+
+ puts("----------------------------------------");
+ printf("MLog Info: virt=0x%p size=%d\n", MLogGetFileLocation(), MLogGetFileSize());
+ puts("----------------------------------------");
+
+
+ uint32_t totalCC = 0;
+
+ if(((1 << app_io_xran_fh_init.io_cfg.timing_core) | app_io_xran_fh_init.io_cfg.pkt_proc_core) & nActiveCoreMask[0])
+ rte_panic("[0 - 63] BBU and IO cores conflict\n");
+ if(app_io_xran_fh_init.io_cfg.pkt_proc_core_64_127 & nActiveCoreMask[1])
+ rte_panic("[64-127] BBU and IO cores conflict\n");
+
+ nActiveCoreMask[0] |= ((1 << app_io_xran_fh_init.io_cfg.timing_core) | app_io_xran_fh_init.io_cfg.pkt_proc_core);
+ nActiveCoreMask[1] |= app_io_xran_fh_init.io_cfg.pkt_proc_core_64_127;
+
+ MLogSetup(nActiveCoreMask[0], nActiveCoreMask[1], nActiveCoreMask[2], nActiveCoreMask[3]);
+
+ for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) {
+ RuntimeConfig* p_o_xu_cfg = p_startupConfiguration[o_xu_id];
+ totalCC += p_o_xu_cfg->numCC;
+ }
+ MLogAddTestCase(nActiveCoreMask, totalCC);
+
/** process all the O-RU|O-DU for use case */
for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) {
RuntimeConfig* p_o_xu_cfg = p_startupConfiguration[o_xu_id];
printf("xran_open failed %d\n", xret);
exit(-1);
}
-
- if (app_io_xran_interface(o_xu_id, p_startupConfiguration[o_xu_id], p_usecaseConfiguration) != 0)
+ if (app_io_xran_interface(o_xu_id, p_startupConfiguration[o_xu_id], p_usecaseConfiguration, &app_io_xran_fh_init) != 0)
exit(-1);
app_io_xran_iq_content_init(o_xu_id, p_startupConfiguration[o_xu_id]);
-
+#ifdef FWK_ENABLED
+ if(p_o_xu_cfg->appMode == APP_O_DU && p_usecaseConfiguration->bbu_offload) {
+ if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_bbu_dl_tti_call_back, NULL, 10, XRAN_CB_TTI)) != XRAN_STATUS_SUCCESS) {
+ printf("xran_reg_physide_cb failed %d\n", xret);
+ exit(-1);
+ }
+ } else {
+ if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_io_xran_dl_tti_call_back, NULL, 10, XRAN_CB_TTI)) != XRAN_STATUS_SUCCESS) {
+ printf("xran_reg_physide_cb failed %d\n", xret);
+ exit(-1);
+ }
+ }
+#else
if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_io_xran_dl_tti_call_back, NULL, 10, XRAN_CB_TTI)) != XRAN_STATUS_SUCCESS) {
printf("xran_reg_physide_cb failed %d\n", xret);
exit(-1);
}
+#endif
if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_io_xran_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX)) != XRAN_STATUS_SUCCESS) {
printf("xran_reg_physide_cb failed %d\n", xret);
exit(-1);
#endif
}
- snprintf(filename, sizeof(filename),"mlog-%s", p_usecaseConfiguration->appMode == 0 ? "o-du" : "o-ru");
-
- /* MLogOpen(0, 32, 0, 0xFFFFFFFF, filename);*/
- MLogOpen(128, 7, 20000, 0, filename);
- MLogSetMask(0);
-
- puts("----------------------------------------");
- printf("MLog Info: virt=0x%016lx size=%d\n", MLogGetFileLocation(), MLogGetFileSize());
- puts("----------------------------------------");
-
- uint64_t nActiveCoreMask[MAX_BBU_POOL_CORE_MASK] = {0};
- uint32_t totalCC = 0;
- nActiveCoreMask[0] = ((1 << app_io_xran_fh_init.io_cfg.timing_core) | app_io_xran_fh_init.io_cfg.pkt_proc_core);
- nActiveCoreMask[1] = app_io_xran_fh_init.io_cfg.pkt_proc_core_64_127;
-
- for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) {
- RuntimeConfig* p_o_xu_cfg = p_startupConfiguration[o_xu_id];
- totalCC += p_o_xu_cfg->numCC;
- }
- MLogAddTestCase(nActiveCoreMask, totalCC);
fcntl(0, F_SETFL, fcntl(0, F_GETFL) | O_NONBLOCK);
for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) {
if (o_xu_id == 0) {
xran_get_time_stats(&nTotalTime, &nUsedTime, &nCoresUsed, nCoreUsedNum, 1);
- nUsedPercent = 0.0;
- if (nTotalTime) {
- nUsedPercent = ((float)nUsedTime * 100.0) / (float)nTotalTime;
- }
+ //nUsedPercent = 0.0;
+ //if (nTotalTime) {
+ // nUsedPercent = ((float)nUsedTime * 100.0) / (float)nTotalTime;
+ //}
mlog_times.core_total_time += nTotalTime;
mlog_times.core_used_time += nUsedTime;
printf("\n");
#endif
}
- printf("[%s%d][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld]\n",
+ printf("[%s%d][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Invalid_Ext1_packets %ld Total %ld]\n",
((p_usecaseConfiguration->appMode == APP_O_DU) ? "o-du" : "o-ru"),
o_xu_id,
x_counters[o_xu_id].rx_counter,
x_counters[o_xu_id].Rx_late,
x_counters[o_xu_id].Rx_corrupt,
x_counters[o_xu_id].Rx_pkt_dupl,
+ x_counters[o_xu_id].rx_invalid_ext1_packets,
x_counters[o_xu_id].Total_msgs_rcvd);
if (x_counters[o_xu_id].rx_counter > old_rx_counter[o_xu_id])
}
}
-
+ MLogSetMask(0x0);
puts("Closing l1 app... Ending all threads...");
xran_close(app_io_xran_handle);
- if(is_mlog_on) {
- app_profile_xran_print_mlog_stats(arg_params.usecase_file);
- rte_pause();
+#ifdef FWK_ENABLED
+ if(p_startupConfiguration[0]->appMode == APP_O_DU && p_usecaseConfiguration->bbu_offload) {
+ app_bbu_close();
}
+#endif
app_io_xran_if_stop();
puts("Dump IQs...");
app_dump_o_xu_buffers(p_usecaseConfiguration, p_startupConfiguration[o_xu_id]);
}
+ if(is_mlog_on) {
+ app_profile_xran_print_mlog_stats(arg_params.usecase_file);
+ rte_pause();
+ }
+
app_io_xran_if_free();
return 0;
}
#define PID_GNB_PROC_TIMING 70
#define PID_GNB_PROC_TIMING_TIMEOUT 71
-#define PID_GNB_SYM_CB 72
#define PID_GNB_PRACH_CB 73
+#define PID_GNB_SYM_CB 72
#define PID_GNB_SRS_CB 74
+#define PID_GNB_BFW_CB 75
+//#define NR5G_SUBTASK_PROFILING_ON
+//#define WLS_SUBTASK_ON
+
+//--------------------------------------------------------------------
+// MAC2PHY API PROC
+//--------------------------------------------------------------------
+#define PID_MAC2PHY_API_HANDLER 1
+#define PID_MAC2PHY_API_HANDLER_NULL 2
+#define PID_MAC2PHY_API_CHECK_LATE_API 3
+#define PID_MAC2PHY_API_RECV 4
+#define PID_MAC2PHY_API_RECV_NULL 5
+#define PID_MAC2PHY_API_CLEANUP 6
+#define PID_MAC2PHY_API_ERROR_CHECK 7
+#define PID_MAC2PHY_API_PARSE 8
+#define PID_MAC2PHY_TX_SDU_PROC 9
+#define PID_MAC2PHY_TX_VECTOR_PROC_DATA 10
+#define PID_MAC2PHY_TX_SDU_ZBC 11
+#define PID_MAC2PHY_RX_VECTOR_PROC 12
+#define PID_MAC2PHY_API_PROC 13
+
+//--------------------------------------------------------------------
+// PHY2MAC API PROC
+//--------------------------------------------------------------------
+#define PID_PHY2MAC_API_PROC_PUSCH 20
+#define PID_PHY2MAC_API_PROC_PUCCH 21
+#define PID_PHY2MAC_API_PROC_UPDATE 22
+#define PID_PHY2MAC_API_PROC_SEND 23
+#define PID_PHY2MAC_URLLC_API_PROC_SEND 24
+
+//--------------------------------------------------------------------
+// PHYSTATS
+//--------------------------------------------------------------------
+#define PID_PHYSTATS 30
+
+//--------------------------------------------------------------------
+// PHYDI
+//--------------------------------------------------------------------
+#define PID_PHYDI_IQ_COPY_DL 35
+#define PID_PHYDI_IQ_COPY_UL 36
+#define PID_PHYDI_IQ_COPY_DL_FRB 37
+#define PID_PHYDI_IQ_COPY_UL_FRB 38
+#define PID_PHYDI_IQ_COPY_PRACH_UL 39
+#define PID_PHYDI_IQ_COPY_SRS_UL 40
+
+//--------------------------------------------------------------------
+// DISPATCH eBbuPool TASKS
+//--------------------------------------------------------------------
+#define PID_GNB_TTI_START_GEN_EXECUTE 43
+#define PID_GNB_SYM2_WAKEUP_GEN_EXECUTE 44
+#define PID_GNB_SYM6_WAKEUP_GEN_EXECUTE 45
+#define PID_GNB_SYM11_WAKEUP_GEN_EXECUTE 46
+#define PID_GNB_SYM13_WAKEUP_GEN_EXECUTE 47
+#define PID_GNB_PRACH_WAKEUP_GEN_EXECUTE 48
+#define PID_GNB_SRS_WAKEUP_GEN_EXECUTE 49
+
+//--------------------------------------------------------------------
+// POLLING
+//--------------------------------------------------------------------
+#define PID_AUX_BBDEV_DL_POLL 50
+#define PID_AUX_BBDEV_DL_POLL_DISPATCH 51
+#define PID_AUX_BBDEV_UL_POLL 52
+#define PID_AUX_BBDEV_UL_POLL_DISPATCH 53
+
+//--------------------------------------------------------------------
+// WLS
+//--------------------------------------------------------------------
+#define PID_AUX_WLS_RX_PROCESS 55
+#define PID_AUX_WLS_SEND_API 56
+#define PID_AUX_WLS_ADD_TO_QUEUE 57
+#define PID_AUX_WLS_REMOVE_FROM_QUEUE 58
+#define PID_AUX_WLS_URLLC_RX_PROCESS 59
+
+//--------------------------------------------------------------------
+// BBU-POOL-TASKS
+//--------------------------------------------------------------------
+#define PID_BBUPOOL_TTI_COMPLETE 60
+#define PID_BBUPOOL_TTI_COMPLETE_PRINT 61
+#define PID_BBUPOOL_TTI_TO_TTI_DURATION 62
+
+#define PID_BBUPOOL_ACTIVATE_CELL 63
+#define PID_BBUPOOL_DE_ACTIVATE_CELL 64
+#define PID_BBUPOOL_CREATE_EMPTY_LIST 65
+#define PID_BBUPOOL_RX_HANDLER 66
+
+//--------------------------------------------------------------------
+// Timing Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_PROC_TIMING 70
+#define PID_GNB_PROC_TIMING_TIMEOUT 71
+#define PID_GNB_TTI_START 72
+#define PID_GNB_SYM2_WAKEUP 73
+#define PID_GNB_SYM6_WAKEUP 74
+#define PID_GNB_SYM11_WAKEUP 75
+#define PID_GNB_SYM13_WAKEUP 76
+#define PID_GNB_PRACH_WAKEUP 77
+#define PID_GNB_SRS_WAKEUP 78
+
+//--------------------------------------------------------------------
+// URLLC Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_URLLC_DL_TASK 80
+#define PID_GNB_URLLC_DL_TOTAL_TASK 81
+#define PID_GNB_URLLC_UL_TASK 82
+#define PID_GNB_URLLC_UL_TOTAL_TASK 83
+#define PID_GNB_URLLC_TASK 84
+#define PID_GNB_URLLC_DL_CALL_BACK 85
+#define PID_GNB_URLLC_UL_CALL_BACK 86
+#define PID_GNB_URLLC_API_CALL_BACK 87
+
+//--------------------------------------------------------------------
+// Latency Tasks (Need 4 values (one per Numerology))
+//--------------------------------------------------------------------
+#define PID_GNB_DL_LINK_PRINT 88
+#define PID_GNB_UL_LINK_PRINT 92
+#define PID_GNB_SRS_LINK_PRINT 96
+
+//--------------------------------------------------------------------
+// GNB UL BBU Tasks (there is gap of 24 for 24 cell support)
+//--------------------------------------------------------------------
+#define PCID_GNB_FH_RX_DATA_CC0 100
+#define PCID_GNB_FH_RX_SRS_CC0 124
+#define PCID_GNB_PUSCH_CE_SYMB0_CC0 148
+#define PCID_GNB_PUSCH_MMSE_SYMB0_CC0 172
+#define PCID_GNB_PUSCH_MMSE_SYMB7_CC0 196
+#define PCID_GNB_PUSCH_REDEMAP_SYMB0_CC0 220
+#define PCID_GNB_PUSCH_REDEMAP_SYMB7_CC0 244
+#define PCID_GNB_PUSCH_LAYDEMAP_SYMB0_CC0 268
+#define PCID_GNB_PUSCH_LAYDEMAP_SYMB7_CC0 292
+#define PCID_GNB_PUSCH_PN_SYMB0_CC0 316
+#define PCID_GNB_PUSCH_PN_SYMB7_CC0 340
+#define PCID_GNB_PUSCH_DEMOD_SYMB0_CC0 364
+#define PCID_GNB_PUSCH_DEMOD_SYMB7_CC0 388
+#define PCID_GNB_PUSCH_DESCRAMBLE_CC0 412
+#define PCID_GNB_PUSCH_DECODER_CC0 436
+#define PCID_GNB_PUSCH_TB_CC0 460
+#define PCID_GNB_UL_CFG_CC0 484
+#define PCID_GNB_PUSCH_DECODER_CB_CC0 508
+#define PCID_GNB_PUSCH_RX_SYMB0_CC0 532
+#define PCID_GNB_PUSCH_RX_SYMB7_CC0 556
+#define PCID_GNB_PRACH_PROCESS_CC0 580
+#define PCID_GNB_PUCCH_RX_CC0 604
+#define PCID_GNB_SRS_RX_CC0 628
+#define PCID_GNB_PUSCH_UCI_DECODER_CC0 652
+#define PCID_GNB_UL_POST_CC0 676
+#define PCID_GNB_UL_IQ_LOG_CC0 700
+#define PCID_GNB_FH_RX_PRACH_CC0 724
+#define PCID_GNB_PUSCH_RX_LINK_CC0 748
+#define PCID_GNB_UL_LINK_CC0 772
+#define PCID_GNB_PUSCH_CE_SYMB7_CC0 796
+#define PCID_GNB_SRS_RX_LINK_CC0 820
+
+
+#define PID_GNB_TASKLIST_NOT_COMPLETED 899
+//--------------------------------------------------------------------
+// GNB DL BBU Tasks (there is gap of 24 for 24 cell support)
+//--------------------------------------------------------------------
+#define PCID_GNB_DL_CFG_CC0 900
+#define PCID_GNB_PDSCH_TB_CC0 924
+#define PCID_GNB_PDSCH_SCRAMBLER_CC0 948
+#define PCID_GNB_PDSCH_MOD_CC0 972
+#define PCID_GNB_PDSCH_PRECODE_CC0 996
+#define PCID_GNB_PDSCH_RS_CC0 1020
+#define PCID_GNB_PDSCH_REMAP_CC0 1044
+#define PCID_GNB_DL_RESET_BUF_CC0 1068
+#define PCID_GNB_DL_SYMBOL_PROC_CC0 1092
+#define PCID_GNB_DL_CSI_PROC_CC0 1116
+#define PCID_GNB_DL_DCI_PROC_CC0 1140
+#define PCID_GNB_DL_UCI_PROC_CC0 1164
+#define PCID_GNB_DL_PBCH_PROC_CC0 1188
+#define PCID_GNB_DL_POST_CC0 1212
+#define PCID_GNB_PDSCH_TB_QUEUE_CC0 1236
+#define PCID_GNB_DL_LINK_CC0 1260
+#define PCID_GNB_DL_DCI_PRECODER_CC0 1284
+#define PCID_GNB_PDSCH_TB_CRC_CC0 1308
+#define PCID_GNB_PDSCH_CB_SETUP_CC0 1332
+
+//--------------------------------------------------------------------
+// Other DL / UL tasks (there is gap of 24 for 24 cell support)
+//--------------------------------------------------------------------
+#define PCID_GNB_PUSCH_TB_CRC_CC0 1500
+#define PCID_GNB_PUSCH_CB_SETUP_CC0 1524
+#define PCID_GNB_DL_BEAM_WEIGHT_TASK_CC0 1548
+#define PCID_GNB_UL_BEAM_WEIGHT_TASK_CC0 1572
+#define PCID_GNB_SRS_CE_CC0 1596
+#define PCID_GNB_SRS_REPORT_CC0 1620
+#define PCID_GNB_DL_BEAM_WEIGHT_COMPRESS_CC0 1644
+#define PCID_GNB_UL_BEAM_WEIGHT_COMPRESS_CC0 1668
+#define PCID_GNB_DL_IQ_COMPRESS_CC0 1692
+#define PCID_GNB_UL_IQ_DECOMPRESS_CC0 1712
+#define PCID_GNB_UL_IQ_FROM_XRAN_CC0 1736
+#define PCID_GNB_UL_IQ_SP_SLOT_FROM_XRAN_CC0 1760
+#define PCID_GNB_UL_SRS_IQ_DECOMPRESS_CC0 1784
+#define PCID_GNB_DL_OFDM_CTRL_COMPRESS_CC0 1808
+#define PCID_GNB_DL_OFDM_RS_COMPRESS_CC0 1832
+#define PCID_GNB_DL_OFDM_DATA_COMPRESS_CC0 1856
+
+//--------------------------------------------------------------------
+// GNB UL Sub Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_PUCCH_F0_SEQ_GEN 2000
+#define PID_GNB_PUCCH_F0_DETECT 2001
+#define PID_GNB_PUCCH_F1_SEQ_GEN1 2002
+#define PID_GNB_PUCCH_F1_SEQ_GEN2 2003
+#define PID_GNB_PUCCH_F1_DESPRD 2004
+#define PID_GNB_PUCCH_F1_DEMOD 2005
+#define PID_GNB_PUCCH_F2_DMRS_GEN 2006
+#define PID_GNB_PUCCH_F2_CE 2007
+#define PID_GNB_PUCCH_F2_EQU 2008
+#define PID_GNB_PUCCH_F2_DEMOD 2009
+#define PID_GNB_PUCCH_F2_DESCR 2010
+#define PID_GNB_PUCCH_F2_DEC 2011
+#define PID_GNB_PUCCH_F3_F4_DMRS_GEN 2012
+#define PID_GNB_PUCCH_F3_F4_CE 2013
+#define PID_GNB_PUCCH_F3_F4_EQU 2014
+#define PID_GNB_PUCCH_F3_F4_IDFT 2015
+#define PID_GNB_PUCCH_F3_F4_DESPRD 2016
+#define PID_GNB_PUCCH_F3_F4_DEMOD 2017
+#define PID_GNB_PUCCH_F3_F4_DESCR 2018
+#define PID_GNB_PUCCH_F3_F4_DEC 2019
+
+//--------------------------------------------------------------------
+// GNB UL BBU Creation Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_PUSCH_DMRS0_GEN_BYPASS 2700
+#define PID_GNB_PUSCH_DMRS0_GEN_EXECUTE 2701
+#define PID_GNB_PUSCH_DMRS1_GEN_BYPASS 2702
+#define PID_GNB_PUSCH_DMRS1_GEN_EXECUTE 2703
+#define PID_GNB_PRACH_GEN_BYPASS 2704
+#define PID_GNB_PRACH_GEN_EXECUTE 2705
+#define PID_GNB_PUCCH_GEN_BYPASS 2706
+#define PID_GNB_PUCCH_GEN_EXECUTE 2707
+#define PID_GNB_SRS_GEN_BYPASS 2708
+#define PID_GNB_SRS_GEN_EXECUTE 2709
+#define PID_GNB_UL_CFG_GEN_BYPASS 2710
+#define PID_GNB_UL_CFG_GEN_EXECUTE 2711
+#define PID_GNB_PUSCH_TB_TASK_GEN_BYPASS 2712
+#define PID_GNB_PUSCH_TB_TASK_GEN_EXECUTE 2713
+#define PID_GNB_PUSCH_DECODE_TASK_GEN_BYPASS 2714
+#define PID_GNB_PUSCH_DECODE_TASK_GEN_EXECUTE 2715
+#define PID_GNB_PUSCH_DATA0_GEN_BYPASS 2716
+#define PID_GNB_PUSCH_DATA0_GEN_EXECUTE 2717
+#define PID_GNB_PUSCH_DATA1_GEN_BYPASS 2718
+#define PID_GNB_PUSCH_DATA1_GEN_EXECUTE 2719
+
+//--------------------------------------------------------------------
+// GNB DL BBU Creation Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_DL_SCRAMBLER_GEN_BYPASS 2720
+#define PID_GNB_DL_SCRAMBLER_GEN_EXECUTE 2721
+#define PID_GNB_DL_CONFIG_GEN_BYPASS 2722
+#define PID_GNB_DL_CONFIG_GEN_EXECUTE 2723
+#define PID_GNB_DL_BEAM_GEN_BYPASS 2724
+#define PID_GNB_DL_BEAM_GEN_EXECUTE 2725
+
+//--------------------------------------------------------------------
+// GNB Pre Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_DL_PDSCH_SYMBOL_PRE_TASK 2730
+#define PID_GNB_UL_PUSCH_CE0_PRE_TASK 2731
+#define PID_GNB_UL_PUSCH_CE7_PRE_TASK 2732
+#define PID_GNB_UL_PUSCH_MMSE0_PRE_TASK 2733
+#define PID_GNB_UL_PUSCH_MMSE7_PRE_TASK 2734
+#define PID_GNB_UL_PUCCH_PRE_TASK 2735
+#define PID_GNB_UL_SRS_PRE_TASK 2736
+#define PID_GNB_UL_PUSCH_LLR_RX_PRE_TASK 2737
+#define PID_GNB_DL_BEAM_WEIGHT_PRE_TASK 2738
+#define PID_GNB_UL_BEAM_WEIGHT_PRE_TASK 2739
+#define PID_GNB_UL_PUSCH_DECODE_PRE_TASK 2740
+
+//--------------------------------------------------------------------
+// GNB Post Tasks
+//--------------------------------------------------------------------
+#define PID_GNB_UL_PUCCH_POST_TASK 2745
+
+//--------------------------------------------------------------------
+// Other tasks
+//--------------------------------------------------------------------
+#define PID_GNB_DL_IFFT0 2750
+#define PID_GNB_DL_IFFT1 2751
+#define PID_GNB_DL_IFFT2 2752
+#define PID_GNB_DL_IFFT3 2753
+#define PID_GNB_DL_IFFT4 2754
+#define PID_GNB_DL_IFFT5 2755
+#define PID_GNB_DL_IFFT6 2756
+#define PID_GNB_DL_IFFT7 2757
+#define PID_GNB_UL_FFT0 2758
+#define PID_GNB_UL_FFT1 2759
+#define PID_GNB_UL_FFT2 2760
+#define PID_GNB_UL_FFT3 2761
+#define PID_GNB_UL_FFT4 2762
+#define PID_GNB_UL_FFT5 2763
+#define PID_GNB_UL_FFT6 2764
+#define PID_GNB_UL_FFT7 2765
+
+#define PID_DLIFFT 2766
+#define PID_DLIFFT_ADD_CP 2767
+#define PID_ULFFT 2768
+
+//--------------------------------------------------------------------
+// AUX RADIO
+//--------------------------------------------------------------------
+#define PID_AUX_RADIO_RX_BYPASS_PROC 2900
+#define PID_AUX_RADIO_RX_STOP 2901
+#define PID_AUX_RADIO_RX_UL_IQ 2902
+#define PID_AUX_RADIO_PRACH_PKT 2903
+#define PID_AUX_RADIO_FE_COMPRESS 2904
+#define PID_AUX_RADIO_FE_DECOMPRESS 2905
+#define PID_AUX_RADIO_TX_BYPASS_PROC 2906
+#define PID_AUX_RADIO_ETH_TX_BURST 2907
+#define PID_AUX_RADIO_TX_DL_IQ 2908
+#define PID_AUX_RADIO_RX_VALIDATE 2909
+#define PID_AUX_RADIO_RX_IRQ_ON 2910
+#define PID_AUX_RADIO_RX_IRQ_OFF 2911
+#define PID_AUX_RADIO_RX_EPOLL_WAIT 2912
+#define PID_AUX_RADIO_TX_LTEMODE_PROC 2913
+#define PID_AUX_RADIO_RX_LTEMODE_PROC 2914
+#define PID_AUX_RADIO_TX_PLAY_BACK_IQ 2915
+
+#define PCID_BBUPOOL_RADIO_DL_COMPRESSION_TASK_CC0 2940
+#define PCID_BBUPOOL_RADIO_DL_IQ_LOG_LTE_TASK_CC0 2960
+#define PCID_BBUPOOL_RADIO_UL_IQ_LOG_LTE_TASK_CC0 2980
+
+//--------------------------------------------------------------------
+// XRAN
+//--------------------------------------------------------------------
+#define PID_XRAN_TTI_TIMER 3100
+#define PID_XRAN_TTI_CB 3101
+#define PID_XRAN_SYM_TIMER 3102
+#define PID_XRAN_PROC_TIMING_TIMEOUT 3103
+#define PID_XRAN_TIME_SYSTIME_POLL 3104
+#define PID_XRAN_TIME_SYSTIME_STOP 3105
+#define PID_XRAN_TIME_ARM_TIMER 3106
+
+#define PID_XRAN_FREQ_RX_PKT 3107
+#define PID_XRAN_RX_STOP 3108
+#define PID_XRAN_RX_UL_IQ 3109
+#define PID_XRAN_PRACH_PKT 3110
+#define PID_XRAN_FE_COMPRESS 3111
+#define PID_XRAN_FE_DECOMPRESS 3112
+#define PID_XRAN_TX_BYPASS_PROC 3113
+#define PID_XRAN_ETH_TX_BURST 3114
+#define PID_XRAN_TX_DL_IQ 3115
+#define PID_XRAN_RX_VALIDATE 3116
+#define PID_XRAN_RX_IRQ_ON 3117
+#define PID_XRAN_RX_IRQ_OFF 3118
+#define PID_XRAN_RX_EPOLL_WAIT 3119
+#define PID_XRAN_TX_LTEMODE_PROC 3120
+#define PID_XRAN_RX_LTEMODE_PROC 3121
+#define PID_XRAN_TX_PLAY_BACK_IQ 3122
+#define PID_XRAN_PROCESS_TX_SYM 3123
+#define PID_XRAN_DISPATCH_TX_SYM 3124
+#define PID_XRAN_PREPARE_TX_PKT 3125
+#define PID_XRAN_ATTACH_EXT_BUF 3126
+#define PID_XRAN_ETH_ENQUEUE_BURST 3127
+
+#define PID_XRAN_CP_DL_CB 3128
+#define PID_XRAN_CP_UL_CB 3129
+#define PID_XRAN_UP_DL_CB 3130
+#define PID_XRAN_SYM_OTA_CB 3131
+#define PID_XRAN_TTI_CB_TO_PHY 3132
+#define PID_XRAN_HALF_SLOT_CB_TO_PHY 3133
+#define PID_XRAN_FULL_SLOT_CB_TO_PHY 3134
+#define PID_XRAN_UP_UL_HALF_DEAD_LINE_CB 3135
+#define PID_XRAN_UP_UL_FULL_DEAD_LINE_CB 3136
+#define PID_XRAN_UP_UL_USER_DEAD_LINE_CB 3137
+
+#define PID_XRAN_PROCESS_UP_PKT 3140
+#define PID_XRAN_PROCESS_UP_PKT_SRS 3141
+#define PID_XRAN_PROCESS_UP_PKT_PARSE 3142
+#define PID_XRAN_PROCESS_CP_PKT 3143
+#define PID_XRAN_PROCESS_DELAY_MEAS_PKT 3144
+#define PID_XRAN_TIME_ARM_TIMER_DEADLINE 3150
+#define PID_XRAN_TIME_ARM_USER_TIMER_DEADLINE 3151
#ifdef __cplusplus
}
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC46=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC11
antC47=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
## control of IQ byte order
antC46=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC11
antC47=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC46=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC11
antC47=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
## control of IQ byte order
antC46=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC11
antC47=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>8</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>8</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC46=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC11
antC47=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11
#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
## control of IQ byte order
#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11
#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
## control of IQ byte order
antC46=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC11
antC47=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin
#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11
#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin
#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11
#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin
ioWorker=0x2000000 # mask [0- no workers]
#dpdkMemorySize=10240
oXuNum=1 # numbers of O-RU connected to O-DU
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,106,0,14,0,1,0,16,1
+PrbElemDl1=50,56,0,14,0,1,0,16,1
+nPrbElemUl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,106,0,14,0,1,0,16,1
+PrbElemUl1=50,56,0,14,0,1,0,16,1
+###########################################################
+
+
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin
antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin
antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin
-
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,106,0,14,0,1,0,16,1
+PrbElemDl1=50,56,0,14,0,1,0,16,1
+nPrbElemUl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,106,0,14,0,1,0,16,1
+PrbElemUl1=50,56,0,14,0,1,0,16,1
+###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC15=./usecase/cat_a/mu0_5mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#prachConfigIndex=1 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/cat_a/mu0_5mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#prachConfigIndex=1 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=1
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
#
#******************************************************************************/
-
# This is simple configuration file. Use '#' sign for comments
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
appMode=0 # O-DU(0) | RU(1)
antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
-mu=3 #mmWave 120Khz Sub Carrier Spacing
-ttiPeriod=125 # in us TTI period (mmWave default 125us)
-nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=1024
-nULFftSize=1024
+nDLFftSize=4096
+nULFftSize=4096
nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-# not used
-#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
ioCore=5
# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=81
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=8
-max_sections_per_symbol=8
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,36,0,14,1,1,0,16,1
-PrbElemDl1=36,36,0,14,2,1,0,16,1
-PrbElemDl2=72,36,0,14,3,1,0,16,1
-PrbElemDl3=108,36,0,14,4,1,0,16,1
-PrbElemDl4=144,36,0,14,5,1,0,16,1
-PrbElemDl5=180,36,0,14,6,1,0,16,1
-PrbElemDl6=216,36,0,14,7,1,0,16,1
-PrbElemDl7=252,21,0,14,8,1,0,16,1
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,36,0,14,1,1,0,16,1
-PrbElemUl1=36,36,0,14,2,1,0,16,1
-PrbElemUl2=72,36,0,14,3,1,0,16,1
-PrbElemUl3=108,36,0,14,4,1,0,16,1
-PrbElemUl4=144,36,0,14,5,1,0,16,1
-PrbElemUl5=180,36,0,14,6,1,0,16,1
-PrbElemUl6=216,36,0,14,7,1,0,16,1
-PrbElemUl7=252,21,0,14,8,1,0,16,1
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
###########################################################
bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
-u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
##O-RU Settings
totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 #in us TODO: update per RU implementation
- #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=50 #in us
-T2a_max_cp_dl=140 #in us
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
#Reception Window C-plane UL
-T2a_min_cp_ul=50 #in us
-T2a_max_cp_ul=140 #in us
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
#Reception Window U-plane
-T2a_min_up=25 #in us
-T2a_max_up=70 #in us
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
#Transmission Window
-Ta3_min=20 #in us
-Ta3_max=32 #in us
+Ta3_min=50 # in us
+Ta3_max=171 # in us
###########################################################
##O-DU Settings
#C-plane
#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=70
-T1a_max_cp_dl=100
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=60
-T1a_max_cp_ul=70
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
#U-plane
##Transmission Window
-T1a_min_up=35
-T1a_max_up=50
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
#Reception Window
-Ta4_min=0
-Ta4_max=45
+Ta4_min=50 # in us
+Ta4_max=331 # in us
###########################################################
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
-
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
-# remote O-XU 1 Eth Link 0
+# #remote O-XU 1 Eth Link 0
oXuRem1Mac0=00:11:22:33:01:01
oXuRem1Mac1=00:11:22:33:01:11
# remote O-XU 1 Eth Link 1
oXuRem1Mac2=00:11:22:33:01:21
oXuRem1Mac3=00:11:22:33:01:31
-# remote O-XU 2 Eth Link 0
+#remote O-XU 2 Eth Link 0
oXuRem2Mac0=00:11:22:33:02:01
oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
+#remote O-XU 2 Eth Link 1
oXuRem2Mac2=00:11:22:33:02:21
oXuRem2Mac3=00:11:22:33:02:31
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=15 # core id
+ioWorker=0x800000000 # mask [0- no workers]
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem1Mac2=00:11:22:33:00:20
+oXuRem1Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>2</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>2</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_du_1.dat #O-RU1
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# #remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+#remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+#remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
ioWorker=0x800000000 # mask [0- no workers]
oXuNum=2 # numbers of O-RU connected to O-DU
-
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./mu3_config_file_o_ru.dat #O-RU0
-oXuCfgFile1=./mu1_config_file_o_ru.dat #O-RU1
+oXuCfgFile0=./config_file_o_ru_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_ru_1.dat #O-RU1
#O-XU 0
#PciBusAddoXu0Vf0=0000:51:11.0
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>3</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>3</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+dpdkMemorySize=8192 #18432
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_du_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_du_2.dat #O-RU2
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# #remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+#remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+#remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=15 # core id
+ioWorker=0x800000000 # mask [0- no workers]
+
+dpdkMemorySize=8192 #18432
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_ru_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_ru_2.dat #O-RU2
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>4</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>4</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+#antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+dpdkMemorySize=10240
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_du_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_du_2.dat #O-RU2
+oXuCfgFile3=./config_file_o_du_3.dat #O-RU3
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# #remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+#remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+#remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
+#remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:01
+oXuRem3Mac1=00:11:22:33:03:11
+#remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:21
+oXuRem3Mac3=00:11:22:33:03:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=20 #core for main()
+systemCore=21
+ioCore=22 # core id
+ioWorker=0x4000000000000000 # mask [0- no workers]
+
+dpdkMemorySize=10240
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_ru_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_ru_2.dat #O-RU2
+oXuCfgFile3=./config_file_o_ru_3.dat #O-RU3
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:00
+oXuRem3Mac1=00:11:22:33:03:10
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:20
+oXuRem3Mac3=00:11:22:33:03:30
\ No newline at end of file
antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
#
#******************************************************************************/
-
# This is simple configuration file. Use '#' sign for comments
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
appMode=0 # O-DU(0) | RU(1)
xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=1 #30Khz Sub Carrier Spacing
nULFftSize=4096
nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
ioCore=5
# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=8
-max_sections_per_symbol=8
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,273,0,14,0,0,0,16,0
-PrbElemDl1=36,36,0,14,2,1,0,16,1
-PrbElemDl2=72,36,0,14,3,1,0,16,1
-PrbElemDl3=108,36,0,14,4,1,0,16,1
-PrbElemDl4=144,36,0,14,5,1,0,16,1
-PrbElemDl5=180,36,0,14,6,1,0,16,1
-PrbElemDl6=216,36,0,14,7,1,0,16,1
-PrbElemDl7=252,21,0,14,8,1,0,16,1
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,136,0,14,0,0,0,16,0
-PrbElemUl1=136,137,0,14,0,0,0,16,0
-PrbElemUl2=72,36,0,14,3,1,0,16,1
-PrbElemUl3=108,36,0,14,4,1,0,16,1
-PrbElemUl4=144,36,0,14,5,1,0,16,1
-PrbElemUl5=180,36,0,14,6,1,0,16,1
-PrbElemUl6=216,36,0,14,7,1,0,16,1
-PrbElemUl7=252,21,0,14,8,1,0,16,1
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
###########################################################
##O-RU Settings
totalBFWeights=32 # Total number of Beamforming Weights on RU
-Tadv_cp_dl=25 # in us
+Tadv_cp_dl=125 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
+Ta3_min=50 # in us
+Ta3_max=171 # in us
###########################################################
##O-DU Settings
#C-plane
#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=392
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
##Transmission Window Fast C-plane UL
T1a_min_cp_ul=285
-T1a_max_cp_ul=300
+T1a_max_cp_ul=336
#U-plane
##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
+Ta4_min=50 # in us
+Ta4_max=331 # in us
###########################################################
#
#******************************************************************************/
-
# This is simple configuration file. Use '#' sign for comments
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
appMode=1 # O-DU(0) | O-RU(1)
xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=1 #30Khz Sub Carrier Spacing
nULFftSize=4096
nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
ioCore=10
# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
-antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
-antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
-antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
-antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
-antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
-antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
-antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=8
-max_sections_per_symbol=8
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,273,0,14,0,0,0,16,0
-PrbElemDl1=36,36,0,14,2,1,0,16,1
-PrbElemDl2=72,36,0,14,3,1,0,16,1
-PrbElemDl3=108,36,0,14,4,1,0,16,1
-PrbElemDl4=144,36,0,14,5,1,0,16,1
-PrbElemDl5=180,36,0,14,6,1,0,16,1
-PrbElemDl6=216,36,0,14,7,1,0,16,1
-PrbElemDl7=252,21,0,14,8,1,0,16,1
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,136,0,14,0,0,0,16,0
-PrbElemUl1=136,137,0,14,0,0,0,16,0
-PrbElemUl2=72,36,0,14,3,1,0,16,1
-PrbElemUl3=108,36,0,14,4,1,0,16,1
-PrbElemUl4=144,36,0,14,5,1,0,16,1
-PrbElemUl5=180,36,0,14,6,1,0,16,1
-PrbElemUl6=216,36,0,14,7,1,0,16,1
-PrbElemUl7=252,21,0,14,8,1,0,16,1
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
###########################################################
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-Tadv_cp_dl=25 # in us
+Tadv_cp_dl=125 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=392 # 428.12us
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
+Ta3_min=50 # in us
+Ta3_max=171 # in us
###########################################################
##O-DU Settings
#C-plane
#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=392
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
##Transmission Window Fast C-plane UL
T1a_min_cp_ul=285
-T1a_max_cp_ul=300
+T1a_max_cp_ul=336
#U-plane
##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
+Ta4_min=50 # in us
+Ta4_max=331 # in us
###########################################################
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=15 # core id
+ioWorker=0x800000000 # mask [0- no workers]
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>2</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>2</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=2 # numbers of O-RU connected to O-DU
-
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./mu3_config_file_o_du.dat #O-DU0
-oXuCfgFile1=./mu1_config_file_o_du.dat #O-DU1
+oXuCfgFile0=./config_file_o_du_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_du_1.dat #O-RU1
#O-XU 0
#PciBusAddoXu0Vf0=0000:51:01.0
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
-# remote O-XU 1 Eth Link 0
+# #remote O-XU 1 Eth Link 0
oXuRem1Mac0=00:11:22:33:01:01
oXuRem1Mac1=00:11:22:33:01:11
# remote O-XU 1 Eth Link 1
oXuRem1Mac2=00:11:22:33:01:21
oXuRem1Mac3=00:11:22:33:01:31
-# remote O-XU 2 Eth Link 0
+#remote O-XU 2 Eth Link 0
oXuRem2Mac0=00:11:22:33:02:01
oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
+#remote O-XU 2 Eth Link 1
oXuRem2Mac2=00:11:22:33:02:21
oXuRem2Mac3=00:11:22:33:02:31
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=15 # core id
+ioWorker=0x800000000 # mask [0- no workers]
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_ru_1.dat #O-RU1
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>3</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>3</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_du_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_du_2.dat #O-RU2
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# #remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+#remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+#remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=20 #core for main()
+systemCore=21
+ioCore=22 # core id
+
+ioWorker=0x4000000000000000 # mask [0- no workers]
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_ru_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_ru_2.dat #O-RU2
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>4</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>4</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2
+#antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2
+#antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2
+#antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2
+#antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3
+#antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3
+#antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
+#antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
+
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+#PrbElemDl2=72,36,0,14,3,1,0,16,1
+#PrbElemDl3=108,36,0,14,4,1,0,16,1
+#PrbElemDl4=144,36,0,14,5,1,0,16,1
+#PrbElemDl5=180,36,0,14,6,1,0,16,1
+#PrbElemDl6=216,36,0,14,7,1,0,16,1
+#PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+#PrbElemUl2=72,36,0,14,3,1,0,16,1
+#PrbElemUl3=108,36,0,14,4,1,0,16,1
+#PrbElemUl4=144,36,0,14,5,1,0,16,1
+#PrbElemUl5=180,36,0,14,6,1,0,16,1
+#PrbElemUl6=216,36,0,14,7,1,0,16,1
+#PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_du_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_du_2.dat #O-RU2
+oXuCfgFile3=./config_file_o_du_3.dat #O-RU3
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# #remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+#remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+#remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
+#remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:01
+oXuRem3Mac1=00:11:22:33:03:11
+#remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:21
+oXuRem3Mac3=00:11:22:33:03:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=20 #core for main()
+systemCore=21
+ioCore=22 # core id
+ioWorker=0x800000 # mask [0- no workers]
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru_0.dat #O-RU0
+oXuCfgFile1=./config_file_o_ru_1.dat #O-RU1
+oXuCfgFile2=./config_file_o_ru_2.dat #O-RU2
+oXuCfgFile3=./config_file_o_ru_3.dat #O-RU3
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:00
+oXuRem3Mac1=00:11:22:33:03:10
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:20
+oXuRem3Mac3=00:11:22:33:03:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachCompMethod=0
prachiqWidth=16
PrbElemDl7=252,21,0,14,8,1,0,16,1
-nPrbElemUl=2
+nPrbElemUl=1
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl0=0,273,0,14,0,0,0,16,0
PrbElemUl1=137,136,0,14,0,0,0,16,0
PrbElemUl2=72,36,0,14,3,1,0,16,1
PrbElemUl3=108,36,0,14,4,1,0,16,1
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
##Numerology
mu=1 #30Khz Sub Carrier Spacing
antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachCompMethod=0
prachiqWidth=16
PrbElemDl7=252,21,0,14,8,1,0,16,1
-nPrbElemUl=2
+nPrbElemUl=1
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl0=0,273,0,14,0,0,0,16,0
PrbElemUl1=137,136,0,14,0,0,0,16,0
PrbElemUl2=72,36,0,14,3,1,0,16,1
PrbElemUl3=108,36,0,14,4,1,0,16,1
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-
-##Numerology
-mu=3 #mmWave 120Khz Sub Carrier Spacing
-ttiPeriod=125 # in us TTI period (mmWave default 125us)
-nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=1024
-nULFftSize=1024
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
- #not used
-#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=10
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=81
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=8
-max_sections_per_symbol=8
-
-nPrbElemDl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,36,0,14,1,1,0,16,1
-PrbElemDl1=36,36,0,14,2,1,0,16,1
-PrbElemDl2=72,36,0,14,3,1,0,16,1
-PrbElemDl3=108,36,0,14,4,1,0,16,1
-PrbElemDl4=144,36,0,14,5,1,0,16,1
-PrbElemDl5=180,36,0,14,6,1,0,16,1
-PrbElemDl6=216,36,0,14,7,1,0,16,1
-PrbElemDl7=252,21,0,14,8,1,0,16,1
-
-
-nPrbElemUl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,36,0,14,1,1,0,16,1
-PrbElemUl1=36,36,0,14,2,1,0,16,1
-PrbElemUl2=72,36,0,14,3,1,0,16,1
-PrbElemUl3=108,36,0,14,4,1,0,16,1
-PrbElemUl4=144,36,0,14,5,1,0,16,1
-PrbElemUl5=180,36,0,14,6,1,0,16,1
-PrbElemUl6=216,36,0,14,7,1,0,16,1
-PrbElemUl7=252,21,0,14,8,1,0,16,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
-u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 #in us TODO: update per RU implementation
- #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-
-#Reception Window C-plane DL
-T2a_min_cp_dl=50 #in us
-T2a_max_cp_dl=140 #in us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=50 #in us
-T2a_max_cp_ul=140 #in us
-
-#Reception Window U-plane
-T2a_min_up=25 #in us
-T2a_max_up=70 #in us
-
-#Transmission Window
-Ta3_min=20 #in us
-Ta3_max=32 #in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=70
-T1a_max_cp_dl=100
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=60
-T1a_max_cp_ul=70
-
-#U-plane
-##Transmission Window
-T1a_min_up=35
-T1a_max_up=50
-
-#Reception Window
-Ta4_min=0
-Ta4_max=45
-###########################################################
-
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # lls-CU(0) | RU(1)
-xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-
-#######################################################################
-#Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,22,0,14,0,1,1,14,1
-PrbElemDl1=22,22,0,14,1,1,1,14,1
-PrbElemDl2=44,22,0,14,2,1,1,14,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,22,0,14,0,1,1,14,1
-PrbElemUl1=22,22,0,14,1,1,1,14,1
-PrbElemUl2=44,22,0,14,2,1,1,14,1
-#######################################################################
-
-##Numerology
-mu=3 #mmWave 120Khz Sub Carrier Spacing
-ttiPeriod=125 # in us TTI period (mmWave default 125us)
-nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=1024
-nULFftSize=1024
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-# not used
-#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-#3c:fd:fe:b9:f8:b5
-#
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=3c:fd:fe:b9:f8:b5
-#00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-maxFrameId=99 # set for compatibility with O-RU
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=81
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=0 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
-u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
-
-##RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 #in us TODO: update per RU implementation
- #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-
-#Reception Window C-plane DL
-T2a_min_cp_dl=50 #in us
-T2a_max_cp_dl=140 #in us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=50 #in us
-T2a_max_cp_ul=140 #in us
-
-#Reception Window U-plane
-T2a_min_up=25 #in us
-T2a_max_up=140 #in us
-
-#Transmission Window
-Ta3_min=20 #in us
-Ta3_max=32 #in us
-
-###########################################################
-##lls-CU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=70
-T1a_max_cp_dl=100
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=60
-T1a_max_cp_ul=70
-
-#U-plane
-##Transmission Window
-T1a_min_up=35
-T1a_max_up=50
-
-#Reception Window
-Ta4_min=0
-Ta4_max=45
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-
-#######################################################################
-#Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,22,0,14,0,1,1,14,1
-PrbElemDl1=22,22,0,14,1,1,1,14,1
-PrbElemDl2=44,22,0,14,2,1,1,14,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,22,0,14,0,1,1,14,1
-PrbElemUl1=22,22,0,14,1,1,1,14,1
-PrbElemUl2=44,22,0,14,2,1,1,14,1
-#######################################################################
-
-##Numerology
-mu=3 #mmWave 120Khz Sub Carrier Spacing
-ttiPeriod=125 # in us TTI period (mmWave default 125us)
-nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=1024
-nULFftSize=1024
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
- #not used
-#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=10
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-maxFrameId=99 # set for compatibility with O-RU
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=81
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
-u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
-
-##RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 #in us TODO: update per RU implementation
- #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-
-#Reception Window C-plane DL
-T2a_min_cp_dl=50 #in us
-T2a_max_cp_dl=140 #in us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=50 #in us
-T2a_max_cp_ul=140 #in us
-
-#Reception Window U-plane
-T2a_min_up=25 #in us
-T2a_max_up=70 #in us
-
-#Transmission Window
-Ta3_min=20 #in us
-Ta3_max=32 #in us
-
-###########################################################
-##lls-CU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=70
-T1a_max_cp_dl=100
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=60
-T1a_max_cp_ul=70
-
-#U-plane
-##Transmission Window
-T1a_min_up=35
-T1a_max_up=50
-
-#Reception Window
-Ta4_min=0
-Ta4_max=45
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # lls-CU(0) | RU(1)
-xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-
-#######################################################################
-#Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,66,0,14,0,1,1,9,1
-PrbElemDl1=22,22,0,14,1,1,1,9,1
-PrbElemDl2=44,22,0,14,2,1,1,9,1
-
-nPrbElemUl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,66,0,14,0,1,1,9,1
-PrbElemUl1=22,22,0,14,1,1,1,9,1
-PrbElemUl2=44,22,0,14,2,1,1,9,1
-#######################################################################
-
-##Numerology
-mu=3 #mmWave 120Khz Sub Carrier Spacing
-ttiPeriod=125 # in us TTI period (mmWave default 125us)
-nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=1024
-nULFftSize=1024
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
- #not used
-#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500
-#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-
-maxFrameId=99 # set for compatibility with O-RU
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=81
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
-u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
-
-##RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 #in us TODO: update per RU implementation
- #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-
-#Reception Window C-plane DL
-T2a_min_cp_dl=50 #in us
-T2a_max_cp_dl=140 #in us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=50 #in us
-T2a_max_cp_ul=140 #in us
-
-#Reception Window U-plane
-T2a_min_up=25 #in us
-T2a_max_up=140 #in us
-
-#Transmission Window
-Ta3_min=20 #in us
-Ta3_max=32 #in us
-
-###########################################################
-##lls-CU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=70
-T1a_max_cp_dl=100
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=60
-T1a_max_cp_ul=70
-
-#U-plane
-##Transmission Window
-T1a_min_up=35
-T1a_max_up=50
-
-#Reception Window
-Ta4_min=0
-Ta4_max=45
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-
-#######################################################################
-#Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,66,0,14,0,1,1,9,1
-PrbElemDl1=22,22,0,14,1,1,1,9,1
-PrbElemDl2=44,22,0,14,2,1,1,9,1
-
-nPrbElemUl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,66,0,14,0,1,1,9,1
-PrbElemUl1=22,22,0,14,1,1,1,9,1
-PrbElemUl2=44,22,0,14,2,1,1,9,1
-#######################################################################
-
-##Numerology
-mu=3 #mmWave 120Khz Sub Carrier Spacing
-ttiPeriod=125 # in us TTI period (mmWave default 125us)
-nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=1024
-nULFftSize=1024
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
- #not used
-#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500
-#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=10
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-maxFrameId=99 # set for compatibility with O-RU
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-#antPrachC0=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0
-#antPrachC1=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0
-#antPrachC2=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0
-#antPrachC3=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0
-
-antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2
-antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2
-antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2
-antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2
-antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3
-antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3
-antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
-antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=81
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
-u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
-
-##RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 #in us TODO: update per RU implementation
- #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-
-#Reception Window C-plane DL
-T2a_min_cp_dl=50 #in us
-T2a_max_cp_dl=140 #in us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=50 #in us
-T2a_max_cp_ul=140 #in us
-
-#Reception Window U-plane
-T2a_min_up=25 #in us
-T2a_max_up=70 #in us
-
-#Transmission Window
-Ta3_min=20 #in us
-Ta3_max=32 #in us
-
-###########################################################
-##lls-CU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=70
-T1a_max_cp_dl=100
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=60
-T1a_max_cp_ul=70
-
-#U-plane
-##Transmission Window
-T1a_min_up=35
-T1a_max_up=50
-
-#Reception Window
-Ta4_min=0
-Ta4_max=45
-###########################################################
-
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>125, 125, 125, 125</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3
antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3
-rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=81
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=12,3,0,0,9,1
ExtBfwUl6=12,3,0,0,9,1
ExtBfwUl7=7,3,0,0,9,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl6=216,36,0,14,7,1,1,9,1
PrbElemUl7=252,21,0,14,8,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
ExtBfwUl0=64,2,0,0,9,1
ExtBfwUl1=13,2,0,0,9,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,64,0,14,0,1,1,9,1
PrbElemUl1=64,26,0,14,1,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=64,2,0,0,9,1
ExtBfwUl1=13,2,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # enable (1)| disable (0) srs
+srsSym=4 # deprecated
+srsSlot=3 # scheduled srs slot within tdd period
+srsNdmOffset=3 # delay offset to start ndm srs u-plane
+srsNdmTxDuration=4 # tx duration for ndm srts u-plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,64,0,14,0,1,1,9,1
PrbElemUl1=64,26,0,14,1,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # enable (1)| disable (0) srs
+srsSym=4 # deprecated
+srsSlot=3 # scheduled srs slot within tdd period
+srsNdmOffset=3 # delay offset to start ndm srs u-plane
+srsNdmTxDuration=4 # tx duration for ndm srts u-plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#66% 180 33% 90
ExtBfwUl0=30,3,0,0,9,1
ExtBfwUl1=30,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # enable (1)| disable (0) srs
+srsSym=4 # deprecated
+srsSlot=3 # scheduled srs slot within tdd period
+srsNdmOffset=3 # delay offset to start ndm srs u-plane
+srsNdmTxDuration=4 # tx duration for ndm srts u-plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,64,0,14,0,1,1,9,1
PrbElemUl1=64,26,0,14,1,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # enable (1)| disable (0) srs srssym=4 # deprecated
+srsSlot=3 # scheduled srs slot within tdd period
+srsNdmOffset=3 # delay offset to start ndm srs u-plane
+srsNdmTxDuration=4 # tx duration for ndm srts u-plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl1=10,3,0,0,9,1
ExtBfwUl2=10,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # enable (1)| disable (0) srs
+srsSym=4 # deprecated
+srsSlot=3 # scheduled srs slot within tdd period
+srsNdmOffset=3 # delay offset to start ndm srs u-plane
+srsNdmTxDuration=4 # tx duration for ndm srts u-plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=30,30,0,14,1,1,1,9,1
PrbElemUl2=60,30,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl1=10,3,0,0,9,1
ExtBfwUl2=10,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=30,30,0,14,1,1,1,9,1
PrbElemUl2=60,30,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#66% 180 33% 90
ExtBfwUl1=10,3,0,0,9,1
ExtBfwUl2=10,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=30,30,0,14,1,1,1,9,1
PrbElemUl2=60,30,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl1=10,3,0,0,9,1
ExtBfwUl2=10,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=30,30,0,14,1,1,1,9,1
PrbElemUl2=60,30,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=10,3,0,0,9,1
ExtBfwUl2=10,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=30,30,0,14,1,1,1,9,1
PrbElemUl2=60,30,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=10,3,0,0,9,1
ExtBfwUl2=10,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=30,30,0,14,1,1,1,9,1
PrbElemUl2=60,30,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 MAX MAX 33% 33% 4.25 1.725 0% DU
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask 0-no workers
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/64qam_ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/64qam_ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/64qam_ant_0.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/64qam_ant_1.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
-# weight base beams
-PrbElemDl0=0,64,0,14,0,1,4,3,1,5064,4095
-PrbElemDl1=64,26,0,14,1,1,4,3,1,5064,4095
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=32,2,0,0,9,1
-ExtBfwDl1=13,2,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,26,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=64,2,0,0,9,1
-ExtBfwUl1=13,2,0,0,9,1
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 MAX MAX 33% 33% 4.25 1.725 0% DU
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15 # core id
-ioWorker=0x800000000 # mask 0-no workers
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
-# weight base beams
-PrbElemDl0=0,64,0,14,0,1,4,3,1,5064,4095
-PrbElemDl1=64,26,0,14,1,1,4,3,1,5064,4095
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,26,0,14,1,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 MAX 16QAM 0.5 33% 90 33% 90 4.25 1.15 0% DU
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/16qam_ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/16qam_ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/16qam_ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/16qam_ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
-# weight base beams
-PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095
-PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=32,2,0,0,9,1
-ExtBfwDl1=13,2,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,26,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=64,2,0,0,9,1
-ExtBfwUl1=13,2,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 MAX 16QAM 0.5 33% 90 33% 90 4.25 1.15 0% DU
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15 # core id
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
-# weight base beams
-PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095
-PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,26,0,14,1,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 64QAM 0.5 16QAM 0.5 66% 180 33% 90 3.425 1.15 DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/qpsk_ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/qpsk_ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/qpsk_ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/qpsk_ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
-# weight base beams
-PrbElemDl0=0,90,0,14,0,1,4,1,1,8192,4095
-PrbElemDl1=90,90,0,14,1,1,4,1,1,8192,4095
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=30,3,0,0,9,1
-ExtBfwDl1=30,3,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,26,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=30,3,0,0,9,1
-ExtBfwUl1=30,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 64QAM 0.5 16QAM 0.5 66% 180 33% 90 3.425 1.15 DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
-# weight base beams
-PrbElemDl0=0,90,0,14,0,1,4,1,1,8192,4095
-PrbElemDl1=90,90,0,14,1,1,4,1,1,8192,4095
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,26,0,14,1,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 16 8 MAX MAX 33% 90 33% 90 17 6.9 0% DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=10,3,0,0,9,1
-ExtBfwDl1=10,3,0,0,9,1
-ExtBfwDl2=10,3,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=10,3,0,0,9,1
-ExtBfwUl1=10,3,0,0,9,1
-ExtBfwUl2=10,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 8T8R 100 4 2 64QAM 0.5 16QAM 0.5 66% 180 33% 90 3.425 1.15 DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 16 8 MAX 16QAM 0.5 33% 90 33% 90 17 4.6 DU
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=10,3,0,0,9,1
-ExtBfwDl1=10,3,0,0,9,1
-ExtBfwDl2=10,3,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=10,3,0,0,9,1
-ExtBfwUl1=10,3,0,0,9,1
-ExtBfwUl2=10,3,0,0,9,1
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 16 8 MAX 16QAM 0.5 33% 90 33% 90 17 4.6 DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 16 8 64QAM 0.5 16QAM 0.5 66% 180 33% 90 13.7 4.6 0%
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-PrbElemDl3=90,30,0,14,3,1,1,9,1
-PrbElemDl4=120,30,0,14,4,1,1,9,1
-PrbElemDl5=150,30,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=10,3,0,0,9,1
-ExtBfwDl1=10,3,0,0,9,1
-ExtBfwDl2=10,3,0,0,9,1
-ExtBfwDl3=10,3,0,0,9,1
-ExtBfwDl4=10,3,0,0,9,1
-ExtBfwDl5=10,3,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=10,3,0,0,9,1
-ExtBfwUl1=10,3,0,0,9,1
-ExtBfwUl2=10,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 8 4 MAX MAX 33% 90 33% 90 8.5 3.45 0% DU
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=10,3,0,0,9,1
-ExtBfwDl1=10,3,0,0,9,1
-ExtBfwDl2=10,3,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=10,3,0,0,9,1
-ExtBfwUl1=10,3,0,0,9,1
-ExtBfwUl2=10,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 8 4 MAX MAX 33% 90 33% 90 8.5 3.45 0% DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 8 4 MAX 16QAM 0.5 33% 90 33% 90 8.5 2.3 DU
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=10,3,0,0,9,1
-ExtBfwDl1=10,3,0,0,9,1
-ExtBfwDl2=10,3,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=10,3,0,0,9,1
-ExtBfwUl1=10,3,0,0,9,1
-ExtBfwUl2=10,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 8 4 MAX 16QAM 0.5 33% 90 33% 90 8.5 2.3 DU
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 8 4 64QAM 0.5 16QAM 0.5 66% 180 33% 90 6.85 2.3 0%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-PrbElemDl3=90,30,0,14,3,1,1,9,1
-PrbElemDl4=120,30,0,14,4,1,1,9,1
-PrbElemDl5=150,30,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=10,3,0,0,9,1
-ExtBfwDl1=10,3,0,0,9,1
-ExtBfwDl2=10,3,0,0,9,1
-ExtBfwDl3=10,3,0,0,9,1
-ExtBfwDl4=10,3,0,0,9,1
-ExtBfwDl5=10,3,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=10,3,0,0,9,1
-ExtBfwUl1=10,3,0,0,9,1
-ExtBfwUl2=10,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD 1 64T64R 100 8 4 64QAM 0.5 16QAM 0.5 66% 180 33% 90 6.85 2.3 0%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-PrbElemDl3=90,30,0,14,3,1,1,9,1
-PrbElemDl4=120,30,0,14,4,1,1,9,1
-PrbElemDl5=150,30,0,14,5,1,1,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>30,70,31,71,32,72,33,73,34,74,35,75,36,76,37,77,38,78,39,79</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+#ioWorker=0x000000000 # mask [0- no workers]
+#ioWorker=0x8000040000 # mask [0- no workers]
+ioWorker=0x100000000 # mask [0- no workers]
+#ioWorker=0x700000600
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+dlCpProcBurst=1
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du.dat #O-DU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
# limitations under the License.
#
#******************************************************************************/
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
# This is simple configuration file. Use '#' sign for comments
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-#ioWorker=0x200000000000 # mask [0- no workers]
-ioWorker=0xE00000C00000 # mask [0- no workers]
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
dpdkMemorySize=8192
iovaMode=0
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
+oXuCfgFile0=./config_file_o_du.dat #O-DU0
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+#ioWorker=0x800000000 # mask [0- no workers]
+#ioWorker=0x800004000 # mask [0- no workers]
+#ioWorker=0xc000000 # second socket
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x3E00 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du_icx.xml
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,56,17,57,18,58,19,59,21,61,22,62,23,63,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwDl0=2,24,0,0,9,1
+ExtBfwDl1=2,24,0,0,9,1
+ExtBfwDl2=2,24,0,0,9,1
+ExtBfwDl3=2,24,0,0,9,1
+ExtBfwDl4=2,24,0,0,9,1
+ExtBfwDl5=2,17,0,0,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwUl0=2,24,0,0,9,1
+ExtBfwUl1=2,24,0,0,9,1
+ExtBfwUl2=2,24,0,0,9,1
+ExtBfwUl3=2,24,0,0,9,1
+ExtBfwUl4=2,24,0,0,9,1
+ExtBfwUl5=2,17,0,0,9,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
Gps_Beta=0
numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
#SlotNumRx8=./peak_rxconfig_3.cfg
#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
#DL PRB / % Used RBs UL PRB / % Used RBs
#66% 180 33% 90
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+#ioWorker=0x000000000 # mask [0- no workers]
+#ioWorker=0x8000040000 # mask [0- no workers]
+ioWorker=0x100000000 # mask [0- no workers]
+#ioWorker=0x700000600
+
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+dlCpProcBurst=1
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=20 #core for main()
-systemCore=22
-ioCore=28 # core id
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
#ioWorker=0x800000000 # mask [0- no workers]
#ioWorker=0x800004000 # mask [0- no workers]
#ioWorker=0xc000000 # second socket
-ioWorker=0x3E0000000 # second socket
+ioWorker=0x3E00 # second socket
-dpdkMemorySize=16384
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+#===== Test case for 32T32R antElm, 4 DL 2 UL layers , 1 CC =====
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x3E00 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>30,70,31,71,32,72,33,73,34,74,35,75,36,76,37,77,38,78,39,79</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
#******************************************************************************/
#Peak: 100 %
-#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
+#184 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
appMode=0 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
nPrbElemDl=6
+extType=1
+
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,48,0,14,0,1,1,9,1
PrbElemDl4=192,48,0,14,4,1,1,9,1
PrbElemDl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
nPrbElemUl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl4=192,48,0,14,4,1,1,9,1
PrbElemUl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#184 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+
+#TODO:
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=6
+extType=1
+
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#===== Test case for 32T32R antElm, 8 DL 4 UL layers , 1 CC =====
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+#ioWorker=0x000000000 # mask [0- no workers]
+#ioWorker=0x8000040000 # mask [0- no workers]
+ioWorker=0x020000000 # mask [0- no workers]
+#ioWorker=0x700000600
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+#===== Test case for 32T32R antElm, 8 DL 4 UL layers , 1 CC =====
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+#ioWorker=0x800000000 # mask [0- no workers]
+#ioWorker=0x800004000 # mask [0- no workers]
+#ioWorker=0xc000000 # second socket
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
+ioCore=8 # core id
+ioWorker=0x3E00 # second socket
+
dpdkMemorySize=8192
-#dpdkMemorySize=17408
iovaMode=0
oXuNum=1 # numbers of O-RU connected to O-DU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
appMode=0 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
#SlotNumRx9=./peak_rxconfig_1.cfg
-
+#TODO:
antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
#DL PRB / % Used RBs UL PRB / % Used RBs
#66% 180 33% 90
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
# limitations under the License.
#
#******************************************************************************/
+
+#===== Test case for 32T32R antElm, 8 DL 4 UL layers , 1 CC =====
# This is simple configuration file. Use '#' sign for comments
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=28 # core id
#ioWorker=0x000000000 # mask [0- no workers]
#ioWorker=0x8000040000 # mask [0- no workers]
-ioWorker=0x1E0000000 # mask [0- no workers]
+ioWorker=0x020000000 # mask [0- no workers]
#ioWorker=0x700000600
-dpdkMemorySize=16384
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+dpdkMemorySize=8192
iovaMode=0
oXuNum=1 # numbers of O-RU connected to O-DU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+#===== Test case for 32T32R antElm, 8 DL 4 UL layers , 1 CC =====
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=20 #core for main()
-systemCore=22
-ioCore=28 # core id
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
#ioWorker=0x800000000 # mask [0- no workers]
#ioWorker=0x800004000 # mask [0- no workers]
#ioWorker=0xc000000 # second socket
-ioWorker=0x3E0000000 # second socket
+ioWorker=0x3E00 # second socket
-dpdkMemorySize=16384
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
+ioCore=8 # core id
+ioWorker=0x3E00 # second socket
+
dpdkMemorySize=8192
-#dpdkMemorySize=17408
iovaMode=0
oXuNum=1 # numbers of O-RU connected to O-DU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
appMode=0 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-ioSleep=1
+#ioSleep=1
# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=0 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=4
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl5=180,36,0,14,6,1,1,9,1
PrbElemDl6=216,36,0,14,7,1,1,9,1
PrbElemDl7=252,21,0,14,8,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl5=180,36,0,14,6,1,1,9,1
PrbElemUl6=216,36,0,14,7,1,1,9,1
PrbElemUl7=252,21,0,14,8,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
ioCore=15
ioWorker=0x800000000
-ioSleep=1
+
# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+#duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+#duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+#ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=0 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=4
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl1=48,48,0,14,2,1,1,9,1
PrbElemDl2=96,48,0,14,3,1,1,9,1
PrbElemDl3=144,48,0,14,4,1,1,9,1
+PrbElemDl4=144,36,0,14,5,1,1,9,1
+PrbElemDl5=180,36,0,14,6,1,1,9,1
+PrbElemDl6=216,36,0,14,7,1,1,9,1
+PrbElemDl7=252,21,0,14,8,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+PrbElemUl2=72,36,0,14,3,1,1,9,1
+PrbElemUl3=108,36,0,14,4,1,1,9,1
+PrbElemUl4=144,36,0,14,5,1,1,9,1
+PrbElemUl5=180,36,0,14,6,1,1,9,1
+PrbElemUl6=216,36,0,14,7,1,1,9,1
+PrbElemUl7=252,21,0,14,8,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl2=12,4,0,0,9,1
ExtBfwUl3=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl2=96,48,0,14,3,1,1,9,1
PrbElemUl3=144,48,0,14,4,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>8</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>8</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl4=12,4,0,0,9,1
ExtBfwUl5=11,3,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl4=192,48,0,14,5,1,1,9,1
PrbElemUl5=240,33,0,14,6,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=12,4,0,0,9,1
ExtBfwUl1=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=12,4,0,0,9,1
ExtBfwUl1=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl0=12,4,0,0,9,1
ExtBfwUl1=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl2=12,4,0,0,9,1
ExtBfwUl3=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl2=96,48,0,14,3,1,1,9,1
PrbElemUl3=144,48,0,14,4,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl2=12,4,0,0,9,1
ExtBfwUl3=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl2=96,48,0,14,3,1,1,9,1
PrbElemUl3=144,48,0,14,4,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>8</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>8</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
#UEs
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
PrbElemDl5=240,33,0,14,6,1,1,9,1
# Extension Parameters for Beamforming weights
# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
+ExtBfwDl0=2,24,0,0,9,1
+ExtBfwDl1=2,24,0,0,9,1
+ExtBfwDl2=2,24,0,0,9,1
+ExtBfwDl3=2,24,0,0,9,1
+ExtBfwDl4=2,24,0,0,9,1
+ExtBfwDl5=2,17,0,0,9,1
nPrbElemUl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl5=240,33,0,14,6,1,1,9,1
# Extension Parameters for Beamforming weights
# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+ExtBfwUl0=2,24,0,0,9,1
+ExtBfwUl1=2,24,0,0,9,1
+ExtBfwUl2=2,24,0,0,9,1
+ExtBfwUl3=2,24,0,0,9,1
+ExtBfwUl4=2,24,0,0,9,1
+ExtBfwUl5=2,17,0,0,9,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
#UEs
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemDl3=144,48,0,14,4,1,1,9,1
PrbElemDl4=192,48,0,14,5,1,1,9,1
PrbElemDl5=240,33,0,14,6,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwDl0=2,24,0,0,9,1
+ExtBfwDl1=2,24,0,0,9,1
+ExtBfwDl2=2,24,0,0,9,1
+ExtBfwDl3=2,24,0,0,9,1
+ExtBfwDl4=2,24,0,0,9,1
+ExtBfwDl5=2,17,0,0,9,1
+
nPrbElemUl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl3=144,48,0,14,4,1,1,9,1
PrbElemUl4=192,48,0,14,5,1,1,9,1
PrbElemUl5=240,33,0,14,6,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwUl0=2,24,0,0,9,1
+ExtBfwUl1=2,24,0,0,9,1
+ExtBfwUl2=2,24,0,0,9,1
+ExtBfwUl3=2,24,0,0,9,1
+ExtBfwUl4=2,24,0,0,9,1
+ExtBfwUl5=2,17,0,0,9,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
# This is simple configuration file. Use '#' sign for comments
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
+mainCore=0 #core for main()
+systemCore=2
+ioCore=10 # core id
+ioWorker=0x4000000000000 # mask [0- no workers]
+dpdkMemorySize=8192
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+iovaMode=0
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./config_file_o_du.dat #O-RU0
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
+
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
oXuRem0Mac1=00:11:22:33:00:10
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=12,4,0,0,9,1
ExtBfwUl1=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=12,4,0,0,9,1
ExtBfwUl1=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl0=12,4,0,0,9,1
ExtBfwUl1=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl0=0,48,0,14,1,1,1,9,1
PrbElemUl1=48,48,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
-
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
#DL PRB / % Used RBs UL PRB / % Used RBs
#33% 90 33% 90
ExtBfwUl2=12,4,0,0,9,1
ExtBfwUl3=12,4,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl2=96,48,0,14,3,1,1,9,1
PrbElemUl3=144,48,0,14,4,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
oXuCfgFile0=./config_file_o_du.dat #O-RU0
#O-XU 0
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-PrbElemDl4=192,48,0,14,5,1,1,9,1
-PrbElemDl5=240,33,0,14,6,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-PrbElemUl4=192,48,0,14,5,1,1,9,1
-PrbElemUl5=240,33,0,14,6,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-PrbElemDl4=192,48,0,14,5,1,1,9,1
-PrbElemDl5=240,33,0,14,6,1,1,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-PrbElemUl4=192,48,0,14,5,1,1,9,1
-PrbElemUl5=240,33,0,14,6,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-PrbElemDl4=192,48,0,14,5,1,1,9,1
-PrbElemDl5=240,33,0,14,6,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-PrbElemUl4=192,48,0,14,5,1,1,9,1
-PrbElemUl5=240,33,0,14,6,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-PrbElemDl4=192,48,0,14,5,1,1,9,1
-PrbElemDl5=240,33,0,14,6,1,1,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-PrbElemUl4=192,48,0,14,5,1,1,9,1
-PrbElemUl5=240,33,0,14,6,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#33% 90 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=96,48,0,14,3,1,1,9,1
-PrbElemUl3=144,48,0,14,4,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=28 # core id
#ioWorker=0x000000000 # mask [0- no workers]
#ioWorker=0x8000040000 # mask [0- no workers]
-ioWorker=0x1E0000000 # mask [0- no workers]
+ioWorker=0x760000000 # mask [0- no workers]
#ioWorker=0x700000600
-
-dpdkMemorySize=16384
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=2 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0xE00 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=20 #core for main()
-systemCore=22
-ioCore=28 # core id
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
#ioWorker=0x800000000 # mask [0- no workers]
#ioWorker=0x800004000 # mask [0- no workers]
#ioWorker=0xc000000 # second socket
-ioWorker=0x3E0000000 # second socket
+ioWorker=0x3E00 # second socket
-dpdkMemorySize=16384
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=2 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0x3E00 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>14</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>14</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>12,52,13,53,14,54,15,55,16,56,17,57,18,59,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>2</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>2</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwDl0=2,24,0,0,9,1
+ExtBfwDl1=2,24,0,0,9,1
+ExtBfwDl2=2,24,0,0,9,1
+ExtBfwDl3=2,24,0,0,9,1
+ExtBfwDl4=2,24,0,0,9,1
+ExtBfwDl5=2,17,0,0,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwUl0=2,24,0,0,9,1
+ExtBfwUl1=2,24,0,0,9,1
+ExtBfwUl2=2,24,0,0,9,1
+ExtBfwUl3=2,24,0,0,9,1
+ExtBfwUl4=2,24,0,0,9,1
+ExtBfwUl5=2,17,0,0,9,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
#******************************************************************************/
#Peak: 100 %
-#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
Gps_Beta=0
numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
#SlotNumRx8=./peak_rxconfig_3.cfg
#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
#DL PRB / % Used RBs UL PRB / % Used RBs
#66% 180 33% 90
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=28 # core id
#ioWorker=0x000000000 # mask [0- no workers]
#ioWorker=0x8000040000 # mask [0- no workers]
-ioWorker=0x1E0000000 # mask [0- no workers]
+ioWorker=0x020000000 # mask [0- no workers]
#ioWorker=0x700000600
-dpdkMemorySize=16384
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=2 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0x200 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+#ioWorker=0x800000000 # mask [0- no workers]
+#ioWorker=0x800004000 # mask [0- no workers]
+#ioWorker=0xc000000 # second socket
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0x3E00 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
#******************************************************************************/
#Peak: 100 %
-#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
+#284 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
appMode=0 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+
nPrbElemDl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl4=192,48,0,14,4,1,1,9,1
PrbElemDl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
nPrbElemUl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl4=192,48,0,14,4,1,1,9,1
PrbElemUl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#284 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+
+#TODO:
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+extType=1
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+ioWorker=0x020000000 # mask [0- no workers]
+dpdkMemorySize=8192
iovaMode=0
-oXuNum=1 # numbers of O-RU connected to O-DU
+oXuNum=2 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+oXuCfgFile1=./peak_o_du.dat #O-DU1
+#oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+oXuCfgFile1=./peak_o_du.dat #O-DU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
+ioCore=8 # core id
+ioWorker=0x3E00 # second socket
+
dpdkMemorySize=8192
-#dpdkMemorySize=17408
iovaMode=0
-oXuNum=1 # numbers of O-RU connected to O-DU
+oXuNum=2 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+oXuCfgFile1=./peak_o_ru.dat #O-RU1
+#oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+oXuCfgFile1=./peak_o_ru.dat #O-RU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
appMode=0 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#******************************************************************************/
#Peak: 100 %
-#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
#UEs
muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
#SlotNumTx0=./peak_txconfig_1.cfg
#SlotNumTx1=./peak_txconfig_1.cfg
#SlotNumRx9=./peak_rxconfig_1.cfg
-
+#TODO:
antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
#DL PRB / % Used RBs UL PRB / % Used RBs
#66% 180 33% 90
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 # in us
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+ioWorker=0x020000000 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+#oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
+ioCore=8 # core id
+ioWorker=0x3E00 # second socket
+
dpdkMemorySize=8192
-#dpdkMemorySize=17408
iovaMode=0
-oXuNum=1 # numbers of O-RU connected to O-DU
+oXuNum=2 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+#oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=8192
+iovaMode=0
+
+oXuNum=2 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask 0-no workers
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=8
-max_sections_per_symbol=8
-
-nPrbElemDl=8
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,36,0,14,1,1,1,9,1
-PrbElemDl1=36,36,0,14,2,1,1,9,1
-PrbElemDl2=72,36,0,14,3,1,1,9,1
-PrbElemDl3=108,36,0,14,4,1,1,9,1
-PrbElemDl4=144,36,0,14,5,1,1,9,1
-PrbElemDl5=180,36,0,14,6,1,1,9,1
-PrbElemDl6=216,36,0,14,7,1,1,9,1
-PrbElemDl7=252,21,0,14,8,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,3,0,0,9,1
-ExtBfwDl1=12,3,0,0,9,1
-ExtBfwDl2=12,3,0,0,9,1
-ExtBfwDl3=12,3,0,0,9,1
-ExtBfwDl4=12,3,0,0,9,1
-ExtBfwDl5=12,3,0,0,9,1
-ExtBfwDl6=12,3,0,0,9,1
-ExtBfwDl7=7,3,0,0,9,1
-
-nPrbElemUl=8
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,36,0,14,1,1,1,9,1
-PrbElemUl1=36,36,0,14,2,1,1,9,1
-PrbElemUl2=72,36,0,14,3,1,1,9,1
-PrbElemUl3=108,36,0,14,4,1,1,9,1
-PrbElemUl4=144,36,0,14,5,1,1,9,1
-PrbElemUl5=180,36,0,14,6,1,1,9,1
-PrbElemUl6=216,36,0,14,7,1,1,9,1
-PrbElemUl7=252,21,0,14,8,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,3,0,0,9,1
-ExtBfwUl1=12,3,0,0,9,1
-ExtBfwUl2=12,3,0,0,9,1
-ExtBfwUl3=12,3,0,0,9,1
-ExtBfwUl4=12,3,0,0,9,1
-ExtBfwUl5=12,3,0,0,9,1
-ExtBfwUl6=12,3,0,0,9,1
-ExtBfwUl7=7,3,0,0,9,1
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=8
-max_sections_per_symbol=8
-
-nPrbElemDl=8
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,36,0,14,1,1,1,9,1
-PrbElemDl1=36,36,0,14,2,1,1,9,1
-PrbElemDl2=72,36,0,14,3,1,1,9,1
-PrbElemDl3=108,36,0,14,4,1,1,9,1
-PrbElemDl4=144,36,0,14,5,1,1,9,1
-PrbElemDl5=180,36,0,14,6,1,1,9,1
-PrbElemDl6=216,36,0,14,7,1,1,9,1
-PrbElemDl7=252,21,0,14,8,1,1,9,1
-
-nPrbElemUl=8
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,36,0,14,1,1,1,9,1
-PrbElemUl1=36,36,0,14,2,1,1,9,1
-PrbElemUl2=72,36,0,14,3,1,1,9,1
-PrbElemUl3=108,36,0,14,4,1,1,9,1
-PrbElemUl4=144,36,0,14,5,1,1,9,1
-PrbElemUl5=180,36,0,14,6,1,1,9,1
-PrbElemUl6=216,36,0,14,7,1,1,9,1
-PrbElemUl7=252,21,0,14,8,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
dpdkMemorySize=8192
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
iovaMode=0
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
oXuCfgFile0=./config_file_o_du.dat #O-RU0
# remote O-XU 0 Eth Link 0
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+oXuBbuCfgFile=./bbu_pool_cfg_o_ru.xml #O-RU0
oXuCfgFile0=./config_file_o_ru.dat #O-RU0
# remote O-XU 0 Eth Link 0
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./config_file_o_du.dat #O-RU0
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./config_file_o_ru.dat #O-RU0
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
oXuRem1Mac1=00:11:22:33:01:11
# remote O-XU 1 Eth Link 1
oXuRem1Mac2=00:11:22:33:01:21
+
oXuRem1Mac3=00:11:22:33:01:31
# remote O-XU 2 Eth Link 0
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=2,25,0,0,9,1
ExtBfwUl1=2,25,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl0=2,25,0,0,9,1
ExtBfwUl1=2,25,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
## control of IQ byte order
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
dpdkMemorySize=8192
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=2,25,0,0,9,1
ExtBfwUl1=2,25,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>10</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
iovaMode=0
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
#oXuRxqNumber=48 # number of HW RX Queues per VF (should >= RX IQ stream per VF)
+
oXuCfgFile0=./config_file_o_du.dat #O-RU0
# remote O-XU 0 Eth Link 0
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=2,25,0,0,9,1
ExtBfwUl1=2,25,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl0=2,25,0,0,9,1
ExtBfwUl1=2,25,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl0=2,25,0,0,9,1
ExtBfwUl1=2,25,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>5,45,6,46,7,47,8,48,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+
nPrbElemDl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl4=192,48,0,14,4,1,1,9,1
PrbElemDl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
nPrbElemUl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl4=192,48,0,14,4,1,1,9,1
PrbElemUl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
#Peak: 100 %
#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
+
# This is simple configuration file. Use '#' sign for comments
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
nPrbElemDl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl4=192,48,0,14,4,1,1,9,1
PrbElemDl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
nPrbElemUl=6
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl4=192,48,0,14,4,1,1,9,1
PrbElemUl5=240,33,0,14,5,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
mainCore=0 #core for main()
systemCore=2
ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioWorker=0x7000000000000 # mask [0- no workers]
+dpdkMemorySize=10240
iovaMode=0
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml #O-RU0
oXuCfgFile0=./config_file_o_du.dat #O-RU0
# remote O-XU 0 Eth Link 0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=11 # core id
+ioWorker=0xF8000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
+
+dpdkMemorySize=10240
+
+iovaMode=0
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# oXuRem0Mac0=68:05:ca:c1:bf:10
+# oXuRem0Mac1=68:05:ca:c1:bf:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
+ioWorker=0xF10000000 # mask [0- no workers]
oXuNum=1 # numbers of O-RU connected to O-DU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+oXuBbuCfgFile=./bbu_pool_cfg_o_ru.xml #O-RU0
oXuCfgFile0=./config_file_o_ru.dat #O-RU0
# remote O-XU 0 Eth Link 0
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,0,1,1,9,1
PrbElemDl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl0=0,50,0,14,0,1,1,9,1
PrbElemUl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
#
#******************************************************************************/
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
+#Peak
+#4%
+#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 %
# This is simple configuration file. Use '#' sign for comments
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF
-duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF
-
-ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app
-ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF
-duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF
-
-ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app
-ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app
-
-# Eth 1
-duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF
-duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF
-ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app
-ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app
-
-
numSlots=20 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=3
+extType=1
+
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,128,0,14,0,1,1,9,1
-PrbElemDl1=128,128,0,14,1,1,1,9,1
-PrbElemDl2=256,17,0,14,2,1,1,9,1
-
-nPrbElemUl=3
+PrbElemDl0=0,50,0,14,0,1,1,9,1
+PrbElemDl1=50,50,0,14,1,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
+
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,128,0,14,0,1,1,9,1
-PrbElemUl1=128,128,0,14,1,1,1,9,1
-PrbElemUl2=256,17,0,14,2,1,1,9,1
+PrbElemUl0=0,50,0,14,0,1,1,9,1
+PrbElemUl1=50,50,0,14,1,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioCore=11 # core id
+ioWorker=0x80000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
-iovaMode=0
+dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
-
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
#NC
#12%
-#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12%
+#323 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12%
# This is simple configuration file. Use '#' sign for comments
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,0,1,1,9,1
PrbElemDl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl0=0,50,0,14,0,1,1,9,1
PrbElemUl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
#
#******************************************************************************/
-#MEC
-#28%
-#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28%
+#NC
+#12%
+#323 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12%
# This is simple configuration file. Use '#' sign for comments
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,0,1,1,9,1
PrbElemDl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl0=0,50,0,14,0,1,1,9,1
PrbElemUl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioCore=11 # core id
+ioWorker=0x80000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
#MC
#20%
-#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20%
+#324 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20%
# This is simple configuration file. Use '#' sign for comments
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+extType=1
+
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,0,1,1,9,1
PrbElemDl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl0=0,50,0,14,0,1,1,9,1
PrbElemUl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
#
#******************************************************************************/
-#TDD 1 64T64R 100 16 8 64QAM 0.5 16QAM 0.5 66% 180 33% 90 13.7 4.6 0%
-
-
+#MC
+#20%
+#324 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20%
# This is simple configuration file. Use '#' sign for comments
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
appMode=1 # O-DU(0) | O-RU(1)
xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
#UEs
nULFftSize=4096
nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=6
+extType=1
+
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
-PrbElemDl3=90,30,0,14,3,1,1,9,1
-PrbElemDl4=120,30,0,14,4,1,1,9,1
-PrbElemDl5=150,30,0,14,5,1,1,9,1
-
-nPrbElemUl=3
+PrbElemDl0=0,50,0,14,0,1,1,9,1
+PrbElemDl1=50,50,0,14,1,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
+
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,30,0,14,0,1,1,9,1
-PrbElemUl1=30,30,0,14,1,1,1,9,1
-PrbElemUl2=60,30,0,14,2,1,1,9,1
-
+PrbElemUl0=0,50,0,14,0,1,1,9,1
+PrbElemUl1=50,50,0,14,1,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
dpdkMemorySize=8192
-
-iovaMode=0
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
-
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioCore=11 # core id
+ioWorker=0x80000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
-iovaMode=0
+dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
-
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
#MEC
#28%
-#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28%
+#325 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28%
# This is simple configuration file. Use '#' sign for comments
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
nPrbElemDl=2
+
+extType=1
+
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,0,1,1,9,1
PrbElemDl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl0=0,50,0,14,0,1,1,9,1
PrbElemUl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
#MEC
#28%
-#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28%
+#325 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28%
# This is simple configuration file. Use '#' sign for comments
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,0,1,1,9,1
PrbElemDl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
PrbElemUl0=0,50,0,14,0,1,1,9,1
PrbElemUl1=50,50,0,14,1,1,1,9,1
# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
+
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
systemCore=2
ioCore=10 # core id
ioWorker=0x4000000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioCore=11 # core id
+ioWorker=0x80000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
-iovaMode=0
+dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
-
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl3=10,4,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl3=10,4,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-puschMaskEnable=1 # Enable (1)| disable (0) PUSCH Mask
-puschMaskSlot=3 # (num mode Frame) slots will not transfer PUSCH channel (def: sym 13)
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,64,0,14,0,1,1,9,1
-PrbElemUl1=64,36,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>20</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>20</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,21,53,22,54,23,55,24,56,25,57,26,58,27,59</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>3</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>10</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>8,48,9,49,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-puschMaskEnable=1 # Enable (1)| disable (0) PUSCH Mask
-puschMaskSlot=3 # (num mode Frame) slots will not transfer PUSCH channel (def: sym 13)
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,46,0,14,0,1,1,9,1
-PrbElemUl1=46,46,0,14,1,1,1,9,1
-PrbElemUl2=92,46,0,14,2,1,1,9,1
-PrbElemUl3=138,46,0,14,3,1,1,9,1
-PrbElemUl4=184,46,0,14,4,1,1,9,1
-PrbElemUl5=230,43,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
#
#******************************************************************************/
# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=22 # core id
-ioWorker=0xC00000800000 # mask [0- no workers]
+ioCore=10 # core id
+#ioWorker=0x200000000000 # mask [0- no workers]
+#ioWorker=0x3C00000 # mask [0- no workers]
+#ioWorker=0x40000000000
+ioWorker=0x800
+#dpdkMemorySize=8192
+#ioWorker=0x000000000 # mask [0- no workers]
+#ioWorker=0x8000040000 # mask [0- no workers]
+#ioWorker=0x1E0000000 # mask [0- no workers]
+#ioWorker=0x700000600
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
dpdkMemorySize=18432
-
iovaMode=0
oXuNum=3 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-#oXuRxqNumber=41 # number of HW RX Queues per VF (should >= RX IQ streams per VF)
+dlCpProcBurst=1 # (1) - send CP as burst
+xranMlogDisable=1 # (1) to reduce Mlog (disable) (0) - keep all mlog (enable default)
+
oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+#oXuCfgFile0=./avg_o_du_tst377.dat #O-DU1
oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
ioWorker=0x1E0000000 # mask [0- no workers]
#ioWorker=0x700000600
-dpdkMemorySize=16384
+dpdkMemorySize=18432
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=1 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+#oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile0=./avg_o_du_tst377.dat #O-DU1
oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
#
#******************************************************************************/
# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
ioCore=8 # core id
+#ioWorker=0x800000000 # mask [0- no workers]
+#ioWorker=0x800004000 # mask [0- no workers]
+#ioWorker=0xc000000 # second socket
ioWorker=0x3E00 # second socket
-
+ioWorker=0x0200 # second socket
+oXuBbuCfgFile=./bbu_pool_cfg_o_ru.xml
dpdkMemorySize=18432
iovaMode=0
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+dlCpProcBurst=1 # (1) - send CP as burst
+xranMlogDisable=1 # (1) to reduce Mlog (disable) (0) - keep all mlog (enable default)
oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+#oXuCfgFile0=./avg_o_ru_tst377.dat #O-RU1
oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
-
oXuRem0Mac1=00:11:22:33:00:10
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:20
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=8 # core id
-ioWorker=0x3E00 # second socket
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_ru_tst376_dynamic.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377_dynamic.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377_dynamic.dat #O-RU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl3=10,4,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl3=10,4,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl5=2,17,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF
-duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF
-
-ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app
-ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF
-duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF
-
-ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app
-ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app
-
-# Eth 1
-duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF
-duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF
-ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app
-ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app
-
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=22 # core id
-ioWorker=0xC00000800000 # mask [0- no workers]
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=8 # core id
-ioWorker=0x3E00 # second socket
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-#PrbElemSrs1=136,137,0,14,0,0,0,16,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF
-duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF
-
-ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app
-ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF
-duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF
-
-ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app
-ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app
-
-# Eth 1
-duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF
-duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF
-ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app
-ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app
-
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=22 # core id
-ioWorker=0xC00000800000 # mask [0- no workers]
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=8 # core id
-ioWorker=0x3E00 # second socket
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+
+ioWorker=0x7E0000000 # mask [0- no workers]
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+oXuCfgFile2=./peak_o_du_tst376.dat #O-DU2
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
mainCore=0 #core for main()
systemCore=2
-ioCore=10 # core id
-#ioWorker=0xE00000C00000 # mask [0- no workers]
-ioWorker=0x1C000000001800
+ioCore=8 # core id
+
+ioWorker=0x3E00 # mask [0- no workers]
+
+
dpdkMemorySize=16384
-#8192
iovaMode=0
-oXuNum=1 # numbers of O-RU connected to O-DU
+oXuNum=3 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+oXuCfgFile2=./peak_o_du_tst376.dat #O-DU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
ioCore=8 # core id
-ioWorker=0x10000000 # mask [0- no workers]
-oXuNum=1 # numbers of O-RU connected to O-DU
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+oXuCfgFile2=./peak_o_ru_tst376.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+oXuCfgFile2=./peak_o_ru_tst376.dat #O-RU2
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
+srsEnable=1 # Enable (1)| disable (0) SRS
srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF
-duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF
-
-ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app
-ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF
-duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF
-
-ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app
-ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app
-
-# Eth 1
-duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF
-duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF
-ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app
-ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app
-
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0xE00000C00000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX antennas on DL UE side
-UlLayersPerUe=1 #number of TX antennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./avg_txconfig_1.cfg
-#SlotNumTx1=./avg_txconfig_1.cfg
-#SlotNumTx2=./avg_txconfig_1.cfg
-#SlotNumTx3=./avg_txconfig_2.cfg
-#SlotNumTx4=./avg_txconfig_0.cfg
-
-#SlotNumTx5=./avg_txconfig_1.cfg
-#SlotNumTx6=./avg_txconfig_1.cfg
-#SlotNumTx7=./avg_txconfig_1.cfg
-#SlotNumTx8=./avg_txconfig_2.cfg
-#SlotNumTx9=./avg_txconfig_0.cfg
-
-#SlotNumRx0=./avg_rxconfig_0.cfg
-#SlotNumRx1=./avg_rxconfig_0.cfg
-#SlotNumRx2=./avg_rxconfig_0.cfg
-#SlotNumRx3=./avg_rxconfig_2.cfg
-#SlotNumRx4=./avg_rxconfig_1.cfg
-
-#SlotNumRx5=./avg_rxconfig_0.cfg
-#SlotNumRx6=./avg_rxconfig_0.cfg
-#SlotNumRx7=./avg_rxconfig_0.cfg
-#SlotNumRx8=./avg_rxconfig_3.cfg
-#SlotNumRx9=./avg_rxconfig_1.cfg
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemUl=4
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=10,4,0,0,9,1
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=4
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,34,0,14,3,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=10,4,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF
-duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF
-
-ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app
-ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF
-duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF
-
-ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app
-ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app
-
-# Eth 1
-duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF
-duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF
-ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app
-ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app
-
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#SlotNumTx0=./peak_txconfig_1.cfg
-#SlotNumTx1=./peak_txconfig_1.cfg
-#SlotNumTx2=./peak_txconfig_1.cfg
-#SlotNumTx3=./peak_txconfig_2.cfg
-#SlotNumTx4=./peak_txconfig_0.cfg
-
-#SlotNumTx5=./peak_txconfig_1.cfg
-#SlotNumTx6=./peak_txconfig_1.cfg
-#SlotNumTx7=./peak_txconfig_1.cfg
-#SlotNumTx8=./peak_txconfig_2.cfg
-#SlotNumTx9=./peak_txconfig_0.cfg
-
-#SlotNumRx0=./peak_rxconfig_0.cfg
-#SlotNumRx1=./peak_rxconfig_0.cfg
-#SlotNumRx2=./peak_rxconfig_0.cfg
-#SlotNumRx3=./peak_rxconfig_2.cfg
-#SlotNumRx4=./peak_rxconfig_1.cfg
-
-#SlotNumRx5=./peak_rxconfig_0.cfg
-#SlotNumRx6=./peak_rxconfig_0.cfg
-#SlotNumRx7=./peak_rxconfig_0.cfg
-#SlotNumRx8=./peak_rxconfig_3.cfg
-#SlotNumRx9=./peak_rxconfig_1.cfg
-
-
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemUl=6
-
-# 0-15 CCs
-PrbElemUlCCMask0=0f
-PrbElemUlCCMask1=0f
-PrbElemUlCCMask2=0f
-PrbElemUlCCMask3=0f
-PrbElemUlCCMask4=0f
-PrbElemUlCCMask5=0f
-
-# 0-63 AntC
-PrbElemUlAntCMask0=ffffffffffffffff
-PrbElemUlAntCMask1=ffffffffffffffff
-PrbElemUlAntCMask2=ffffffffffffffff
-PrbElemUlAntCMask3=ffffffffffffffff
-PrbElemUlAntCMask4=ffffffffffffffff
-PrbElemUlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=12,4,0,0,9,1
-ExtBfwUl1=12,4,0,0,9,1
-ExtBfwUl2=12,4,0,0,9,1
-ExtBfwUl3=12,4,0,0,9,1
-ExtBfwUl4=12,4,0,0,9,1
-ExtBfwUl5=11,3,0,0,9,1
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs S
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-nPrbElemDl=6
-
-# 0-15 CCs
-PrbElemDlCCMask0=0f
-PrbElemDlCCMask1=0f
-PrbElemDlCCMask2=0f
-PrbElemDlCCMask3=0f
-PrbElemDlCCMask4=0f
-PrbElemDlCCMask5=0f
-
-# 0-63 AntC
-PrbElemDlAntCMask0=ffffffffffffffff
-PrbElemDlAntCMask1=ffffffffffffffff
-PrbElemDlAntCMask2=ffffffffffffffff
-PrbElemDlAntCMask3=ffffffffffffffff
-PrbElemDlAntCMask4=ffffffffffffffff
-PrbElemDlAntCMask5=ffffffffffffffff
-
-
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=12,4,0,0,9,1
-ExtBfwDl1=12,4,0,0,9,1
-ExtBfwDl2=12,4,0,0,9,1
-ExtBfwDl3=12,4,0,0,9,1
-ExtBfwDl4=12,4,0,0,9,1
-ExtBfwDl5=11,3,0,0,9,1
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=22 # core id
-ioWorker=0xE00000C00000 # mask [0- no workers]
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-# 3501 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=8 # core id
-ioWorker=0x3E00 # second socket
-
-dpdkMemorySize=18432
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=20 #core for main()
-systemCore=22
-ioCore=28 # core id
-#ioWorker=0x800000000 # mask [0- no workers]
-#ioWorker=0x800004000 # mask [0- no workers]
-#ioWorker=0xc000000 # second socket
-ioWorker=0x3E0000000 # second socket
-
-dpdkMemorySize=16384
-iovaMode=0
-
-oXuNum=3 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#384 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+extType=1
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#384 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+
+#TODO:
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+extType=1
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=28 # core id
#ioWorker=0x000000000 # mask [0- no workers]
#ioWorker=0x8000040000 # mask [0- no workers]
-ioWorker=0x1E0000000 # mask [0- no workers]
+ioWorker=0x060000000 # mask [0- no workers]
#ioWorker=0x700000600
dpdkMemorySize=16384
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
-oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1
-oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+oXuCfgFile1=./peak_o_du.dat #O-DU1
+oXuCfgFile2=./peak_o_du.dat #O-DU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0xE00000C00000 # mask [0- no workers]
+ioCore=8 # core id
+
+ioWorker=0x200 # mask [0- no workers]
+
dpdkMemorySize=16384
-#8192
iovaMode=0
-oXuNum=1 # numbers of O-RU connected to O-DU
+oXuNum=3 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+oXuCfgFile1=./peak_o_du.dat #O-DU1
+oXuCfgFile2=./peak_o_du.dat #O-DU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+
appMode=1 # All O-DU(0) | O-RU(1)
instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=20 #core for main()
-systemCore=22
-ioCore=28 # core id
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
#ioWorker=0x800000000 # mask [0- no workers]
#ioWorker=0x800004000 # mask [0- no workers]
#ioWorker=0xc000000 # second socket
-ioWorker=0x3E0000000 # second socket
+ioWorker=0x3E00 # second socket
dpdkMemorySize=16384
iovaMode=0
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+oXuCfgFile1=./peak_o_ru.dat #O-RU1
+oXuCfgFile2=./peak_o_ru.dat #O-RU2
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0x3E00 # second socket
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=3 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+oXuCfgFile1=./peak_o_ru.dat #O-RU1
+oXuCfgFile2=./peak_o_ru.dat #O-RU2
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-ioSleep=1
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-PrbElemDl4=144,36,0,14,5,1,1,9,1
-PrbElemDl5=180,36,0,14,6,1,1,9,1
-PrbElemDl6=216,36,0,14,7,1,1,9,1
-PrbElemDl7=252,21,0,14,8,1,1,9,1
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-PrbElemUl2=72,36,0,14,3,1,1,9,1
-PrbElemUl3=108,36,0,14,4,1,1,9,1
-PrbElemUl4=144,36,0,14,5,1,1,9,1
-PrbElemUl5=180,36,0,14,6,1,1,9,1
-PrbElemUl6=216,36,0,14,7,1,1,9,1
-PrbElemUl7=252,21,0,14,8,1,1,9,1
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-ioWorker=0x800000000
-ioSleep=1
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=0 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=4
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,1,1,1,9,1
-PrbElemDl1=48,48,0,14,2,1,1,9,1
-PrbElemDl2=96,48,0,14,3,1,1,9,1
-PrbElemDl3=144,48,0,14,4,1,1,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,1,1,1,9,1
-PrbElemUl1=48,48,0,14,2,1,1,9,1
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=32 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:01.0
-#PciBusAddoXu0Vf1=0000:51:01.1
-#PciBusAddoXu0Vf2=0000:51:01.2
-#PciBusAddoXu0Vf3=0000:51:01.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:01.4
-#PciBusAddoXu1Vf1=0000:51:01.5
-#PciBusAddoXu1Vf2=0000:51:01.6
-#PciBusAddoXu1Vf3=0000:51:01.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:02.0
-#PciBusAddoXu2Vf1=0000:51:02.1
-#PciBusAddoXu2Vf2=0000:51:02.2
-#PciBusAddoXu2Vf3=0000:51:02.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-#O-XU 0
-#PciBusAddoXu0Vf0=0000:51:11.0
-#PciBusAddoXu0Vf1=0000:51:11.1
-#PciBusAddoXu0Vf2=0000:51:11.2
-#PciBusAddoXu0Vf3=0000:51:11.3
-
-#O-XU 1
-#PciBusAddoXu1Vf0=0000:51:11.4
-#PciBusAddoXu1Vf1=0000:51:11.5
-#PciBusAddoXu1Vf2=0000:51:11.6
-#PciBusAddoXu1Vf3=0000:51:11.7
-
-#O-XU 2
-#PciBusAddoXu2Vf0=0000:51:12.0
-#PciBusAddoXu2Vf1=0000:51:12.1
-#PciBusAddoXu2Vf2=0000:51:12.2
-#PciBusAddoXu2Vf3=0000:51:12.3
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,64,0,0,9,1
ExtBfwUl2=2,9,0,0,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+rsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
PrbElemUl1=128,128,0,14,1,1,1,9,1
PrbElemUl2=256,17,0,14,2,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF
-duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF
-
-ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app
-ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF
-duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF
-
-ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app
-ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app
-
-# Eth 1
-duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF
-duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF
-ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app
-ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app
-
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,128,0,14,0,1,1,9,1
-PrbElemDl1=128,128,0,14,1,1,1,9,1
-PrbElemDl2=256,17,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,64,0,0,9,1
-ExtBfwDl1=2,64,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-
-nPrbElemUl=3
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,128,0,14,0,1,1,9,1
-PrbElemUl1=128,128,0,14,1,1,1,9,1
-PrbElemUl2=256,17,0,14,2,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,64,0,0,9,1
-ExtBfwUl1=2,64,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+#antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+#antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+#antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+#antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+extType=1
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+#ioWorker=0x000000000 # mask [0- no workers]
+#ioWorker=0x8000040000 # mask [0- no workers]
+ioWorker=0x7E00000000 # mask [0- no workers]
+#ioWorker=0x700000600
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+oXuCfgFile2=./peak_o_du_tst376.dat #O-DU2
+oXuCfgFile3=./peak_o_du_tst376.dat #O-DU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:01
+oXuRem3Mac1=00:11:22:33:03:11
+
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:21
+oXuRem3Mac3=00:11:22:33:03:31
\ No newline at end of file
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+
+ioWorker=0x7E00 # mask [0- no workers]
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0
+oXuCfgFile1=./peak_o_du_tst376.dat #O-DU1
+oXuCfgFile2=./peak_o_du_tst376.dat #O-DU2
+oXuCfgFile3=./peak_o_du_tst376.dat #O-DU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:01
+oXuRem3Mac1=00:11:22:33:03:11
+
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:21
+oXuRem3Mac3=00:11:22:33:03:31
\ No newline at end of file
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+#ioWorker=0x800000000 # mask [0- no workers]
+#ioWorker=0x800004000 # mask [0- no workers]
+#ioWorker=0xc000000 # second socket
+ioWorker=0x7E00 # second socket
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+oXuCfgFile2=./peak_o_ru_tst376.dat #O-RU2
+oXuCfgFile3=./peak_o_ru_tst376.dat #O-RU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:00
+oXuRem3Mac1=00:11:22:33:03:10
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:20
+oXuRem3Mac3=00:11:22:33:03:30
+
# limitations under the License.
#
#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
-# 3501 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
-# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 %
appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
mainCore=0 #core for main()
systemCore=2
ioCore=8 # core id
-ioWorker=0x3E00 # second socket
-dpdkMemorySize=18432
+ioWorker=0x7E00 # second socket
+
+dpdkMemorySize=16384
iovaMode=0
-oXuNum=3 # numbers of O-RU connected to O-DU
+oXuNum=4 # numbers of O-RU connected to O-DU
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0
-oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1
-oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2
+oXuCfgFile1=./peak_o_ru_tst376.dat #O-RU1
+oXuCfgFile2=./peak_o_ru_tst376.dat #O-RU2
+oXuCfgFile3=./peak_o_ru_tst376.dat #O-RU3
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:00
# remote O-XU 2 Eth Link 1
oXuRem2Mac2=00:11:22:33:02:20
oXuRem2Mac3=00:11:22:33:02:30
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:00
+oXuRem3Mac1=00:11:22:33:03:10
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:20
+oXuRem3Mac3=00:11:22:33:03:30
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#484 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+#UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+extType=1
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak: 100 %
+#484 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
+
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#SlotNumTx0=./peak_txconfig_1.cfg
+#SlotNumTx1=./peak_txconfig_1.cfg
+#SlotNumTx2=./peak_txconfig_1.cfg
+#SlotNumTx3=./peak_txconfig_2.cfg
+#SlotNumTx4=./peak_txconfig_0.cfg
+
+#SlotNumTx5=./peak_txconfig_1.cfg
+#SlotNumTx6=./peak_txconfig_1.cfg
+#SlotNumTx7=./peak_txconfig_1.cfg
+#SlotNumTx8=./peak_txconfig_2.cfg
+#SlotNumTx9=./peak_txconfig_0.cfg
+
+#SlotNumRx0=./peak_rxconfig_0.cfg
+#SlotNumRx1=./peak_rxconfig_0.cfg
+#SlotNumRx2=./peak_rxconfig_0.cfg
+#SlotNumRx3=./peak_rxconfig_2.cfg
+#SlotNumRx4=./peak_rxconfig_1.cfg
+
+#SlotNumRx5=./peak_rxconfig_0.cfg
+#SlotNumRx6=./peak_rxconfig_0.cfg
+#SlotNumRx7=./peak_rxconfig_0.cfg
+#SlotNumRx8=./peak_rxconfig_3.cfg
+#SlotNumRx9=./peak_rxconfig_1.cfg
+
+
+#TODO:
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+#antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+#antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+#antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+#antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+#antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+#antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+#antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+#antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+#antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+#antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+#antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+#antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+#antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+#antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+#antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+#antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+extType=1
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,24,0,0,9,1,1
+ExtBfwDl1=2,24,0,0,9,1,1
+ExtBfwDl2=2,24,0,0,9,1,1
+ExtBfwDl3=2,24,0,0,9,1,1
+ExtBfwDl4=2,24,0,0,9,1,1
+ExtBfwDl5=2,17,0,0,9,1,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,24,0,0,9,1,1
+ExtBfwUl1=2,24,0,0,9,1,1
+ExtBfwUl2=2,24,0,0,9,1,1
+ExtBfwUl3=2,24,0,0,9,1,1
+ExtBfwUl4=2,24,0,0,9,1,1
+ExtBfwUl5=2,17,0,0,9,1,1
+
+nPrbElemSrs=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=20 #core for main()
+systemCore=22
+ioCore=28 # core id
+#ioWorker=0x000000000 # mask [0- no workers]
+#ioWorker=0x8000040000 # mask [0- no workers]
+ioWorker=0x060000000 # mask [0- no workers]
+#ioWorker=0x700000600
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+oXuCfgFile1=./peak_o_du.dat #O-DU1
+oXuCfgFile2=./peak_o_du.dat #O-DU2
+oXuCfgFile3=./peak_o_du.dat #O-DU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:01
+oXuRem3Mac1=00:11:22:33:03:11
+
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:21
+oXuRem3Mac3=00:11:22:33:03:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x200 # mask [0- no workers]
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_du.dat #O-DU0
+oXuCfgFile1=./peak_o_du.dat #O-DU1
+oXuCfgFile2=./peak_o_du.dat #O-DU2
+oXuCfgFile3=./peak_o_du.dat #O-DU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:01
+oXuRem3Mac1=00:11:22:33:03:11
+
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:21
+oXuRem3Mac3=00:11:22:33:03:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+#ioWorker=0x800000000 # mask [0- no workers]
+#ioWorker=0x800004000 # mask [0- no workers]
+#ioWorker=0xc000000 # second socket
+ioWorker=0x7E00 # second socket
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+oXuCfgFile1=./peak_o_ru.dat #O-RU1
+oXuCfgFile2=./peak_o_ru.dat #O-RU2
+oXuCfgFile3=./peak_o_ru.dat #O-RU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:00
+oXuRem3Mac1=00:11:22:33:03:10
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:20
+oXuRem3Mac3=00:11:22:33:03:30
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+mainCore=0 #core for main()
+systemCore=2
+ioCore=8 # core id
+ioWorker=0x7E00 # second socket
+
+dpdkMemorySize=16384
+iovaMode=0
+
+oXuNum=4 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./peak_o_ru.dat #O-RU0
+oXuCfgFile1=./peak_o_ru.dat #O-RU1
+oXuCfgFile2=./peak_o_ru.dat #O-RU2
+oXuCfgFile3=./peak_o_ru.dat #O-RU3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
+
+# remote O-XU 3 Eth Link 0
+oXuRem3Mac0=00:11:22:33:03:00
+oXuRem3Mac1=00:11:22:33:03:10
+# remote O-XU 3 Eth Link 1
+oXuRem3Mac2=00:11:22:33:03:20
+oXuRem3Mac3=00:11:22:33:03:30
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak
-#4%
-#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 %
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
mainCore=0 #core for main()
systemCore=2
-ioCore=21 # core id
-ioWorker=0x200000000000 # mask [0- no workers]
-dpdkMemorySize=8192
+ioCore=11 # core id
+ioWorker=0x80000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
-iovaMode=0
+dpdkMemorySize=8192
oXuNum=1 # numbers of O-RU connected to O-DU
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
-
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36%
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,48,0,14,0,1,1,9,1
-PrbElemDl1=48,48,0,14,1,1,1,9,1
-PrbElemDl2=96,48,0,14,2,1,1,9,1
-PrbElemDl3=144,48,0,14,3,1,1,9,1
-PrbElemDl4=192,48,0,14,4,1,1,9,1
-PrbElemDl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,24,0,0,9,1
-ExtBfwDl1=2,24,0,0,9,1
-ExtBfwDl2=2,24,0,0,9,1
-ExtBfwDl3=2,24,0,0,9,1
-ExtBfwDl4=2,24,0,0,9,1
-ExtBfwDl5=2,17,0,0,9,1
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,48,0,14,0,1,1,9,1
-PrbElemUl1=48,48,0,14,1,1,1,9,1
-PrbElemUl2=96,48,0,14,2,1,1,9,1
-PrbElemUl3=144,48,0,14,3,1,1,9,1
-PrbElemUl4=192,48,0,14,4,1,1,9,1
-PrbElemUl5=240,33,0,14,5,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,24,0,0,9,1
-ExtBfwUl1=2,24,0,0,9,1
-ExtBfwUl2=2,24,0,0,9,1
-ExtBfwUl3=2,24,0,0,9,1
-ExtBfwUl4=2,24,0,0,9,1
-ExtBfwUl5=2,17,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
ExtBfwUl1=2,25,0,0,9,1
nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
###########################################################
oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuCfgFile0=./config_file_o_du.dat #O-RU0
# remote O-XU 0 Eth Link 0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+
+mainCore=0 #core for main()
+systemCore=2
+ioCore=11 # core id
+ioWorker=0x80000000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du_icx.xml
+
+dpdkMemorySize=8192
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
-
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-ioCore=15
-# Eth 0
-duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
-duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
-
-# Eth 1
-duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
-duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
-ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MEC
-#28%
-#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36%
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
-nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,50,0,14,0,1,1,9,1
-PrbElemDl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,25,0,0,9,1
-ExtBfwDl1=2,25,0,0,9,1
-
-nPrbElemUl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,50,0,14,0,1,1,9,1
-PrbElemUl1=50,50,0,14,1,1,1,9,1
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,25,0,0,9,1
-ExtBfwUl1=2,25,0,0,9,1
-
-nPrbElemSrs=1
-PrbElemSrs0=0,273,0,14,0,0,1,9,0
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-ioCore=15 # core id
-ioWorker=0x800000000 # mask [0- no workers]
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-#ioWorker=0xE00000C00000 # mask [0- no workers]
-ioWorker=0x1C000000001800
-dpdkMemorySize=8192
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-#DL PRB / % Used RBs UL PRB / % Used RBs
-#66% 180 33% 90
-
-###########################################################
-##Section Settings
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MEC
-#28%
-#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MEC
-#28%
-#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36%
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
-dpdkMemorySize=8192
-#dpdkMemorySize=17408
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#Peak: 100 %
-#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 %
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=16
-max_sections_per_symbol=16
-
-nPrbElemDl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,18,0,14,5,1,1,9,1
-PrbElemDl6=108,18,0,14,6,1,1,9,1
-PrbElemDl7=126,18,0,14,7,1,1,9,1
-PrbElemDl8=144,18,0,14,8,1,1,9,1
-PrbElemDl9=162,18,0,14,9,1,1,9,1
-PrbElemDl10=180,18,0,14,10,1,1,9,1
-PrbElemDl11=198,18,0,14,11,1,1,9,1
-PrbElemDl12=216,18,0,14,12,1,1,9,1
-PrbElemDl13=234,18,0,14,13,1,1,9,1
-PrbElemDl14=252,18,0,14,14,1,1,9,1
-PrbElemDl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,9,0,0,9,1
-ExtBfwDl6=2,9,0,0,9,1
-ExtBfwDl7=2,9,0,0,9,1
-ExtBfwDl8=2,9,0,0,9,1
-ExtBfwDl9=2,9,0,0,9,1
-ExtBfwDl10=2,9,0,0,9,1
-ExtBfwDl11=2,9,0,0,9,1
-ExtBfwDl12=2,9,0,0,9,1
-ExtBfwDl13=2,9,0,0,9,1
-ExtBfwDl14=2,9,0,0,9,1
-ExtBfwDl15=2,2,0,0,9,1
-
-
-nPrbElemUl=16
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,18,0,14,5,1,1,9,1
-PrbElemUl6=108,18,0,14,6,1,1,9,1
-PrbElemUl7=126,18,0,14,7,1,1,9,1
-PrbElemUl8=144,18,0,14,8,1,1,9,1
-PrbElemUl9=162,18,0,14,9,1,1,9,1
-PrbElemUl10=180,18,0,14,10,1,1,9,1
-PrbElemUl11=198,18,0,14,11,1,1,9,1
-PrbElemUl12=216,18,0,14,12,1,1,9,1
-PrbElemUl13=234,18,0,14,13,1,1,9,1
-PrbElemUl14=252,18,0,14,14,1,1,9,1
-PrbElemUl15=270,3,0,14,15,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,9,0,0,9,1
-ExtBfwUl6=2,9,0,0,9,1
-ExtBfwUl7=2,9,0,0,9,1
-ExtBfwUl8=2,9,0,0,9,1
-ExtBfwUl9=2,9,0,0,9,1
-ExtBfwUl10=2,9,0,0,9,1
-ExtBfwUl11=2,9,0,0,9,1
-ExtBfwUl12=2,9,0,0,9,1
-ExtBfwUl13=2,9,0,0,9,1
-ExtBfwUl14=2,9,0,0,9,1
-ExtBfwUl15=2,2,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
-dpdkMemorySize=8192
-#dpdkMemorySize=17408
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=2 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#NC
-#12%
-#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
-dpdkMemorySize=8192
-#dpdkMemorySize=17408
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MC
-#20%
-#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
-dpdkMemorySize=8192
-#dpdkMemorySize=17408
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MEC
-#28%
-#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28%
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#MEC
-#28%
-#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
-dpdkMemorySize=8192
-#dpdkMemorySize=17408
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36%
-
-
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-appMode=0 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
-DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
-UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
-UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-#EC
-#36%
-#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36%
-
-# This is simple configuration file. Use '#' sign for comments
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-appMode=1 # O-DU(0) | O-RU(1)
-xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
-ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
-antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
-antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
-antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
-
-#UEs
-muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
-DlLayersPerUe=1 #number of RX anntennas on DL UE side
-UlLayersPerUe=1 #number of TX anntennas on UL UE side
-
-
-##Numerology
-mu=1 #30Khz Sub Carrier Spacing
-
-ttiPeriod=500 # in us TTI period (30Khz default 500us)
-
-nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
-nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
-nDLFftSize=4096
-nULFftSize=4096
-
-nFrameDuplexType=1 # 0 - FDD 1 - TDD
-nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
-sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
-sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
-
-MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
- #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
-Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
-Gps_Beta=0
-
-numSlots=20 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
-prachConfigIndex=189
-
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
-
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
-###########################################################
-##Section Settings
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-max_sections_per_slot=12
-max_sections_per_symbol=12
-
-nPrbElemDl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemDl0=0,18,0,14,0,1,1,9,1
-PrbElemDl1=18,18,0,14,1,1,1,9,1
-PrbElemDl2=36,18,0,14,2,1,1,9,1
-PrbElemDl3=54,18,0,14,3,1,1,9,1
-PrbElemDl4=72,18,0,14,4,1,1,9,1
-PrbElemDl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwDl0=2,9,0,0,9,1
-ExtBfwDl1=2,9,0,0,9,1
-ExtBfwDl2=2,9,0,0,9,1
-ExtBfwDl3=2,9,0,0,9,1
-ExtBfwDl4=2,9,0,0,9,1
-ExtBfwDl5=2,5,0,0,9,1
-
-
-nPrbElemUl=6
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-# weight base beams
-PrbElemUl0=0,18,0,14,0,1,1,9,1
-PrbElemUl1=18,18,0,14,1,1,1,9,1
-PrbElemUl2=36,18,0,14,2,1,1,9,1
-PrbElemUl3=54,18,0,14,3,1,1,9,1
-PrbElemUl4=72,18,0,14,4,1,1,9,1
-PrbElemUl5=90,10,0,14,5,1,1,9,1
-
-# Extension Parameters for Beamforming weights
-# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
-ExtBfwUl0=2,9,0,0,9,1
-ExtBfwUl1=2,9,0,0,9,1
-ExtBfwUl2=2,9,0,0,9,1
-ExtBfwUl3=2,9,0,0,9,1
-ExtBfwUl4=2,9,0,0,9,1
-ExtBfwUl5=2,5,0,0,9,1
-
-
-nPrbElemSrs=11
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
-PrbElemSrs0=0,30,0,1,0,0,1,9,0
-PrbElemSrs1=30,30,0,1,0,0,1,9,0
-PrbElemSrs2=60,30,0,1,0,0,1,9,0
-PrbElemSrs3=90,30,0,1,0,0,1,9,0
-PrbElemSrs4=120,30,0,1,0,0,1,9,0
-PrbElemSrs5=150,30,0,1,0,0,1,9,0
-PrbElemSrs6=180,30,0,1,0,0,1,9,0
-PrbElemSrs7=210,30,0,1,0,0,1,9,0
-PrbElemSrs8=240,30,0,1,0,0,1,9,0
-PrbElemSrs9=270,30,0,1,0,0,1,9,0
-PrbElemSrs10=270,3,0,1,0,0,1,9,0
-
-
-###########################################################
-
-## control of IQ byte order
-iqswap=0 #do swap of IQ before send buffer to eth
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
-compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane
-##Debug
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
-
-##O-RU Settings
-totalBFWeights=64 # Total number of Beamforming Weights on RU
-
-Tadv_cp_dl=25 # in us
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
-#Reception Window C-plane DL
-T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
-
-#Reception Window C-plane UL
-T2a_min_cp_ul=285 # 285.42us
-T2a_max_cp_ul=429 # 428.12us
-
-#Reception Window U-plane
-T2a_min_up=71 # 71.35in us
-T2a_max_up=428 # 428.12us
-
-#Transmission Window
-Ta3_min=20 # in us
-Ta3_max=32 # in us
-
-###########################################################
-##O-DU Settings
-#C-plane
-#Transmission Window Fast C-plane DL
-T1a_min_cp_dl=285
-T1a_max_cp_dl=429
-
-##Transmission Window Fast C-plane UL
-T1a_min_cp_ul=285
-T1a_max_cp_ul=300
-
-#U-plane
-##Transmission Window
-T1a_min_up=96 #71 + 25 us
-T1a_max_up=196 #71 + 25 us
-
-#Reception Window
-Ta4_min=0 # in us
-Ta4_max=75 # in us
-###########################################################
-
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=0 # All O-DU(0) | O-RU(1)
-instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
-
-mainCore=0 #core for main()
-systemCore=2
-ioCore=10 # core id
-ioWorker=0x4000000000000 # mask [0- no workers]
-dpdkMemorySize=8192
-
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_du.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:01
-oXuRem0Mac1=00:11:22:33:00:11
-
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:21
-oXuRem0Mac3=00:11:22:33:00:31
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:01
-oXuRem1Mac1=00:11:22:33:01:11
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:21
-oXuRem1Mac3=00:11:22:33:01:31
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:01
-oXuRem2Mac1=00:11:22:33:02:11
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:21
-oXuRem2Mac3=00:11:22:33:02:31
+++ /dev/null
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-# This is simple configuration file. Use '#' sign for comments
-appMode=1 # All O-DU(0) | O-RU(1)
-instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
-mainCore=0 #core for main()
-systemCore=2
-ioCore=4 # core id
-ioWorker=0x3E0 # second socket
-dpdkMemorySize=8192
-#dpdkMemorySize=17408
-iovaMode=0
-
-oXuNum=1 # numbers of O-RU connected to O-DU
-
-oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
-oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
-oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs
-
-oXuCfgFile0=./config_file_o_ru.dat #O-RU0
-
-# remote O-XU 0 Eth Link 0
-oXuRem0Mac0=00:11:22:33:00:00
-oXuRem0Mac1=00:11:22:33:00:10
-# remote O-XU 0 Eth Link 1
-oXuRem0Mac2=00:11:22:33:00:20
-oXuRem0Mac3=00:11:22:33:00:30
-
-# remote O-XU 1 Eth Link 0
-oXuRem1Mac0=00:11:22:33:01:00
-oXuRem1Mac1=00:11:22:33:01:10
-# remote O-XU 1 Eth Link 1
-oXuRem1Mac2=00:11:22:33:01:20
-oXuRem1Mac3=00:11:22:33:01:30
-
-# remote O-XU 2 Eth Link 0
-oXuRem2Mac0=00:11:22:33:02:00
-oXuRem2Mac1=00:11:22:33:02:10
-# remote O-XU 2 Eth Link 1
-oXuRem2Mac2=00:11:22:33:02:20
-oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>6</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
+
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
oXuCfgFile0=./config_file_o_du.dat #O-RU0
#O-XU 0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndexLTE=189 # PRACH config index for LTE
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndexLTE=189 # PRACH config index for LTE
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_10mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_10mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_10mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_10mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_10mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_10mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_10mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_10mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_10mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_10mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_10mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_10mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_10mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_10mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_10mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_10mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_10mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_10mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_10mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_10mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_10mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_10mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_10mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_10mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_10mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_10mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_10mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_10mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_10mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_10mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_10mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_10mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_10mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_10mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_10mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_10mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_10mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_10mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_10mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_10mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
#PciBusAddoXu2Vf2=0000:51:02.2
#PciBusAddoXu2Vf3=0000:51:02.3
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
+
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_10mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_10mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_10mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_10mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_10mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_10mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_10mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_10mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_10mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_10mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_10mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_10mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_10mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_10mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_10mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_10mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_10mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_10mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_10mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_10mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_10mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_10mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_10mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_10mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_10mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_10mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_10mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_10mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_10mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_10mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_10mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_10mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_10mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_10mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_10mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_10mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_10mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_10mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_10mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_10mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
#PciBusAddoXu2Vf2=0000:51:02.2
#PciBusAddoXu2Vf3=0000:51:02.3
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
+
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC5=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC6=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC7=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC8=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC9=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC10=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC11=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC12=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC13=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC14=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC15=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC16=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC17=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC18=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC19=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC20=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC21=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC22=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC23=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC24=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC25=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC26=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC27=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC28=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC29=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC30=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC31=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC5=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC6=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC7=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC8=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC9=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC10=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC11=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC12=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC13=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC14=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC15=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC16=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC17=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC18=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC19=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC20=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC21=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC22=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC23=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC24=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC25=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC26=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC27=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC28=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC29=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC30=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC31=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
#PciBusAddoXu2Vf2=0000:51:02.2
#PciBusAddoXu2Vf3=0000:51:02.3
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
# remote O-XU 0 Eth Link 0
oXuRem0Mac0=00:11:22:33:00:01
oXuRem0Mac1=00:11:22:33:00:11
+
# remote O-XU 0 Eth Link 1
oXuRem0Mac2=00:11:22:33:00:21
oXuRem0Mac3=00:11:22:33:00:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_20mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_20mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_20mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_20mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_20mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_20mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_20mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_20mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_20mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_20mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_20mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_20mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_20mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_20mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_20mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_20mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_20mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_20mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_20mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_20mhz/ant_3.bin #CC5
+antC24=./usecase/dss/mu0_20mhz/ant_0.bin #CC6
+antC25=./usecase/dss/mu0_20mhz/ant_1.bin #CC6
+antC26=./usecase/dss/mu0_20mhz/ant_2.bin #CC6
+antC27=./usecase/dss/mu0_20mhz/ant_3.bin #CC6
+antC28=./usecase/dss/mu0_20mhz/ant_0.bin #CC7
+antC29=./usecase/dss/mu0_20mhz/ant_1.bin #CC7
+antC30=./usecase/dss/mu0_20mhz/ant_2.bin #CC7
+antC31=./usecase/dss/mu0_20mhz/ant_3.bin #CC7
+antC32=./usecase/dss/mu0_20mhz/ant_0.bin #CC8
+antC33=./usecase/dss/mu0_20mhz/ant_1.bin #CC8
+antC34=./usecase/dss/mu0_20mhz/ant_2.bin #CC8
+antC35=./usecase/dss/mu0_20mhz/ant_3.bin #CC8
+antC36=./usecase/dss/mu0_20mhz/ant_0.bin #CC9
+antC37=./usecase/dss/mu0_20mhz/ant_1.bin #CC9
+antC38=./usecase/dss/mu0_20mhz/ant_2.bin #CC9
+antC39=./usecase/dss/mu0_20mhz/ant_3.bin #CC9
+antC40=./usecase/dss/mu0_20mhz/ant_0.bin #CC10
+antC41=./usecase/dss/mu0_20mhz/ant_1.bin #CC10
+antC42=./usecase/dss/mu0_20mhz/ant_2.bin #CC10
+antC43=./usecase/dss/mu0_20mhz/ant_3.bin #CC10
+antC44=./usecase/dss/mu0_20mhz/ant_0.bin #CC11
+antC45=./usecase/dss/mu0_20mhz/ant_1.bin #CC11
+antC46=./usecase/dss/mu0_20mhz/ant_2.bin #CC11
+antC47=./usecase/dss/mu0_20mhz/ant_3.bin #CC11
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_20mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_20mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_20mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_20mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_20mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_20mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_20mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_20mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_20mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_20mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_20mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_20mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_20mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_20mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_20mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_20mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_20mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_20mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_20mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_20mhz/ant_3.bin #CC5
+antC24=./usecase/dss/mu0_20mhz/ant_0.bin #CC6
+antC25=./usecase/dss/mu0_20mhz/ant_1.bin #CC6
+antC26=./usecase/dss/mu0_20mhz/ant_2.bin #CC6
+antC27=./usecase/dss/mu0_20mhz/ant_3.bin #CC6
+antC28=./usecase/dss/mu0_20mhz/ant_0.bin #CC7
+antC29=./usecase/dss/mu0_20mhz/ant_1.bin #CC7
+antC30=./usecase/dss/mu0_20mhz/ant_2.bin #CC7
+antC31=./usecase/dss/mu0_20mhz/ant_3.bin #CC7
+antC32=./usecase/dss/mu0_20mhz/ant_0.bin #CC8
+antC33=./usecase/dss/mu0_20mhz/ant_1.bin #CC8
+antC34=./usecase/dss/mu0_20mhz/ant_2.bin #CC8
+antC35=./usecase/dss/mu0_20mhz/ant_3.bin #CC8
+antC36=./usecase/dss/mu0_20mhz/ant_0.bin #CC9
+antC37=./usecase/dss/mu0_20mhz/ant_1.bin #CC9
+antC38=./usecase/dss/mu0_20mhz/ant_2.bin #CC9
+antC39=./usecase/dss/mu0_20mhz/ant_3.bin #CC9
+antC40=./usecase/dss/mu0_20mhz/ant_0.bin #CC10
+antC41=./usecase/dss/mu0_20mhz/ant_1.bin #CC10
+antC42=./usecase/dss/mu0_20mhz/ant_2.bin #CC10
+antC43=./usecase/dss/mu0_20mhz/ant_3.bin #CC10
+antC44=./usecase/dss/mu0_20mhz/ant_0.bin #CC11
+antC45=./usecase/dss/mu0_20mhz/ant_1.bin #CC11
+antC46=./usecase/dss/mu0_20mhz/ant_2.bin #CC11
+antC47=./usecase/dss/mu0_20mhz/ant_3.bin #CC11
+
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_5mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_5mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_20mhz/ant_3.bin #CC0
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_5mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_5mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_5mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_5mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_5mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_5mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_5mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_5mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_5mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_5mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_5mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_5mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_5mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_5mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_5mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_5mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_5mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_5mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_5mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_5mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_5mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_5mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_5mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_5mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_5mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_5mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_5mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_5mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_5mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_5mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_5mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_5mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_5mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_5mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_5mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_5mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_5mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_5mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_5mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_5mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_5mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_5mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x6000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+#oXuCfgFile1=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=1 # All O-DU(0) | O-RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=15 # core id
+ioWorker=0x60000000 # mask [0- no workers]
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_ru.dat #O-RU0
+#oXuCfgFile1=./config_file_o_ru.dat
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:11.0
+#PciBusAddoXu0Vf1=0000:51:11.1
+#PciBusAddoXu0Vf2=0000:51:11.2
+#PciBusAddoXu0Vf3=0000:51:11.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:11.4
+#PciBusAddoXu1Vf1=0000:51:11.5
+#PciBusAddoXu1Vf2=0000:51:11.6
+#PciBusAddoXu1Vf3=0000:51:11.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:12.0
+#PciBusAddoXu2Vf1=0000:51:12.1
+#PciBusAddoXu2Vf2=0000:51:12.2
+#PciBusAddoXu2Vf3=0000:51:12.3
+
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:00
+oXuRem0Mac1=00:11:22:33:00:10
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:20
+oXuRem0Mac3=00:11:22:33:00:30
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:00
+oXuRem1Mac1=00:11:22:33:01:10
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:20
+oXuRem1Mac3=00:11:22:33:01:30
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:00
+oXuRem2Mac1=00:11:22:33:02:10
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:20
+oXuRem2Mac3=00:11:22:33:02:30
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>5</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>6</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0,0,0,0,0,0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_5mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_5mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_5mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_5mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_5mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_5mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_5mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_5mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_5mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_5mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_5mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_5mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_5mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_5mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_5mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_5mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_5mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_5mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_5mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_5mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_5mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G-NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-4] DDDSU, for S it's 10:2:2
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+#ioSleep=1
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/dss/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/dss/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/dss/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/dss/mu0_5mhz/ant_3.bin #CC0
+antC4=./usecase/dss/mu0_5mhz/ant_0.bin #CC1
+antC5=./usecase/dss/mu0_5mhz/ant_1.bin #CC1
+antC6=./usecase/dss/mu0_5mhz/ant_2.bin #CC1
+antC7=./usecase/dss/mu0_5mhz/ant_3.bin #CC1
+antC8=./usecase/dss/mu0_5mhz/ant_0.bin #CC2
+antC9=./usecase/dss/mu0_5mhz/ant_1.bin #CC2
+antC10=./usecase/dss/mu0_5mhz/ant_2.bin #CC2
+antC11=./usecase/dss/mu0_5mhz/ant_3.bin #CC2
+antC12=./usecase/dss/mu0_5mhz/ant_0.bin #CC3
+antC13=./usecase/dss/mu0_5mhz/ant_1.bin #CC3
+antC14=./usecase/dss/mu0_5mhz/ant_2.bin #CC3
+antC15=./usecase/dss/mu0_5mhz/ant_3.bin #CC3
+antC16=./usecase/dss/mu0_5mhz/ant_0.bin #CC4
+antC17=./usecase/dss/mu0_5mhz/ant_1.bin #CC4
+antC18=./usecase/dss/mu0_5mhz/ant_2.bin #CC4
+antC19=./usecase/dss/mu0_5mhz/ant_3.bin #CC4
+antC20=./usecase/dss/mu0_5mhz/ant_0.bin #CC5
+antC21=./usecase/dss/mu0_5mhz/ant_1.bin #CC5
+antC22=./usecase/dss/mu0_5mhz/ant_2.bin #CC5
+antC23=./usecase/dss/mu0_5mhz/ant_3.bin #CC5
+
+## RACH TODO: update for PRACH
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+###########################################################
+##Section Settings
+dssEnable=1 # Enable (1)| disable (0) - flag to enable extType-9
+dssPeriod=5
+technology=1,1,0,0,1 #Consider each comma separated value as a technology(NR/LTE) for a given slot. 1-NR, 0-LTE. this pattern repeats after every dssPeriod
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+# This is simple configuration file. Use '#' sign for comments
+appMode=0 # All O-DU(0) | O-RU(1)
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
+
+oXuNum=1 # numbers of O-RU connected to O-DU
+
+oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU
+oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link)
+
+oXuCfgFile0=./config_file_o_du.dat #O-RU0
+
+#O-XU 0
+#PciBusAddoXu0Vf0=0000:51:01.0
+#PciBusAddoXu0Vf1=0000:51:01.1
+#PciBusAddoXu0Vf2=0000:51:01.2
+#PciBusAddoXu0Vf3=0000:51:01.3
+
+#O-XU 1
+#PciBusAddoXu1Vf0=0000:51:01.4
+#PciBusAddoXu1Vf1=0000:51:01.5
+#PciBusAddoXu1Vf2=0000:51:01.6
+#PciBusAddoXu1Vf3=0000:51:01.7
+
+#O-XU 2
+#PciBusAddoXu2Vf0=0000:51:02.0
+#PciBusAddoXu2Vf1=0000:51:02.1
+#PciBusAddoXu2Vf2=0000:51:02.2
+#PciBusAddoXu2Vf3=0000:51:02.3
+
+# remote O-XU 0 Eth Link 0
+#oXuRem0Mac0=b4:96:91:94:de:40
+#oXuRem0Mac1=b4:96:91:94:de:41
+# remote O-XU 0 Eth Link 0
+oXuRem0Mac0=00:11:22:33:00:01
+oXuRem0Mac1=00:11:22:33:00:11
+
+# remote O-XU 0 Eth Link 1
+oXuRem0Mac2=00:11:22:33:00:21
+oXuRem0Mac3=00:11:22:33:00:31
+
+# remote O-XU 1 Eth Link 0
+oXuRem1Mac0=00:11:22:33:01:01
+oXuRem1Mac1=00:11:22:33:01:11
+# remote O-XU 1 Eth Link 1
+oXuRem1Mac2=00:11:22:33:01:21
+oXuRem1Mac3=00:11:22:33:01:31
+
+# remote O-XU 2 Eth Link 0
+oXuRem2Mac0=00:11:22:33:02:01
+oXuRem2Mac1=00:11:22:33:02:11
+# remote O-XU 2 Eth Link 1
+oXuRem2Mac2=00:11:22:33:02:21
+oXuRem2Mac3=00:11:22:33:02:31
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC15=./usecase/lte_a/mu0_10mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/lte_a/mu0_10mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
antC15=./usecase/lte_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/lte_a/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
antC15=./usecase/lte_a/mu0_5mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
antC15=./usecase/lte_a/mu0_5mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,25,0,14,1,1,1,9,1
PrbElemDl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,25,0,0,9,1,1
+ExtBfwDl1=1,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,25,0,14,1,1,1,9,1
PrbElemUl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,25,0,0,9,1,1
+ExtBfwUl1=1,25,0,0,9,1,1
###########################################################
## control of IQ byte order
antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,25,0,14,1,1,1,9,1
PrbElemDl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,25,0,0,9,1,1
+ExtBfwDl1=1,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,25,0,14,1,1,1,9,1
PrbElemUl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,25,0,0,9,1,1
+ExtBfwUl1=1,25,0,0,9,1,1
###########################################################
## control of IQ byte order
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
+ioWorker=0x3000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,25,0,14,1,1,1,9,1
PrbElemDl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,25,0,0,9,1,1
+ExtBfwDl1=1,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,25,0,14,1,1,1,9,1
PrbElemUl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,25,0,0,9,1,1
+ExtBfwUl1=1,25,0,0,9,1,1
###########################################################
## control of IQ byte order
antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,25,0,14,1,1,1,9,1
PrbElemDl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,25,0,0,9,1,1
+ExtBfwDl1=1,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,25,0,14,1,1,1,9,1
PrbElemUl1=25,25,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,25,0,0,9,1,1
+ExtBfwUl1=1,25,0,0,9,1,1
###########################################################
## control of IQ byte order
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
+ioWorker=0x3000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,1,1,1,9,1
PrbElemDl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,50,0,14,1,1,1,9,1
PrbElemUl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
###########################################################
## control of IQ byte order
antC15=./usecase/lte_b/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,1,1,1,9,1
PrbElemDl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,50,0,14,1,1,1,9,1
PrbElemUl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
###########################################################
## control of IQ byte order
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
+ioWorker=0x3000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,1,1,1,9,1
PrbElemDl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,50,0,14,1,1,1,9,1
PrbElemUl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
###########################################################
## control of IQ byte order
antC15=./usecase/lte_b/mu0_20mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,50,0,14,1,1,1,9,1
PrbElemDl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=2,25,0,0,9,1,1
+ExtBfwDl1=2,25,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,50,0,14,1,1,1,9,1
PrbElemUl1=50,50,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=2,25,0,0,9,1,1
+ExtBfwUl1=2,25,0,0,9,1,1
###########################################################
## control of IQ byte order
appMode=0 # All O-DU(0) | O-RU(1)
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
-ioWorker=0x2000000 # mask [0- no workers]
+ioWorker=0x3000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,15,0,14,1,1,1,9,1
PrbElemDl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,15,0,0,9,1,1
+ExtBfwDl1=1,10,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,15,0,14,1,1,1,9,1
PrbElemUl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,15,0,0,9,1,1
+ExtBfwUl1=1,10,0,0,9,1,1
###########################################################
## control of IQ byte order
antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,15,0,14,1,1,1,9,1
PrbElemDl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,15,0,0,9,1,1
+ExtBfwDl1=1,10,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,15,0,14,1,1,1,9,1
PrbElemUl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,15,0,0,9,1,1
+ExtBfwUl1=1,10,0,0,9,1,1
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=../bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>0,0,0,0</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>1000, 1000, 1000, 1000</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
--- /dev/null
+<?xml version="1.0"?>
+<!--******************************************************************************-->
+<!-- -->
+<!-- Copyright (c) 2019 Intel. -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -->
+<!-- See the License for the specific language governing permissions and -->
+<!-- limitations under the License. -->
+<!-- -->
+<!--******************************************************************************-->
+<eBbuPoolConfig>
+ <version>21.03</version>
+
+ <eBbuPool>
+ <!-- Logical core index to pin eBbuPool maintain thread, non-real time -->
+ <eBbuPoolMainThreadCore>0</eBbuPoolMainThreadCore>
+ <!-- 1: Enable consumer thread sleep; 0: disable. Consumer thread is real-time thread -->
+ <eBbuPoolConsumerSleep>1</eBbuPoolConsumerSleep>
+ </eBbuPool>
+
+ <Queue>
+ <!-- Queue depth, maximum 1024 -->
+ <QueueDepth>1024</QueueDepth>
+ <!-- Queue numbers, maximum 8 -->
+ <QueueNum>4</QueueNum>
+ <!-- Queue context, maximum 8 -->
+ <QueuCtxNum>1</QueuCtxNum>
+ </Queue>
+
+ <Test>
+ <!-- Logical core index to pin the timer thread, which is a real-time thread -->
+ <TimerThreadCore>1</TimerThreadCore>
+ <!-- Number of control threads, which are responsible to enqueue trigger events for different cells -->
+ <CtrlThreadNum>1</CtrlThreadNum>
+ <!-- Logical core list for control threads, which are real-time threads -->
+ <CtrlThreadCoreList>6</CtrlThreadCoreList>
+ <!-- Number of cosumer threads, maximum 256 -->
+ <TestCoreNum>4</TestCoreNum>
+ <!-- The core index list of the consumer threads -->
+ <TestCoreList>16,48,17,49,18,50,19,51,20,52,4,44,5,45,22,23,24,25,6,26,7,27,8,28,9,29,10,30,11,31,12,32,13,33,13,34,15,35,16,36,17,37,18,38,19,39</TestCoreList>
+ <!-- Number of cells to test, maximum 40 -->
+ <TestCellNum>1</TestCellNum>
+ <!-- The frame format of each cell: 0, FDD; 1, DDDSU; 2, DDDDDDDSUU -->
+ <TestCellFrameFormat>1,1,1,1</TestCellFrameFormat>
+ <!-- The TTI of each cell, unit micro-second -->
+ <TestCellTti>500, 500, 500, 500</TestCellTti>
+ <!-- The number of events per cell, maximum 1000 -->
+ <TestCellEventNum>50, 50, 50, 50</TestCellEventNum>
+ </Test>
+
+ <Misc>
+ <!-- Mlog enable: 0 disable; 1 enable-->
+ <MlogEnable>1</MlogEnable>
+ </Misc>
+
+</eBbuPoolConfig>
+
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
#rachOffset=43 # RB offset for prach detection (see RIU spec)
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,15,0,14,1,1,1,9,1
PrbElemDl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,15,0,0,9,1,1
+ExtBfwDl1=1,10,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,15,0,14,1,1,1,9,1
PrbElemUl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,15,0,0,9,1,1
+ExtBfwUl1=1,10,0,0,9,1,1
###########################################################
## control of IQ byte order
antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
## RACH TODO: update for PRACH
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
prachConfigIndex=189
-srsEanble=0 # Enable (1)| disable (0) SRS
+srsEnable=0 # Enable (1)| disable (0) SRS
srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
###########################################################
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-
+extType=1
nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemDl0=0,15,0,14,1,1,1,9,1
PrbElemDl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwDl0=1,15,0,0,9,1,1
+ExtBfwDl1=1,10,0,0,9,1,1
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
PrbElemUl0=0,15,0,14,1,1,1,9,1
PrbElemUl1=15,10,0,14,2,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth, extType
+ExtBfwUl0=1,15,0,0,9,1,1
+ExtBfwUl1=1,10,0,0,9,1,1
###########################################################
## control of IQ byte order
instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
ioCore=5 # core id
ioWorker=0x2000000 # mask [0- no workers]
+oXuBbuCfgFile=./bbu_pool_cfg_o_du.xml
oXuNum=1 # numbers of O-RU connected to O-DU
LIBXRANSO=0
MLOG=0
COMMAND_LINE=
+SAMPLEAPP=0
echo Number of commandline arguments: $#
while [[ $# -ne 0 ]]
MLOG)
MLOG=1
;;
+ FWK)
+ FWK=1
+ ;;
+ SAMPLEAPP)
+ SAMPLEAPP=1
+ ;;
xclean)
COMMAND_LINE+=$key
COMMAND_LINE+=" "
MLOG=1
fi
-echo 'Building xRAN Library'
+if [ -z "$DIR_WIRELESS_FW" ]
+then
+ echo 'DIR_WIRELESS_FW folder is not set. Disable FWK (DIR_WIRELESS_FW='$DIR_WIRELESS_FW')'
+ FWK=0
+else
+ echo 'DIR_WIRELESS_FW folder is set. Enable FWK (DIR_WIRELESS_FW='$DIR_WIRELESS_FW')'
+ FWK=1
+fi
+
+ORU=1
+echo 'Building xRAN Library for O-RU'
+echo "LIBXRANSO = ${LIBXRANSO}"
+echo "MLOG = ${MLOG}"
+echo "FWK = ${FWK}"
+echo "ORU = ${ORU}"
+
+cd $XRAN_FH_LIB_DIR
+make $COMMAND_LINE MLOG=${MLOG} LIBXRANSO=${LIBXRANSO} ORU=${ORU}
+
+if [ "$SAMPLEAPP" -eq "1" ]
+then
+ echo 'Building xRAN O-RU Test Application'
+ cd $XRAN_FH_APP_DIR
+ make $COMMAND_LINE MLOG=${MLOG} FWK=${FWK} ORU=${ORU}
+else
+ echo 'Not building xRAN Test Application...'
+fi
+
+ORU=0
+echo 'Building xRAN Library for O-DU'
echo "LIBXRANSO = ${LIBXRANSO}"
echo "MLOG = ${MLOG}"
+echo "FWK = ${FWK}"
+echo "ORU = ${ORU}"
cd $XRAN_FH_LIB_DIR
-make $COMMAND_LINE MLOG=${MLOG} LIBXRANSO=${LIBXRANSO} #DEBUG=1 VERBOSE=1
+make $COMMAND_LINE MLOG=${MLOG} LIBXRANSO=${LIBXRANSO} ORU=${ORU}
-echo 'Building xRAN Test Application'
+if [ "$SAMPLEAPP" -eq "1" ]
+then
+ echo 'Building xRAN O-DU Test Application'
cd $XRAN_FH_APP_DIR
-make $COMMAND_LINE MLOG=${MLOG} #DEBUG=1 VERBOSE=1
+ make $COMMAND_LINE MLOG=${MLOG} FWK=${FWK} ORU=${ORU}
+else
+ echo 'Not building xRAN Test Application...'
+fi
if [ -z ${GTEST_ROOT+x} ];
then
##############################################################
# Tools configuration
##############################################################
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
CC := icc
CPP := icpc
AS := as
AR := ar
LD := icc
+else ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ CC := icx
+ CPP := icpx
+ AS := as
+ AR := llvm-ar
+ LD := icx
+else
+ $(error "Please define WIRELESS_SDK_TOOLCHAIN environment variable")
+endif
+
OBJDUMP := objdump
ifeq ($(SHELL),cmd.exe)
RM := rm -rf
endif
+ifeq ($(ORU),1)
+ PROJECT_NAME := libxran-oru
+ BUILDDIR := build-oru
+else
PROJECT_NAME := libxran
+ BUILDDIR := build
+endif
PROJECT_TYPE := lib
PROJECT_DIR := $(XRAN_DIR)/lib
-BUILDDIR := ./build
ifeq ($(XRAN_LIB_SO),)
PROJECT_BINARY := $(BUILDDIR)/$(PROJECT_NAME).a
endif
RTE_TARGET ?= x86_64-native-linux-icc
-
RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk)
+
API_DIR := $(PROJECT_DIR)/api
SRC_DIR := $(PROJECT_DIR)/src
ETH_DIR := $(PROJECT_DIR)/ethernet
$(SRC_DIR)/xran_common.c \
$(SRC_DIR)/xran_ul_tables.c \
$(SRC_DIR)/xran_frame_struct.c \
- $(SRC_DIR)/xran_app_frag.c \
$(SRC_DIR)/xran_dev.c \
$(SRC_DIR)/xran_rx_proc.c \
$(SRC_DIR)/xran_tx_proc.c \
-fPIC \
-Wall \
-Wimplicit-function-declaration \
- -g -O3 -wd1786 -mcmodel=large
+ -g -O3 -mcmodel=large
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
+CC_FLAGS += -wd1786 -restrict
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+CC_FLAGS += -march=icelake-server -mintrinsic-promote -Wno-unused-function -Wno-intrinsic-promote -Wno-error
+endif
+
+CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe \
+ -falign-functions=16 \
+ -Werror -Wno-unused-variable -std=c++14 -mcmodel=large -fPIC
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
+CPP_FLAGS += -fp-model fast=2 -no-prec-div -no-prec-sqrt -fast-transcendentals -restrict
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+CPP_FLAGS += -fp-model fast -march=icelake-server -mintrinsic-promote -Wno-unused-function -Wno-intrinsic-promote -Wno-error
+endif
-CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -no-prec-div \
- -no-prec-div -fp-model fast=2 -fPIC \
- -no-prec-sqrt -falign-functions=16 -fast-transcendentals \
- -Werror -Wno-unused-variable -std=c++14 -mcmodel=large
INC := -I$(API_DIR) -I$(ETH_DIR) -I$(SRC_DIR) -I$(RTE_INC)
DEF :=
DEF += -UMLOG_ENABLED
endif
+ifeq ($(ORU),1)
+ DEF += -DXRAN_O_RU_BUILD
+else
+ DEF += -UXRAN_O_RU_BUILD
+endif
#DEF += -DFCN_ADAPT
#DEF += -DFCN_1_2_6_EARLIER
AS_FLAGS :=
AR_FLAGS := rc
-PROJECT_OBJ_DIR := build/obj
+PROJECT_OBJ_DIR := $(BUILDDIR)/obj
CC_OBJS := $(patsubst %.c,%.o,$(CC_SRC))
CPP_OBJS := $(patsubst %.cpp,%.o,$(CPP_SRC))
AS_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(AS_OBJS))
#-qopt-report=5 -qopt-matmul -qopt-report-phase=all
-CPP_COMP := -O3 -DNDEBUG -xcore-avx512 -fPIE -restrict -fasm-blocks
-CPP_COMP_SNC := -O3 -DNDEBUG -march=icelake-server -fPIE -restrict -fasm-blocks
+CPP_COMP := -O3 -DNDEBUG -xcore-avx512 -fPIE -fasm-blocks
+CPP_COMP_SNC := -O3 -DNDEBUG -march=icelake-server -fPIE -fasm-blocks
CC_FLAGS_FULL := $(CC_FLAGS) $(INC) $(DEF)
CPP_FLAGS_FULL := $(CPP_FLAGS) $(CPP_COMP) $(INC) $(DEF)
CPP_FLAGS_FULL_SNC := $(CPP_FLAGS) $(CPP_COMP_SNC) $(INC) $(DEF)
#include "xran_pkt_cp.h"
#include "xran_transport.h"
-#define XRAN_MAX_SECTIONDB_CTX 2
+#define XRAN_MAX_SECTIONDB_CTX 4
-#define XRAN_MAX_NUM_EXTENSIONS XRAN_MAX_PRBS /* Maximum number of extensions in a section [up to 1 ext section per RB]*/
+#define XRAN_MAX_NUM_EXTENSIONS 10//XRAN_MAX_PRBS /* Maximum number of extensions in a section [up to 1 ext section per RB]*/
#define XRAN_MAX_NUM_UE 16 /* Maximum number of UEs/Lyaers */
#define XRAN_MAX_NUM_ANT_BF 64 /* Maximum number of beamforming antenna,
* could be defined as XRAN_MAX_ANTENNA_NR */
/**
* This structure contains the information to generate the section body of C-Plane message */
struct xran_section_info {
- uint8_t type; /* type of this section */
+ /** for U-plane */
+ struct xran_section_desc sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ int32_t freqOffset; /* X 24bits */
+ uint32_t startPrbc:9; /* X X X X X 9bits */
+ uint32_t numPrbc:9; /* X X X X X 8bits */ /* will be converted to zero if >255 */
+ uint32_t type:4; /* type of this section */
/* section type bit- */
/* 0 1 3 5 6 7 length */
- uint8_t startSymId; /* X X X X X X 4bits */
- uint8_t numSymbol; /* X X X X 4bits */
- uint8_t symInc; /* X X X X X 1bit */
- uint16_t id; /* X X X X X 12bits */
- uint16_t reMask; /* X X X X 12bits */
- uint16_t startPrbc; /* X X X X X 10bits */
- uint16_t numPrbc; /* X X X X X 8bits */ /* will be converted to zero if >255 */
- uint8_t rb; /* X X X X X 1bit */
- uint8_t compMeth; /* X X X 4bits */
- uint8_t iqWidth; /* X X X 4bits */
- uint8_t ef; /* X X X X 1bit */
- int32_t freqOffset; /* X 24bits */
+ uint32_t startSymId:4; /* X X X X X X 4bits */
+ uint32_t numSymbol:4; /* X X X X 4bits */
+ uint32_t res:2;
uint16_t beamId; /* X X 15bits */
uint16_t ueId; /* X X 15bits */
uint16_t regFactor; /* X 16bits */
- uint16_t pad0;
- /** for U-plane */
- struct xran_section_desc sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ uint16_t id; /* X X X X X 12bits */
+ uint16_t reMask; /* X X X X 12bits */
+
+ uint8_t symInc:1; /* X X X X X 1bit */
+ uint8_t rb:1; /* X X X X X 1bit */
+ uint8_t ef:1; /* X X X X 1bit */
+ uint8_t prbElemBegin:1; /* Flag to indicate beginning of a PRB element */
+ uint8_t prbElemEnd:1; /* Flag to indicate end of a PRB element */
+ uint8_t reserved:3;
+ uint8_t compMeth:4; /* X X X 4bits */
+ uint8_t iqWidth:4; /* X X X 4bits */
};
uint16_t bfwNumber; /**< number of bf weights in this section */
uint8_t bfwIqWidth;
uint8_t bfwCompMeth;
- int16_t *p_bfwIQ; /**< pointer to formed section extention */
+ int8_t *p_bfwIQ; /**< pointer to formed section extention */
int16_t bfwIQ_sz; /**< size of buffer with section extention information */
union {
uint8_t exponent;
struct xran_sectionext9_info {
uint8_t technology;
+ uint8_t reserved;
};
struct xran_sectionext10_info {
/**
* This structure to hold the information to generate the sections of C-Plane message */
struct xran_section_gen_info {
- struct xran_section_info info; /**< The information for section */
+ struct xran_section_info *info; /**< The information for section */
- uint32_t exDataSize; /**< The number of Extensions or type 6/7 data */
/** the array to store section extension */
struct xran_section_ext_gen_info exData[XRAN_MAX_NUM_EXTENSIONS];
+ uint32_t exDataSize; /**< The number of Extensions or type 6/7 data */
};
+
/**
* This structure to hold the information to generate a C-Plane message */
struct xran_cp_gen_params {
struct xran_sectionext4_info ext4;
struct xran_sectionext5_info ext5;
struct xran_sectionext6_info ext6;
+ struct xran_sectionext9_info ext9;
struct xran_sectionext10_info ext10;
struct xran_sectionext11_recv_info ext11;
} u;
struct xran_section_recv_info {
struct xran_section_info info; /**< The information for received section */
- int32_t numExts;
+ uint32_t numExts;
/** the array to store section extension */
struct xran_section_ext_recv_info exts[XRAN_MAX_NUM_EXTENSIONS];
};
uint8_t dir; /**< UL or DL */
uint8_t sectionType; /**< each section must have same type with this */
uint16_t numSections; /**< the number of sections received */
+ uint8_t numSetBFW; /**<Set of BFWs */
+ uint8_t ext1count; /**<Count set of extension type-1 BFWs*/
+ uint32_t tti; /**<micro-second*/
+ uint8_t dssPeriod; /**< DSS pattern period for LTE/NR */
+ uint8_t technology_arr[XRAN_MAX_DSS_PERIODICITY]; /**< technology array represents slot is LTE(0)/NR(1) */
+
struct xran_cp_header_params hdr;
/**< The information for C-Plane message header */
int32_t xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf,
struct xran_cp_gen_params *params,
uint8_t CC_ID, uint8_t Ant_ID,
- uint8_t seq_id);
+ uint8_t seq_id,
+ uint16_t start_sect_id);
int32_t xran_parse_cp_pkt(struct rte_mbuf *mbuf,
struct xran_cp_recv_params *result,
- struct xran_recv_packet_info *pkt_info);
+ struct xran_recv_packet_info *pkt_info, void* handle, uint32_t *mb_free);
int32_t xran_cp_init_sectiondb(void *pHandle);
int32_t xran_cp_free_sectiondb(void *pHandle);
int32_t xran_cp_add_section_info(void *pHandle,
uint8_t dir, uint8_t cc_id, uint8_t ruport_id,
uint8_t ctx_id, struct xran_section_info *info);
+
+struct xran_section_info *
+xran_cp_get_section_info_ptr(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id);
+
int32_t xran_cp_add_multisection_info(void *pHandle,
uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id,
struct xran_cp_gen_params *gen_info);
int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination buffer */
uint16_t ext1_dst_len, /**< dest buffer size */
int16_t *p_bfw_iq_src, /**< source buffer of IQs */
- uint16_t rbNumber, /**< number RBs to ext1 chain */
- uint16_t bfwNumber, /**< number of bf weights in this set of sections */
- uint8_t bfwiqWidth, /**< bit size of IQs */
- uint8_t bfwCompMeth); /**< compression method */
+ struct xran_prb_elm *p_pRbMapElm);
struct rte_mbuf *xran_attach_cp_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len,
struct rte_mbuf_ext_shared_info * p_share_data);
int32_t xran_cp_attach_ext_buf(struct rte_mbuf *mbuf, uint8_t *extbuf_start, uint16_t extbuf_len,
/** Macro to calculate Slot number */
#define XranGetSlotNum(tti, numSlotPerSfn) ((uint32_t)tti % ((uint32_t)numSlotPerSfn))
-#define XRAN_PORTS_NUM (4) /**< number of XRAN ports (aka O-RU|O-DU devices) supported */
+#define XRAN_PORTS_NUM (8) /**< number of XRAN ports (aka O-RU|O-DU devices) supported */
#define XRAN_ETH_PF_LINKS_NUM (4) /**< number of Physical Ethernet links per one O-RU|O-DU */
+#define XRAN_MAX_PRACH_ANT_NUM (4) /**< number of XRAN Prach ports supported */
+
+#if defined(XRAN_O_RU_BUILD)
+ #define XRAN_N_FE_BUF_LEN (20) /**< Number of TTIs (slots) */
+#else
#define XRAN_N_FE_BUF_LEN (20) /**< Number of TTIs (slots) */
+#endif
+
#define XRAN_MAX_SECTOR_NR (16) /**< Max sectors per XRAN port */
#define XRAN_MAX_ANTENNA_NR (16) /**< Max number of extended Antenna-Carriers:
a data flow for a single antenna (or spatial stream) for a single carrier in a single sector */
#define XRAN_MAX_PRBS (275) /**< Max of PRBs per CC per antanna for 5G NR */
#define XRAN_NUM_OF_SC_PER_RB (12) /**< Number of subcarriers per RB */
-#define XRAN_MAX_SECTIONS_PER_SLOT (24) /**< Max number of different sections in single slot (section may be equal to RB allocation for UE) */
+#define XRAN_MAX_DSS_PERIODICITY (15) /**< Max DSS pattern period */
+
+#define XRAN_MAX_SECTIONS_PER_SLOT (273) /**< Max number of different sections in single slot (section may be equal to RB allocation for UE) */
#define XRAN_MIN_SECTIONS_PER_SLOT (6) /**< Min number of different sections in single slot (section may be equal to RB allocation for UE) */
#define XRAN_MAX_SECTIONS_PER_SYM (XRAN_MAX_SECTIONS_PER_SLOT) /**< Max number of different sections in single slot (section may be equal to RB allocation for UE) */
#define XRAN_MIN_SECTIONS_PER_SYM (XRAN_MIN_SECTIONS_PER_SLOT) /**< Min number of different sections in single slot (section may be equal to RB allocation for UE) */
-#define XRAN_MAX_FRAGMENT (1) /**< Max number of fragmentations in single symbol */
+#define XRAN_MAX_FRAGMENT (4) /**< Max number of fragmentations in single symbol */
#define XRAN_MAX_SET_BFWS (64) /**< Assumed 64Ant, BFP 9bit with 9K jumbo frame */
#define XRAN_MAX_PKT_BURST (448+4) /**< 4x14x8 symbols per ms */
#define XRAN_VF_QUEUE_MAX (XRAN_MAX_ANTENNA_NR*2+XRAN_MAX_ANT_ARRAY_ELM_NR) /**< MAX number of HW queues for given VF */
+#define XRAN_HALF_CB_SYM 0 /**< Half of the Slot (offset +7) */
+#define XRAN_THREE_FOURTHS_CB_SYM 3 /**< 2/4 of the Slot (offset +7) */
+#define XRAN_FULL_CB_SYM 7 /**< Full Slot (offset +7) */
+#define XRAN_ONE_FOURTHS_CB_SYM 12 /**< 1/4 of the Slot (offset +7) */
+
#ifdef _XRAN_DEBUG
#define xran_log_dbg(fmt, ...) \
fprintf(stderr, \
int32_t one_vf_cu_plane; /**< 1 - C-plane and U-plane use one VF */
struct xran_ecpri_del_meas_cmn eowd_cmn[2];/**<ecpriowdmeasurementscommonsettingsforO-DUandO-RU*/
struct xran_ecpri_del_meas_port eowd_port[2][XRAN_VF_MAX]; /**< ecpri owd measurements per port variables for O-DU and O-RU */
+ int32_t bbu_offload; /**< enable packet handling on BBU cores */
};
/** XRAN spec section 3.1.3.1.6 ecpriRtcid / ecpriPcid define */
int8_t *p_o_ru_addr; /**< O-RU Ethernet Mac Address */
uint16_t totalBfWeights;/**< The total number of beamforming weights on RU for extensions */
+ int32_t mlogxranenable; /**< whether or not enable mlog during runtime 0:disable 1:enable */
+ uint8_t dlCpProcBurst; /**< When set to 1, dl cp processing will be done on single symbol. When set to 0, DL CP processing
+ will be spread across all allowed symbols and multiple cores to reduce burstiness */
};
struct xran_ext11_bfw_info {
uint16_t beamId; /* 15bits, needs to strip MSB */
uint8_t *pBFWs; /* external buffer pointer */
};
+
/** Beamforming waights for single stream for each PRBs given number of Antenna elements */
struct xran_cp_bf_weight{
int16_t nAntElmTRx; /**< num TRX for this allocation */
int16_t ext_section_sz; /**< extType section size */
- int8_t* p_ext_start; /**< pointer to start of buffer for full C-plane packet */
+ void* p_ext_start; /**< pointer to start of buffer for full C-plane packet */
int8_t* p_ext_section; /**< pointer to form extType */
+ uint8_t extType; /* This parameter determines whether to use extType-1 or 11, 1 - use ext1 and 0 - ext11 */
/* For ext 11 */
uint8_t bfwCompMeth; /* Compression Method for BFW */
uint8_t bfwIqWidth; /* Bitwidth of BFW */
/** section descriptor for given number of PRBs used on U-plane packet creation */
struct xran_section_desc {
- uint16_t section_id; /**< section id used for this element */
- uint16_t num_prbu;
- uint16_t start_prbu;
+ uint32_t section_id:9; /**< section id used for this element */
+ uint32_t num_prbu:9;
+ uint32_t start_prbu:9;
+ uint32_t reserved:5;
int16_t iq_buffer_offset; /**< Offset in bytes for the content of IQs with in main symbol buffer */
int16_t iq_buffer_len; /**< Length in bytes for the content of IQs with in main symbol buffer */
uint16_t ScaleFactor; /**< scale factor for modulation compression */
int16_t reMask; /**< 12-bit RE Mask for modulation compression */
int16_t BeamFormingType; /**< index based, weights based or attribute based beam forming*/
+ int16_t nSectId; /**< section id */
+ int16_t IsNewSect; /**< flag for new C-Plane section */
+ int16_t UP_nRBStart; /**< start RB of RB allocation for U-Plane */
+ int16_t UP_nRBSize; /**< start RB of RB allocation for U-Plane */
int16_t nSecDesc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /**< number of section descriptors per symbol */
- struct xran_section_desc * p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT][XRAN_MAX_FRAGMENT]; /**< section desctiptors to U-plane data given RBs */
+ struct xran_section_desc sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT][XRAN_MAX_FRAGMENT]; /**< section desctiptors to U-plane data given RBs */
struct xran_cp_bf_weight bf_weight; /**< beam forming information relevant for given RBs */
union {
uint16_t timeOffset;
int32_t freqOffset;
uint8_t eAxC_offset;
+ uint8_t nPrachConfIdxLTE;
};
/**< SRS configuration required for XRAN based FH */
struct xran_srs_config {
- uint16_t symbMask; /**< symbols used for SRS with in U/S slot [bits 0-13] */
+ uint16_t symbMask; /* deprecated */
+ uint16_t slot; /**< SRS slot within TDD period (special slot), for O-RU emulation */
+ uint8_t ndm_offset; /**< tti offset to delay the transmission of NDM SRS UP, for O-RU emulation */
+ uint16_t ndm_txduration; /**< symbol duration for NDM SRS UP transmisson, for O-RU emulation */
uint8_t eAxC_offset; /**< starting value of eAxC for SRS packets */
};
uint8_t enableCP; /**< enable C-plane */
uint8_t prachEnable; /**< enable PRACH */
uint8_t srsEnable; /**< enable SRS (Cat B specific) */
+ uint8_t srsEnableCp; /**< enable SRS Cp(Cat B specific) */
+ uint8_t SrsDelaySym; /**< enable SRS Cp(Cat B specific) */
uint8_t puschMaskEnable;/**< enable pusch mask> */
uint8_t puschMaskSlot; /**< specific which slot pusch channel masked> */
uint8_t cp_vlan_tag; /**< C-plane vlan tag */
uint16_t max_sections_per_slot; /**< M-Plane settings for section */
uint16_t max_sections_per_symbol; /**< M-Plane settings for section */
+ int32_t RunSlotPrbMapBySymbolEnable; /**< enable prb mapping by symbol with multisection*/
+
+ uint8_t dssEnable; /**< enable DSS (extension-9) */
+ uint8_t dssPeriod; /**< DSS pattern period for LTE/NR */
+ uint8_t technology[XRAN_MAX_DSS_PERIODICITY]; /**< technology array represents slot is LTE(0)/NR(1) */
};
/**
uint64_t rx_pusch_packets[XRAN_MAX_ANTENNA_NR];
uint64_t rx_prach_packets[XRAN_MAX_ANTENNA_NR];
uint64_t rx_srs_packets;
+ uint64_t rx_invalid_ext1_packets; /**< Counts the invalid extType-1 packets - valid for packets received from O-DU*/
+ uint64_t timer_missed_sym;
+ uint64_t timer_missed_slot;
};
/**
uint32_t nNumberOfElements; /**< The number of elements in the physical contiguous memory segment */
uint32_t nOffsetInBytes; /**< Offset in bytes to the start of the data in the physical contiguous
* memory segment */
- uint32_t nIsPhyAddr;
uint8_t *pData; /**< The data pointer is a virtual address */
void *pCtrl; /**< pointer to control section coresponding to data buffer */
+ void *pRing; /**< pointer to ring with prepared mbufs */
};
/**
*/
int32_t xran_bm_allocate_buffer(void * pHandle, uint32_t nPoolIndex, void **ppData, void **ppCtrl);
+/**
+ * @ingroup xran
+ *
+ * Function allocates buffer used between XRAN layer and PHY. In general case it's DPDK mbuf.
+ *
+ * @param pHandle
+ * Pointer to XRAN layer handle for given CC
+ * @param rng_name_prefix
+ * prefix of ring name
+ * @param cc_id
+ * Component Carrier ID
+ * @param buff_id
+ * Buffer id for given ring
+ * @param ant_id
+ * Antenna id for given ring
+ * @param symb_id
+ * Symbol id for given ring
+ * @param ppRing
+ * Pointer to pointer where to store address of internal DDPD ring
+ *
+ * @return
+ * 0 - on success
+ */
+int32_t xran_bm_allocate_ring(void * pHandle, const char *rng_name_prefix, uint16_t cc_id, uint16_t buff_id, uint16_t ant_id, uint16_t symb_id, void **ppRing);
+
/**
* @ingroup xran
*
*/
int32_t xran_reg_physide_cb(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id);
+/**
+ * @ingroup xran
+ *
+ * Function registers callback to XRAN layer. Function support callbacks align to OTA time. TTI even, half of slot,
+ * full slot with respect to PTP time.
+ *
+ * @param pHandle
+ * Pointer to XRAN layer handle for given CC
+ * @param Cb
+ * pointer to callback function
+ * @param cbParam
+ * pointer to Callback Function parameters
+ * @param skipTtiNum
+ * number of calls to be skipped before first call
+ * @param callback_to_phy_id
+ * call back time identification (see enum callback_to_phy_id)
+ * @param xran_port_id
+ * XRAN device ID
+ *
+ * @return
+ * 0 - in case of success
+ * -1 - in case of failure
+ */
+int32_t xran_reg_physide_cb_by_dev_id(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id, uint8_t xran_port_id);
+
/**
* @ingroup xran
*
* 0 - on success
*/
int32_t xran_set_debug_stop(int32_t value, int32_t count);
+
+/**
+ * @ingroup xran
+ *
+ * function initialize PRB map from config input
+ *
+ * @param p_PrbMapIn
+ * Input PRBmap from config
+ * @param p_PrbMapOut
+ * Output PRBmap
+ * @return
+ * 0 - on success
+ */
+int32_t xran_init_PrbMap_from_cfg(struct xran_prb_map* p_PrbMapIn, struct xran_prb_map* p_PrbMapOut, uint32_t mtu);
+
+/**
+ * @ingroup xran
+ *
+ * function initialize PRB map from config input
+ *
+ * @param p_PrbMapIn
+ * Input PRBmap from config for Rx
+ * @param p_PrbMapOut
+ * Output PRBmap
+ * @return
+ * 0 - on success
+ */
+
+int32_t xran_init_PrbMap_from_cfg_for_rx(struct xran_prb_map* p_PrbMapIn, struct xran_prb_map* p_PrbMapOut, uint32_t mtu);
+
+int32_t xran_get_num_prb_elm(struct xran_prb_map* p_PrbMapIn, uint32_t mtu);
+
+/**
+ * @ingroup xran
+ *
+ * function initialize PRB map from config input by symbol
+ *
+ * @param p_PrbMapIn
+ * Input PRBmap from config
+ * @param p_PrbMapOut
+ * Output PRBmap
+ * @return
+ * 0 - on success
+ */
+int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, struct xran_prb_map* p_PrbMapOut, uint32_t mtu, uint32_t xran_max_prb);
+
+/**
+ * @ingroup xran
+ *
+ * Function prepares DL U-plane packets for symbol for O-RAN FH. Enques resulting packet to ring for TX at appropriate time
+ *
+ * @param pHandle
+ * pointer to O-RU port structure
+ * @return
+ * 0 - on success
+ */
+int32_t xran_prepare_up_dl_sym(uint16_t xran_port_id, uint32_t nSlotIdx, uint32_t nCcStart, uint32_t nCcNum, uint32_t nSymMask, uint32_t nAntStart,
+ uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum);
+/**
+ * @ingroup xran
+ *
+ * Function prepares DL C-plane packets for slot for O-RAN FH. Enques resulting packet to ring for TX at appropriate time
+ *
+ * @param pHandle
+ * pointer to O-RU port structure
+ * @return
+ * 0 - on success
+ */
+int32_t xran_prepare_cp_dl_slot(uint16_t xran_port_id, uint32_t nSlotIdx, uint32_t nCcStart, uint32_t nCcNum, uint32_t nSymMask, uint32_t nAntStart,
+ uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum);
+
+/**
+ * @ingroup xran
+ *
+ * Function prepares UL C-plane packets for slot for O-RAN FH. Enques resulting packet to ring for TX at appropriate time
+ *
+ * @param pHandle
+ * pointer to O-RU port structure
+ * @return
+ * 0 - on success
+ */
+int32_t xran_prepare_cp_ul_slot(uint16_t xran_port_id, uint32_t nSlotIdx, uint32_t nCcStart, uint32_t nCcNum, uint32_t nSymMask, uint32_t nAntStart,
+ uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum);
+
#ifdef __cplusplus
}
#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2020 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief This file provides public interface to xRAN Front Haul layer implementation as defined in the
+ * ORAN-WG4.CUS.0-v01.00 spec. Implementation specific to
+ * (O-DU): a logical node that includes the eNB/gNB functions as
+ * listed in section 2.1 split option 7-2x.
+ *
+ *
+ * @file xran_fh_o_ru.h
+ * @ingroup group_lte_source_xran
+ * @author Intel Corporation
+ *
+ **/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <sys/types.h>
+#include <sys/queue.h>
+#include <netinet/in.h>
+#include <setjmp.h>
+#include <stdarg.h>
+#include <ctype.h>
+#include <errno.h>
+#include <getopt.h>
+#include <unistd.h>
+#include "xran_fh_o_du.h"
+
+/**
+ * @ingroup
+ *
+ * Function configures TX and RX output buffers
+ *
+ * @param pHandle
+ * Pointer to XRAN layer handle for given CC
+ * @param pSrcRxCpBuffer
+ * list of memory buffers to use to deliver BFWs from XRAN layer to the application for Validation
+ * @param pSrcTxCpBuffer
+ * list of memory buffers to use to deliver BFWs from XRAN layer to the application for Validation
+ * @param xran_transport_callback_fn pCallback
+ * Callback function to call with arrival of C-Plane packets for given CC
+ * @param pCallbackTag
+ * Parameters of Callback function
+ *
+ * @return
+ * 0 - on success
+ * -1 - on error
+ */
+
+int32_t xran_5g_bfw_config(void * pHandle, struct xran_buffer_list *pSrcRxCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN],
+ struct xran_buffer_list *pSrcTxCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN],
+ xran_transport_callback_fn pCallback,
+ void *pCallbackTag);
+
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
#define PID_XRAN_BBDEV_UL_POLL 53
#define PID_XRAN_BBDEV_UL_POLL_DISPATCH 54
-#define PID_TTI_TIMER 2100
-#define PID_TTI_CB 2101
-
-#define PID_SYM_TIMER 2102
-//#define PID_GNB_PROC_TIMING_TIMEOUT 2103
-
-#define PID_TIME_SYSTIME_POLL 2104
-#define PID_TIME_SYSTIME_STOP 2105
-#define PID_TIME_ARM_TIMER 2106
-#define PID_TIME_ARM_TIMER_DEADLINE 2107
-#define PID_TIME_ARM_USER_TIMER_DEADLINE 2108
-
-
-#define PID_RADIO_FREQ_RX_PKT 2400
-#define PID_RADIO_RX_STOP 2401
-#define PID_RADIO_RX_UL_IQ 2402
-#define PID_RADIO_PRACH_PKT 2403
-#define PID_RADIO_FE_COMPRESS 2404
-#define PID_RADIO_FE_DECOMPRESS 2405
-#define PID_RADIO_TX_BYPASS_PROC 2406
-#define PID_RADIO_ETH_TX_BURST 2407
-#define PID_RADIO_TX_DL_IQ 2408
-#define PID_RADIO_RX_VALIDATE 2409
-
-#define PID_RADIO_RX_IRQ_ON 2410
-#define PID_RADIO_RX_IRQ_OFF 2411
-#define PID_RADIO_RX_EPOLL_WAIT 2412
-
-#define PID_RADIO_TX_LTEMODE_PROC 2413
-#define PID_RADIO_RX_LTEMODE_PROC 2414
-
-#define PID_RADIO_TX_PLAY_BACK_IQ 2415
-
-#define PID_PROCESS_TX_SYM 2416
-#define PID_DISPATCH_TX_SYM 2417
-#define PID_PREPARE_TX_PKT 2418
-#define PID_ATTACH_EXT_BUF 2419
-#define PID_ETH_ENQUEUE_BURST 2420
-
-#define PID_CP_DL_CB 2500
-#define PID_CP_UL_CB 2501
-#define PID_UP_DL_CB 2502
-#define PID_SYM_OTA_CB 2503
-#define PID_TTI_CB_TO_PHY 2504
-#define PID_HALF_SLOT_CB_TO_PHY 2505
-#define PID_FULL_SLOT_CB_TO_PHY 2506
-#define PID_UP_UL_HALF_DEAD_LINE_CB 2507
-#define PID_UP_UL_FULL_DEAD_LINE_CB 2508
-#define PID_UP_UL_USER_DEAD_LINE_CB 2509
-
-#define PID_PROCESS_UP_PKT 2600
-#define PID_PROCESS_UP_PKT_SRS 2601
-#define PID_PROCESS_UP_PKT_PARSE 2602
-#define PID_PROCESS_CP_PKT 2700
-#define PID_PROCESS_DELAY_MEAS_PKT 2800
-
+#define PID_TTI_TIMER 3100
+#define PID_TTI_CB 3101
+
+#define PID_SYM_TIMER 3102
+//#define PID_GNB_PROC_TIMING_TIMEOUT 3103
+
+#define PID_TIME_SYSTIME_POLL 3104
+#define PID_TIME_SYSTIME_STOP 3105
+#define PID_TIME_ARM_TIMER 3106
+
+#define PID_RADIO_FREQ_RX_PKT 3107
+#define PID_RADIO_RX_STOP 3108
+#define PID_RADIO_RX_UL_IQ 3109
+#define PID_RADIO_PRACH_PKT 3110
+#define PID_RADIO_FE_COMPRESS 3111
+#define PID_RADIO_FE_DECOMPRESS 3112
+#define PID_RADIO_TX_BYPASS_PROC 3113
+#define PID_RADIO_ETH_TX_BURST 3114
+#define PID_RADIO_TX_DL_IQ 3115
+#define PID_RADIO_RX_VALIDATE 3116
+#define PID_RADIO_RX_IRQ_ON 3117
+#define PID_RADIO_RX_IRQ_OFF 3118
+#define PID_RADIO_RX_EPOLL_WAIT 3119
+#define PID_RADIO_TX_LTEMODE_PROC 3120
+#define PID_RADIO_RX_LTEMODE_PROC 3121
+#define PID_RADIO_TX_PLAY_BACK_IQ 3122
+#define PID_PROCESS_TX_SYM 3123
+#define PID_DISPATCH_TX_SYM 3124
+#define PID_PREPARE_TX_PKT 3125
+#define PID_ATTACH_EXT_BUF 3126
+#define PID_ETH_ENQUEUE_BURST 3127
+
+#define PID_CP_DL_CB 3128
+#define PID_CP_UL_CB 3129
+#define PID_UP_DL_CB 3130
+#define PID_SYM_OTA_CB 3131
+#define PID_TTI_CB_TO_PHY 3132
+#define PID_HALF_SLOT_CB_TO_PHY 3133
+#define PID_FULL_SLOT_CB_TO_PHY 3134
+#define PID_UP_UL_HALF_DEAD_LINE_CB 3135
+#define PID_UP_UL_FULL_DEAD_LINE_CB 3136
+#define PID_UP_UL_USER_DEAD_LINE_CB 3137
+#define PID_PROCESS_UP_PKT 3140
+#define PID_PROCESS_UP_PKT_SRS 3141
+#define PID_PROCESS_UP_PKT_PARSE 3142
+#define PID_PROCESS_CP_PKT 3143
+#define PID_PROCESS_DELAY_MEAS_PKT 3144
+#define PID_UP_UL_ONE_FOURTHS_DEAD_LINE_CB 3145
+#define PID_UP_UL_THREE_FOURTHS_DEAD_LINE_CB 3146
+#define PID_UP_STATIC_SRS_DEAD_LINE_CB 3147
+
+#define PID_TIME_ARM_TIMER_DEADLINE 3150
+#define PID_TIME_ARM_USER_TIMER_DEADLINE 3151
+
+#define PID_REQUEUE_TX_SYM 3160
#ifdef __cplusplus
}
#define MLOG_FALSE ( 0 )
#define MLogOpen(a, b, c, d, e) MLOG_FALSE
+#define MLogSetup(a, b, c, d) MLOG_FALSE
#define MLogRestart(a) MLOG_FALSE
#define MLogPrint(a) MLOG_FALSE
#define MLogGetFileLocation() NULL
#endif /* MLOG_ENABLED */
+void MLogXRANTask(uint32_t taskid, uint64_t ticksstart, uint64_t ticksstop);
+uint64_t MLogXRANTick(void);
+
#ifdef __cplusplus
}
#endif /* #ifdef __cplusplus */
#define XRAN_MTU_DEFAULT RTE_ETHER_MTU
#define XRAN_APP_LAYER_MAX_SIZE_L2_DEFAUT (XRAN_MTU_DEFAULT - 8) /**< In case of L2 only solution, application layer maximum transmission unit size
is standard IEEE 802.3 Ethernet frame payload
- size (1500 bytes) \96 transport overhead (8 bytes) = 1492 bytes (or larger for Jumbo frames) */
+ size (1500 bytes) ? transport overhead (8 bytes) = 1492 bytes (or larger for Jumbo frames) */
#ifndef OK
#define OK 0 /* Function executed correctly */
TimeStamp ts; /**< Table 2-17 Octet 7-16 */
int64_t CompensationValue; /**< Table 2-17 Octet 17 */
uint8_t DummyBytes[1400]; /**< Table 2-17 Octet 25 */
-} __rte_packed;
+} /*__rte_packed*/;
/**
******************************************************************************
{
union xran_ecpri_cmn_hdr cmnhdr;
struct xran_ecpri_delay_meas_pl deMeasPl;
-} __rte_packed;
+ }/*__rte_packed*/;
/**
******************************************************************************
* The structure does not need the conversion of byte order.
*/
struct xran_cp_radioapp_section_ext9 {
+ uint8_t reserved;
+ uint8_t technology; /**< 5.4.7.9.1 technology (interface name) */
+ uint8_t extLen; /**< 5.4.6.3 extension length, in 32bits words */
uint8_t extType:7; /**< 5.4.6.1 extension type */
uint8_t ef:1; /**< 5.4.6.2 extension flag */
- uint8_t extLen; /**< 5.4.6.3 extension length, in 32bits words */
- uint8_t technology; /**< 5.4.7.9.1 technology (interface name) */
- uint8_t reserved;
} __attribute__((__packed__));
/**
uint8_t numBundPrb; /**< 5.4.7.11.3 Number of bundled PRBs per beamforming weights */
uint8_t bfwCompMeth:4; /**< 5.4.7.11.1 Beamforming weight Compression method (5.4.7.1.1) */
uint8_t bfwIqWidth:4; /**< 5.4.7.11.1 Beamforming weight IQ bit width (5.4.7.1.1) */
- } all_bits;
+ } __attribute__((__packed__)) all_bits;
struct{
uint32_t data_field1;
uint16_t data_field2;
- }data_field;
+ } __attribute__((__packed__)) data_field;
/*
* bfwCompParam 5.4.7.11.2 beamforming weight compression parameter for PRB bundle
* beamId beam ID for PRB bundle (15bits)
long sleep_next_tick(long interval);
int timing_set_debug_stop(int value, int count);
int timing_get_debug_stop(void);
-inline uint64_t timing_get_current_second(void);
+uint64_t timing_get_current_second(void);
uint8_t timing_get_numerology(void);
int timing_set_numerology(uint8_t value);
uint32_t xran_max_ota_sym_idx(uint8_t numerlogy);
uint8_t *compMeth,
uint8_t *iqWidth);
-inline int xran_prepare_iq_symbol_portion(
+int xran_prepare_iq_symbol_portion(
struct rte_mbuf *mbuf,
const void *iq_data_start,
const enum xran_input_byte_order iq_buf_byte_order,
uint8_t Ant_ID,
uint8_t seq_id,
enum xran_comp_hdr_type staticEn,
- uint32_t do_copy);
+ uint32_t do_copy,
+ uint16_t num_sections,
+ uint16_t section_id_start,
+ uint16_t iq_offset);
#ifdef __cplusplus
}
#include <time.h>
#include <unistd.h>
#include <immintrin.h>
+#include <numa.h>
#include <rte_config.h>
#include <rte_common.h>
#include <rte_log.h>
/* Process vlan tag. Cut the ethernet header. Call the etherype handlers. */
int xran_ethdi_filter_packet(struct rte_mbuf *pkt_q[], uint16_t vf_id, uint16_t q_id, uint16_t num)
{
- int ret;
struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
- struct rte_ether_hdr* eth_hdr;
uint16_t port_id = ctx->vf2xran_port[vf_id];
struct xran_eaxc_info *p_cid = &ctx->vf_and_q2cid[vf_id][q_id];
- ret = xran_handle_ether(ETHER_TYPE_ECPRI, pkt_q, port_id, p_cid, num);
+ xran_handle_ether(ETHER_TYPE_ECPRI, pkt_q, port_id, p_cid, num);
return MBUF_FREE;
}
char socket_limit[32] = "--socket-limit=8192";
char ring_name[32] = "";
int32_t xran_port = -1;
- portid_t port_id;
queueid_t qi = 0;
- uint16_t count;
+ uint32_t cpu = 0;
+ uint32_t node = 0;
+
+ cpu = sched_getcpu();
+ node = numa_node_of_cpu(cpu);
char *argv[] = { name, core_mask, "-n2", iova_mode, socket_mem, socket_limit, "--proc-type=auto",
"--file-prefix", name, "-a0000:00:00.0", bbdev_wdev, bbdev_vdev};
-
if (io_cfg == NULL)
return 0;
if(io_cfg->bbdev_mode != XRAN_BBDEV_NOT_USED){
if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_ON){
// hw-accelerated bbdev
printf("hw-accelerated bbdev %s\n", io_cfg->bbdev_dev[0]);
-
snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-a%s", io_cfg->bbdev_dev[0]);
-
} else if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_OFF){
-
snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "%s", "--vdev=baseband_turbo_sw");
} else if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_SW){
printf("software and hw-accelerated bbdev %s\n", io_cfg->bbdev_dev[0]);
-
snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-a%s", io_cfg->bbdev_dev[0]);
-
snprintf(bbdev_vdev, RTE_DIM(bbdev_vdev), "%s", "--vdev=baseband_turbo_sw");
} else {
rte_panic("Cannot init DPDK incorrect [bbdev_mode %d]\n", io_cfg->bbdev_mode);
}
if (io_cfg->dpdkMemorySize){
- snprintf(socket_mem, RTE_DIM(socket_mem), "--socket-mem=%d", io_cfg->dpdkMemorySize);
- snprintf(socket_limit, RTE_DIM(socket_limit), "--socket-limit=%d", io_cfg->dpdkMemorySize);
+ printf("node %d\n", node);
+ if (node == 1){
+ snprintf(socket_mem, RTE_DIM(socket_mem), "--socket-mem=0,%d", io_cfg->dpdkMemorySize);
+ snprintf(socket_limit, RTE_DIM(socket_limit), "--socket-limit=0,%d", io_cfg->dpdkMemorySize);
+ } else {
+ snprintf(socket_mem, RTE_DIM(socket_mem), "--socket-mem=%d,0", io_cfg->dpdkMemorySize);
+ snprintf(socket_limit, RTE_DIM(socket_limit), "--socket-limit=%d,0", io_cfg->dpdkMemorySize);
+ }
}
if (io_cfg->core < 64)
struct rte_mbuf *mbufs[BURST_SIZE];
uint16_t dequeued, sent = 0;
uint32_t remaining;
- int i;
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
dequeued = rte_ring_dequeue_burst(r, (void **)mbufs, BURST_SIZE,
&remaining);
while (1) { /* When tx queue is full it is trying again till succeed */
sent += rte_eth_tx_burst(port, 0, &mbufs[sent], dequeued - sent);
if (sent == dequeued){
- MLogTask(PID_RADIO_ETH_TX_BURST, t1, MLogTick());
+ MLogXRANTask(PID_RADIO_ETH_TX_BURST, t1, MLogXRANTick());
return remaining;
}
}
const uint16_t rxed = rte_eth_rx_burst(port[port_id], qi, mbufs, BURST_RX_IO_SIZE);
if (rxed != 0){
unsigned enq_n = 0;
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
ctx->rx_vf_queue_cnt[port[port_id]][qi] += rxed;
enq_n = rte_ring_enqueue_burst(ctx->rx_ring[port_id][qi], (void*)mbufs, rxed, NULL);
if(rxed - enq_n)
rte_panic("error enq\n");
- MLogTask(PID_RADIO_RX_VALIDATE, t1, MLogTick());
+ MLogXRANTask(PID_RADIO_RX_VALIDATE, t1, MLogXRANTick());
}
}
/* TX */
- const uint16_t sent = xran_tx_from_ring(port[port_id], ctx->tx_ring[port_id]);
+ xran_tx_from_ring(port[port_id], ctx->tx_ring[port_id]);
/* One way Delay Measurements */
if ((cfg->eowd_cmn[cfg->id].owdm_enable != 0) && (cfg->eowd_cmn[cfg->id].measVf == port_id))
{
//rte_timer_manage();
for (port_id = 0; port_id < XRAN_VF_MAX && port_id < ctx->io_cfg.num_vfs; port_id++){
- struct rte_mbuf *mbufs[BURST_RX_IO_SIZE];
if(port[port_id] == 0xFF)
return 0;
/* TX */
- const uint16_t sent = xran_tx_from_ring(port[port_id], ctx->tx_ring[port_id]);
+ xran_tx_from_ring(port[port_id], ctx->tx_ring[port_id]);
if (XRAN_STOPPED == xran_if_current_state)
return -1;
rte_timer_manage();
+ if (XRAN_RUNNING != xran_if_current_state)
+ return 0;
+
for (port_id = 0; port_id < XRAN_VF_MAX && port_id < ctx->io_cfg.num_vfs; port_id++){
struct rte_mbuf *mbufs[BURST_RX_IO_SIZE];
if(port[port_id] == 0xFF)
const uint16_t rxed = rte_eth_rx_burst(port[port_id], qi, mbufs, BURST_RX_IO_SIZE);
if (rxed != 0){
unsigned enq_n = 0;
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
ctx->rx_vf_queue_cnt[port[port_id]][qi] += rxed;
enq_n = rte_ring_enqueue_burst(ctx->rx_ring[port_id][qi], (void*)mbufs, rxed, NULL);
if(rxed - enq_n)
rte_panic("error enq\n");
- MLogTask(PID_RADIO_RX_VALIDATE, t1, MLogTick());
+ MLogXRANTask(PID_RADIO_RX_VALIDATE, t1, MLogXRANTick());
}
}
if (XRAN_STOPPED == xran_if_current_state)
};
static char *const entity_names[] = {
- "ORAN O-DU sim app",
- "ORAN O-RU sim app"
+ (char *)"ORAN O-DU sim app",
+ (char *)"ORAN O-RU sim app"
};
typedef int (*PROCESS_CB)(void * arg);
struct rte_mempool *socket_direct_pool = NULL;
struct rte_mempool *socket_indirect_pool = NULL;
-struct rte_mempool *_eth_mbuf_pool_vf_rx[16][RTE_MAX_QUEUES_PER_PORT] = {NULL};
+struct rte_mempool *_eth_mbuf_pool_vf_rx[16][RTE_MAX_QUEUES_PER_PORT] = {};
struct rte_mempool *_eth_mbuf_pool_vf_small[16] = {NULL};
void
uint16_t nb_rx_desc, unsigned int socket_id,
struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp)
{
- unsigned int i, mp_n;
int ret;
#ifndef RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT
#define RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT 0x00100000
void xran_init_port_mempool(int p_id, uint32_t mtu)
{
- int ret;
- int sock_id = rte_eth_dev_socket_id(p_id);
char rx_pool_name[32] = "";
- uint16_t data_room_size = MBUF_POOL_ELEMENT;
-
- if (mtu <= 1500) {
- data_room_size = MBUF_POOL_ELM_SMALL;
-}
snprintf(rx_pool_name, RTE_DIM(rx_pool_name), "%s_%d", "mempool_small_", p_id);
printf("[%d] %s\n", p_id, rx_pool_name);
if (_eth_mbuf_pool_vf_small[p_id] == NULL)
rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno));
-
-
}
/* Prepend ethernet header, possibly vlan tag. */
void xran_add_eth_hdr_vlan(struct rte_ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb)
{
+
/* add in the ethernet header */
struct rte_ether_hdr *h = (struct rte_ether_hdr *)rte_pktmbuf_mtod(mb, struct rte_ether_hdr*);
rte_eth_macaddr_get(mb->port, &h->s_addr); /* set source addr */
h->d_addr = *dst; /* set dst addr */
h->ether_type = rte_cpu_to_be_16(ethertype); /* ethertype too */
-
+#if 0
+ struct rte_ether_addr *s = &h->s_addr;
+ printf("src=%x:%x:%x:%x:%x:%x, dst=%x:%x:%x:%x:%x:%x\n", s->addr_bytes[0],
+ s->addr_bytes[1],
+ s->addr_bytes[2],
+ s->addr_bytes[3],
+ s->addr_bytes[4],
+ s->addr_bytes[5],
+ dst->addr_bytes[0],
+ dst->addr_bytes[1],
+ dst->addr_bytes[2],
+ dst->addr_bytes[3],
+ dst->addr_bytes[4],
+ dst->addr_bytes[5]
+ );
+#endif
#if defined(DPDKIO_DEBUG) && DPDKIO_DEBUG > 1
{
char dst[RTE_ETHER_ADDR_FMT_SIZE] = "(empty)";
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (c) 2020 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
-/**
- * @brief xRAN application fragmentation for U-plane packets
- *
- * @file xran_app_frag.c
- * @ingroup group_source_xran
- * @author Intel Corporation
- **/
-
-#include <stdio.h>
-#include <stddef.h>
-#include <errno.h>
-#include <immintrin.h>
-#include <rte_mbuf.h>
-#include <rte_memcpy.h>
-#include <rte_mempool.h>
-#include <rte_debug.h>
-
-#include "xran_app_frag.h"
-#include "xran_cp_api.h"
-#include "xran_pkt_up.h"
-#include "xran_printf.h"
-#include "xran_common.h"
-
-static inline void __fill_xranhdr_frag(struct xran_up_pkt_hdr *dst,
- const struct xran_up_pkt_hdr *src, uint16_t rblen_bytes,
- uint16_t rboff_bytes, uint16_t startPrbc, uint16_t numPrbc, uint32_t mf, uint8_t *seqid, uint8_t iqWidth)
-{
- struct data_section_hdr loc_data_sec_hdr;
- struct xran_ecpri_hdr loc_ecpri_hdr;
-
- rte_memcpy(dst, src, sizeof(*dst));
-
- dst->ecpri_hdr.ecpri_seq_id.bits.seq_id = (*seqid)++;
-
- print_dbg("sec [%d %d] sec %d mf %d g_sec %d\n",startPrbc, numPrbc, dst->ecpri_hdr.ecpri_seq_id.seq_id, mf, *seqid);
-
- loc_data_sec_hdr.fields.all_bits = rte_be_to_cpu_32(dst->data_sec_hdr.fields.all_bits);
-
- /* update RBs */
- loc_data_sec_hdr.fields.start_prbu = startPrbc + rboff_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth);
- loc_data_sec_hdr.fields.num_prbu = rblen_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth);
-
- print_dbg("sec [%d %d] pkt [%d %d] rboff_bytes %d rblen_bytes %d\n",startPrbc, numPrbc, loc_data_sec_hdr.fields.start_prbu, loc_data_sec_hdr.fields.num_prbu,
- rboff_bytes, rblen_bytes);
-
- dst->data_sec_hdr.fields.all_bits = rte_cpu_to_be_32(loc_data_sec_hdr.fields.all_bits);
-
- dst->ecpri_hdr.cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr) + rblen_bytes + xran_get_ecpri_hdr_size());
-}
-
-static inline void __fill_xranhdr_frag_comp(struct xran_up_pkt_hdr_comp *dst,
- const struct xran_up_pkt_hdr_comp *src, uint16_t rblen_bytes,
- uint16_t rboff_bytes, uint16_t startPrbc, uint16_t numPrbc, uint32_t mf, uint8_t *seqid, uint8_t iqWidth)
-{
- struct data_section_hdr loc_data_sec_hdr;
- struct xran_ecpri_hdr loc_ecpri_hdr;
-
- rte_memcpy(dst, src, sizeof(*dst));
-
- dst->ecpri_hdr.ecpri_seq_id.bits.seq_id = (*seqid)++;
-
- print_dbg("sec [%d %d] sec %d mf %d g_sec %d\n", startPrbc, numPrbc, dst->ecpri_hdr.ecpri_seq_id.seq_id, mf, *seqid);
-
- loc_data_sec_hdr.fields.all_bits = rte_be_to_cpu_32(dst->data_sec_hdr.fields.all_bits);
-
- /* update RBs */
- loc_data_sec_hdr.fields.start_prbu = startPrbc + rboff_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth);
- loc_data_sec_hdr.fields.num_prbu = rblen_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth);
-
- print_dbg("sec [%d %d] pkt [%d %d] rboff_bytes %d rblen_bytes %d\n",startPrbc, numPrbc, loc_data_sec_hdr.fields.start_prbu, loc_data_sec_hdr.fields.num_prbu,
- rboff_bytes, rblen_bytes);
-
- dst->data_sec_hdr.fields.all_bits = rte_cpu_to_be_32(loc_data_sec_hdr.fields.all_bits);
-
- dst->ecpri_hdr.cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr) + sizeof(struct data_section_compression_hdr) + rblen_bytes + xran_get_ecpri_hdr_size());
-}
-
-
-
-static inline void __free_fragments(struct rte_mbuf *mb[], uint32_t num)
-{
- uint32_t i;
- for (i = 0; i != num; i++)
- rte_pktmbuf_free(mb[i]);
-}
-
-/**
- * XRAN fragmentation.
- *
- * This function implements the application fragmentation of XRAN packets.
- *
- * @param pkt_in
- * The input packet.
- * @param pkts_out
- * Array storing the output fragments.
- * @param mtu_size
- * Size in bytes of the Maximum Transfer Unit (MTU) for the outgoing XRAN
- * datagrams. This value includes the size of the XRAN headers.
- * @param pool_direct
- * MBUF pool used for allocating direct buffers for the output fragments.
- * @param pool_indirect
- * MBUF pool used for allocating indirect buffers for the output fragments.
- * @return
- * Upon successful completion - number of output fragments placed
- * in the pkts_out array.
- * Otherwise - (-1) * <errno>.
- */
-int32_t
-xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */
- struct rte_mbuf **pkts_out,
- uint16_t nb_pkts_out,
- uint16_t mtu_size,
- struct rte_mempool *pool_direct,
- struct rte_mempool *pool_indirect,
- int16_t nRBStart, /**< start RB of RB allocation */
- int16_t nRBSize, /**< number of RBs used */
- uint8_t *seqid,
- uint8_t iqWidth,
- uint8_t isUdCompHdr)
-{
- struct rte_mbuf *in_seg = NULL;
- uint32_t out_pkt_pos = 0, in_seg_data_pos = 0;
- uint32_t more_in_segs;
- uint16_t fragment_offset, frag_size;
- uint16_t frag_bytes_remaining;
- struct eth_xran_up_pkt_hdr *in_hdr;
- struct xran_up_pkt_hdr *in_hdr_xran;
-
- struct eth_xran_up_pkt_hdr_comp *in_hdr_comp = NULL;
- struct xran_up_pkt_hdr_comp *in_hdr_xran_comp = NULL;
-
- int32_t eth_xran_up_headers_sz = 0;
- eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr);
-
- if(isUdCompHdr)
- eth_xran_up_headers_sz += sizeof(struct data_section_compression_hdr);
-
- /*
- * Ensure the XRAN payload length of all fragments is aligned to a
- * multiple of 48 bytes (1 RB with IQ of 16 bits each)
- */
- frag_size = ((mtu_size - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqWidth))*XRAN_PAYLOAD_1_RB_SZ(iqWidth);
-
- print_dbg("frag_size %d\n",frag_size);
-
- if(isUdCompHdr){
- in_hdr_comp = rte_pktmbuf_mtod(pkt_in, struct eth_xran_up_pkt_hdr_comp*);
- in_hdr_xran_comp = &in_hdr_comp->xran_hdr;
- if (unlikely(frag_size * nb_pkts_out <
- (uint16_t)(pkt_in->pkt_len - sizeof (struct xran_up_pkt_hdr_comp)))){
- print_err("-EINVAL\n");
- return -EINVAL;
- }
- }else {
- in_hdr = rte_pktmbuf_mtod(pkt_in, struct eth_xran_up_pkt_hdr *);
- in_hdr_xran = &in_hdr->xran_hdr;
- /* Check that pkts_out is big enough to hold all fragments */
- if (unlikely(frag_size * nb_pkts_out <
- (uint16_t)(pkt_in->pkt_len - sizeof (struct xran_up_pkt_hdr)))){
- print_err("-EINVAL\n");
- return -EINVAL;
- }
- }
-
- in_seg = pkt_in;
- if(isUdCompHdr){
- in_seg_data_pos = sizeof(struct eth_xran_up_pkt_hdr_comp);
- }else{
- in_seg_data_pos = sizeof(struct eth_xran_up_pkt_hdr);
- }
- out_pkt_pos = 0;
- fragment_offset = 0;
-
- more_in_segs = 1;
- while (likely(more_in_segs)) {
- struct rte_mbuf *out_pkt = NULL, *out_seg_prev = NULL;
- uint32_t more_out_segs;
- struct xran_up_pkt_hdr *out_hdr;
- struct xran_up_pkt_hdr_comp *out_hdr_comp;
-
- /* Allocate direct buffer */
- out_pkt = rte_pktmbuf_alloc(pool_direct);
- if (unlikely(out_pkt == NULL)) {
- print_err("pool_direct -ENOMEM\n");
- __free_fragments(pkts_out, out_pkt_pos);
- return -ENOMEM;
- }
-
- print_dbg("[%d] out_pkt %p\n",more_in_segs, out_pkt);
-
- /* Reserve space for the XRAN header that will be built later */
- //out_pkt->data_len = sizeof(struct xran_up_pkt_hdr);
- //out_pkt->pkt_len = sizeof(struct xran_up_pkt_hdr);
- if(isUdCompHdr){
- if(rte_pktmbuf_append(out_pkt, sizeof(struct xran_up_pkt_hdr_comp)) ==NULL){
- rte_panic("sizeof(struct xran_up_pkt_hdr)");
- }
- }else{
- if(rte_pktmbuf_append(out_pkt, sizeof(struct xran_up_pkt_hdr)) ==NULL){
- rte_panic("sizeof(struct xran_up_pkt_hdr)");
- }
- }
-
- frag_bytes_remaining = frag_size;
-
- out_seg_prev = out_pkt;
- more_out_segs = 1;
- while (likely(more_out_segs && more_in_segs)) {
- uint32_t len;
-#ifdef XRAN_ATTACH_MBUF
- struct rte_mbuf *out_seg = NULL;
-
- /* Allocate indirect buffer */
- print_dbg("Allocate indirect buffer \n");
- out_seg = rte_pktmbuf_alloc(pool_indirect);
- if (unlikely(out_seg == NULL)) {
- print_err("pool_indirect -ENOMEM\n");
- rte_pktmbuf_free(out_pkt);
- __free_fragments(pkts_out, out_pkt_pos);
- return -ENOMEM;
- }
-
- print_dbg("[%d %d] out_seg %p\n",more_out_segs, more_in_segs, out_seg);
- out_seg_prev->next = out_seg;
- out_seg_prev = out_seg;
-
- /* Prepare indirect buffer */
- rte_pktmbuf_attach(out_seg, in_seg);
-#endif
- len = frag_bytes_remaining;
- if (len > (in_seg->data_len - in_seg_data_pos)) {
- len = in_seg->data_len - in_seg_data_pos;
- }
-#ifdef XRAN_ATTACH_MBUF
- out_seg->data_off = in_seg->data_off + in_seg_data_pos;
- out_seg->data_len = (uint16_t)len;
- out_pkt->pkt_len = (uint16_t)(len +
- out_pkt->pkt_len);
- out_pkt->nb_segs += 1;
-#else
-{
- char* pChar = rte_pktmbuf_mtod(in_seg, char*);
- void *iq_src = (pChar + in_seg_data_pos);
- void *iq_dst = rte_pktmbuf_append(out_pkt, len);
-
- print_dbg("rte_pktmbuf_attach\n");
- if(iq_src && iq_dst)
- rte_memcpy(iq_dst, iq_src, len);
- else
- print_err("iq_src %p iq_dst %p\n len %d room %d\n", iq_src, iq_dst, len, rte_pktmbuf_tailroom(out_pkt));
-}
-#endif
- in_seg_data_pos += len;
- frag_bytes_remaining -= len;
-
- /* Current output packet (i.e. fragment) done ? */
- if (unlikely(frag_bytes_remaining == 0))
- more_out_segs = 0;
-
- /* Current input segment done ? */
- if (unlikely(in_seg_data_pos == in_seg->data_len)) {
- in_seg = in_seg->next;
- in_seg_data_pos = 0;
-
- if (unlikely(in_seg == NULL))
- more_in_segs = 0;
- }
- }
-
- /* Build the XRAN header */
- print_dbg("Build the XRAN header\n");
-
-
- if(isUdCompHdr){
- out_hdr_comp = rte_pktmbuf_mtod(out_pkt, struct xran_up_pkt_hdr_comp*);
- __fill_xranhdr_frag_comp(out_hdr_comp, in_hdr_xran_comp,
- (uint16_t)out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr_comp),
- fragment_offset, nRBStart, nRBSize, more_in_segs, seqid, iqWidth);
-
- fragment_offset = (uint16_t)(fragment_offset +
- out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr_comp));
- } else {
- out_hdr = rte_pktmbuf_mtod(out_pkt, struct xran_up_pkt_hdr *);
- __fill_xranhdr_frag(out_hdr, in_hdr_xran,
- (uint16_t)out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr),
- fragment_offset, nRBStart, nRBSize, more_in_segs, seqid, iqWidth);
-
- fragment_offset = (uint16_t)(fragment_offset +
- out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr));
- }
-
- //out_pkt->l3_len = sizeof(struct xran_up_pkt_hdr);
-
- /* Write the fragment to the output list */
- pkts_out[out_pkt_pos] = out_pkt;
- print_dbg("out_pkt_pos %d data_len %d pkt_len %d\n", out_pkt_pos, out_pkt->data_len, out_pkt->pkt_len);
- out_pkt_pos ++;
- //rte_pktmbuf_dump(stdout, out_pkt, 96);
- }
-
- return out_pkt_pos;
-}
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (c) 2020 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
-
-/**
- * @brief Header file for functions to perform application level fragmentation
- *
- * @file xran_app_frag.h
- * @ingroup group_source_xran
- * @author Intel Corporation
- **/
-
-#ifndef _XRAN_APP_FRAG_
-#define _XRAN_APP_FRAG_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdio.h>
-
-#include <rte_config.h>
-#include <rte_malloc.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_byteorder.h>
-
-#include "xran_fh_o_du.h"
-#include "xran_cp_api.h"
-
-int32_t
-xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */
- struct rte_mbuf **pkts_out,
- uint16_t nb_pkts_out,
- uint16_t mtu_size,
- struct rte_mempool *pool_direct,
- struct rte_mempool *pool_indirect,
- int16_t nRBStart, /**< start RB of RB allocation */
- int16_t nRBSize, /**< number of RBs used */
- uint8_t *seqid,
- uint8_t iqWidth,
- uint8_t isUdCompHdr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _XRAN_APP_FRAG_ */
-
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
inline void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
inline void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
{
void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
{
void
compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_16RB(dataIn, totShiftBits);
#pragma unroll(16)
for (int n = 0; n < 16; ++n)
{
void
compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i exponents = computeExponent_4RB(dataIn, totShiftBits);
#pragma unroll(4)
for (int n = 0; n < 4; ++n)
{
void xran_timer_arm(struct rte_timer *tim, void* arg, void *p_dev_ctx)
{
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx;
- uint64_t t3 = MLogTick();
+ uint64_t t3 = MLogXRANTick();
if (xran_if_current_state == XRAN_RUNNING){
rte_timer_cb_t fct = (rte_timer_cb_t)arg;
rte_timer_reset_sync(tim, 0, SINGLE, p_xran_dev_ctx->fh_init.io_cfg.timing_core, fct, p_dev_ctx);
}
- MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick());
+ MLogXRANTask(PID_TIME_ARM_TIMER, t3, MLogXRANTick());
}
void xran_timer_arm_cp_dl(struct rte_timer *tim, void* arg, void *p_dev_ctx)
{
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx;
- uint64_t t3 = MLogTick();
+ uint64_t t3 = MLogXRANTick();
unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_CP_DL, p_xran_dev_ctx);
rte_timer_cb_t fct = (rte_timer_cb_t)arg;
rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_dev_ctx);
}
- MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick());
+ MLogXRANTask(PID_TIME_ARM_TIMER, t3, MLogXRANTick());
}
void xran_timer_arm_cp_ul(struct rte_timer *tim, void* arg, void *p_dev_ctx)
{
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx;
- uint64_t t3 = MLogTick();
+ uint64_t t3 = MLogXRANTick();
unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_CP_UL, p_xran_dev_ctx);
rte_timer_cb_t fct = (rte_timer_cb_t)arg;
rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_dev_ctx);
}
- MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick());
+ MLogXRANTask(PID_TIME_ARM_TIMER, t3, MLogXRANTick());
}
void xran_timer_arm_for_deadline(struct rte_timer *tim, void* arg, void *p_dev_ctx)
{
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx;
- uint64_t t3 = MLogTick();
+ uint64_t t3 = MLogXRANTick();
unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_DEADLINE, p_xran_dev_ctx);
int32_t rx_tti;
- int32_t cc_id;
uint32_t nFrameIdx;
uint32_t nSubframeIdx;
uint32_t nSlotIdx;
rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_xran_dev_ctx);
}
- MLogTask(PID_TIME_ARM_TIMER_DEADLINE, t3, MLogTick());
+ MLogXRANTask(PID_TIME_ARM_TIMER_DEADLINE, t3, MLogXRANTick());
}
void xran_timer_arm_user_cb(struct rte_timer *tim, void* arg, void *p_ctx)
{
struct cb_user_per_sym_ctx* p_sym_cb_ctx = (struct cb_user_per_sym_ctx *)p_ctx;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_sym_cb_ctx->p_dev;
- uint64_t t3 = MLogTick();
+ uint64_t t3 = MLogXRANTick();
unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_SYM_CB, NULL);
int32_t rx_tti;
- int32_t cc_id;
uint32_t nFrameIdx = 0;
uint32_t nSubframeIdx = 0;
uint32_t nSlotIdx = 0;
p_sym_cb_ctx->user_timer_put = 0;
}
- MLogTask(PID_TIME_ARM_USER_TIMER_DEADLINE, t3, MLogTick());
+ MLogXRANTask(PID_TIME_ARM_USER_TIMER_DEADLINE, t3, MLogXRANTick());
}
void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore)
{
- uint64_t t3 = MLogTick();
+ uint64_t t3 = MLogXRANTick();
if (xran_if_current_state == XRAN_RUNNING){
rte_timer_cb_t fct = (rte_timer_cb_t)CbFct;
rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, CbArg);
}
- MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick());
+ MLogXRANTask(PID_TIME_ARM_TIMER, t3, MLogXRANTick());
}
int32_t
xran_timing_create_cbs(void *args)
{
- int32_t res = XRAN_STATUS_SUCCESS;
- int32_t do_reset = 0;
- uint64_t t1 = 0;
- int32_t result1,i,j;
- uint32_t delay_cp_dl;
+ //int32_t res = XRAN_STATUS_SUCCESS;
+ int32_t j;
+ uint32_t delay_cp_dl_max, delay_cp_dl_min;
uint32_t delay_cp_ul;
uint32_t delay_up;
uint32_t time_diff_us;
uint32_t delay_cp2up;
- uint32_t sym_cp_dl;
+ uint32_t sym_cp_dl_max, sym_cp_dl_min;
uint32_t sym_cp_ul;
uint32_t time_diff_nSymb;
int32_t sym_up;
struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *)args;
- uint64_t tWake = 0, tWakePrev = 0, tUsed = 0;
struct cb_elem_entry * cb_elm = NULL;
uint32_t interval_us_local = p_dev_ctx->interval_us_local;
if (p_dev_ctx->fh_init.io_cfg.id == O_DU) {
- delay_cp_dl = interval_us_local - p_dev_ctx->fh_cfg.T1a_max_cp_dl;
+ delay_cp_dl_max = interval_us_local - p_dev_ctx->fh_cfg.T1a_max_cp_dl;
+ delay_cp_dl_min = interval_us_local - p_dev_ctx->fh_cfg.T1a_min_cp_dl;
delay_cp_ul = interval_us_local - p_dev_ctx->fh_cfg.T1a_max_cp_ul;
+
+ uint8_t numSlots=0; /* How many slots you need to go backwards from OTA */
+ uint32_t max_dl_delay_offset=interval_us_local; /* Start of the slot in which you will start CP DL */
+ while(p_dev_ctx->fh_cfg.T1a_max_cp_dl > max_dl_delay_offset)
+ {
+ max_dl_delay_offset += interval_us_local;
+ numSlots++;
+ }
+
+ /* Delay from start of 'a' slot */
+ delay_cp_dl_max = max_dl_delay_offset - p_dev_ctx->fh_cfg.T1a_max_cp_dl;
+ /* Symbol on which we will start CP transmission */
+ sym_cp_dl_max = delay_cp_dl_max*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1;
+ /* Backward offset from OTA in terms of symbols when Cp transmission will start
+ * i.e. cp transmission will start 'max_dl_offset_sym' symbols before OTA
+ */
+ uint8_t max_dl_offset_sym = (numSlots+1)*N_SYM_PER_SLOT - sym_cp_dl_max;
+ /* Handle corner case of symbol-0*/
+ sym_cp_dl_max%=N_SYM_PER_SLOT;
+
+ uint32_t min_dl_delay_offset=interval_us_local;
+ numSlots=0;
+ while(p_dev_ctx->fh_cfg.T1a_min_cp_dl > min_dl_delay_offset)
+ {
+ min_dl_delay_offset += interval_us_local;
+ numSlots++;
+ }
+ delay_cp_dl_min = min_dl_delay_offset - p_dev_ctx->fh_cfg.T1a_min_cp_dl;
+ sym_cp_dl_min = delay_cp_dl_min*1000/(interval_us_local*1000/N_SYM_PER_SLOT) - 1;
+ uint8_t min_dl_offset_sym = (numSlots+1)*N_SYM_PER_SLOT - sym_cp_dl_min;
+ sym_cp_dl_min%=N_SYM_PER_SLOT;
+
+
+ uint32_t ul_delay_offset=interval_us_local;
+ numSlots=0;
+ while(p_dev_ctx->fh_cfg.T1a_max_cp_ul > ul_delay_offset)
+ {
+ ul_delay_offset += interval_us_local;
+ numSlots++;
+ }
+ delay_cp_ul = ul_delay_offset - p_dev_ctx->fh_cfg.T1a_max_cp_ul;
+ sym_cp_ul = (delay_cp_ul*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1);
+ uint8_t ul_offset_sym = (numSlots+1)*N_SYM_PER_SLOT - sym_cp_ul;
+ sym_cp_ul%=N_SYM_PER_SLOT;
+
+ printf("delay_cp_dl_max=%u, sym_cp_dl_max=%u, max_dl_offset_sym=%u\n"
+ "delay_cp_dl_min=%u, sym_cp_dl_min=%u, min_dl_offset_sym=%u\n"
+ "delay_cp_ul=%u, sym_cp_ul=%u, ul_offset_sym=%u\n",
+ delay_cp_dl_max, sym_cp_dl_max, max_dl_offset_sym,
+ delay_cp_dl_min, sym_cp_dl_min, min_dl_offset_sym,
+ delay_cp_ul, sym_cp_ul, ul_offset_sym);
+
+
delay_up = p_dev_ctx->fh_cfg.T1a_max_up;
time_diff_us = p_dev_ctx->fh_cfg.Ta4_max;
- delay_cp2up = delay_up-delay_cp_dl;
+ delay_cp2up = delay_up-delay_cp_dl_max;
+
- sym_cp_dl = delay_cp_dl*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1;
- sym_cp_ul = delay_cp_ul*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1;
time_diff_nSymb = time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT);
p_dev_ctx->sym_up = sym_up = -(delay_up*1000/(interval_us_local*1000/N_SYM_PER_SLOT));
p_dev_ctx->sym_up_ul = time_diff_nSymb = (time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1);
- printf("Start C-plane DL %d us after TTI [trigger on sym %d]\n", delay_cp_dl, sym_cp_dl);
+ printf("C-plane DL from %d us after TTI [trigger on sym %d] to %d us after TTI [trigger on sym %d]\n",
+ delay_cp_dl_max, sym_cp_dl_max, delay_cp_dl_min, sym_cp_dl_min);
+
printf("Start C-plane UL %d us after TTI [trigger on sym %d]\n", delay_cp_ul, sym_cp_ul);
printf("Start U-plane DL %d us before OTA [offset in sym %d]\n", delay_up, sym_up);
printf("Start U-plane UL %d us OTA [offset in sym %d]\n", time_diff_us, time_diff_nSymb);
printf("C-plane to U-plane delay %d us after TTI\n", delay_cp2up);
printf("Start Sym timer %ld ns\n", TX_TIMER_INTERVAL/N_SYM_PER_SLOT);
- cb_elm = xran_create_cb(xran_timer_arm_cp_dl, tx_cp_dl_cb, (void*)p_dev_ctx);
- if(cb_elm){
- LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[sym_cp_dl],
- cb_elm,
- pointers);
- } else {
+ if(1 == p_dev_ctx->fh_init.dlCpProcBurst){
+ p_dev_ctx->numSymsForDlCP = 1;
+ }
+ else{
+ if(max_dl_offset_sym >= min_dl_offset_sym) /* corner case where only 1 symbol is available for transmission */
+ p_dev_ctx->numSymsForDlCP = max_dl_offset_sym - min_dl_offset_sym + 1;
+ else
+ p_dev_ctx->numSymsForDlCP = 1;
+
+ }
+
+ int count=0;
+ while (count < p_dev_ctx->numSymsForDlCP)
+ {
+ cb_elm =
+ xran_create_cb (xran_timer_arm_cp_dl, tx_cp_dl_cb, (void *) p_dev_ctx);
+ if (cb_elm)
+ {
+ LIST_INSERT_HEAD (&p_dev_ctx->sym_cb_list_head[sym_cp_dl_max],
+ cb_elm, pointers);
+ }
+ else
+ {
print_err("cb_elm is NULL\n");
- res = XRAN_STATUS_FAIL;
+ //res = XRAN_STATUS_FAIL;
goto err0;
}
+ printf ("created sym cp dl cb for symbol %u\n", sym_cp_dl_max);
+
+ sym_cp_dl_max = (sym_cp_dl_max+1)%N_SYM_PER_SLOT;
+ max_dl_offset_sym--;
+ count++;
+ }
cb_elm = xran_create_cb(xran_timer_arm_cp_ul, tx_cp_ul_cb, (void*)p_dev_ctx);
if(cb_elm){
pointers);
} else {
print_err("cb_elm is NULL\n");
- res = XRAN_STATUS_FAIL;
+ //res = XRAN_STATUS_FAIL;
goto err0;
}
/* Full slot UL OTA + time_diff_us */
cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_full_cb, (void*)p_dev_ctx);
if(cb_elm){
- LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[time_diff_nSymb],
+ LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[time_diff_nSymb % XRAN_NUM_OF_SYMBOL_PER_SLOT],
cb_elm,
pointers);
} else {
print_err("cb_elm is NULL\n");
- res = XRAN_STATUS_FAIL;
+ //res = XRAN_STATUS_FAIL;
+ goto err0;
+ }
+
+ /* 1/4 UL OTA + time_diff_us*/
+ cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_one_fourths_cb, (void*)p_dev_ctx);
+ if(cb_elm){
+ LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[(time_diff_nSymb + 1*(N_SYM_PER_SLOT/4)) % XRAN_NUM_OF_SYMBOL_PER_SLOT],
+ cb_elm,
+ pointers);
+ } else {
+ print_err("cb_elm is NULL\n");
+ //res = XRAN_STATUS_FAIL;
goto err0;
}
/* Half slot UL OTA + time_diff_us*/
cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_half_cb, (void*)p_dev_ctx);
if(cb_elm){
- LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[time_diff_nSymb + N_SYM_PER_SLOT/2],
+ LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[(time_diff_nSymb + N_SYM_PER_SLOT/2) % XRAN_NUM_OF_SYMBOL_PER_SLOT],
cb_elm,
pointers);
} else {
print_err("cb_elm is NULL\n");
- res = XRAN_STATUS_FAIL;
+ //res = XRAN_STATUS_FAIL;
+ goto err0;
+ }
+
+ /* 3/4 UL OTA + time_diff_us*/
+ cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_three_fourths_cb, (void*)p_dev_ctx);
+ if(cb_elm){
+ LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[(time_diff_nSymb + 4*(N_SYM_PER_SLOT/4)) % XRAN_NUM_OF_SYMBOL_PER_SLOT],
+ cb_elm,
+ pointers);
+ } else {
+ print_err("cb_elm is NULL\n");
+ //res = XRAN_STATUS_FAIL;
goto err0;
}
} else { // APP_O_RU
p_dev_ctx->sym_up = sym_up = delay_up*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1;
printf("Start UL U-plane %d us after OTA [offset in sym %d]\n", delay_up, sym_up);
- /* calcualte when to Receive DL U-plane */
+ /* calculate when to Receive DL U-plane */
delay_up = p_dev_ctx->fh_cfg.T2a_max_up;
sym_up = delay_up*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1;
printf("Receive DL U-plane %d us after OTA [offset in sym %d]\n", delay_up, sym_up);
/* Full slot UL OTA + time_diff_us */
cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_full_cb, (void*)p_dev_ctx);
if(cb_elm){
- LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[sym_up],
+ LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[sym_up % XRAN_NUM_OF_SYMBOL_PER_SLOT],
cb_elm,
pointers);
} else {
print_err("cb_elm is NULL\n");
- res = -1;
+ //res = -1;
goto err0;
}
int32_t
xran_timing_destroy_cbs(void *args)
{
- int res = XRAN_STATUS_SUCCESS;
- int32_t do_reset = 0;
- uint64_t t1 = 0;
- int32_t result1,i,j;
+ //int res = XRAN_STATUS_SUCCESS;
+ int32_t j;
struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *)args;
- struct cb_elem_entry * cb_elm = NULL;
for (j = 0; j< XRAN_NUM_OF_SYMBOL_PER_SLOT; j++){
struct cb_elem_entry *cb_elm;
return 0;
}
+int32_t
+xran_reg_physide_cb_by_dev_id(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id id, uint8_t xran_port_id)
+{
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx_by_id(xran_port_id);
+ if (!p_xran_dev_ctx)
+ {
+ print_err("Null xRAN context on port id %u!!\n", xran_port_id);
+ return -1;
+ }
+
+ if(xran_get_if_state() == XRAN_RUNNING) {
+ print_err("Cannot register callback while running!!\n");
+ return (-1);
+ }
+ p_xran_dev_ctx->ttiCb[id] = Cb;
+ p_xran_dev_ctx->TtiCbParam[id] = cbParam;
+ p_xran_dev_ctx->SkipTti[id] = skipTtiNum;
+
+ return 0;
+}
#include <pthread.h>
#include <immintrin.h>
#include <rte_mbuf.h>
+#include <stdio.h>
+#include <stdbool.h>
#include "xran_common.h"
#include "ethdi.h"
static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */
+extern int32_t first_call;
+
#define MBUFS_CNT 16
extern int32_t xran_process_rx_sym(void *arg,
uint16_t sym_inc[MBUFS_CNT];
uint16_t rb[MBUFS_CNT];
uint16_t sect_id[MBUFS_CNT];
+ uint16_t prb_elem_id[MBUFS_CNT] = {0};
uint8_t compMeth[MBUFS_CNT] = { 0 };
uint8_t iqWidth[MBUFS_CNT] = { 0 };
uint32_t pkt_size[MBUFS_CNT];
- void* pHandle = NULL;
- int32_t valid_res, res_loc;
int expect_comp = (p_dev_ctx->fh_cfg.ru_conf.compMeth != XRAN_COMPMETHOD_NONE);
enum xran_comp_hdr_type staticComp = p_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
struct rte_mbuf* mb = NULL;
struct xran_prb_map* pRbMap = NULL;
struct xran_prb_elm* prbMapElm = NULL;
- uint16_t iq_sample_size_bits;
+ //uint16_t iq_sample_size_bits;
+ uint16_t idxElm = 0, total_sections = 0;
#if XRAN_MLOG_VAR
uint32_t mlogVar[10];
#endif
if (xran_port < 0) {
- print_err("Invalid pHandle - %p", pHandle);
+ print_err("Invalid pHandle");
return MBUF_FREE;
}
return MBUF_FREE;
}
+ if(first_call == 0) {
+ for(i = 0; i < num; i++ )
+ ret_data[i] = MBUF_FREE;
+ return MBUF_FREE;
+ }
+
conf = &(p_dev_ctx->eAxc_id_cfg);
if (conf == NULL) {
rte_panic("conf == NULL");
{
compMeth[i] = compMeth_ini;
iqWidth[i] = iqWidth_ini;
- valid_res = XRAN_STATUS_SUCCESS;
frame_id[i] = radio_hdr[i]->frame_id;
subframe_id[i] = radio_hdr[i]->sf_slot_sym.subframe_id;
rb[i] = data_hdr[i]->fields.rb;
sect_id[i] = data_hdr[i]->fields.sect_id;
+ if (num_prbu[i] == 0)
+ num_prbu[i] = p_dev_ctx->fh_cfg.nULRBs;
+
if (expect_comp && (staticComp != XRAN_COMP_HDR_TYPE_STATIC))
{
compMeth[i] = data_compr_hdr[i]->ud_comp_hdr.ud_comp_meth;
if (CC_ID[i] >= XRAN_MAX_CELLS_PER_PORT || Ant_ID[i] >= max_ant_num || symb_id[i] >= XRAN_NUM_OF_SYMBOL_PER_SLOT)
{
ptr_seq_id_num_port[CC_ID[i] * max_ant_num + Ant_ID[i]] = seq_id[i]; // for next
- valid_res = XRAN_STATUS_FAIL;
pCnt->Rx_pkt_dupl++;
// print_err("Invalid CC ID - %d or antenna ID or Symbol ID- %d", CC_ID[i], Ant_ID[i], symb_id[i]);
}
pCnt->rx_counter++;
pCnt->Rx_on_time++;
pCnt->Total_msgs_rcvd++;
+ struct xran_prach_cp_config *PrachCfg = NULL;
+ if(p_dev_ctx->dssEnable){
+ tti = frame_id[i] * SLOTS_PER_SYSTEMFRAME(p_dev_ctx->interval_us_local) +
+ subframe_id[i] * SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local) + slot_id[i];
+ int techSlot = (tti % p_dev_ctx->dssPeriod);
+ if(p_dev_ctx->technology[techSlot] == 1)
+ PrachCfg = &(p_dev_ctx->PrachCPConfig);
+ else
+ PrachCfg = &(p_dev_ctx->PrachCPConfigLTE);
+ }
+ else{
+ PrachCfg = &(p_dev_ctx->PrachCPConfig);
+ }
if (Ant_ID[i] >= p_dev_ctx->srs_cfg.eAxC_offset && p_dev_ctx->fh_cfg.srsEnable)
{
pCnt->rx_srs_packets++;
}
}
- else if (Ant_ID[i] >= p_dev_ctx->PrachCPConfig.eAxC_offset && p_dev_ctx->fh_cfg.prachEnable)
+ else if (Ant_ID[i] >= PrachCfg->eAxC_offset && p_dev_ctx->fh_cfg.prachEnable)
{
- Ant_ID[i] -= p_dev_ctx->PrachCPConfig.eAxC_offset;
+ Ant_ID[i] -= PrachCfg->eAxC_offset;
if (last[i] == 1)
{
prach_idx[num_prach] = i;
print_dbg("Completed receiving PRACH symbol %d, size=%d bytes\n", symb_id[i], num_bytes[i]);
- int16_t res = xran_process_prach_sym(p_dev_ctx,
+ xran_process_prach_sym(p_dev_ctx,
pkt,
iq_samp_buf[i],
num_bytes[i],
print_dbg("SRS receiving symbol %d, size=%d bytes\n",
symb_id[i], symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID[i]][Ant_ID[i]]);
- uint64_t t1 = MLogTick();
- int16_t res = xran_process_srs_sym(p_dev_ctx,
+ uint64_t t1 = MLogXRANTick();
+ xran_process_srs_sym(p_dev_ctx,
pkt,
iq_samp_buf[i],
num_bytes[i],
expect_comp,
compMeth[i],
iqWidth[i]);
- MLogTask(PID_PROCESS_UP_PKT_SRS, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_UP_PKT_SRS, t1, MLogXRANTick());
}
if (num_pusch == MBUFS_CNT)
{
for (i = 0; i < MBUFS_CNT; i++)
{
- iq_sample_size_bits = 16;
- if (expect_comp)
- iq_sample_size_bits = iqWidth[i];
+ //iq_sample_size_bits = 16;
+ //if (expect_comp)
+ // iq_sample_size_bits = iqWidth[i];
tti = frame_id[i] * SLOTS_PER_SYSTEMFRAME(p_dev_ctx->interval_us_local) +
subframe_id[i] * SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local) + slot_id[i];
if (pRbMap)
{
- prbMapElm = &pRbMap->prbMap[sect_id[i]];
- if (sect_id[i] >= pRbMap->nPrbElm)
+ /** Get the prb_elem_id */
+ total_sections=0;
+ if(pRbMap->prbMap[0].bf_weight.extType == 1)
+ {
+ for(idxElm=0 ; idxElm < pRbMap->nPrbElm ; idxElm++)
+ {
+ total_sections += pRbMap->prbMap[idxElm].bf_weight.numSetBFWs;
+ if(total_sections >= (sect_id[i] + 1))
{
-// print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], pRbMap->nPrbElm);
+ prb_elem_id[i] = idxElm;
+ break;
+ }
+ }
+ }
+ else
+ {
+ prb_elem_id[i] = sect_id[i];
+ }
+
+ if (prb_elem_id[i] >= pRbMap->nPrbElm)
+ {
+ print_err("sect_id %d, prb_elem_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], prb_elem_id[i], pRbMap->nPrbElm);
ret_data[i] = MBUF_FREE;
continue;
}
else
{
struct xran_section_desc* p_sec_desc = NULL;
- prbMapElm = &pRbMap->prbMap[sect_id[i]];
- p_sec_desc = prbMapElm->p_sec_desc[symb_id[i]][0];
+ prbMapElm = &pRbMap->prbMap[prb_elem_id[i]];
+ int16_t nSecDesc = prbMapElm->nSecDesc[symb_id[i]];
+ p_sec_desc = &prbMapElm->sec_desc[symb_id[i]][nSecDesc];
if (p_sec_desc)
{
p_sec_desc->iq_buffer_len = num_bytes_pusch[i];
p_sec_desc->iq_buffer_offset = iq_offset[i];
ret_data[i] = MBUF_KEEP;
+ prbMapElm->nSecDesc[symb_id[i]] += 1;
}
else
{
{
i = pusch_idx[j];
- iq_sample_size_bits = 16;
- if (expect_comp)
- iq_sample_size_bits = iqWidth[i];
+ //iq_sample_size_bits = 16;
+ //if (expect_comp)
+ // iq_sample_size_bits = iqWidth[i];
tti = frame_id[i] * SLOTS_PER_SYSTEMFRAME(p_dev_ctx->interval_us_local) +
subframe_id[i] * SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local) + slot_id[i];
if (pRbMap)
{
- prbMapElm = &pRbMap->prbMap[sect_id[i]];
- if (sect_id[i] >= pRbMap->nPrbElm)
+ /** Get the prb_elem_id */
+ total_sections=0;
+ if(pRbMap->prbMap[0].bf_weight.extType == 1)
+ {
+ for(idxElm=0 ; idxElm < pRbMap->nPrbElm ; idxElm++)
+ {
+ total_sections += pRbMap->prbMap[idxElm].bf_weight.numSetBFWs;
+ if(total_sections >= (sect_id[i] + 1))
+ {
+ prb_elem_id[i] = idxElm;
+ break;
+ }
+ }
+ }
+ else
+ {
+ prb_elem_id[i] = sect_id[i];
+ }
+
+ if (prb_elem_id[i] >= pRbMap->nPrbElm)
{
-// print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], pRbMap->nPrbElm);
+ print_err("sect_id %d, prb_elem_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], prb_elem_id[i], pRbMap->nPrbElm);
ret_data[i] = MBUF_FREE;
continue;
}
else
{
struct xran_section_desc* p_sec_desc = NULL;
- prbMapElm = &pRbMap->prbMap[sect_id[i]];
- p_sec_desc = prbMapElm->p_sec_desc[symb_id[i]][0];
+ prbMapElm = &pRbMap->prbMap[prb_elem_id[i]];
+ int16_t nSecDesc = prbMapElm->nSecDesc[symb_id[i]];
+ p_sec_desc = &prbMapElm->sec_desc[symb_id[i]][nSecDesc];
if (p_sec_desc)
{
p_sec_desc->iq_buffer_len = num_bytes_pusch[i];
p_sec_desc->iq_buffer_offset = iq_offset[i];
ret_data[i] = MBUF_KEEP;
+ prbMapElm->nSecDesc[symb_id[i]] += 1;
}
else
{
int
process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
{
- uint64_t tt1 = MLogTick();
+ uint64_t tt1 = MLogXRANTick();
struct xran_device_ctx *p_dev_ctx = (struct xran_device_ctx *)handle;
void *iq_samp_buf;
union ecpri_seq_id seq;
uint8_t compMeth = 0;
uint8_t iqWidth = 0;
- void *pHandle = NULL;
int ret = MBUF_FREE;
uint32_t mb_free = 0;
int32_t valid_res = 0;
int expect_comp = (p_dev_ctx->fh_cfg.ru_conf.compMeth != XRAN_COMPMETHOD_NONE);
enum xran_comp_hdr_type staticComp = p_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+ if(first_call == 0)
+ return ret;
+
if (staticComp == XRAN_COMP_HDR_TYPE_STATIC)
{
compMeth = p_dev_ctx->fh_cfg.ru_conf.compMeth;
iqWidth = p_dev_ctx->fh_cfg.ru_conf.iqWidth;
}
- if(p_dev_ctx->xran2phy_mem_ready == 0)
+ if(p_dev_ctx->xran2phy_mem_ready == 0 || first_call == 0)
return MBUF_FREE;
- num_bytes = xran_extract_iq_samples(pkt,
- &iq_samp_buf,
- &CC_ID,
- &Ant_ID,
- &frame_id,
- &subframe_id,
- &slot_id,
- &symb_id,
- &seq,
- &num_prbu,
- &start_prbu,
- &sym_inc,
- &rb,
- §_id,
- expect_comp,
- staticComp,
- &compMeth,
- &iqWidth);
- if (num_bytes <= 0){
+ num_bytes = xran_extract_iq_samples(pkt, &iq_samp_buf,
+ &CC_ID, &Ant_ID, &frame_id, &subframe_id, &slot_id, &symb_id, &seq,
+ &num_prbu, &start_prbu, &sym_inc, &rb, §_id,
+ expect_comp, staticComp, &compMeth, &iqWidth);
+ if (num_bytes <= 0)
+ {
print_err("num_bytes is wrong [%d]\n", num_bytes);
return MBUF_FREE;
}
+ if (num_prbu == 0)
+ num_prbu = p_dev_ctx->fh_cfg.nULRBs;
- valid_res = xran_pkt_validate(p_dev_ctx,
- pkt,
- iq_samp_buf,
- num_bytes,
- CC_ID,
- Ant_ID,
- frame_id,
- subframe_id,
- slot_id,
- symb_id,
- &seq,
- num_prbu,
- start_prbu,
- sym_inc,
- rb,
- sect_id);
-#ifndef FCN_ADAPT
- if(valid_res != 0) {
- print_dbg("valid_res is wrong [%d] ant %u (%u : %u : %u : %u) seq %u num_bytes %d\n", valid_res, Ant_ID, frame_id, subframe_id, slot_id, symb_id, seq.seq_id, num_bytes);
- return MBUF_FREE;
- }
-#endif
- MLogTask(PID_PROCESS_UP_PKT_PARSE, tt1, MLogTick());
- if (Ant_ID >= p_dev_ctx->srs_cfg.eAxC_offset && p_dev_ctx->fh_cfg.srsEnable) {
+ MLogXRANTask(PID_PROCESS_UP_PKT_PARSE, tt1, MLogXRANTick());
+ /* do not validate for NDM SRS */
+ if (Ant_ID >= p_dev_ctx->srs_cfg.eAxC_offset && p_dev_ctx->fh_cfg.srsEnable)
+ {
/* SRS packet has ruportid = 2*num_eAxc + ant_id */
Ant_ID -= p_dev_ctx->srs_cfg.eAxC_offset;
symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes;
- if (seq.bits.e_bit == 1) {
+ if (seq.bits.e_bit == 1)
+ {
print_dbg("SRS receiving symbol %d, size=%d bytes\n",
symb_id, symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]);
- if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) {
- uint64_t t1 = MLogTick();
+ if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID])
+ {
+ uint64_t t1 = MLogXRANTick();
int16_t res = xran_process_srs_sym(p_dev_ctx,
- pkt,
- iq_samp_buf,
- num_bytes,
- CC_ID,
- Ant_ID,
- frame_id,
- subframe_id,
- slot_id,
- symb_id,
- num_prbu,
- start_prbu,
- sym_inc,
- rb,
- sect_id,
- &mb_free,
- expect_comp,
- compMeth,
- iqWidth);
- if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) {
+ pkt, iq_samp_buf, num_bytes,
+ CC_ID, Ant_ID, frame_id, subframe_id, slot_id, symb_id,
+ num_prbu, start_prbu, sym_inc, rb, sect_id,
+ &mb_free, expect_comp, compMeth, iqWidth);
+ if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID])
ret = mb_free;
- } else {
+ else
print_err("res != symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]\n");
- }
+
pCnt->rx_srs_packets++;
- MLogTask(PID_PROCESS_UP_PKT_SRS, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_UP_PKT_SRS, t1, MLogXRANTick());
}
symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] = 0;
}
- else {
+ else
print_dbg("Transport layer fragmentation (eCPRI) is not supported\n");
+ } /* if (Ant_ID >= p_dev_ctx->srs_cfg.eAxC_offset && p_dev_ctx->fh_cfg.srsEnable) */
+
+ else
+ {
+ valid_res = xran_pkt_validate(p_dev_ctx,
+ pkt, iq_samp_buf, num_bytes,
+ CC_ID, Ant_ID, frame_id, subframe_id, slot_id, symb_id,
+ &seq, num_prbu, start_prbu, sym_inc, rb, sect_id);
+#ifndef FCN_ADAPT
+ if(valid_res != 0)
+ {
+ print_dbg("valid_res is wrong [%d] ant %u (%u : %u : %u : %u) seq %u num_bytes %d\n", valid_res, Ant_ID, frame_id, subframe_id, slot_id, symb_id, seq.bits.seq_id, num_bytes);
+ return MBUF_FREE;
+ }
+#endif
+ int tti = 0;
+ struct xran_prach_cp_config *PrachCfg = NULL;
+ if(p_dev_ctx->dssEnable){
+ tti = frame_id * SLOTS_PER_SYSTEMFRAME(p_dev_ctx->interval_us_local) +
+ subframe_id * SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local) + slot_id;
+ int techSlot = (tti % p_dev_ctx->dssPeriod);
+ if(p_dev_ctx->technology[techSlot] == 1)
+ PrachCfg = &(p_dev_ctx->PrachCPConfig);
+ else
+ PrachCfg = &(p_dev_ctx->PrachCPConfigLTE);
+ }
+ else{
+ PrachCfg = &(p_dev_ctx->PrachCPConfig);
}
- } else if (Ant_ID >= p_dev_ctx->PrachCPConfig.eAxC_offset && p_dev_ctx->fh_cfg.prachEnable) {
+ if (Ant_ID >= PrachCfg->eAxC_offset && p_dev_ctx->fh_cfg.prachEnable)
+ {
/* PRACH packet has ruportid = num_eAxc + ant_id */
- Ant_ID -= p_dev_ctx->PrachCPConfig.eAxC_offset;
+ Ant_ID -= PrachCfg->eAxC_offset;
symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes;
- if (seq.bits.e_bit == 1) {
+ if (seq.bits.e_bit == 1)
+ {
print_dbg("Completed receiving PRACH symbol %d, size=%d bytes\n",
symb_id, num_bytes);
- if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) {
+ if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID])
+ {
int16_t res = xran_process_prach_sym(p_dev_ctx,
- pkt,
- iq_samp_buf,
- num_bytes,
- CC_ID,
- Ant_ID,
- frame_id,
- subframe_id,
- slot_id,
- symb_id,
- num_prbu,
- start_prbu,
- sym_inc,
- rb,
- sect_id,
- &mb_free);
- if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) {
+ pkt, iq_samp_buf, num_bytes,
+ CC_ID, Ant_ID, frame_id, subframe_id, slot_id, symb_id,
+ num_prbu, start_prbu, sym_inc, rb, sect_id, &mb_free);
+ if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID])
ret = mb_free;
- } else {
+ else
print_err("res != symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]\n");
- }
+
pCnt->rx_prach_packets[Ant_ID]++;
}
symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] = 0;
- } else {
+ }
+ else
print_dbg("Transport layer fragmentation (eCPRI) is not supported\n");
}
-
- } else { /* PUSCH */
+ else
+ {
+ /* PUSCH */
symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes;
- if (seq.bits.e_bit == 1) {
+ if (seq.bits.e_bit == 1)
+ {
print_dbg("Completed receiving symbol %d, size=%d bytes\n",
symb_id, symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]);
- if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) {
- uint64_t t1 = MLogTick();
+ if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID])
+ {
+ uint64_t t1 = MLogXRANTick();
int res = xran_process_rx_sym(p_dev_ctx,
- pkt,
- iq_samp_buf,
- symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID],
- CC_ID,
- Ant_ID,
- frame_id,
- subframe_id,
- slot_id,
- symb_id,
- num_prbu,
- start_prbu,
- sym_inc,
- rb,
- sect_id,
- &mb_free,
- expect_comp,
- compMeth,
- iqWidth);
- if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) {
+ pkt, iq_samp_buf, symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID],
+ CC_ID, Ant_ID, frame_id, subframe_id, slot_id, symb_id,
+ num_prbu, start_prbu, sym_inc, rb, sect_id,
+ &mb_free, expect_comp, compMeth, iqWidth);
+ if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID])
ret = mb_free;
- } else {
+ else
print_err("res != symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]\n");
- }
+
pCnt->rx_pusch_packets[Ant_ID]++;
- MLogTask(PID_PROCESS_UP_PKT, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_UP_PKT, t1, MLogXRANTick());
}
symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] = 0;
- } else {
- print_dbg("Transport layer fragmentation (eCPRI) is not supported\n");
}
+ else
+ print_dbg("Transport layer fragmentation (eCPRI) is not supported\n");
}
+ } /* else */
return ret;
}
+#if 0
static int set_iq_bit_width(uint8_t iq_bit_width, struct data_section_compression_hdr *compr_hdr)
{
if (iq_bit_width == MAX_IQ_BIT_WIDTH)
return 0;
}
+#endif
/* Send a single 5G symbol over multiple packets */
inline int32_t prepare_symbol_ex(enum xran_pkt_dir direction,
- uint16_t section_id,
+ uint16_t section_id_start,
struct rte_mbuf *mb,
uint8_t *data,
uint8_t compMeth,
uint8_t RU_Port_ID,
uint8_t seq_id,
uint32_t do_copy,
- enum xran_comp_hdr_type staticEn)
+ enum xran_comp_hdr_type staticEn,
+ uint16_t num_sections,
+ uint16_t iq_offset)
{
- int32_t n_bytes;
+ int32_t n_bytes , iq_len_aggr = 0;
int32_t prep_bytes;
- int16_t nPktSize;
- uint32_t off;
+ int16_t nPktSize,idx, nprb_per_section;
+ uint32_t curr_sect_id;
int parm_size;
- struct xran_up_pkt_gen_params xp = { 0 };
-
+ struct xran_up_pkt_gen_params xp[XRAN_MAX_SECTIONS_PER_SLOT] = { 0 };
+ bool prbElemBegin , prbElemEnd;
iqWidth = (iqWidth==0) ? 16 : iqWidth;
switch(compMeth) {
default:
parm_size = 0;
}
- n_bytes = (3 * iqWidth + parm_size) * prb_num;
- n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN);
- nPktSize = sizeof(struct rte_ether_hdr)
+ nprb_per_section = prb_num/num_sections;
+ if(prb_num%num_sections)
+ nprb_per_section++;
+
+ n_bytes = (3 * iqWidth + parm_size)*nprb_per_section;
+ // n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN);
+
+ for(idx=0 ; idx < num_sections ; idx++)
+ {
+ prbElemBegin = (idx == 0) ? 1 : 0;
+ prbElemEnd = (idx + 1 == num_sections) ? 1 : 0;
+ curr_sect_id = section_id_start + idx ;
+
+ iq_len_aggr += n_bytes;
+
+ if(prbElemBegin)
+ {
+ nPktSize = sizeof(struct rte_ether_hdr)
+ sizeof(struct xran_ecpri_hdr)
- + sizeof(struct radio_app_common_hdr)
- + sizeof(struct data_section_hdr)
- + n_bytes;
- if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
- nPktSize += sizeof(struct data_section_compression_hdr);
+ + sizeof(struct radio_app_common_hdr) ;
+ }
- /* radio app header */
- xp.app_params.data_feature.value = 0x10;
- xp.app_params.data_feature.data_direction = direction;
- //xp.app_params.payl_ver = 1;
- //xp.app_params.filter_id = 0;
- xp.app_params.frame_id = frame_id;
- xp.app_params.sf_slot_sym.subframe_id = subframe_id;
- xp.app_params.sf_slot_sym.slot_id = xran_slotid_convert(slot_id, 0);
- xp.app_params.sf_slot_sym.symb_id = symbol_no;
+ if(prbElemEnd){
+ if(((idx+1)*nprb_per_section) > prb_num){
+ nprb_per_section = (prb_num - idx*nprb_per_section);
+ // n_bytes = (3 * iqWidth + parm_size)*(nprb_per_section);
+ }
+ }
+
+ nPktSize += sizeof(struct data_section_hdr);
+
+ if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
+ nPktSize += sizeof(struct data_section_compression_hdr);
+
+ nPktSize += n_bytes;
+
+ /** radio app header
+ * Setting app_params is redundant , its needed only once to create common Radio app header.
+ */
+ xp[idx].app_params.data_feature.value = 0x10;
+ xp[idx].app_params.data_feature.data_direction = direction;
+ // xp[idx].app_params.payl_ver = 1;
+ // xp[idx].app_params.filter_id = 0;
+ xp[idx].app_params.frame_id = frame_id;
+ xp[idx].app_params.sf_slot_sym.subframe_id = subframe_id;
+ xp[idx].app_params.sf_slot_sym.slot_id = xran_slotid_convert(slot_id, 0);
+ xp[idx].app_params.sf_slot_sym.symb_id = symbol_no;
/* convert to network byte order */
- xp.app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp.app_params.sf_slot_sym.value);
+ xp[idx].app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp[idx].app_params.sf_slot_sym.value);
- xp.sec_hdr.fields.all_bits = 0;
- xp.sec_hdr.fields.sect_id = section_id;
- xp.sec_hdr.fields.num_prbu = (uint8_t)prb_num;
- xp.sec_hdr.fields.start_prbu = (uint8_t)prb_start;
- //xp.sec_hdr.fields.sym_inc = 0;
- //xp.sec_hdr.fields.rb = 0;
+ // printf("start_prbu = %d, prb_num = %d,num_sections = %d, nprb_per_section = %d,curr_sect_id = %d\n",(prb_start + idx*nprb_per_section),prb_num,num_sections,nprb_per_section,curr_sect_id);
+ xp[idx].sec_hdr.fields.all_bits = 0;
+ xp[idx].sec_hdr.fields.sect_id = curr_sect_id;
+ xp[idx].sec_hdr.fields.num_prbu = XRAN_CONVERT_NUMPRBC(nprb_per_section); //(uint8_t)prb_num;
+ xp[idx].sec_hdr.fields.start_prbu = prb_start;
+ xp[idx].sec_hdr.fields.sym_inc = 0;
+ xp[idx].sec_hdr.fields.rb = 0;
/* compression */
- xp.compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth;
- xp.compr_hdr_param.ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth);
- xp.compr_hdr_param.rsrvd = 0;
+ xp[idx].compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth;
+ xp[idx].compr_hdr_param.ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth);
+ xp[idx].compr_hdr_param.rsrvd = 0;
+ prb_start += nprb_per_section;
+
+#if 0
+ printf("\nidx %hu num_prbu %u sect_id %u start_prbu %u sym_inc %u curr_sec_id %u",idx,(uint32_t)xp[idx].sec_hdr.fields.num_prbu,
+ (uint32_t)xp[idx].sec_hdr.fields.sect_id,
+ (uint32_t)xp[idx].sec_hdr.fields.start_prbu,
+ (uint32_t)xp[idx].sec_hdr.fields.sym_inc,curr_sect_id);
+
+#endif
/* network byte order */
- xp.sec_hdr.fields.all_bits = rte_cpu_to_be_32(xp.sec_hdr.fields.all_bits);
+ xp[idx].sec_hdr.fields.all_bits = rte_cpu_to_be_32(xp[idx].sec_hdr.fields.all_bits);
if (mb == NULL){
MLogPrint(NULL);
errx(1, "out of mbufs after %d packets", 1);
}
+ } /* for(idx=0 ; idx < num_sections ; idx++) */
+
+ //printf("\niq_len_aggr %u",iq_len_aggr);
prep_bytes = xran_prepare_iq_symbol_portion(mb,
data,
iq_buf_byte_order,
- n_bytes,
- &xp,
+ iq_len_aggr,
+ xp,
CC_ID,
RU_Port_ID,
seq_id,
staticEn,
- do_copy);
+ do_copy,
+ num_sections,
+ section_id_start,
+ iq_offset);
if (prep_bytes <= 0)
errx(1, "failed preparing symbol");
return 0;
}
+int send_symbol_mult_section_ex(void *handle,
+ enum xran_pkt_dir direction,
+ uint16_t section_id,
+ struct rte_mbuf *mb, uint8_t *data,
+ uint8_t compMeth, uint8_t iqWidth,
+ const enum xran_input_byte_order iq_buf_byte_order,
+ uint8_t frame_id, uint8_t subframe_id,
+ uint8_t slot_id, uint8_t symbol_no,
+ int prb_start, int prb_num,
+ uint8_t CC_ID, uint8_t RU_Port_ID, uint8_t seq_id)
+{
+ uint32_t do_copy = 0;
+ int32_t n_bytes;
+ int hdr_len, parm_size;
+ int32_t sent=0;
+ uint32_t loop = 0;
+ struct xran_device_ctx *p_dev_ctx = (struct xran_device_ctx *)handle;
+ struct xran_common_counters *pCnt = &p_dev_ctx->fh_counters;
+ enum xran_comp_hdr_type staticEn= XRAN_COMP_HDR_TYPE_DYNAMIC;
+
+ if (p_dev_ctx != NULL)
+ {
+ staticEn = p_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+
+ hdr_len = sizeof(struct xran_ecpri_hdr)
+ + sizeof(struct radio_app_common_hdr)
+ + sizeof(struct data_section_hdr);
+ if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
+ hdr_len += sizeof(struct data_section_compression_hdr);
+
+ switch(compMeth) {
+ case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
+ case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
+ default:
+ parm_size = 0;
+ }
+ int prb_num_pre_sec = (prb_num+2)/3;
+ int prb_offset = 0;
+ int data_offset = 0;
+ int prb_num_sec;
+ rte_iova_t ext_buff_iova = 0;
+
+ struct rte_mbuf *send_mb;
+ char *p_sec_iq = NULL;
+ char *ext_buff = NULL;
+ uint16_t ext_buff_len = 0;
+ struct rte_mbuf_ext_shared_info * p_share_data = NULL;
+ struct rte_mbuf *eth_oran_hdr = NULL;
+ struct rte_mbuf *tmp = NULL;
+ for (loop = 0; loop < 3;loop++)
+ {
+ seq_id = xran_get_upul_seqid(handle, CC_ID, RU_Port_ID);
+
+ prb_num_sec = ((loop+1)*prb_num_pre_sec > prb_num) ? (prb_num - loop*prb_num_pre_sec) : prb_num_pre_sec;
+ n_bytes = (3 * iqWidth + parm_size) * prb_num_sec;
+ char * pChar = NULL;
+
+ send_mb = xran_ethdi_mbuf_alloc(); /* will be freede by ETH */
+ if(send_mb == NULL) {
+ MLogPrint(NULL);
+ errx(1, "out of mbufs after %d packets", 1);
+ }
+
+ pChar = rte_pktmbuf_append(send_mb, hdr_len + n_bytes);
+ if(pChar == NULL) {
+ MLogPrint(NULL);
+ errx(1, "incorrect mbuf size %d packets", 1);
+ }
+ pChar = rte_pktmbuf_prepend(send_mb, sizeof(struct rte_ether_hdr));
+ if(pChar == NULL) {
+ MLogPrint(NULL);
+ errx(1, "incorrect mbuf size %d packets", 1);
+ }
+ do_copy = 1; /* new mbuf hence copy of IQs */
+ pChar = rte_pktmbuf_mtod(send_mb, char*);
+ char *pdata_start = (pChar + sizeof(struct rte_ether_hdr) + hdr_len);
+ memcpy(pdata_start,data + data_offset,n_bytes);
+
+
+ sent = prepare_symbol_ex(direction,
+ section_id,
+ send_mb,
+ data + data_offset,
+ compMeth,
+ iqWidth,
+ iq_buf_byte_order,
+ frame_id,
+ subframe_id,
+ slot_id,
+ symbol_no,
+ prb_start+prb_offset,
+ prb_num_sec,
+ CC_ID,
+ RU_Port_ID,
+ seq_id,
+ do_copy,
+ staticEn,
+ 1,
+ 0); /*Send a single section */
+ prb_offset += prb_num_sec;
+ data_offset += n_bytes;
+ if(sent) {
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(send_mb);
+ p_dev_ctx->send_upmbuf2ring(send_mb, ETHER_TYPE_ECPRI, xran_map_ecpriPcid_to_vf(p_dev_ctx, direction, CC_ID, RU_Port_ID));
+ }
+
+ }
+
+#ifdef DEBUG
+ printf("Symbol %2d sent (%d packets, %d bytes)\n", symbol_no, i, n_bytes);
+#endif
+ }
+ return sent;
+}
/* Send a single 5G symbol over multiple packets */
errx(1, "incorrect mbuf size %d packets", 1);
}
do_copy = 1; /* new mbuf hence copy of IQs */
+
+ /**copy prach data start**/
+ pChar = rte_pktmbuf_mtod(mb, char*);
+ char *pdata_start = (pChar + sizeof(struct rte_ether_hdr) + hdr_len);
+ memcpy(pdata_start,data,n_bytes);
+ /**copy prach data end**/
+
+
}
else {
rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */
RU_Port_ID,
seq_id,
do_copy,
- staticEn);
+ staticEn,
+ 1,
+ 0); /*Send a single section */
if(sent){
pCnt->tx_counter++;
for(i=0; i<nsection; i++)
xran_cp_add_section_info(pHandle, dir, cc_id, ru_port_id,
(slot_id + subframe_id*SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local))%XRAN_MAX_SECTIONDB_CTX,
- §_geninfo[i].info);
+ sect_geninfo[i].info);
return (ret);
}
params->hdr.compMeth = comp_method;
nsection = 0;
- sect_geninfo[nsection].info.type = params->sectionType; // for database
- sect_geninfo[nsection].info.startSymId = params->hdr.startSymId; // for database
- sect_geninfo[nsection].info.iqWidth = params->hdr.iqWidth; // for database
- sect_geninfo[nsection].info.compMeth = params->hdr.compMeth; // for database
- sect_geninfo[nsection].info.id = xran_alloc_sectionid(pHandle, dir, cc_id, ru_port_id, slot_id);
- sect_geninfo[nsection].info.rb = XRAN_RBIND_EVERY;
- sect_geninfo[nsection].info.symInc = symInc;
- sect_geninfo[nsection].info.startPrbc = prb_start;
- sect_geninfo[nsection].info.numPrbc = prb_num;
- sect_geninfo[nsection].info.numSymbol = numsym;
- sect_geninfo[nsection].info.reMask = 0xfff;
- sect_geninfo[nsection].info.beamId = beam_id;
+ sect_geninfo[nsection].info->type = params->sectionType; // for database
+ sect_geninfo[nsection].info->startSymId = params->hdr.startSymId; // for database
+ sect_geninfo[nsection].info->iqWidth = params->hdr.iqWidth; // for database
+ sect_geninfo[nsection].info->compMeth = params->hdr.compMeth; // for database
+ sect_geninfo[nsection].info->id = xran_alloc_sectionid(pHandle, dir, cc_id, ru_port_id, subframe_id, slot_id);
+ sect_geninfo[nsection].info->rb = XRAN_RBIND_EVERY;
+ sect_geninfo[nsection].info->symInc = symInc;
+ sect_geninfo[nsection].info->startPrbc = prb_start;
+ sect_geninfo[nsection].info->numPrbc = prb_num;
+ sect_geninfo[nsection].info->numSymbol = numsym;
+ sect_geninfo[nsection].info->reMask = 0xfff;
+ sect_geninfo[nsection].info->beamId = beam_id;
for (loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) {
- sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_offset = iq_buffer_offset;
- sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_len = iq_buffer_len;
+ sect_geninfo[0].info->sec_desc[loc_sym].iq_buffer_offset = iq_buffer_offset;
+ sect_geninfo[0].info->sec_desc[loc_sym].iq_buffer_len = iq_buffer_len;
}
- sect_geninfo[nsection].info.ef = 0;
+ sect_geninfo[nsection].info->ef = 0;
sect_geninfo[nsection].exDataSize = 0;
// sect_geninfo[nsection].exData = NULL;
nsection++;
return (-1);
}
- ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, ru_port_id, seq_id);
+ ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, ru_port_id, seq_id,0);
if(ret < 0){
print_err("Fail to build control plane packet - [%d:%d:%d] dir=%d\n",
frame_id, subframe_id, slot_id, dir);
}
int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struct xran_section_gen_info *sect_geninfo, struct rte_mbuf *mbuf, struct xran_device_ctx *pxran_lib_ctx,
- uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id,
+ uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id, int tti,
uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint16_t occasionid, uint8_t seq_id)
{
int nsection, ret;
- struct xran_prach_cp_config *pPrachCPConfig = &(pxran_lib_ctx->PrachCPConfig);
+ struct xran_prach_cp_config *pPrachCPConfig = NULL;;
+ int i=0;
+ if(pxran_lib_ctx->dssEnable){
+ i = tti % pxran_lib_ctx->dssPeriod;
+ if(pxran_lib_ctx->technology[i]==1) {
+ pPrachCPConfig = &(pxran_lib_ctx->PrachCPConfig);
+ }
+ else
+ {
+ pPrachCPConfig = &(pxran_lib_ctx->PrachCPConfigLTE);
+ }
+ }
+ else
+ pPrachCPConfig = &(pxran_lib_ctx->PrachCPConfig);
+
uint16_t timeOffset;
uint16_t nNumerology = pxran_lib_ctx->fh_cfg.frame_conf.nNumerology;
uint8_t startSymId;
{
timeOffset += startSymId * (2048 + 144);
}
+
+ if(XRAN_FILTERINDEX_PRACH_ABC == pPrachCPConfig->filterIdx)
+ {
timeOffset = timeOffset >> nNumerology; //original number is Tc, convert to Ts based on mu
if ((slot_id == 0) || (slot_id == (SLOTNUM_PER_SUBFRAME(pxran_lib_ctx->interval_us_local) >> 1)))
timeOffset += 16;
+ }
+ else
+ {
+ //when prach scs lower than 15khz, timeOffset base 15khz not need to adjust.
+ }
params->dir = XRAN_DIR_UL;
params->sectionType = XRAN_CP_SECTIONTYPE_3;
/* use timeOffset field for the CP length value for prach sequence */
params->hdr.timeOffset = timeOffset;
params->hdr.fftSize = xran_get_conf_fftsize(pHandle);
+ /*convert to o-ran ecpri specs scs index*/
+ switch(pPrachCPConfig->filterIdx)
+ {
+ case XRAN_FILTERINDEX_PRACH_012:
+ params->hdr.scs = 12;
+ break;
+ case XRAN_FILTERINDEX_NPRACH:
+ params->hdr.scs = 13;
+ break;
+ case XRAN_FILTERINDEX_PRACH_3:
+ params->hdr.scs = 14;
+ break;
+ case XRAN_FILTERINDEX_LTE4:
+ params->hdr.scs = 15;
+ break;
+ case XRAN_FILTERINDEX_PRACH_ABC:
params->hdr.scs = xran_get_conf_prach_scs(pHandle);
+ break;
+ default:
+ print_err("prach filterIdx error - [%d:%d:%d]--%d\n", frame_id, subframe_id, slot_id,pPrachCPConfig->filterIdx);
+ params->hdr.scs = 0;
+ break;
+ }
params->hdr.cpLength = 0;
nsection = 0;
- sect_geninfo[nsection].info.type = params->sectionType; // for database
- sect_geninfo[nsection].info.startSymId = params->hdr.startSymId; // for database
- sect_geninfo[nsection].info.iqWidth = params->hdr.iqWidth; // for database
- sect_geninfo[nsection].info.compMeth = params->hdr.compMeth; // for database
- sect_geninfo[nsection].info.id = xran_alloc_sectionid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id, slot_id);
- sect_geninfo[nsection].info.rb = XRAN_RBIND_EVERY;
- sect_geninfo[nsection].info.symInc = XRAN_SYMBOLNUMBER_NOTINC;
- sect_geninfo[nsection].info.startPrbc = pPrachCPConfig->startPrbc;
- sect_geninfo[nsection].info.numPrbc = pPrachCPConfig->numPrbc,
- sect_geninfo[nsection].info.numSymbol = pPrachCPConfig->numSymbol;
- sect_geninfo[nsection].info.reMask = 0xfff;
- sect_geninfo[nsection].info.beamId = beam_id;
- sect_geninfo[nsection].info.freqOffset = pPrachCPConfig->freqOffset;
+ sect_geninfo[nsection].info->type = params->sectionType; // for database
+ sect_geninfo[nsection].info->startSymId = params->hdr.startSymId; // for database
+ sect_geninfo[nsection].info->iqWidth = params->hdr.iqWidth; // for database
+ sect_geninfo[nsection].info->compMeth = params->hdr.compMeth; // for database
+ sect_geninfo[nsection].info->id = xran_alloc_sectionid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id, subframe_id, slot_id);
+ sect_geninfo[nsection].info->rb = XRAN_RBIND_EVERY;
+ sect_geninfo[nsection].info->symInc = XRAN_SYMBOLNUMBER_NOTINC;
+ sect_geninfo[nsection].info->startPrbc = pPrachCPConfig->startPrbc;
+ sect_geninfo[nsection].info->numPrbc = pPrachCPConfig->numPrbc,
+ sect_geninfo[nsection].info->numSymbol = pPrachCPConfig->numSymbol;
+ sect_geninfo[nsection].info->reMask = 0xfff;
+ sect_geninfo[nsection].info->beamId = beam_id;
+ sect_geninfo[nsection].info->freqOffset = pPrachCPConfig->freqOffset;
+ sect_geninfo[nsection].info->prbElemBegin = 1;
+ sect_geninfo[nsection].info->prbElemEnd = 1;
+
pxran_lib_ctx->prach_last_symbol[cc_id] = pPrachCPConfig->startSymId + pPrachCPConfig->numSymbol*pPrachCPConfig->occassionsInPrachSlot - 1;
- sect_geninfo[nsection].info.ef = 0;
+ sect_geninfo[nsection].info->ef = 0;
sect_geninfo[nsection].exDataSize = 0;
// sect_geninfo[nsection].exData = NULL;
nsection++;
params->numSections = nsection;
params->sections = sect_geninfo;
- ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, prach_port_id, seq_id);
+ ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, prach_port_id, seq_id,0);
if(ret < 0){
print_err("Fail to build prach control packet - [%d:%d:%d]\n", frame_id, subframe_id, slot_id);
rte_pktmbuf_free(mbuf);
assert(r);
struct rte_mbuf *mbufs[MBUFS_CNT];
- int i;
uint32_t remaining;
- uint64_t t1;
+ //uint64_t t1;
const uint16_t dequeued = rte_ring_dequeue_burst(r, (void **)mbufs,
RTE_DIM(mbufs), &remaining);
rte_timer_manage();
if (ctx->bbdev_dec) {
- t1 = MLogTick();
+ t1 = MLogXRANTick();
retPoll = ctx->bbdev_dec();
if (retPoll == 1)
{
- t2 = MLogTick();
- MLogTask(PID_XRAN_BBDEV_UL_POLL + retPoll, t1, t2);
+ t2 = MLogXRANTick();
+ MLogXRANTask(PID_XRAN_BBDEV_UL_POLL + retPoll, t1, t2);
}
}
if (ctx->bbdev_enc) {
- t1 = MLogTick();
+ t1 = MLogXRANTick();
retPoll = ctx->bbdev_enc();
if (retPoll == 1)
{
- t2 = MLogTick();
- MLogTask(PID_XRAN_BBDEV_DL_POLL + retPoll, t1, t2);
+ t2 = MLogXRANTick();
+ MLogXRANTask(PID_XRAN_BBDEV_DL_POLL + retPoll, t1, t2);
}
}
break;
}
- if (XRAN_STOPPED == xran_if_current_state)
- return -1;
+ if (XRAN_STOPPED == xran_if_current_state)
+ return -1;
if(p_io_cfg->io_sleep)
nanosleep(&sleeptime,NULL);
puts("Pkt processing thread finished.");
return 0;
}
-
int xran_process_delmeas_follow_up(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id);
void xran_initialize_ecpri_del_meas_port(struct xran_ecpri_del_meas_cmn* pCmn, struct xran_ecpri_del_meas_port* pPort,uint16_t full_init);
+int send_symbol_mult_section_ex(void* handle,
+ enum xran_pkt_dir direction,
+ uint16_t section_id,
+ struct rte_mbuf *mb,
+ uint8_t *data,
+ uint8_t compMeth,
+ uint8_t iqWidth,
+ const enum xran_input_byte_order iq_buf_byte_order,
+ uint8_t frame_id,
+ uint8_t subframe_id,
+ uint8_t slot_id,
+ uint8_t symbol_no,
+ int prb_start,
+ int prb_num,
+ uint8_t CC_ID,
+ uint8_t RU_Port_ID,
+ uint8_t seq_id);
+
int send_symbol_ex(void* handle,
enum xran_pkt_dir direction,
uint16_t section_id,
uint8_t RU_Port_ID,
uint8_t seq_id,
uint32_t do_copy,
- enum xran_comp_hdr_type staticEn);
-inline int32_t prepare_sf_slot_sym (enum xran_pkt_dir direction,
+ enum xran_comp_hdr_type staticEn,
+ uint16_t num_sections,
+ uint16_t iq_buffer_offset);
+int32_t prepare_sf_slot_sym (enum xran_pkt_dir direction,
uint8_t frame_id,
uint8_t subframe_id,
uint8_t slot_id,
uint16_t beam_id, uint8_t cc_id, uint8_t ru_port_id, uint8_t comp_method, uint8_t iqWidth, uint8_t seq_id, uint8_t symInc);
int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struct xran_section_gen_info *sect_geninfo, struct rte_mbuf *mbuf, struct xran_device_ctx *pxran_lib_ctx,
- uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id,
+ uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id, int tti,
uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint16_t occasionid, uint8_t seq_id);
struct xran_eaxcid_config *xran_get_conf_eAxC(void *pHandle);
int xran_register_cb_mbuf2ring(xran_ethdi_mbuf_send_fn mbuf_send_cp, xran_ethdi_mbuf_send_fn mbuf_send_up);
-uint16_t xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id);
+//uint16_t xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id);
uint8_t xran_get_seqid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id);
int32_t ring_processing_func(void* arg);
-int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx);
+int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx, enum xran_ran_tech xran_tech);
void xran_updateSfnSecStart(void);
uint32_t xran_slotid_convert(uint16_t slot_id, uint16_t dir);
#include "xran_compression.h"
#include "xran_dev.h"
-PSECTION_DB_TYPE p_sectiondb[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL};
+PSECTION_DB_TYPE p_sectiondb[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL,NULL, NULL, NULL, NULL};
static const uint8_t zeropad[XRAN_SECTIONEXT_ALIGN] = { 0, 0, 0, 0 };
static const uint8_t bitmask[] = { 0x00, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff };
return (XRAN_STATUS_SUCCESS);
}
+
+struct xran_section_info *
+xran_cp_get_section_info_ptr(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id)
+{
+ struct xran_sectioninfo_db *ptr;
+ struct xran_section_info *list;
+
+ ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id);
+ if(unlikely(ptr == NULL)) {
+ return NULL;
+ }
+
+ if(unlikely(ptr->cur_index >= XRAN_MAX_NUM_SECTIONS)) {
+ print_err("No more space to add section information!");
+ return NULL;
+ }
+
+ list = xran_get_section_info(ptr, ptr->cur_index);
+ if (list)
+ {
+ ptr->cur_index++;
+ return list;
+ }
+ else
+ {
+ print_err("Null list in section db\n!");
+ return NULL;
+ }
+
+}
+
+
+
int32_t
xran_cp_add_multisection_info(void *pHandle, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, struct xran_cp_gen_params *gen_info)
{
if (list)
{
for(i=0; i<num_sections; i++) {
- memcpy(&list[i], &gen_info->sections[i].info, sizeof(struct xran_section_info));
+ memcpy(&list[i], gen_info->sections[i].info, sizeof(struct xran_section_info));
ptr->cur_index++;
}
}
struct xran_section_info *
xran_cp_find_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, uint16_t section_id)
{
- int32_t index, num_index;
struct xran_sectioninfo_db *ptr;
ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id);
if(unlikely(ptr == NULL))
return (NULL);
- if(ptr->cur_index > XRAN_MAX_NUM_SECTIONS)
- num_index = XRAN_MAX_NUM_SECTIONS;
- else
- num_index = ptr->cur_index;
-
- for(index=0; index < num_index; index++) {
- if(ptr->list[index].id == section_id) {
- return (xran_get_section_info(ptr, index));
+ if(section_id > ptr->cur_index || section_id < 0)
+ {
+ print_err("No section ID in the list - %d, ptr->cur_index is %d", section_id, ptr->cur_index);
}
- }
-
- print_dbg("No section ID in the list - %d", section_id);
- return (NULL);
+ return (xran_get_section_info(ptr, section_id));
}
/**
int32_t
xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id)
{
- int32_t index;
struct xran_sectioninfo_db *ptr;
ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id);
int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination buffer */
uint16_t ext1_dst_len, /**< dest buffer size */
int16_t *p_bfw_iq_src, /**< source buffer of IQs */
- uint16_t rbNum, /* number RBs to ext1 chain */
- uint16_t bfwNumPerRb, /* number of bf weights per RB (i.e. antenna elements) */
- uint8_t bfwiqWidth, /* bit size of IQs */
- uint8_t bfwCompMeth) /* compression method */
+ struct xran_prb_elm *p_pRbMapElm)
{
struct xran_cp_radioapp_section_ext1 *p_ext1;
-
uint8_t *p_bfw_content = NULL;
int32_t parm_size = 0;
int32_t bfw_iq_bits = 0;
int32_t total_len = 0;
- int32_t comp_len = 0;
- uint8_t ext_flag = XRAN_EF_F_ANOTHER_ONE;
- int16_t idxRb = 0;
+ uint16_t idxSection = 0;
+ int32_t section_len = 0;
+ int16_t numCPSections = (p_pRbMapElm->bf_weight.numSetBFWs == 0 ? 1 : p_pRbMapElm->bf_weight.numSetBFWs);
+
int16_t cur_ext_len = 0;
int8_t *p_ext1_dst_cur = NULL;
+ int16_t bfwNumPerRb = p_pRbMapElm->bf_weight.nAntElmTRx;
+ uint8_t bfwiqWidth = p_pRbMapElm->bf_weight.bfwIqWidth;
+ uint8_t bfwCompMeth = p_pRbMapElm->bf_weight.bfwCompMeth;
+ struct xran_cp_radioapp_section1 *p_section1;
struct xranlib_compress_request bfp_com_req;
struct xranlib_compress_response bfp_com_rsp;
else
return (XRAN_STATUS_INVALID_PARAM);
- /* create extType=1 section for each RB */
- for (idxRb = 0; idxRb < rbNum; idxRb++) {
- print_dbg("%s RB %d\n", __FUNCTION__, idxRb);
+ /* create section for each PRB bundle */
+ for (idxSection = 0; idxSection < numCPSections ; idxSection++) {
+ print_dbg("%s Section %d\n", __FUNCTION__, idxSection);
if(total_len >= ext1_dst_len){
print_err("p_ext1_dst overflow\n");
- return -1;
+ return XRAN_STATUS_RESOURCE;
+ }
+
+ cur_ext_len = 0;
+ p_section1 = (struct xran_cp_radioapp_section1 *)p_ext1_dst_cur;
+ if(p_section1 == NULL) {
+ print_err("p_section is null!\n");
+ return (XRAN_STATUS_INVALID_PARAM);
}
- cur_ext_len = 0; /** populate one extType=1 section with BFW for 1 RB */
+ section_len = sizeof(struct xran_cp_radioapp_section1);
+
+ p_ext1_dst_cur = p_ext1_dst_cur + section_len;
+ total_len += section_len;
+
parm_size = sizeof(struct xran_cp_radioapp_section_ext1);
p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst_cur;
if(p_ext1 == NULL) {
cur_ext_len += parm_size;
- if(idxRb+1 == rbNum)
- ext_flag = XRAN_EF_F_LAST;
-
p_ext1->extType = XRAN_CP_SECTIONEXTCMD_1;
- p_ext1->ef = ext_flag;
+ p_ext1->ef = XRAN_EF_F_LAST; //only one ext-1 per CP section
p_ext1->bfwCompMeth = bfwCompMeth;
p_ext1->bfwIqWidth = XRAN_CONVERT_BFWIQWIDTH(bfwiqWidth);
print_dbg("req 0x%08p iqWidth %d\n",bfp_com_req.data_in, bfp_com_req.iqWidth);
- parm_size = 1; /* exponent as part of bfwCompParam 1 octet */
+ parm_size = 1; /* (reserved + exponent) as part of bfwCompParam 1 octet */
break;
case XRAN_BFWCOMPMETHOD_BLKSCALE:
rte_panic("XRAN_BFWCOMPMETHOD_BLKSCALE");
parm_size++;
print_dbg("copy BF W %p -> %p size %d \n", p_bfw_iq_src, p_bfw_content, parm_size);
- if (p_ext1->bfwIqWidth == 0 || p_ext1->bfwIqWidth == 16){
+
+ if (p_ext1->bfwCompMeth == XRAN_BFWCOMPMETHOD_NONE){ //5.4.7.1.1
memcpy(p_bfw_content, p_bfw_iq_src, parm_size);
} else {
bfp_com_rsp.data_out = (int8_t*)p_bfw_content;
if(xranlib_compress_bfw(&bfp_com_req, &bfp_com_rsp) == 0){
- comp_len = bfp_com_rsp.len;
- print_dbg("comp_len %d parm_size %d\n", comp_len, parm_size);
+ print_dbg("comp_len %d parm_size %d\n", bfp_com_rsp.len, parm_size);
} else {
print_err("compression failed\n");
return (XRAN_STATUS_FAIL);
parm_size = cur_ext_len % XRAN_SECTIONEXT_ALIGN;
if(parm_size) {
parm_size = XRAN_SECTIONEXT_ALIGN - parm_size;
- p_bfw_content = (uint8_t *)(p_bfw_content + parm_size);
memcpy(p_bfw_content, zeropad, RTE_MIN(parm_size, sizeof(zeropad)));
+ p_bfw_content += parm_size;
cur_ext_len += parm_size;
print_dbg("zeropad %d cur_ext_len %d\n", parm_size, cur_ext_len);
}
rte_panic("ext1 should be aligned on 4-bytes boundary");
p_ext1->extLen = cur_ext_len / XRAN_SECTIONEXT_ALIGN;
- print_dbg("[%d] %p iq %p p_ext1->extLen %d\n",idxRb, p_ext1, p_ext1+1, p_ext1->extLen);
+ print_dbg("%p iq %p p_ext1->extLen %d\n",p_ext1, p_ext1+1, p_ext1->extLen);
/* update for next RB */
p_ext1_dst_cur += cur_ext_len;
p_bfw_iq_src = p_bfw_iq_src + bfwNumPerRb*2;
total_len += cur_ext_len;
- }
+ } /*for(idxSection < numCPSections */
print_dbg("total_len %d\n", total_len);
return (total_len);
return (parm_size);
}
+static int32_t
+xran_prepare_sectionext_9(struct rte_mbuf *mbuf, struct xran_sectionext9_info * params, int32_t last_flag)
+{
+ struct xran_cp_radioapp_section_ext9 *ext9;
+ int32_t parm_size;
+
+ parm_size = sizeof(struct xran_cp_radioapp_section_ext9);
+ ext9 = (struct xran_cp_radioapp_section_ext9 *)rte_pktmbuf_append(mbuf, parm_size);
+ if(ext9 == NULL) {
+ print_err("Fail to allocate the space for section extension 9");
+ return(XRAN_STATUS_RESOURCE);
+ }
+
+ ext9->extType = XRAN_CP_SECTIONEXTCMD_9;
+ ext9->ef = last_flag;
+ ext9->extLen = parm_size / XRAN_SECTIONEXT_ALIGN;
+ ext9->technology = params->technology;
+ ext9->reserved = params->reserved;
+
+ *(uint32_t *)ext9 = rte_cpu_to_be_32(*(uint32_t*)ext9);
+
+ return (parm_size);
+}
+
static int32_t
xran_prepare_sectionext_5(struct rte_mbuf *mbuf, struct xran_sectionext5_info *params, int32_t last_flag)
{
/* Exclude headers can be present */
avail_len = mtu - ( RTE_PKTMBUF_HEADROOM \
+ sizeof(struct xran_ecpri_hdr) \
- + sizeof(struct xran_cp_radioapp_common_header) \
+ + sizeof(struct xran_cp_radioapp_section1_header) \
+ sizeof(struct xran_cp_radioapp_section1) \
+ sizeof(union xran_cp_radioapp_section_ext6) \
+ sizeof(union xran_cp_radioapp_section_ext10) );
hdr_len = ( RTE_PKTMBUF_HEADROOM \
+ sizeof(struct xran_ecpri_hdr) \
- + sizeof(struct xran_cp_radioapp_common_header) \
+ + sizeof(struct xran_cp_radioapp_section1_header) \
+ sizeof(struct xran_cp_radioapp_section1) \
+ exthdr_size );
return (hdr_len);
hdr_offset = xran_cp_get_hdroffset_section1(sizeof(union xran_cp_radioapp_section_ext11));
/* Copy BFWs to destination buffer */
- ptr = dst + hdr_offset + 2;
+ ptr = dst + hdr_offset;
switch(compMeth) {
/* No compression */
case XRAN_BFWCOMPMETHOD_NONE:
*/
int32_t xran_append_section_extensions(struct rte_mbuf *mbuf, struct xran_section_gen_info *params)
{
- int32_t i, ret;
+ int32_t i;
uint32_t totalen;
int32_t last_flag;
int32_t ext_size;
totalen = 0;
- ret = XRAN_STATUS_SUCCESS;
-
print_dbg("params->exDataSize %d\n", params->exDataSize);
for(i=0; i < params->exDataSize; i++) {
if(params->exData[i].data == NULL) {
print_err("Invalid parameter - extension data %d is NULL", i);
- ret = XRAN_STATUS_INVALID_PARAM;
continue;
}
case XRAN_CP_SECTIONEXTCMD_6:
ext_size = xran_prepare_sectionext_6(mbuf, params->exData[i].data, last_flag);
break;
+ case XRAN_CP_SECTIONEXTCMD_9:
+ ext_size = xran_prepare_sectionext_9(mbuf, params->exData[i].data, last_flag);
+ break;
case XRAN_CP_SECTIONEXTCMD_10:
ext_size = xran_prepare_sectionext_10(mbuf, params->exData[i].data, last_flag);
break;
break;
default:
print_err("Extension Type %d is not supported!", params->exData[i].type);
- ret = XRAN_STATUS_INVALID_PARAM;
ext_size = 0;
}
xran_prepare_section0(struct xran_cp_radioapp_section0 *section, struct xran_section_gen_info *params)
{
#if (XRAN_STRICT_PARM_CHECK)
- if(unlikely(params->info.numSymbol > XRAN_SYMBOLNUMBER_MAX)) {
- print_err("Invalid number of Symbols - %d", params->info.numSymbol);
+ if(unlikely(params->info->numSymbol > XRAN_SYMBOLNUMBER_MAX)) {
+ print_err("Invalid number of Symbols - %d", params->info->numSymbol);
return (XRAN_STATUS_INVALID_PARAM);
}
#endif
- section->hdr.u1.common.sectionId = params->info.id;
- section->hdr.u1.common.rb = params->info.rb;
- section->hdr.u1.common.symInc = params->info.symInc;
- section->hdr.u1.common.startPrbc = params->info.startPrbc;
- section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc);
+ section->hdr.u1.common.sectionId = params->info->id;
+ section->hdr.u1.common.rb = params->info->rb;
+ section->hdr.u1.common.symInc = params->info->symInc;
+ section->hdr.u1.common.startPrbc = params->info->startPrbc;
+ section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info->numPrbc);
- section->hdr.u.s0.reMask = params->info.reMask;
- section->hdr.u.s0.numSymbol = params->info.numSymbol;
+ section->hdr.u.s0.reMask = params->info->reMask;
+ section->hdr.u.s0.numSymbol = params->info->numSymbol;
section->hdr.u.s0.reserved = 0;
// for network byte order
struct xran_section_gen_info *params)
{
#if (XRAN_STRICT_PARM_CHECK)
- if(unlikely(params->info.numSymbol > XRAN_SYMBOLNUMBER_MAX)) {
- print_err("Invalid number of Symbols - %d", params->info.numSymbol);
+ if(unlikely(params->info->numSymbol > XRAN_SYMBOLNUMBER_MAX)) {
+ print_err("Invalid number of Symbols - %d", params->info->numSymbol);
return (XRAN_STATUS_INVALID_PARAM);
}
#endif
- /*section->hdr.u1.common.sectionId = params->info.id;
- section->hdr.u1.common.rb = params->info.rb;
- section->hdr.u1.common.symInc = params->info.symInc;
- section->hdr.u1.common.startPrbc = params->info.startPrbc;
- section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc);
-
- section->hdr.u.s1.reMask = params->info.reMask;
- section->hdr.u.s1.numSymbol = params->info.numSymbol;
- section->hdr.u.s1.beamId = params->info.beamId;
- section->hdr.u.s1.ef = params->info.ef;*/
-
- section->hdr.u.first_4byte = (params->info.reMask << xran_cp_radioapp_sec_hdr_sc_ReMask)
- | (params->info.numSymbol << xran_cp_radioapp_sec_hdr_sc_NumSym)
- | (params->info.ef << xran_cp_radioapp_sec_hdr_sc_Ef)
- | (params->info.beamId << xran_cp_radioapp_sec_hdr_sc_BeamID);
- section->hdr.u1.second_4byte = (params->info.id << xran_cp_radioapp_sec_hdr_c_SecId)
- | (params->info.rb << xran_cp_radioapp_sec_hdr_c_RB)
- | (params->info.symInc << xran_cp_radioapp_sec_hdr_c_SymInc)
- | (params->info.startPrbc << xran_cp_radioapp_sec_hdr_c_StartPrbc)
- | ((XRAN_CONVERT_NUMPRBC(params->info.numPrbc)) << xran_cp_radioapp_sec_hdr_c_NumPrbc);
+ /*section->hdr.u1.common.sectionId = params->info->id;
+ section->hdr.u1.common.rb = params->info->rb;
+ section->hdr.u1.common.symInc = params->info->symInc;
+ section->hdr.u1.common.startPrbc = params->info->startPrbc;
+ section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info->numPrbc);
+
+ section->hdr.u.s1.reMask = params->info->reMask;
+ section->hdr.u.s1.numSymbol = params->info->numSymbol;
+ section->hdr.u.s1.beamId = params->info->beamId;
+ section->hdr.u.s1.ef = params->info->ef;*/
+
+ section->hdr.u.first_4byte = (params->info->reMask << xran_cp_radioapp_sec_hdr_sc_ReMask)
+ | (params->info->numSymbol << xran_cp_radioapp_sec_hdr_sc_NumSym)
+ | (params->info->ef << xran_cp_radioapp_sec_hdr_sc_Ef)
+ | (params->info->beamId << xran_cp_radioapp_sec_hdr_sc_BeamID);
+ section->hdr.u1.second_4byte = (params->info->id << xran_cp_radioapp_sec_hdr_c_SecId)
+ | (params->info->rb << xran_cp_radioapp_sec_hdr_c_RB)
+ | (params->info->symInc << xran_cp_radioapp_sec_hdr_c_SymInc)
+ | (params->info->startPrbc << xran_cp_radioapp_sec_hdr_c_StartPrbc)
+ | ((XRAN_CONVERT_NUMPRBC(params->info->numPrbc)) << xran_cp_radioapp_sec_hdr_c_NumPrbc);
// for network byte order
*((uint64_t *)section) = rte_cpu_to_be_64(*((uint64_t *)section));
struct xran_section_gen_info *params)
{
#if (XRAN_STRICT_PARM_CHECK)
- if(unlikely(params->info.numSymbol > XRAN_SYMBOLNUMBER_MAX)) {
- print_err("Invalid number of Symbols - %d", params->info.numSymbol);
+ if(unlikely(params->info->numSymbol > XRAN_SYMBOLNUMBER_MAX)) {
+ print_err("Invalid number of Symbols - %d", params->info->numSymbol);
return (XRAN_STATUS_INVALID_PARAM);
}
#endif
- /*section->hdr.u1.common.sectionId = params->info.id;
- section->hdr.u1.common.rb = params->info.rb;
- section->hdr.u1.common.symInc = params->info.symInc;
- section->hdr.u1.common.startPrbc = params->info.startPrbc;
- section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc);
-
- section->hdr.u.s3.reMask = params->info.reMask;
- section->hdr.u.s3.numSymbol = params->info.numSymbol;
- section->hdr.u.s3.beamId = params->info.beamId;
- section->hdr.u.s3.ef = params->info.ef;*/
-
- section->hdr.u.first_4byte = (params->info.reMask << xran_cp_radioapp_sec_hdr_sc_ReMask)
- | (params->info.numSymbol << xran_cp_radioapp_sec_hdr_sc_NumSym)
- | (params->info.ef << xran_cp_radioapp_sec_hdr_sc_Ef)
- | (params->info.beamId << xran_cp_radioapp_sec_hdr_sc_BeamID);
- section->hdr.u1.second_4byte = (params->info.id << xran_cp_radioapp_sec_hdr_c_SecId)
- | (params->info.rb << xran_cp_radioapp_sec_hdr_c_RB)
- | (params->info.symInc << xran_cp_radioapp_sec_hdr_c_SymInc)
- | (params->info.startPrbc << xran_cp_radioapp_sec_hdr_c_StartPrbc)
- | ((XRAN_CONVERT_NUMPRBC(params->info.numPrbc)) << xran_cp_radioapp_sec_hdr_c_NumPrbc);
-
- section->freqOffset = rte_cpu_to_be_32(params->info.freqOffset)>>8;
+ /*section->hdr.u1.common.sectionId = params->info->id;
+ section->hdr.u1.common.rb = params->info->rb;
+ section->hdr.u1.common.symInc = params->info->symInc;
+ section->hdr.u1.common.startPrbc = params->info->startPrbc;
+ section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info->numPrbc);
+
+ section->hdr.u.s3.reMask = params->info->reMask;
+ section->hdr.u.s3.numSymbol = params->info->numSymbol;
+ section->hdr.u.s3.beamId = params->info->beamId;
+ section->hdr.u.s3.ef = params->info->ef;*/
+
+ section->hdr.u.first_4byte = (params->info->reMask << xran_cp_radioapp_sec_hdr_sc_ReMask)
+ | (params->info->numSymbol << xran_cp_radioapp_sec_hdr_sc_NumSym)
+ | (params->info->ef << xran_cp_radioapp_sec_hdr_sc_Ef)
+ | (params->info->beamId << xran_cp_radioapp_sec_hdr_sc_BeamID);
+ section->hdr.u1.second_4byte = (params->info->id << xran_cp_radioapp_sec_hdr_c_SecId)
+ | (params->info->rb << xran_cp_radioapp_sec_hdr_c_RB)
+ | (params->info->symInc << xran_cp_radioapp_sec_hdr_c_SymInc)
+ | (params->info->startPrbc << xran_cp_radioapp_sec_hdr_c_StartPrbc)
+ | ((XRAN_CONVERT_NUMPRBC(params->info->numPrbc)) << xran_cp_radioapp_sec_hdr_c_NumPrbc);
+
+ section->freqOffset = rte_cpu_to_be_32(params->info->freqOffset)>>8;
section->reserved = 0;
/* for network byte order (header, 8 bytes) */
* XRAN_STATUS_RESOURCE if failed to allocate the space to packet buffer
*/
int32_t
-xran_append_control_section(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params)
+xran_append_control_section(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params,uint16_t start_sect_id)
{
- int32_t i, ret, ext_flag;
+ int32_t i, ret;
uint32_t totalen;
void *section;
int32_t section_size;
return (XRAN_STATUS_INVALID_PARAM);
}
- for(i=0; i < params->numSections; i++) {
+ for(i=start_sect_id; i < (start_sect_id + params->numSections); i++) {
section = rte_pktmbuf_append(mbuf, section_size);
if(section == NULL) {
print_err("Fail to allocate the space for section[%d]!", i);
return (XRAN_STATUS_RESOURCE);
}
- print_dbg("%s %d ef %d\n", __FUNCTION__, i, params->sections[i].info.ef);
+ print_dbg("%s %d ef %d\n", __FUNCTION__, i, params->sections[i].info->ef);
ret = xran_prepare_section_func((void *)section,
(void *)¶ms->sections[i]);
if(ret < 0){
}
totalen += section_size;
- if(params->sections[i].info.ef) {
- print_dbg("sections[%d].info.ef %d exDataSize %d type %d\n", i, params->sections[i].info.ef,
+ if(params->sections[i].info->ef) {
+ print_dbg("sections[%d].info.ef %d exDataSize %d type %d\n", i, params->sections[i].info->ef,
params->sections[i].exDataSize, params->sections[i].exData[0].type);
ret = xran_append_section_extensions(mbuf, ¶ms->sections[i]);
if(ret < 0)
xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf,
struct xran_cp_gen_params *params,
uint8_t CC_ID, uint8_t Ant_ID,
- uint8_t seq_id)
+ uint8_t seq_id,
+ uint16_t start_sect_id)
{
int32_t ret;
uint32_t payloadlen;
}
payloadlen += ret;
- ret = xran_append_control_section(mbuf, params);
+ ret = xran_append_control_section(mbuf, params,start_sect_id);
if(ret < 0) {
print_err("%s %d\n", __FUNCTION__, ret);
return (ret);
int32_t total_len;
struct xran_cp_radioapp_section_ext1 *ext1;
uint8_t *data;
- int32_t parm_size, iq_size;
+ int32_t parm_size = 0, iq_size, iq_size_bytes;
int32_t N;
void *pHandle;
len += sizeof(struct xran_cp_radioapp_section_ext1);
data += sizeof(struct xran_cp_radioapp_section_ext1);
+ extinfo->p_bfwIQ = (int8_t*)(data);
switch(ext1->bfwCompMeth) {
case XRAN_BFWCOMPMETHOD_NONE:
len += parm_size;
data += parm_size;
+ iq_size_bytes = parm_size;
/* Get BF weights */
iq_size = N * extinfo->bfwIqWidth * 2; // total in bits
parm_size = iq_size>>3; // total in bytes (/8)
if(iq_size%8) parm_size++; // round up
+ iq_size_bytes += parm_size;
//memcpy(data, extinfo->p_bfwIQ, parm_size);
- extinfo->p_bfwIQ = (int16_t*)data;
+ extinfo->bfwIQ_sz = iq_size_bytes;
len += parm_size;
len += (XRAN_SECTIONEXT_ALIGN - parm_size);
if(len != total_len) {
- // TODO: fix this print_err("The size of extension 1 is not correct! [%d:%d]", len, total_len);
+ print_err("The size of extension 1 is not correct! [%d:%d]", len, total_len);
}
return (total_len);
xran_parse_section_ext5(void *ext,
struct xran_sectionext5_info *extinfo)
{
- int32_t len;
struct xran_cp_radioapp_section_ext_hdr *ext_hdr;
struct xran_cp_radioapp_section_ext5 ext5;
int32_t parm_size;
parm_size = XRAN_MAX_MODCOMP_ADDPARMS;
}
- len = 0;
data = (uint8_t *)(ext_hdr + 1);
i = 0;
return (total_len);
}
+int32_t
+xran_parse_section_ext9(void *ext,
+ struct xran_sectionext9_info *extinfo, struct xran_cp_recv_params *result)
+{
+ int32_t len = 0;
+ int32_t total_len;
+ int8_t dssSlot = 0;
+ int8_t presumed_technology = -1;
+ struct xran_cp_radioapp_section_ext9 *ext9;
+
+ ext9 = (struct xran_cp_radioapp_section_ext9 *)ext;
+ *(uint32_t *)ext9 = rte_be_to_cpu_32(*(uint32_t *)ext9);
+
+ total_len = ext9->extLen * XRAN_SECTIONEXT_ALIGN;
+
+ if(result) {
+ dssSlot = result->tti % result->dssPeriod;
+ presumed_technology = result->technology_arr[dssSlot];
+ } else {
+ print_err("\nTechnology verification parameters not received");
+ // return (-1);
+ }
+
+ if(presumed_technology != ext9->technology) {
+ print_err("\nWrong technology recieved! [%d,%d]", presumed_technology, ext9->technology);
+ // return (-1);
+ }
+
+ extinfo->technology = ext9->technology;
+ extinfo->reserved = ext9->reserved;
+
+ len += sizeof(struct xran_cp_radioapp_section_ext9);
+ if(len != total_len) {
+ print_err("\nThe size of extension 9 is not correct! [%d:%d]", len, total_len);
+ }
+
+ return (total_len);
+}
+
+
int32_t
xran_parse_section_ext10(void *ext,
struct xran_sectionext10_info *extinfo)
len += (XRAN_SECTIONEXT_ALIGN - parm_size);
if(len != total_len) {
- print_err("The size of extension 11 is not correct! [%d:%d]", len, total_len);
+ //print_err("The size of extension 11 is not correct! [%d:%d]", len, total_len);
}
return (total_len);
int32_t
xran_parse_section_extension(struct rte_mbuf *mbuf,
- void *ext,
- struct xran_section_recv_info *section)
+ void *ext, struct xran_cp_recv_params *result,
+ int32_t section_idx)
{
+ struct xran_section_recv_info *section = &result->sections[section_idx];
int32_t total_len, len, numext;
uint8_t *ptr;
int32_t flag_last;
section->exts[numext].type = ext_type;
switch(ext_type) {
case XRAN_CP_SECTIONEXTCMD_1:
+ result->ext1count++;
len = xran_parse_section_ext1(ptr, §ion->exts[numext].u.ext1);
break;
case XRAN_CP_SECTIONEXTCMD_2:
case XRAN_CP_SECTIONEXTCMD_6:
len = xran_parse_section_ext6(ptr, §ion->exts[numext].u.ext6);
break;
+ case XRAN_CP_SECTIONEXTCMD_9:
+ len = xran_parse_section_ext9(ptr, §ion->exts[numext].u.ext9, result);
+ break;
case XRAN_CP_SECTIONEXTCMD_10:
len = xran_parse_section_ext10(ptr, §ion->exts[numext].u.ext10);
break;
int32_t
xran_parse_cp_pkt(struct rte_mbuf *mbuf,
struct xran_cp_recv_params *result,
- struct xran_recv_packet_info *pkt_info)
+ struct xran_recv_packet_info *pkt_info, void* handle, uint32_t *mb_free)
{
struct xran_ecpri_hdr *ecpri_hdr;
struct xran_cp_radioapp_common_header *apphdr;
- int32_t i, ret;
- int32_t extlen;
-
+ struct xran_common_counters* pCnt = NULL;
+ struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_map *pRbMap_desc = NULL;
+ struct xran_prb_elm * prbMapElm = NULL;
+ struct rte_mbuf *mb = NULL;
+ int32_t i, j, ret, extlen;
+ int tti = 0,interval = 0;
+ uint8_t idx = 0, ctx_id = 0;
+ struct xran_device_ctx * p_dev_ctx = NULL;
+ struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)handle;
+ if(unlikely(p_xran_dev_ctx == NULL)){
+ print_err("p_xran_dev_ctx is NULL\n");
+ return XRAN_STATUS_INVALID_PARAM;
+ }
+ p_dev_ctx = xran_dev_get_ctx();
ret = xran_parse_ecpri_hdr(mbuf, &ecpri_hdr, pkt_info);
+ struct xran_eaxc_info eaxc = pkt_info->eaxc;
+ struct xran_section_info *info = NULL;
if(ret < 0 && ecpri_hdr == NULL)
return (XRAN_STATUS_INVALID_PACKET);
/* Process radio header. */
apphdr = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_ecpri_hdr));
- if(apphdr == NULL) {
- print_err("Invalid packet - radio app hedaer!");
+ if(unlikely(apphdr == NULL)) {
+ print_err("Invalid packet - radio app header!");
return (XRAN_STATUS_INVALID_PACKET);
}
result->hdr.startSymId = apphdr->field.startSymbolId;
result->sectionType = apphdr->sectionType;
result->numSections = apphdr->numOfSections;
+ result->ext1count = 0;
+ interval = p_xran_dev_ctx->interval_us_local;
+ tti = apphdr->field.frameId * SLOTS_PER_SYSTEMFRAME(interval) + apphdr->field.subframeId * SLOTNUM_PER_SUBFRAME(interval) + apphdr->field.slotId;
+ result->tti = tti;
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
#if 0
printf("[CP%5d] eAxC[%d:%d:%02d:%02d] %s seq[%03d-%03d-%d] sec[%d-%d] frame[%3d-%2d-%2d] sym%02d\n",
pkt_info->payload_len,
result->hdr.compMeth = hdr->udComp.udCompMeth;
section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section1_header));
- if(section == NULL) {
+ if(unlikely(section == NULL)) {
print_err("Invalid packet: section type1 - radio app hedaer!");
return (XRAN_STATUS_INVALID_PACKET);
}
section = (void *)rte_pktmbuf_adj(mbuf,
sizeof(struct xran_cp_radioapp_section1));
- if(section == NULL) {
+ if(unlikely(section == NULL)) {
print_err("Invalid packet: section type1 - number of section [%d:%d]!",
result->numSections, i);
result->numSections = i;
ret = XRAN_STATUS_INVALID_PACKET;
break;
}
+ if (eaxc.ruPortId < p_xran_dev_ctx->srs_cfg.eAxC_offset)
+ {
+ struct xran_flat_buffer *pBuffer = NULL;
+ if(result->dir == 1)
+ pBuffer = p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][eaxc.ccId][eaxc.ruPortId].sBufferList.pBuffers;
+ else if(result->dir == 0)
+ pBuffer = p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][eaxc.ccId][eaxc.ruPortId].sBufferList.pBuffers;
+ if(pBuffer)
+ pRbMap = (struct xran_prb_map *)pBuffer->pData;
+ if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][eaxc.ccId][eaxc.ruPortId].sBufferList.pBuffers)
+ pRbMap_desc = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][eaxc.ccId][eaxc.ruPortId].sBufferList.pBuffers->pData;
+
+ if(i == 0){
+ if((pRbMap_desc != NULL) && (pRbMap_desc->nPrbElm <= p_xran_dev_ctx->sectiondb_elm[ctx_id][result->dir][eaxc.ccId][eaxc.ruPortId])){
+ p_xran_dev_ctx->sectiondb_elm[ctx_id][result->dir][eaxc.ccId][eaxc.ruPortId]=0;
+ xran_cp_reset_section_info(handle, result->dir, eaxc.ccId, eaxc.ruPortId, ctx_id);
+ }
+ idx = p_xran_dev_ctx->sectiondb_elm[ctx_id][result->dir][eaxc.ccId][eaxc.ruPortId]++;
+
+ if(p_dev_ctx){
+ result->numSetBFW = p_dev_ctx->numSetBFWs_arr[idx];
+ if(likely(pRbMap!=NULL)){
+ prbMapElm = &pRbMap->prbMap[idx];
+ mb = prbMapElm->bf_weight.p_ext_start;
+ if(mb){
+ rte_pktmbuf_free(mb);
+ }
+ prbMapElm->bf_weight.p_ext_start = mbuf;
+ prbMapElm->bf_weight.p_ext_section = (void *)section;
+ *mb_free = MBUF_KEEP;
+ }
+ }
+ }
+ info = xran_cp_get_section_info_ptr(handle, result->dir, eaxc.ccId, eaxc.ruPortId, ctx_id);
+ if(likely(info != NULL))
+ {
+ info->prbElemBegin = (i == 0 ) ? 1 : 0;
+ info->prbElemEnd = (i == (result->numSections -1)) ? 1 : 0;
+ info->ef = result->sections[i].info.ef;
+ info->startPrbc = result->sections[i].info.startPrbc;
+ info->numPrbc = result->sections[i].info.numPrbc;
+ info->type = result->sections[i].info.type;
+ info->startSymId = result->hdr.startSymId;
+ info->iqWidth = result->hdr.iqWidth;
+ info->compMeth = result->hdr.compMeth;
+ info->id = result->sections[i].info.id;
+ info->rb = XRAN_RBIND_EVERY;
+ info->numSymbol = result->sections[i].info.numSymbol;
+ info->reMask = 0xfff;
+ info->beamId = result->sections[i].info.beamId;
+ info->symInc = XRAN_SYMBOLNUMBER_NOTINC;
+
+ int loc_sym=0;
+ if(likely(pRbMap_desc != NULL)){
+ prbMapElm = &pRbMap_desc->prbMap[idx];
+ for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++)
+ {
+ struct xran_section_desc *p_sec_desc = &prbMapElm->sec_desc[loc_sym][0];
+
+ if(likely(p_sec_desc!=NULL))
+ {
+ info->sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset;
+ info->sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len;
+
+ p_sec_desc->section_id = info->id;
+ }
+ else
+ {
+ print_err("section desc is NULL\n");
+ }
+ } /* for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) */
+ }
+ }
if(result->sections[i].info.ef) {
- // parse section extension
- extlen = xran_parse_section_extension(mbuf, (void *)section, &result->sections[i]);
+ result->dssPeriod = p_xran_dev_ctx->dssPeriod;
+ for( j=0; j< p_xran_dev_ctx->dssPeriod; j++) {
+ result->technology_arr[j] = p_xran_dev_ctx->technology[j];
+ }
+ extlen = xran_parse_section_extension(mbuf, (void *)section, result, i);
if(extlen > 0) {
section = (void *)rte_pktmbuf_adj(mbuf, extlen);
- if(section == NULL) {
+ if(unlikely(section == NULL)) {
print_err("Invalid packet: section type1 - section extension [%d]!", i);
ret = XRAN_STATUS_INVALID_PACKET;
break;
}
else extlen = 0;
}
+ else if((eaxc.ruPortId >= p_xran_dev_ctx->srs_cfg.eAxC_offset) && p_xran_dev_ctx->fh_cfg.srsEnable){
+ int32_t ant_id = ((eaxc.ruPortId - p_xran_dev_ctx->srs_cfg.eAxC_offset) & 0x3F); /*Klocwork fix*/
+ if(p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][eaxc.ccId][ant_id].sBufferList.pBuffers){
+ pRbMap_desc = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][eaxc.ccId][ant_id].sBufferList.pBuffers->pData;
+ }
+ if(i == 0){
+ if((pRbMap_desc != NULL) && (pRbMap_desc->nPrbElm <= p_xran_dev_ctx->sectiondb_elm[ctx_id][result->dir][eaxc.ccId][eaxc.ruPortId])){
+ p_xran_dev_ctx->sectiondb_elm[ctx_id][result->dir][eaxc.ccId][eaxc.ruPortId]=0;
+ xran_cp_reset_section_info(handle, result->dir, eaxc.ccId, eaxc.ruPortId, ctx_id);
+ }
+ idx = p_xran_dev_ctx->sectiondb_elm[ctx_id][result->dir][eaxc.ccId][eaxc.ruPortId]++;
+ }
+ info = xran_cp_get_section_info_ptr(handle, result->dir, eaxc.ccId, eaxc.ruPortId, ctx_id);
+ if(likely(info != NULL))
+ {
+ info->prbElemBegin = (i == 0 ) ? 1 : 0;
+ info->prbElemEnd = (i == (result->numSections -1)) ? 1 : 0;
+ info->ef = result->sections[i].info.ef;
+ info->type = result->sections[i].info.type;
+ info->startSymId = result->hdr.startSymId;
+ info->iqWidth = result->hdr.iqWidth;
+ info->compMeth = result->hdr.compMeth;
+ info->id = result->sections[i].info.id;
+ info->rb = XRAN_RBIND_EVERY;
+ info->numSymbol = result->sections[i].info.numSymbol;
+ info->reMask = 0xfff;
+ info->beamId = result->sections[i].info.beamId;
+ info->symInc = XRAN_SYMBOLNUMBER_NOTINC;
+ int loc_sym=0;
+ if(likely(pRbMap_desc != NULL)){
+ prbMapElm = &pRbMap_desc->prbMap[idx];
+ info->startPrbc = prbMapElm->nRBStart;
+ info->numPrbc = prbMapElm->nRBSize;
+
+ struct xran_section_desc *p_sec_desc = NULL;
+ for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++)
+ {
+ p_sec_desc = &prbMapElm->sec_desc[loc_sym][0];
+
+ if(likely(p_sec_desc!=NULL))
+ {
+ info->sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset;
+ info->sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len;
+ p_sec_desc->section_id = info->id;
+ }
+ else
+ {
+ print_err("section desc is NULL\n");
+ }
+ } /* for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) */
+ }
+ }
+ /*Assuming SRS CP will not have extension, removed the ef flag check and extension processing*/
+ }
+ }
+ pCnt = &p_xran_dev_ctx->fh_counters;
+ /* SRS should not have extension */
+ if(pCnt && (result->sections[0].info.ef) && (result->sections[0].exts[0].type == 1) && (result->numSections != result->numSetBFW) && (result->ext1count != result->numSetBFW)){
+ print_err("extension 1 is not Valid! [%d:%d:%d]", result->numSections, result->numSetBFW, result->ext1count);
+ pCnt->rx_invalid_ext1_packets++;
+ }
}
break;
if(result->sections[i].info.ef) {
// parse section extension
- extlen = xran_parse_section_extension(mbuf, (void *)section, &result->sections[i]);
+ extlen = xran_parse_section_extension(mbuf, (void *)section, result, i);
if(extlen > 0) {
section = (void *)rte_pktmbuf_adj(mbuf, extlen);
if(section == NULL) {
#include <rte_memzone.h>
#include <rte_mbuf.h>
#include <rte_ring.h>
+#include <rte_malloc.h>
#include "xran_fh_o_du.h"
#include "xran_dev.h"
#include "xran_frame_struct.h"
#include "xran_printf.h"
-#include "xran_app_frag.h"
#include "xran_cp_proc.h"
#include "xran_tx_proc.h"
//////////////////////////////////////////
// For RU emulation
-struct xran_section_recv_info *recvSections[XRAN_PORTS_NUM] = {NULL,NULL,NULL,NULL};
+struct xran_section_recv_info *recvSections[XRAN_PORTS_NUM] = {NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL};
struct xran_cp_recv_params recvCpInfo[XRAN_PORTS_NUM];
+extern int32_t first_call;
+
static void
extbuf_free_callback(void *addr __rte_unused, void *opaque __rte_unused)
{
int32_t
process_cplane(struct rte_mbuf *pkt, void* handle)
{
+ uint32_t mb_free = MBUF_FREE;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)handle;
- if(p_xran_dev_ctx) {
+ if(p_xran_dev_ctx && xran_if_current_state == XRAN_RUNNING) {
if(xran_dev_get_ctx_by_id(0)->fh_cfg.debugStop) /* check CP with standard tests only */
- xran_parse_cp_pkt(pkt, &recvCpInfo[p_xran_dev_ctx->xran_port_id], &parse_recv[p_xran_dev_ctx->xran_port_id]);
+ xran_parse_cp_pkt(pkt, &recvCpInfo[p_xran_dev_ctx->xran_port_id], &parse_recv[p_xran_dev_ctx->xran_port_id],(void*)p_xran_dev_ctx, &mb_free);
}
-
- return (MBUF_FREE);
+ return (mb_free);
}
int32_t
}
struct rte_mbuf *
-xran_attach_cp_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len,
+xran_attach_cp_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start/*ext_start*/, int8_t* p_ext_buff/*ext-section*/, uint16_t ext_buff_len,
struct rte_mbuf_ext_shared_info * p_share_data)
{
struct rte_mbuf *mb_oran_hdr_ext = NULL;
- struct rte_mbuf *tmp = NULL;
+ //struct rte_mbuf *tmp = NULL;
int8_t *ext_buff = NULL;
rte_iova_t ext_buff_iova = 0;
ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM +
sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_section1_header) +
- sizeof(struct xran_cp_radioapp_section1));
+ sizeof(struct xran_cp_radioapp_section1_header));
ext_buff_len += (RTE_PKTMBUF_HEADROOM +
sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_section1_header) +
- sizeof(struct xran_cp_radioapp_section1)) + 18;
+ sizeof(struct xran_cp_radioapp_section1_header) + 18);
// mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_small);
mb_oran_hdr_ext = xran_ethdi_mbuf_indir_alloc();
return mb_oran_hdr_ext;
}
+/* TO DO: __thread is slow. We should allocate global 2D array and index it using current core index
+ * for better performance.
+ */
+__thread struct xran_section_gen_info sect_geninfo[XRAN_MAX_SECTIONS_PER_SLOT];
+
int32_t
xran_cp_create_and_send_section(void *pHandle, uint8_t ru_port_id, int dir, int tti, int cc_id,
- struct xran_prb_map *prbMap, enum xran_category category, uint8_t ctx_id)
+ struct xran_prb_map *prbMap, struct xran_prb_elm_proc_info_t *prbElmProcInfo, enum xran_category category, uint8_t ctx_id)
{
int32_t ret = 0;
struct xran_device_ctx *p_x_ctx = (struct xran_device_ctx *)pHandle;
struct xran_common_counters *pCnt = &p_x_ctx->fh_counters;
struct xran_cp_gen_params params;
- struct xran_section_gen_info sect_geninfo[1];
struct rte_mbuf *mbuf;
uint32_t interval = p_x_ctx->interval_us_local;
uint8_t PortId = p_x_ctx->xran_port_id;
+ int16_t numCPSections=0, ext_offset=0, start_sect_id=0;
-
- uint32_t i, j, loc_sym;
+ uint32_t i, j, loc_sym,idx;
uint32_t nsection = 0;
struct xran_prb_elm *pPrbMapElem = NULL;
- struct xran_prb_elm *pPrbMapElemPrev = NULL;
+ // struct xran_prb_elm *pPrbMapElemPrev = NULL;
uint32_t slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval));
uint32_t subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
uint32_t frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
uint8_t seq_id = 0;
- uint16_t vf_id = 0;
+ uint16_t vf_id = 0 , curr_sec_id = 0 , prb_per_section, start_Prb;
+ int32_t startSym = 0, numSyms = 0;
- int next;
+ int next=0;
struct xran_sectionext1_info ext1;
struct xran_sectionext4_info ext4 = {0};
+ struct xran_sectionext9_info ext9;
struct xran_sectionext11_info ext11;
- //frame_id = (frame_id & 0xff); /* ORAN frameId, 8 bits, [0, 255] */
- frame_id = ((frame_id + ((0 == tti)?NUM_OF_FRAMES_PER_SECOND:0)) & 0xff); /* ORAN frameId, 8 bits, [0, 255] */
+ frame_id = (frame_id & 0xff); /* ORAN frameId, 8 bits, [0, 255] */
+ if(unlikely((category != XRAN_CATEGORY_A) && (category != XRAN_CATEGORY_B)))
+ {
+ print_err("Unsupported Category %d\n", category);
+ return (-1);
+ }
+
+ /* Generate a C-Plane message per each section,
+ * not a C-Plane message with multi sections */
+ if(0 == p_x_ctx->RunSlotPrbMapBySymbolEnable)
+ {
if(prbMap) {
+
+ nsection = prbMap->nPrbElm;
+ i=0;
+ if(XRAN_DIR_DL == dir)
+ {
+ if(0 == p_x_ctx->numSymsForDlCP)
+ {
+ print_dbg("No symbol available for DL CP transmission\n");
+ return (-1);
+ }
+
+ if(prbMap->nPrbElm == prbElmProcInfo->nPrbElmProcessed && 0 != prbElmProcInfo->numSymsRemaining)
+ {
+ prbElmProcInfo->numSymsRemaining--;
+ print_dbg("All sections already processed\n");
+ return (-1);
+ }
+
+ if(0== prbElmProcInfo->numSymsRemaining)
+ { /* new slot */
+ prbElmProcInfo->numSymsRemaining = p_x_ctx->numSymsForDlCP;
+ prbElmProcInfo->nPrbElmPerSym = prbMap->nPrbElm/p_x_ctx->numSymsForDlCP;
+ prbElmProcInfo->nPrbElmProcessed = 0;
+ }
+
+ if(1 == prbElmProcInfo->numSymsRemaining)
+ {/* last symbol:: send all remaining */
nsection = prbMap->nPrbElm;
+ }
+ else
+ {
+ if(0 == prbElmProcInfo->nPrbElmPerSym)
+ nsection=prbElmProcInfo->nPrbElmProcessed + 1;
+ else
+ nsection = prbElmProcInfo->nPrbElmProcessed + prbElmProcInfo->nPrbElmPerSym;
+ }
+
+ i=prbElmProcInfo->nPrbElmProcessed;
+ prbElmProcInfo->numSymsRemaining--;
+
+ } //dir = DL
+ else
+ {
+ nsection = prbMap->nPrbElm;
+ i=0;
+ } //dir = UL
+
pPrbMapElem = &prbMap->prbMap[0];
- } else {
+ }
+ else
+ {
print_err("prbMap is NULL\n");
return (-1);
}
+
+ curr_sec_id = 0;
+ if(pPrbMapElem->bf_weight.extType == 1)
+ {
+ for(j=0;j<i;j++)
+ curr_sec_id += prbMap->prbMap[j].bf_weight.numSetBFWs;
+ }
+ else
+ curr_sec_id = i;
+
+ // start_id=curr_sec_id;
+ uint8_t generateCpPkt=0;
+ uint8_t replacePrbStartNSize=0; /* In case of application fragmentation, we send 1 cplane packets for multiple
+ uplane packets i.e. 1 cp packet for multiple PRBs. This flag is used to
+ achieve that by setting different values for cp packet preparation and for
+ cp-up database update */
+
/* Generate a C-Plane message per each section,
* not a C-Plane message with multi sections */
- for (i = 0; i < nsection; i++) {
+ for (; i < nsection; i++) {
int startSym, numSyms;
pPrbMapElem = &prbMap->prbMap[i];
+ prb_per_section = pPrbMapElem->bf_weight.numBundPrb;
+ start_Prb = pPrbMapElem->nRBStart;
+
+ if((pPrbMapElem->bf_weight.extType == 1) &&
+ (((i+1)<nsection && prbMap->prbMap[i+1].IsNewSect==1) ||
+ (i+1) == nsection))
+ { /*ext1*/
+ generateCpPkt=1;
+ }
+ else if(pPrbMapElem->IsNewSect)
+ generateCpPkt=1;
+ else
+ generateCpPkt=0;
+
/* For Special Subframe,
* Check validity of given symbol range with slot configuration
* and adjust symbol range accordingly. */
if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_FDD) != 1
- && xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1) {
+ && xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ {
/* This function cannot handle two or more groups of consecutive same type of symbol.
* If there are two or more, then it might cause an error */
startSym = xran_check_symbolrange(
PortId, cc_id, tti,
pPrbMapElem->nStartSymb,
pPrbMapElem->numSymb, &numSyms);
- if(startSym < 0 || numSyms == 0) {
+ if(startSym < 0 || numSyms == 0)
+ {
/* if start symbol is not valid, then skip this section */
print_err("Skip section %d due to invalid symbol range - [%d:%d], [%d:%d]",
i,
startSym, numSyms);
continue;
}
- } else {
+ }
+ else
+ {
startSym = pPrbMapElem->nStartSymb;
numSyms = pPrbMapElem->numSymb;
}
print_dbg("cp[%d:%d:%d] ru_port_id %d dir=%d\n",
frame_id, subframe_id, slot_id, ru_port_id, dir);
- seq_id = xran_get_cp_seqid(pHandle, XRAN_DIR_DL, cc_id, ru_port_id);
-
- sect_geninfo[0].info.type = params.sectionType;
- sect_geninfo[0].info.startSymId = params.hdr.startSymId;
- sect_geninfo[0].info.iqWidth = params.hdr.iqWidth;
- sect_geninfo[0].info.compMeth = params.hdr.compMeth;
-
- sect_geninfo[0].info.id = i; /* do not revert 'i' to
- xran_alloc_sectionid(pHandle, dir, cc_id, ru_port_id, slot_id); */
-
- if(sect_geninfo[0].info.id > XRAN_MAX_SECTIONS_PER_SLOT)
- print_err("sectinfo->id %d\n", sect_geninfo[0].info.id);
-#if 0
- if (dir == XRAN_DIR_UL) {
- for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) {
- int32_t sec_desc_idx = pPrbMapElem->nSecDesc[loc_sym];
- struct xran_section_desc *p_sec_desc = pPrbMapElem->p_sec_desc[loc_sym][0];
- if(p_sec_desc) {
- p_sec_desc->section_id = sect_geninfo[0].info.id;
- if(p_sec_desc->pCtrl) {
- rte_pktmbuf_free(p_sec_desc->pCtrl);
- p_sec_desc->pCtrl = NULL;
- p_sec_desc->pData = NULL;
+ if(pPrbMapElem->bf_weight.extType == 1)
+ {
+ /* Send multiple CP sections per prbElement for ext-1 */
+ numCPSections = pPrbMapElem->bf_weight.numSetBFWs;
+ }
+ else
+ {
+ numCPSections = 1;
+ replacePrbStartNSize = 1; /* in case of no app fragmentation, UP_nRBSize will be same as nRBSize. So,
+ always replacing the elements when ext1 is not in use */
+ }
+
+ /** Prepare section info for multiple sections in a PRB element */
+ for(idx=0; idx < numCPSections; idx++) {
+
+ sect_geninfo[curr_sec_id].exDataSize=0;
+ sect_geninfo[curr_sec_id].info = xran_cp_get_section_info_ptr(pHandle, dir, cc_id, ru_port_id, ctx_id);
+ if(unlikely(sect_geninfo[curr_sec_id].info == NULL))
+ {
+ rte_panic("xran_cp_get_section_info_ptr failed\n");
}
+
+ struct xran_section_info *info = sect_geninfo[curr_sec_id].info;
+ info->prbElemBegin = (idx == 0 ) ? 1 : 0;
+ info->prbElemEnd = (idx + 1 == numCPSections) ? 1 : 0;
+ info->ef = 0;
+ info->freqOffset = 0;
+ info->ueId = 0;
+ info->regFactor = 0;
+
+ if((idx+1)*prb_per_section > pPrbMapElem->nRBSize){
+ prb_per_section = pPrbMapElem->nRBSize - idx*prb_per_section;
}
- else {
- print_err("section desc is NULL\n");
+
+ if(numCPSections == 1)
+ {
+ info->startPrbc = pPrbMapElem->nRBStart;
+ info->numPrbc = pPrbMapElem->nRBSize;
}
- sec_desc_idx--;
- pPrbMapElem->nSecDesc[loc_sym] = 0;
+ else
+ {
+ info->startPrbc = start_Prb;
+ info->numPrbc = prb_per_section;
+ start_Prb += prb_per_section;
}
+
+ info->type = params.sectionType;
+ info->startSymId = params.hdr.startSymId;
+ info->iqWidth = params.hdr.iqWidth;
+ info->compMeth = params.hdr.compMeth;
+ info->id = curr_sec_id;
+
+ if(info->prbElemBegin && pPrbMapElem->IsNewSect==1)
+ {
+ start_sect_id = info->id;
}
-#endif
- sect_geninfo[0].info.rb = XRAN_RBIND_EVERY;
- sect_geninfo[0].info.startPrbc = pPrbMapElem->nRBStart;
- sect_geninfo[0].info.numPrbc = pPrbMapElem->nRBSize;
- sect_geninfo[0].info.numSymbol = numSyms;
- sect_geninfo[0].info.reMask = 0xfff;
- sect_geninfo[0].info.beamId = pPrbMapElem->nBeamIndex;
- sect_geninfo[0].info.symInc = XRAN_SYMBOLNUMBER_NOTINC;
-
- for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) {
- struct xran_section_desc *p_sec_desc = pPrbMapElem->p_sec_desc[loc_sym][0];
- if(p_sec_desc) {
- p_sec_desc->section_id = sect_geninfo[0].info.id;
-
- sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset;
- sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len;
- } else {
- print_err("section desc is NULL\n");
+ if(unlikely(info->id > XRAN_MAX_SECTIONS_PER_SLOT))
+ print_err("sectinfo->id %d\n", info->id);
+
+ info->rb = XRAN_RBIND_EVERY;
+ info->numSymbol = numSyms;
+ info->reMask = 0xfff;
+ info->beamId = pPrbMapElem->nBeamIndex;
+ info->symInc = XRAN_SYMBOLNUMBER_NOTINC;
+
+ for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++)
+ {
+ struct xran_section_desc *p_sec_desc = &pPrbMapElem->sec_desc[loc_sym][0];
+
+ if(p_sec_desc)
+ {
+ info->sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset;
+ info->sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len;
+
+ p_sec_desc->section_id = info->id;
}
+ else
+ {
+ print_err("section desc is NULL\n");
}
- if(unlikely((category != XRAN_CATEGORY_A) && (category != XRAN_CATEGORY_B))) {
- print_err("Unsupported Category %d\n", category);
- return (-1);
- }
+ } /* for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) */
/* Add extentions if required */
+ if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update))
+ {
+ if(pPrbMapElem->bf_weight.extType == 1) /* Prepare section data for ext-1 */
+ {
next = 0;
- sect_geninfo[0].exDataSize = 0;
+ sect_geninfo[curr_sec_id].exDataSize = 0;
+ memset(&ext1, 0, sizeof (struct xran_sectionext1_info));
+ ext1.bfwNumber = pPrbMapElem->bf_weight.nAntElmTRx;
+ ext1.bfwIqWidth = pPrbMapElem->iqWidth;
+ ext1.bfwCompMeth = pPrbMapElem->compMethod;
+ /* ext-1 buffer contains CP sections */
+ ext1.bfwIQ_sz = ONE_EXT_LEN(pPrbMapElem); //76
+
+ ext_offset = (idx*ONE_CPSEC_EXT_LEN(pPrbMapElem)) + sizeof(struct xran_cp_radioapp_section1);
+ ext1.p_bfwIQ = (int8_t*)(pPrbMapElem->bf_weight.p_ext_section + ext_offset);
+
+ sect_geninfo[curr_sec_id].exData[next].type = XRAN_CP_SECTIONEXTCMD_1;
+ sect_geninfo[curr_sec_id].exData[next].len = sizeof(ext1);
+ sect_geninfo[curr_sec_id].exData[next].data = &ext1;
+
+ info->ef = 1;
+ sect_geninfo[curr_sec_id].exDataSize++;
+ next++;
+ }
+ else
+ {
+ /*ext-11*/
+ }
+
+ } /* if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) */
+
+ curr_sec_id++;
+ } /* for(idx=0; idx < numCPSections;idx++) */
+
+ if (dir==XRAN_DIR_UL || generateCpPkt) //only send actual new CP section
+ {
/* Extension 4 for modulation compression */
- if(pPrbMapElem->compMethod == XRAN_COMPMETHOD_MODULATION) {
+ if(pPrbMapElem->compMethod == XRAN_COMPMETHOD_MODULATION)
+ {
mbuf = xran_ethdi_mbuf_alloc();
ext4.csf = 0; //no shift for now only
ext4.modCompScaler = pPrbMapElem->ScaleFactor;
+ /* TO DO: Should this be the current section id? */
sect_geninfo[0].exData[next].type = XRAN_CP_SECTIONEXTCMD_4;
sect_geninfo[0].exData[next].len = sizeof(ext4);
sect_geninfo[0].exData[next].data = &ext4;
- sect_geninfo[0].info.ef = 1;
+ sect_geninfo[0].info->ef = 1;
sect_geninfo[0].exDataSize++;
next++;
}
/* Extension 1 or 11 for Beam forming weights */
- if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) {
- /* add extantion section for BF Weights if update is needed */
- if(pPrbMapElem->bf_weight.numBundPrb == 0) {
- /* No bundled PRBs, using Extension 1 */
- struct rte_mbuf_ext_shared_info * p_share_data = &p_x_ctx->cp_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id][sect_geninfo[0].info.id];
-
- /*add extention section for BF Weights if update is needed */
- if(pPrbMapElem->bf_weight.p_ext_start) {
+ /* add section extention for BF Weights if update is needed */
+ if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update))
+ {
+ if(pPrbMapElem->bf_weight.extType == 1) /* Using Extension 1 */
+ {
+ //TODO: Should this change ?
+ struct rte_mbuf_ext_shared_info * p_share_data =
+ &p_x_ctx->cp_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id][sect_geninfo[0].info->id];
+
+ if(pPrbMapElem->bf_weight.p_ext_start)
+ {
/* use buffer with BF Weights for mbuf */
mbuf = xran_attach_cp_ext_buf(vf_id, pPrbMapElem->bf_weight.p_ext_start,
pPrbMapElem->bf_weight.p_ext_section,
pPrbMapElem->bf_weight.ext_section_sz, p_share_data);
- } else {
+ }
+ else
+ {
print_err("p %d cc %d dir %d Alloc fail!\n", PortId, cc_id, dir);
- return (-1);
+ ret=-1;
+ goto _create_and_send_section_error;
}
-
- memset(&ext1, 0, sizeof (struct xran_sectionext1_info));
- ext1.bfwNumber = pPrbMapElem->bf_weight.nAntElmTRx;
- ext1.bfwIqWidth = pPrbMapElem->iqWidth;
- ext1.bfwCompMeth = pPrbMapElem->compMethod;
- ext1.p_bfwIQ = (int16_t*)pPrbMapElem->bf_weight.p_ext_section;
- ext1.bfwIQ_sz = pPrbMapElem->bf_weight.ext_section_sz;
-
- sect_geninfo[0].exData[next].type = XRAN_CP_SECTIONEXTCMD_1;
- sect_geninfo[0].exData[next].len = sizeof(ext1);
- sect_geninfo[0].exData[next].data = &ext1;
-
- sect_geninfo[0].info.ef = 1;
- sect_geninfo[0].exDataSize++;
- next++;
- } else { /* if(pPrbMapElem->bf_weight.numBundPrb == 0) */
+ } /* if(pPrbMapElem->bf_weight.extType == 1) */
+ else
+ {
/* Using Extension 11 */
struct rte_mbuf_ext_shared_info *shared_info;
+ next = 0;
- shared_info = &p_x_ctx->bfw_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id][sect_geninfo[0].info.id];
-
-
+ shared_info = &p_x_ctx->bfw_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id][sect_geninfo[0].info->id];
shared_info->free_cb = NULL;
shared_info->fcb_opaque = NULL;
mbuf = xran_ethdi_mbuf_indir_alloc();
if(unlikely(mbuf == NULL)) {
rte_panic("Alloc fail!\n");
- return (-1);
}
//mbuf = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]);
- if(xran_cp_attach_ext_buf(mbuf, (uint8_t *)pPrbMapElem->bf_weight.p_ext_start, pPrbMapElem->bf_weight.maxExtBufSize, shared_info) < 0) {
+ if(xran_cp_attach_ext_buf(mbuf, (uint8_t *)pPrbMapElem->bf_weight.p_ext_start, pPrbMapElem->bf_weight.maxExtBufSize, shared_info) < 0)
+ {
rte_pktmbuf_free(mbuf);
- return (-1);
+ ret=-1;
+ goto _create_and_send_section_error;
}
rte_mbuf_ext_refcnt_update(shared_info, 0);
sect_geninfo[0].exData[next].len = sizeof(ext11);
sect_geninfo[0].exData[next].data = &ext11;
- sect_geninfo[0].info.ef = 1;
+ sect_geninfo[0].info->ef = 1;
sect_geninfo[0].exDataSize++;
next++;
}
- } else { /* if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) */
+ } /* if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) */
+ else
+ {
mbuf = xran_ethdi_mbuf_alloc();
- sect_geninfo[0].info.ef = 0;
+
+ sect_geninfo[0].info->ef = 0;
sect_geninfo[0].exDataSize = 0;
+
+ if(p_x_ctx->dssEnable == 1) {
+ uint8_t dssSlot = 0;
+ dssSlot = tti % (p_x_ctx->dssPeriod);
+
+ ext9.technology = p_x_ctx->technology[dssSlot];
+ ext9.reserved = 0;
+
+ sect_geninfo[0].exData[next].type = XRAN_CP_SECTIONEXTCMD_9;
+ sect_geninfo[0].exData[next].len = sizeof(ext9);
+ sect_geninfo[0].exData[next].data = &ext9;
+
+ sect_geninfo[0].info->ef = 1;
+ sect_geninfo[0].exDataSize++;
+ next++;
+ }
}
- if(unlikely(mbuf == NULL)) {
+ if(unlikely(mbuf == NULL))
+ {
print_err("Alloc fail!\n");
- return (-1);
+ ret=-1;
+ goto _create_and_send_section_error;
}
- params.numSections = 1;//nsection;
+ params.numSections = numCPSections;
params.sections = sect_geninfo;
- ret = xran_prepare_ctrl_pkt(mbuf, ¶ms, cc_id, ru_port_id, seq_id);
- if(ret < 0) {
+ seq_id = xran_get_cp_seqid(pHandle, ((XRAN_DIR_DL == dir)? XRAN_DIR_DL : XRAN_DIR_UL), cc_id, ru_port_id);
+ ret = xran_prepare_ctrl_pkt(mbuf, ¶ms, cc_id, ru_port_id, seq_id,start_sect_id);
+ } /* if (dir==XRAN_DIR_UL || generateCpPkt) */
+
+ if(replacePrbStartNSize && XRAN_DIR_DL == dir)
+ {
+ sect_geninfo[curr_sec_id-1].info->startPrbc = pPrbMapElem->UP_nRBStart;
+ sect_geninfo[curr_sec_id-1].info->numPrbc = pPrbMapElem->UP_nRBSize;
+ }
+
+ if(ret < 0)
+ {
print_err("Fail to build control plane packet - [%d:%d:%d] dir=%d\n",
frame_id, subframe_id, slot_id, dir);
- } else {
+ }
+ else
+ {
+ if((dir==XRAN_DIR_UL) || generateCpPkt) //only send actual new CP section
+ {
int32_t cp_sent = 0;
int32_t pkt_len = 0;
/* add in the ethernet header */
pCnt->tx_bytes_counter += pkt_len; //rte_pktmbuf_pkt_len(mbuf);
if(pkt_len > p_x_ctx->fh_init.mtu)
rte_panic("section %d: pkt_len = %d maxExtBufSize %d\n", i, pkt_len, pPrbMapElem->bf_weight.maxExtBufSize);
- //rte_mbuf_sanity_check(mbuf, 0);
+
cp_sent = p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, vf_id);
- if(cp_sent != 1) {
+ if(cp_sent != 1)
+ {
rte_pktmbuf_free(mbuf);
}
- xran_cp_add_section_info(pHandle, dir, cc_id, ru_port_id, ctx_id, §_geninfo[0].info);
+ }
}
} /* for (i=0; i<nsection; i++) */
+ }
+#if 1
+ else
+ {
+ /* Generate a C-Plane message with multi sections,
+ * a C-Plane message for each section*/
+ if(prbMap)
+ {
+ if(0 == prbMap->nPrbElm)
+ {
+ print_dbg("prbMap->nPrbElm is %d\n",prbMap->nPrbElm);
+ return 0;
+ }
+
+ nsection = prbMap->nPrbElm;
+ i=0;
+ if(XRAN_DIR_DL == dir)
+ {
+ prbElmProcInfo->numSymsRemaining = 0;
+ prbElmProcInfo->nPrbElmProcessed = 0;
+ prbElmProcInfo->nPrbElmPerSym = prbMap->nPrbElm;
+ nsection = prbMap->nPrbElm;
+ } //dir = DL
+ else
+ {
+ nsection = prbMap->nPrbElm;
+ } //dir = UL
+ }
+ else
+ {
+ print_err("prbMap is NULL\n");
+ return (-1);
+ }
+
+ pPrbMapElem = &prbMap->prbMap[0];
+
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_FDD) != 1
+ && xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ {
+ startSym = xran_check_symbolrange(
+ ((dir==XRAN_DIR_DL)?XRAN_SYMBOL_TYPE_DL:XRAN_SYMBOL_TYPE_UL),
+ PortId, cc_id, tti,
+ pPrbMapElem->nStartSymb,
+ pPrbMapElem->numSymb, &numSyms);
+
+ if(startSym < 0 || numSyms == 0)
+ {
+ /* if start symbol is not valid, then skip this section */
+ print_err("Skip section %d due to invalid symbol range - [%d:%d], [%d:%d]",
+ i,
+ pPrbMapElem->nStartSymb, pPrbMapElem->numSymb,
+ startSym, numSyms);
+ }
+ }
+ else
+ {
+ startSym = pPrbMapElem->nStartSymb;
+ numSyms = pPrbMapElem->numSymb;
+ }
+
+ vf_id = xran_map_ecpriRtcid_to_vf(p_x_ctx, dir, cc_id, ru_port_id);
+ params.dir = dir;
+ params.sectionType = XRAN_CP_SECTIONTYPE_1;
+ params.hdr.filterIdx = XRAN_FILTERINDEX_STANDARD;
+ params.hdr.frameId = frame_id;
+ params.hdr.subframeId = subframe_id;
+ params.hdr.slotId = slot_id;
+ params.hdr.startSymId = startSym;
+ params.hdr.iqWidth = pPrbMapElem->iqWidth;
+ params.hdr.compMeth = pPrbMapElem->compMethod;
+ params.sections = sect_geninfo;
+
+ for (i = 0, j = 0; j < nsection; j++)
+ {
+ sect_geninfo[i].exDataSize=0;
+ sect_geninfo[i].info = xran_cp_get_section_info_ptr(pHandle, dir, cc_id, ru_port_id, ctx_id);
+ sect_geninfo[i].info->prbElemBegin = ((j == 0 ) ? 1 : 0);
+ sect_geninfo[i].info->prbElemEnd = ((j + 1 == nsection) ? 1 : 0);
+ if(sect_geninfo[i].info == NULL)
+ {
+ rte_panic("xran_cp_get_section_info_ptr failed\n");
+ }
+ pPrbMapElem = &prbMap->prbMap[j];
+
+ sect_geninfo[i].info->type = XRAN_CP_SECTIONTYPE_1;
+ sect_geninfo[i].info->startSymId = pPrbMapElem->nStartSymb;
+ sect_geninfo[i].info->iqWidth = params.hdr.iqWidth;
+ sect_geninfo[i].info->compMeth = params.hdr.compMeth;
+ sect_geninfo[i].info->id = pPrbMapElem->nSectId;
+
+ if(sect_geninfo[i].info->id > XRAN_MAX_SECTIONS_PER_SLOT)
+ print_err("sectinfo->id %d\n", sect_geninfo[i].info->id);
+
+ sect_geninfo[i].info->rb = XRAN_RBIND_EVERY;
+ sect_geninfo[i].info->startPrbc = pPrbMapElem->UP_nRBStart;
+ sect_geninfo[i].info->numPrbc = pPrbMapElem->UP_nRBSize;
+ sect_geninfo[i].info->numSymbol = pPrbMapElem->numSymb;
+ sect_geninfo[i].info->reMask = 0xfff;
+ sect_geninfo[i].info->beamId = pPrbMapElem->nBeamIndex;
+
+ if(startSym == pPrbMapElem->nStartSymb)
+ sect_geninfo[i].info->symInc = XRAN_SYMBOLNUMBER_NOTINC;
+ else
+ {
+ if((startSym + numSyms) == pPrbMapElem->nStartSymb)
+ {
+ sect_geninfo[i].info->symInc = XRAN_SYMBOLNUMBER_INC;
+ startSym = pPrbMapElem->nStartSymb;
+ numSyms = pPrbMapElem->numSymb;
+ }
+ else
+ {
+ sect_geninfo[i].info->startSymId = startSym;
+ sect_geninfo[i].info->numSymbol = numSyms;
+ print_dbg("Last startSym is %d. Last numSyms is %d. But current pPrbMapElem->nStartSymb is %d.\n", startSym, numSyms, pPrbMapElem->nStartSymb);
+ }
+ }
+
+
+ for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++)
+ {
+ struct xran_section_desc *p_sec_desc = &pPrbMapElem->sec_desc[loc_sym][0];
+ if(p_sec_desc)
+ {
+ p_sec_desc->section_id = sect_geninfo[i].info->id;
+
+ sect_geninfo[i].info->sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset;
+ sect_geninfo[i].info->sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len;
+ }
+ else
+ {
+ print_err("section desc is NULL\n");
+ }
+ }
+
+ next = 0;
+ sect_geninfo[i].exDataSize = 0;
+
+ /* Extension 4 for modulation compression */
+ if(pPrbMapElem->compMethod == XRAN_COMPMETHOD_MODULATION)
+ {
+ // print_dbg("[%s]:%d Modulation Compression need to verify for this code branch and may not be available\n");
+ print_err("[%s]:%d Modulation Compression need to verify for this code branch and may not be available\n",__FUNCTION__, __LINE__);
+ }
+ /* Extension 1 or 11 for Beam forming weights */
+ /* add section extention for BF Weights if update is needed */
+ if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update))
+ {
+ // print_dbg("[%s]:%d Category B need to verify for this code branch and may not be available\n");
+ print_err("[%s]:%d Category B need to verify for this code branch and may not be available\n",__FUNCTION__, __LINE__);
+ } /* if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) */
+ else
+ {
+ sect_geninfo[i].info->ef = 0;
+ sect_geninfo[i].exDataSize = 0;
+
+ if(p_x_ctx->dssEnable == 1) {
+ uint8_t dssSlot = 0;
+ dssSlot = tti % (p_x_ctx->dssPeriod);
+
+ ext9.technology = p_x_ctx->technology[dssSlot];
+ ext9.reserved = 0;
+
+ sect_geninfo[i].exData[next].type = XRAN_CP_SECTIONEXTCMD_9;
+ sect_geninfo[i].exData[next].len = sizeof(ext9);
+ sect_geninfo[i].exData[next].data = &ext9;
+
+ sect_geninfo[i].info->ef = 1;
+ sect_geninfo[i].exDataSize++;
+ next++;
+ }
+ }
+
+ // xran_cp_add_section_info(pHandle, dir, cc_id, ru_port_id, ctx_id, §_geninfo[i].info);
+
+ if(pPrbMapElem->IsNewSect == 1)
+ {
+ sect_geninfo[i].info->startPrbc = pPrbMapElem->nRBStart;
+ sect_geninfo[i].info->numPrbc = pPrbMapElem->nRBSize;
+ i++;
+ }
+ }
+
+ params.numSections = i;
+
+ mbuf = xran_ethdi_mbuf_alloc();
+ if(unlikely(mbuf == NULL))
+ {
+ print_err("Alloc fail!\n");
+ ret=-1;
+ goto _create_and_send_section_error;
+ }
+
+ seq_id = xran_get_cp_seqid(pHandle, ((XRAN_DIR_DL == dir)? XRAN_DIR_DL : XRAN_DIR_UL), cc_id, ru_port_id);
+ ret = xran_prepare_ctrl_pkt(mbuf, ¶ms, cc_id, ru_port_id, seq_id,start_sect_id);
+
+ if(ret < 0)
+ {
+ print_err("Fail to build control plane packet - [%d:%d:%d] dir=%d\n",
+ frame_id, subframe_id, slot_id, dir);
+ }
+ else
+ {
+
+ int32_t cp_sent = 0;
+ int32_t pkt_len = 0;
+ /* add in the ethernet header */
+ struct rte_ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h));
+ pkt_len = rte_pktmbuf_pkt_len(mbuf);
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += pkt_len; //rte_pktmbuf_pkt_len(mbuf);
+ if(pkt_len > p_x_ctx->fh_init.mtu)
+ rte_panic("section %d: pkt_len = %d maxExtBufSize %d\n", i, pkt_len, pPrbMapElem->bf_weight.maxExtBufSize);
+
+ cp_sent = p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, vf_id);
+ if(cp_sent != 1)
+ {
+ rte_pktmbuf_free(mbuf);
+ }
+ }
+
+ struct xran_section_info *info;
+ for (j = 0; j < nsection; j++)
+ {
+ pPrbMapElem = &prbMap->prbMap[j];
+ info = xran_cp_find_section_info(pHandle, dir, cc_id, ru_port_id, ctx_id,j);
+ if(info == NULL)
+ {
+ rte_panic("xran_cp_get_section_info_ptr failed\n");
+ }
+ info->startPrbc = pPrbMapElem->UP_nRBStart;
+ info->numPrbc = pPrbMapElem->UP_nRBSize;
+ }
+ }
+#endif
+_create_and_send_section_error:
+ if(XRAN_DIR_DL == dir)
+ {
+ prbElmProcInfo->nPrbElmProcessed = nsection;
+ }
return ret;
}
}
recvSections[xran_port_id] = malloc(sizeof(struct xran_section_recv_info) * XRAN_MAX_NUM_SECTIONS);
- if(recvSections == NULL) {
+ if(recvSections[xran_port_id] == NULL) {
print_err("Fail to allocate memory!");
return (-1);
}
int32_t process_cplane(struct rte_mbuf *pkt, void* handle);
int32_t xran_cp_create_and_send_section(void *pHandle, uint8_t ru_port_id, int dir, int tti, int cc_id, struct xran_prb_map *prbMap,
+ struct xran_prb_elm_proc_info_t *prbElmProcInfo,
enum xran_category category, uint8_t ctx_id);
+
int32_t xran_ruemul_init(void *pHandle);
int32_t xran_ruemul_release(void *pHandle);
+#define ONE_EXT_LEN(prbMap) (prbMap->bf_weight.ext_section_sz / prbMap->bf_weight.numSetBFWs) - sizeof(struct xran_cp_radioapp_section1)
+#define ONE_CPSEC_EXT_LEN(prbMap) (prbMap->bf_weight.ext_section_sz / prbMap->bf_weight.numSetBFWs)
+
static __rte_always_inline uint16_t
-xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id)
+xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t subframe_id, uint8_t slot_id)
{
int8_t xran_port = 0;
if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){
/* if new slot has been started,
* then initializes section id again for new start */
- if(xran_section_id_curslot[xran_port][dir][cc_id][ant_id] != slot_id) {
+ if(xran_section_id_curslot[xran_port][dir][cc_id][ant_id] != (subframe_id * 2 + slot_id)) {
xran_section_id[xran_port][dir][cc_id][ant_id] = 0;
- xran_section_id_curslot[xran_port][dir][cc_id][ant_id] = slot_id;
+ xran_section_id_curslot[xran_port][dir][cc_id][ant_id] = (subframe_id * 2 + slot_id);
}
return(xran_section_id[xran_port][dir][cc_id][ant_id]++);
int xran_generate_delay_meas(uint16_t port_id, void* handle, uint8_t actionType, uint8_t MeasurementID )
{
struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle;
- struct xran_ecpri_delay_meas_pkt *ecpri_delmeas_pkt;
int pkt_len;
- struct rte_mbuf *mbuf,*pkt;
+ struct rte_mbuf *mbuf;
char* pChar;
struct xran_ecpri_delay_meas_pl * pdm= NULL;
uint64_t tcv1,tr2m,trm;
int xran_process_delmeas_request(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id)
{
int ret_value = FAIL;
-
- struct xran_ecpri_delay_meas_pl *txDelayHdr;
TimeStamp pt1;
struct rte_mbuf* pkt1;
- char* pchar;
+ //char* pchar;
uint64_t tcv1, tcv2,t2m,trm, td12, t1m;
struct xran_ecpri_del_meas_pkt *pdm= NULL;
- union xran_ecpri_cmn_hdr *cmn;
struct timespec tr, t2;
struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle;
struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id];
struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id];
struct rte_ether_hdr *eth_hdr;
struct rte_ether_addr addr;
- struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
+ //struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
//101620
struct xran_io_cfg* cfg = &p_xran_dev_ctx->fh_init.io_cfg;
// struct xran_io_cfg *cfg = &ctx->io_cfg;
// 2) Copy MeasurementID to the Delay Measurement Response packet
// but first prepend ethernet header since the info is still in the buffer
// pchar = rte_pktmbuf_prepend(pkt, (uint16_t)(sizeof(struct rte_ether_hdr)+ sizeof(union xran_ecpri_cmn_hdr ))); // Pointer to new data start address 10/20/20 Now not removing ecpri_cmn in process_delay_meas
- pchar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
+ /*pchar = */rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX);
pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr));
// 3) Get time stamp T1 from the Timestamp field i.e. t1
// Still need to define the DB to save the info and run averages
td12 = t2m - tcv2 - (t1m + tcv1);
// 12) Send the response right away
- struct rte_ether_hdr *h = (struct rte_ether_hdr *)rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr*);
#ifdef XRAN_OWD_DEBUG_PKTS
+ struct rte_ether_hdr *h = (struct rte_ether_hdr *)rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr*);
uint8_t *pc = &h->s_addr.addr_bytes[0];
printf(" Src MAC from packet: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pc[0],pc[1],pc[2],pc[3],pc[4],pc[5]);
uint8_t *pd = &h->d_addr.addr_bytes[0];
int xran_process_delmeas_request_w_fup(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id)
{
int ret_value = FAIL;
- struct xran_ecpri_delay_meas_pl* txDelayHdr;
- TimeStamp pt2;
- struct rte_mbuf* pkt1;
uint64_t trm;
struct xran_ecpri_del_meas_pkt* pdm= ptr;
struct timespec tr;
struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle;
- struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id];
+ //struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id];
struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id];
- struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
- struct xran_io_cfg *cfg = &ctx->io_cfg;
- int32_t* port = &cfg->port[port_id];
+ //struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
+ //struct xran_io_cfg *cfg = &ctx->io_cfg;
+ //int32_t* port = &cfg->port[port_id];
// Since we are processing the receipt of a delay measurement request with follow up packet the following actions
// need to be taken (Per eCPRI V2.0 Figure 26)
int xran_process_delmeas_response(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id)
{
int ret_value = 1;
- struct xran_ecpri_delay_meas_pl* txDelayHdr;
TimeStamp pt2;
- struct rte_mbuf* pkt1;
- uint64_t tcv1, tcv2,t2m,trm, td12;
+ uint64_t tcv2,t2m;
struct xran_ecpri_del_meas_pkt* pdm;
- struct timespec tr, t2;
+ //struct timespec t2;
struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle;
struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id];
struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id];
- struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
- struct xran_io_cfg *cfg = &ctx->io_cfg;
- struct xran_io_cfg* cfg1 = &p_xran_dev_ctx->fh_init.io_cfg;
- int32_t* port = &cfg->port[port_id];
+ //struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
+ //struct xran_io_cfg *cfg = &ctx->io_cfg;
+ //struct xran_io_cfg* cfg1 = &p_xran_dev_ctx->fh_init.io_cfg;
+ //int32_t* port = &cfg->port[port_id];
// Since we are processing the receipt of a delay measurement response packet the following actions
int xran_process_delmeas_rem_request(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id)
{
int ret_value = FAIL;
- struct xran_ecpri_delay_meas_pl* txDelayHdr;
struct rte_mbuf* pkt1;
uint64_t tcv1,tr2m,trm;
struct xran_ecpri_del_meas_pkt* pdm;
- char* pchar;
+ //char* pchar;
struct timespec tr2, tr;
struct rte_ether_hdr *eth_hdr;
struct rte_ether_addr addr;
trm = xran_timespec_to_ns(&tr);
// 2) Copy MeasurementID to the Delay Measurement Request packet
// but first prepend ethernet header since the info is still in the buffer
- pchar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
+ /*pchar = */rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX);
pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr));
int xran_process_delmeas_rem_request_w_fup(struct rte_mbuf* pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id)
{
int ret_value = FAIL;
- struct xran_ecpri_delay_meas_pl* txDelayHdr;
- TimeStamp pt2;
struct rte_mbuf* pkt1;
struct rte_mbuf* pkt2;
uint64_t tcv1,tsm,t1;
struct rte_ether_hdr *eth_hdr;
struct rte_ether_addr addr;
struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle;
- struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id];
+ //struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id];
struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id];
struct xran_ecpri_del_meas_pkt* pdm;
struct timespec tr, ts;
- char* pchar;
+ //char* pchar;
struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
t1 = xran_timespec_to_ns(&tr);
// 2) Copy MeasurementID to the Delay Measurement Request packet
// but first prepend ethernet header since the info is still in the buffer
- pchar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
+ /*pchar = */rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX);
pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr));
int xran_process_delmeas_follow_up(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id)
{
int ret_value = FAIL;
- struct xran_ecpri_delay_meas_pl *txDelayHdr;
struct rte_mbuf *pkt1;
- char* pChar= NULL;
+ //char* pChar= NULL;
uint64_t tcv1,tr2m, tcv2, t1;
struct xran_ecpri_del_meas_pkt *pdm;
- struct timespec tr2, tr;
+ struct timespec tr2;
struct rte_ether_hdr *eth_hdr;
struct rte_ether_addr addr;
TimeStamp pt1;
// 2) Copy MeasurementID to the Delay Measurement Response packet
// but first prepend ethernet header since the info is still in the buffer
- pChar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
+ /*pChar = */rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr));
pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX);
pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr));
{
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)handle;
struct xran_ecpri_del_meas_pkt *ecpri_delmeas_pkt;
- union xran_ecpri_cmn_hdr * ecpricmn;
+ //union xran_ecpri_cmn_hdr * ecpricmn;
int ret_value = FAIL;
#ifdef XRAN_OWD_DEBUG_PKTS
printf("pdm Device is %d\n", p_xran_dev_ctx->fh_init.io_cfg.id);
#endif
- /* Process eCPRI cmn header. */
+ /* Process eCPRI cmn header. */
// (void *)rte_pktmbuf_adj(pkt, sizeof(*ecpricmn));
ecpri_delmeas_pkt = (struct xran_ecpri_del_meas_pkt *)rte_pktmbuf_mtod(pkt, struct xran_ecpri_del_meas_pkt *);
// The processing of the delay measurement here corresponds to eCPRI sections 3.2.4.6.2 and 3.42.6.3
#include "ethdi.h"
#include "xran_printf.h"
-static struct xran_device_ctx *g_xran_dev_ctx[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL};
+static struct xran_device_ctx *g_xran_dev_ctx[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
int32_t
xran_dev_create_ctx(uint32_t xran_ports_num)
return g_xran_dev_ctx[xran_port_id];
}
-static struct xran_fh_config *xran_lib_get_ctx_fhcfg(void *pHandle)
+static inline struct xran_fh_config *xran_lib_get_ctx_fhcfg(void *pHandle)
{
struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx*)pHandle;
return (&(p_dev_ctx->fh_cfg));
int32_t
xran_init_vfs_mapping(void *pHandle)
{
- int ctx, dir, cc, ant, i;
+ int dir, cc, ant, i;
struct xran_device_ctx* p_dev = NULL;
uint8_t xran_port_id = 0;
uint16_t vf_id = 0;
for(dir=0; dir < 2; dir++){
for(cc=0; cc < xran_get_num_cc(p_dev); cc++){
for(ant=0; ant < xran_get_num_eAxc(p_dev)*2 + xran_get_num_ant_elm(p_dev); ant++){
- if(total_vf_cnt = 2 && eth_ctx->io_cfg.one_vf_cu_plane){
+ if((total_vf_cnt == 2) && eth_ctx->io_cfg.one_vf_cu_plane){
if(ant & 1) { /* split ant half and half on VFs */
vf_id = vf_id_all[XRAN_UP_VF+1];
xran_set_map_ecpriPcid_to_vf(p_dev, dir, cc, ant, vf_id);
uint64_t current_second;
};
-#define XRAN_MAX_POOLS_PER_SECTOR_NR 8 /**< 2x(TX_OUT, RX_IN, PRACH_IN, SRS_IN) with C-plane */
+#define XRAN_MAX_POOLS_PER_SECTOR_NR 10 /**< 2x(TX_OUT, RX_IN, PRACH_IN, SRS_IN, BFW_BUF) with C-plane */
typedef struct sectorHandleInfo
{
}XranSectorHandleInfo, *PXranSectorHandleInfo;
typedef void (*XranSymCallbackFn)(struct rte_timer *tim, void* arg, void *p_dev_ctx);
-typedef int32_t (*tx_sym_gen_fn)(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id,
+typedef int32_t (*tx_sym_gen_fn)(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db);
#define XRAN_IQ_FLOW_MAX 512 /**< Maximum flow IQ flows per XRAN port */
+#define XRAN_MAX_MEM_IF_RING_SIZE 8*32
+
struct mbuf_table {
uint16_t len;
struct rte_mbuf *m_table[MBUF_TABLE_SIZE];
struct rte_mbuf_ext_shared_info sh_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
};
+
+/** Structure to hold the information for tracking the prb element processing across symbols.
+ * C-Plane processing for every slot is spread equally across symbols that fall within allowed window.
+ * This structure is used to keep track of processing that is done.
+ */
+struct xran_prb_elm_proc_info_t {
+ uint16_t nPrbElmPerSym; /**< Number of prb elements to be processed per symbol */
+ uint16_t nPrbElmProcessed; /**< Holds the number of PrbElms Processed in a given symbol time by xran. */
+ uint8_t numSymsRemaining; /**< Number of symbols for DL CP transmission remaining in this slot */
+};
+
struct __rte_cache_aligned xran_device_ctx
{
uint8_t sector_id;
struct xran_fh_init fh_init;
struct xran_fh_config fh_cfg;
struct xran_prach_cp_config PrachCPConfig;
+ struct xran_prach_cp_config PrachCPConfigLTE;
uint32_t enablePrach;
uint32_t enableCP;
int32_t DynamicSectionEna;
+ int32_t RunSlotPrbMapBySymbolEnable;
int64_t offset_sec;
int64_t offset_nsec; //offset to GPS time calcuated based on alpha and beta
uint32_t interval_us_local;
uint32_t enableSrs;
+ uint16_t enableSrsCp;
+ uint16_t nSrsDelaySym;
uint8_t puschMaskEnable;
uint8_t puschMaskSlot;
struct xran_srs_config srs_cfg; /** configuration of SRS */
BbuIoBufCtrlStruct sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
BbuIoBufCtrlStruct sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
+ BbuIoBufCtrlStruct sFHCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ BbuIoBufCtrlStruct sFHCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
/* buffers lists */
struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
+ // struct xran_flat_buffer sFHCpRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
xran_transport_callback_fn pCallback[XRAN_MAX_SECTOR_NR];
void *pCallbackTag[XRAN_MAX_SECTOR_NR];
LIST_HEAD(sym_cb_elem_list, cb_elem_entry) sym_cb_list_head[XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ uint8_t numSetBFWs_arr[XRAN_MAX_SECTIONS_PER_SLOT];
+
int32_t sym_up; /**< when we start sym 0 of up with respect to OTA time as measured in symbols */
int32_t sym_up_ul;
struct xran_common_counters fh_counters;
- xran_ethdi_mbuf_send_fn send_cpmbuf2ring; /**< callback to send mbufs of C-Plane packets to the ring */
- xran_ethdi_mbuf_send_fn send_upmbuf2ring; /**< callback to send mbufs of U-Plane packets to the ring */
+ xran_ethdi_mbuf_send_fn send_cpmbuf2ring; /**< callback to send mbufs of C-Plane packets to the VF ring */
+ xran_ethdi_mbuf_send_fn send_upmbuf2ring; /**< callback to send mbufs of U-Plane packets to the VF ring */
struct xran_timer_ctx timer_ctx[MAX_NUM_OF_XRAN_CTX];
struct xran_timer_ctx cb_timer_ctx[MAX_CB_TIMER_CTX];
struct rte_flow *p_iq_flow[XRAN_IQ_FLOW_MAX];
uint32_t iq_flow_cnt; /**< number of IQ flows configured */
+
+ uint8_t ndm_srs_scheduled; /* set if SRS has been scheduled */
+ uint8_t ndm_srs_schedperiod; /* SRS slot within TDD period */
+ uint32_t ndm_srs_txtti; /* first slot for transmit SRS within TDD period */
+ uint32_t ndm_srs_tti; /* original SRS slot */
+ uint8_t numSymsForDlCP; /**< number of symbols for DL CP transmission */
+ struct xran_prb_elm_proc_info_t prbElmProcInfo[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
+ uint8_t dssEnable; /**< enable DSS (extension-9) */
+ uint8_t dssPeriod; /**< DSS pattern period for LTE/NR */
+ uint8_t technology[XRAN_MAX_DSS_PERIODICITY]; /**< technology array represents slot is LTE(0)/NR(1) */
+ /* Keeps track of how many sections are processed while parsing C-plan packet */
+ uint8_t sectiondb_elm[XRAN_MAX_SECTIONDB_CTX][XRAN_DIR_MAX][XRAN_COMPONENT_CARRIERS_MAX][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR];
};
struct xran_eaxcid_config *xran_get_conf_eAxC(void *pHandle);
125 // mu = 3
};
+#if 0
// F1 Tables 38.101-1 Table F.5.3. Window length for normal CP
static uint16_t nCpSizeF1[3][13][2] =
{
{ {0, 0}, {104, 72}, {208, 144}, {416, 288}}, // Numerology 2 (60KHz)
{{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
};
+#endif
-static uint32_t xran_fs_max_slot_num[XRAN_PORTS_NUM] = {8000, 8000, 8000, 8000};
-static uint32_t xran_fs_max_slot_num_SFN[XRAN_PORTS_NUM] = {20480,20480,20480,20480}; /* max slot number counted as SFN is 0-1023 */
-static uint16_t xran_fs_num_slot_tdd_loop[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP };
-static uint16_t xran_fs_num_dl_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
-static uint16_t xran_fs_num_ul_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
-static uint8_t xran_fs_slot_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}};
-static uint8_t xran_fs_slot_symb_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{XRAN_SLOT_TYPE_INVALID}}};
-static float xran_fs_ul_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {0.0};
-static float xran_fs_dl_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {0.0};
+
+static uint32_t xran_fs_max_slot_num[XRAN_PORTS_NUM] = {8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000};
+static uint32_t xran_fs_max_slot_num_SFN[XRAN_PORTS_NUM] = {20480,20480,20480,20480,20480,20480,20480,20480}; /* max slot number counted as SFN is 0-1023 */
+static uint16_t xran_fs_num_slot_tdd_loop[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{ XRAN_NUM_OF_SLOT_IN_TDD_LOOP }};
+static uint16_t xran_fs_num_dl_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{{0}}};
+static uint16_t xran_fs_num_ul_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{{0}}};
+static uint8_t xran_fs_slot_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{{XRAN_SLOT_TYPE_INVALID}}};
+static uint8_t xran_fs_slot_symb_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{{XRAN_SLOT_TYPE_INVALID}}}};
+static float xran_fs_ul_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{0.0}};
+static float xran_fs_dl_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{0.0}};
extern uint16_t xran_max_frame;
uint32_t nSlotNum, nSymNum, nVal, i, j;
uint32_t numDlSym, numUlSym, numGuardSym;
uint32_t numDlSlots = 0, numUlSlots = 0, numSpDlSlots = 0, numSpUlSlots = 0, numSpSlots = 0;
+#ifdef PRINTF_DBG_OK
char sSlotPattern[XRAN_SLOT_TYPE_LAST][10] = {"IN\0", "DL\0", "UL\0", "SP\0", "FD\0"};
+#endif
// nPhyInstanceId Carrier ID
// nFrameDuplexType 0 = FDD 1 = TDD
int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx)
{
- int32_t nSfIdxMod, nSfType, ret = 0;
+ int32_t nSfIdxMod;
nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1);
#include <pthread.h>
#include <malloc.h>
#include <immintrin.h>
-
+#include <numa.h>
#include <rte_common.h>
#include <rte_eal.h>
#include <rte_errno.h>
#include <rte_ecpri.h>
#endif
#include "xran_fh_o_du.h"
+#include "xran_fh_o_ru.h"
#include "xran_main.h"
#include "ethdi.h"
#include "xran_dev.h"
#include "xran_frame_struct.h"
#include "xran_printf.h"
-#include "xran_app_frag.h"
#include "xran_cp_proc.h"
#include "xran_tx_proc.h"
#include "xran_rx_proc.h"
#include "xran_mlog_lnx.h"
-static xran_cc_handle_t pLibInstanceHandles[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {NULL};
+static xran_cc_handle_t pLibInstanceHandles[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{NULL}};
uint64_t interval_us = 1000; //the TTI interval of the cell with maximum numerology
-uint32_t xran_lib_ota_tti[XRAN_PORTS_NUM] = {0,0,0,0}; /**< Slot index in a second [0:(1000000/TTI-1)] */
-uint32_t xran_lib_ota_sym[XRAN_PORTS_NUM] = {0,0,0,0}; /**< Symbol index in a slot [0:13] */
-uint32_t xran_lib_ota_sym_idx[XRAN_PORTS_NUM] = {0,0,0,0}; /**< Symbol index in a second [0 : 14*(1000000/TTI)-1]
+uint32_t xran_lib_ota_tti[XRAN_PORTS_NUM] = {0,0,0,0,0,0,0,0}; /**< Slot index in a second [0:(1000000/TTI-1)] */
+uint32_t xran_lib_ota_sym[XRAN_PORTS_NUM] = {0,0,0,0,0,0,0,0}; /**< Symbol index in a slot [0:13] */
+uint32_t xran_lib_ota_sym_idx[XRAN_PORTS_NUM] = {0,0,0,0,0,0,0,0}; /**< Symbol index in a second [0 : 14*(1000000/TTI)-1]
where TTI is TTI interval in microseconds */
uint16_t xran_SFN_at_Sec_Start = 0; /**< SFN at current second start */
static uint64_t xran_total_tick = 0, xran_used_tick = 0;
static uint32_t xran_num_cores_used = 0;
static uint32_t xran_core_used[64] = {0};
-static int32_t first_call = 0;
+int32_t first_call = 0;
+int32_t mlogxranenable = 0;
struct cp_up_tx_desc * xran_pkt_gen_desc_alloc(void);
int32_t xran_pkt_gen_desc_free(struct cp_up_tx_desc *p_desc);
}
}
+#if 0
static inline int32_t
xran_getSlotIdxSecond(uint32_t interval)
{
int32_t slotIndxSecond = frameIdxSecond * SLOTS_PER_SYSTEMFRAME(interval);
return slotIndxSecond;
}
+#endif
enum xran_if_state
xran_get_if_state(void)
struct xran_srs_config *p_srs = &(p_xran_dev_ctx->srs_cfg);
if(p_srs){
- p_srs->symbMask = pConf->srs_conf.symbMask;
+ p_srs->symbMask = pConf->srs_conf.symbMask; /* deprecated */
+ p_srs->slot = pConf->srs_conf.slot;
+ p_srs->ndm_offset = pConf->srs_conf.ndm_offset;
+ p_srs->ndm_txduration = pConf->srs_conf.ndm_txduration;
p_srs->eAxC_offset = pConf->srs_conf.eAxC_offset;
- print_dbg("SRS sym %d\n", p_srs->symbMask );
+
+ print_dbg("SRS sym %d\n", p_srs->slot);
+ print_dbg("SRS NDM offset %d\n", p_srs->ndm_offset);
+ print_dbg("SRS NDM Tx %d\n", p_srs->ndm_txduration);
print_dbg("SRS eAxC_offset %d\n", p_srs->eAxC_offset);
}
return (XRAN_STATUS_SUCCESS);
xran_init_prach_lte(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx)
{
/* update Rach for LTE */
- return xran_init_prach(pConf, p_xran_dev_ctx);
+ return xran_init_prach(pConf, p_xran_dev_ctx, XRAN_RAN_LTE);
}
int32_t
-xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx)
+xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx, enum xran_ran_tech xran_tech)
{
int32_t i;
uint8_t slotNr;
struct xran_prach_config* pPRACHConfig = &(pConf->prach_conf);
const xRANPrachConfigTableStruct *pxRANPrachConfigTable;
uint8_t nNumerology = pConf->frame_conf.nNumerology;
- uint8_t nPrachConfIdx = pPRACHConfig->nPrachConfIdx;
- struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
-
+ uint8_t nPrachConfIdx = -1;// = pPRACHConfig->nPrachConfIdx;
+ struct xran_prach_cp_config *pPrachCPConfig = NULL;
+ if(pConf->dssEnable){
+ /*Check Slot type and */
+ if(xran_tech == XRAN_RAN_5GNR){
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ nPrachConfIdx = pPRACHConfig->nPrachConfIdx;
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfigLTE);
+ nPrachConfIdx = pPRACHConfig->nPrachConfIdxLTE;
+ }
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ nPrachConfIdx = pPRACHConfig->nPrachConfIdx;
+ }
if (nNumerology > 2)
pxRANPrachConfigTable = &gxranPrachDataTable_mmw[nPrachConfIdx];
else if (pConf->frame_conf.nFrameDuplexType == 1)
if(pConf->log_level)
printf("xRAN open PRACH config: Numerology %u ConfIdx %u, preambleFmrt %u startsymb %u, numSymbol %u, occassionsInPrachSlot %u\n", nNumerology, nPrachConfIdx, preambleFmrt, pxRANPrachConfigTable->startingSym, pxRANPrachConfigTable->duration, pxRANPrachConfigTable->occassionsInPrachSlot);
+ if (preambleFmrt <= 2)
+ {
+ pPrachCPConfig->filterIdx = XRAN_FILTERINDEX_PRACH_012; // 1 PRACH preamble format 0 1 2
+ }
+ else if (preambleFmrt == 3)
+ {
+ pPrachCPConfig->filterIdx = XRAN_FILTERINDEX_PRACH_3; // 1 PRACH preamble format 3
+ }
+ else
+ {
pPrachCPConfig->filterIdx = XRAN_FILTERINDEX_PRACH_ABC; // 3, PRACH preamble format A1~3, B1~4, C0, C2
+ }
pPrachCPConfig->startSymId = pxRANPrachConfigTable->startingSym;
pPrachCPConfig->startPrbc = pPRACHConfig->nPrachFreqStart;
pPrachCPConfig->numPrbc = (preambleFmrt >= FORMAT_A1)? 12 : 70;
sym_ota_cb(struct rte_timer *tim, void *arg, unsigned long *used_tick)
{
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
- long t1 = MLogTick(), t2;
+ long t1 = MLogXRANTick(), t2;
long t3;
if(XranGetSymNum(xran_lib_ota_sym_idx[p_xran_dev_ctx->xran_port_id], XRAN_NUM_OF_SYMBOL_PER_SLOT) == 0){
}
}
- t2 = MLogTick();
- MLogTask(PID_SYM_OTA_CB, t1, t2);
+ t2 = MLogXRANTick();
+ MLogXRANTask(PID_SYM_OTA_CB, t1, t2);
}
uint32_t
uint32_t mlogVar[10];
uint32_t mlogVarCnt = 0;
uint64_t t1 = MLogTick();
- uint64_t t3 = 0;
uint32_t reg_tti = 0;
uint32_t reg_sfn = 0;
- uint32_t i;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)p_xran_dev_ctx->timer_ctx;
pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process = xran_lib_ota_tti[PortId];
+ /** tti as seen from PHY */
+ int32_t nSfIdx = -1;
+ uint32_t nFrameIdx;
+ uint32_t nSubframeIdx;
+ uint32_t nSlotIdx;
+ uint64_t nSecond;
+ uint8_t Numerlogy = p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology;
+ uint8_t nNrOfSlotInSf = 1<<Numerlogy;
+
+ xran_get_slot_idx(0, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ nSfIdx = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*nNrOfSlotInSf
+ + nSubframeIdx*nNrOfSlotInSf
+ + nSlotIdx;
+
mlogVar[mlogVarCnt++] = 0x11111111;
mlogVar[mlogVarCnt++] = xran_lib_ota_tti[PortId];
mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx[PortId];
mlogVar[mlogVarCnt++] = frame_id;
mlogVar[mlogVarCnt++] = subframe_id;
mlogVar[mlogVarCnt++] = slot_id;
- mlogVar[mlogVarCnt++] = 0;
+ mlogVar[mlogVarCnt++] = xran_lib_ota_tti[PortId] % XRAN_N_FE_BUF_LEN;
+ mlogVar[mlogVarCnt++] = nSfIdx;
+ mlogVar[mlogVarCnt++] = nSfIdx % XRAN_N_FE_BUF_LEN;
MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
print_dbg("[%d]SFN %d sf %d slot %d\n",xran_lib_ota_tti[PortId], frame_id, subframe_id, slot_id);
xran_lib_ota_tti[PortId] = 0;
}
- MLogTask(PID_TTI_CB, t1, MLogTick());
+ MLogXRANTask(PID_TTI_CB, t1, MLogTick());
+}
+
+
+int32_t
+xran_prepare_cp_dl_slot(uint16_t xran_port_id, uint32_t nSlotIdx, uint32_t nCcStart, uint32_t nCcNum, uint32_t nSymMask, uint32_t nAntStart,
+ uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
+{
+ long t1 = MLogXRANTick();
+ int32_t ret = XRAN_STATUS_SUCCESS;
+ int tti, buf_id;
+ uint32_t slot_id, subframe_id, frame_id;
+ int cc_id;
+ uint8_t ctx_id;
+ uint8_t ant_id, num_eAxc, num_CCPorts;
+ void *pHandle;
+ //int num_list;
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx_by_id(xran_port_id);
+ if(unlikely(!p_xran_dev_ctx))
+ {
+ print_err("Null xRAN context!!\n");
+ return ret;
+ }
+ //struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)&p_xran_dev_ctx->timer_ctx[0];
+ uint32_t interval_us_local = p_xran_dev_ctx->interval_us_local;
+ uint8_t PortId = p_xran_dev_ctx->xran_port_id;
+ pHandle = p_xran_dev_ctx;
+
+ num_eAxc = xran_get_num_eAxc(pHandle);
+ num_CCPorts = xran_get_num_cc(pHandle);
+
+ if(first_call && p_xran_dev_ctx->enableCP)
+ {
+ tti = nSlotIdx ;//pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process;
+ buf_id = tti % XRAN_N_FE_BUF_LEN;
+
+ slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval_us_local));
+ subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval_us_local), SUBFRAMES_PER_SYSTEMFRAME);
+ frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us_local));
+ if (tti == 0)
+ {
+ /* Wrap around to next second */
+ frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
+ }
+
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
+
+ print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id);
+#if defined(__INTEL_COMPILER)
+#pragma vector always
+#endif
+ for(ant_id = nAntStart; (ant_id < (nAntStart + nAntNum) && ant_id < num_eAxc); ++ant_id) {
+ for(cc_id = nCcStart; (cc_id < (nCcStart + nCcNum) && cc_id < num_CCPorts); cc_id++) {
+ /* start new section information list */
+ xran_cp_reset_section_info(pHandle, XRAN_DIR_DL, cc_id, ant_id, ctx_id);
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) {
+ if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers) {
+ if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData) {
+ /*num_list = */xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_DL, tti, cc_id,
+ (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData,
+ &(p_xran_dev_ctx->prbElmProcInfo[buf_id][cc_id][ant_id]),
+ p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
+ } else {
+ print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pData]\n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id);
+ }
+ } else {
+ print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pBuffers] \n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id);
+ }
+ } /* if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) */
+ } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */
+ } /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */
+ MLogXRANTask(PID_CP_DL_CB, t1, MLogXRANTick());
+ }
+ return ret;
}
void
tx_cp_dl_cb(struct rte_timer *tim, void *arg)
{
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
int tti, buf_id;
uint32_t slot_id, subframe_id, frame_id;
int cc_id;
uint8_t ctx_id;
uint8_t ant_id, num_eAxc, num_CCPorts;
void *pHandle;
- int num_list;
+ //int num_list;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
- if(!p_xran_dev_ctx)
+
+ if(unlikely(!p_xran_dev_ctx))
{
print_err("Null xRAN context!!\n");
return;
}
+
+ if (p_xran_dev_ctx->fh_init.io_cfg.bbu_offload)
+ return;
+
struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)&p_xran_dev_ctx->timer_ctx[0];
uint32_t interval_us_local = p_xran_dev_ctx->interval_us_local;
uint8_t PortId = p_xran_dev_ctx->xran_port_id;
num_eAxc = xran_get_num_eAxc(pHandle);
num_CCPorts = xran_get_num_cc(pHandle);
- if(first_call && p_xran_dev_ctx->enableCP) {
-
+ if(first_call && p_xran_dev_ctx->enableCP)
+ {
tti = pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process;
buf_id = tti % XRAN_N_FE_BUF_LEN;
slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval_us_local));
subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval_us_local), SUBFRAMES_PER_SYSTEMFRAME);
frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us_local));
- if (tti == 0){
+ if (tti == 0)
+ {
/* Wrap around to next second */
frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
}
- ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME(interval_us_local)) % XRAN_MAX_SECTIONDB_CTX;
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id);
for(ant_id = 0; ant_id < num_eAxc; ++ant_id) {
for(cc_id = 0; cc_id < num_CCPorts; cc_id++ ) {
- /* start new section information list */
+ if(0== p_xran_dev_ctx->prbElmProcInfo[buf_id][cc_id][ant_id].numSymsRemaining)
+ {/* Start of new slot - reset the section info */
xran_cp_reset_section_info(pHandle, XRAN_DIR_DL, cc_id, ant_id, ctx_id);
+ }
if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) {
if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers) {
if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData){
- num_list = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_DL, tti, cc_id,
+ /*num_list = */xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_DL, tti, cc_id,
(struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData,
+ &(p_xran_dev_ctx->prbElmProcInfo[buf_id][cc_id][ant_id]),
p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
- } else {
- print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pData]\n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id);
}
- } else {
- print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pBuffers] \n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id);
+ else
+ print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pData]\n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id);
}
} /* if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) */
} /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */
} /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */
- MLogTask(PID_CP_DL_CB, t1, MLogTick());
+ MLogXRANTask(PID_CP_DL_CB, t1, MLogXRANTick());
+ }
+}
+
+void
+rx_ul_static_srs_cb(struct rte_timer *tim, void *arg)
+{
+ long t1 = MLogXRANTick();
+ struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
+ xran_status_t status = 0;
+ int32_t rx_tti = 0;// = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+ int32_t cc_id = 0;
+ //uint32_t nFrameIdx;
+ //uint32_t nSubframeIdx;
+ //uint32_t nSlotIdx;
+ //uint64_t nSecond;
+ struct xran_timer_ctx* p_timer_ctx = NULL;
+
+ if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
+ return;
+
+ p_timer_ctx = &p_xran_dev_ctx->cb_timer_ctx[p_xran_dev_ctx->timer_put++ % MAX_CB_TIMER_CTX];
+
+ if (p_xran_dev_ctx->timer_put >= MAX_CB_TIMER_CTX)
+ p_xran_dev_ctx->timer_put = 0;
+
+ rx_tti = p_timer_ctx->tti_to_process;
+
+ if(rx_tti == 0)
+ rx_tti = (xran_fs_get_max_slot_SFN(p_xran_dev_ctx->xran_port_id)-1);
+ else
+ rx_tti -= 1; /* end of RX for prev TTI as measured against current OTA time */
+
+ /* U-Plane */
+ for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) {
+
+ if(0 == p_xran_dev_ctx->enableSrsCp)
+ {
+ if(p_xran_dev_ctx->pSrsCallback[cc_id]){
+ struct xran_cb_tag *pTag = p_xran_dev_ctx->pSrsCallbackTag[cc_id];
+ if(pTag) {
+ //pTag->cellId = cc_id;
+ pTag->slotiId = rx_tti;
+ pTag->symbol = XRAN_FULL_CB_SYM; /* last 7 sym means full slot of Symb */
+ p_xran_dev_ctx->pSrsCallback[cc_id](p_xran_dev_ctx->pSrsCallbackTag[cc_id], status);
+ }
+ }
+ }
+ }
+ MLogXRANTask(PID_UP_STATIC_SRS_DEAD_LINE_CB, t1, MLogXRANTick());
+}
+
+
+
+void
+rx_ul_deadline_one_fourths_cb(struct rte_timer *tim, void *arg)
+{
+ long t1 = MLogXRANTick();
+ struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
+ xran_status_t status;
+ /* half of RX for current TTI as measured against current OTA time */
+ int32_t rx_tti;
+ int32_t cc_id;
+ //uint32_t nFrameIdx;
+ //uint32_t nSubframeIdx;
+ //uint32_t nSlotIdx;
+ //uint64_t nSecond;
+ struct xran_timer_ctx* p_timer_ctx = NULL;
+ /*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME
+ + nSubframeIdx*SLOTNUM_PER_SUBFRAME
+ + nSlotIdx;*/
+ if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
+ return;
+
+ p_timer_ctx = &p_xran_dev_ctx->cb_timer_ctx[p_xran_dev_ctx->timer_put++ % MAX_CB_TIMER_CTX];
+ if (p_xran_dev_ctx->timer_put >= MAX_CB_TIMER_CTX)
+ p_xran_dev_ctx->timer_put = 0;
+
+ rx_tti = p_timer_ctx->tti_to_process;
+
+ for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) {
+ if(p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] == 0){
+ if(p_xran_dev_ctx->pCallback[cc_id]) {
+ struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id];
+ if(pTag) {
+ //pTag->cellId = cc_id;
+ pTag->slotiId = rx_tti;
+ pTag->symbol = XRAN_ONE_FOURTHS_CB_SYM;
+ status = XRAN_STATUS_SUCCESS;
+
+ p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status);
+ }
+ }
+ } else {
+ p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] = 0;
+ }
+ }
+
+ if(p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]){
+ if(p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX] <= 0){
+ p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX](p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]);
+ }else{
+ p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX]--;
+ }
}
+
+ MLogXRANTask(PID_UP_UL_ONE_FOURTHS_DEAD_LINE_CB, t1, MLogXRANTick());
}
void
rx_ul_deadline_half_cb(struct rte_timer *tim, void *arg)
{
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
xran_status_t status;
/* half of RX for current TTI as measured against current OTA time */
int32_t rx_tti;
int32_t cc_id;
- uint32_t nFrameIdx;
- uint32_t nSubframeIdx;
- uint32_t nSlotIdx;
- uint64_t nSecond;
+ //uint32_t nFrameIdx;
+ //uint32_t nSubframeIdx;
+ //uint32_t nSlotIdx;
+ //uint64_t nSecond;
+ struct xran_timer_ctx* p_timer_ctx = NULL;
+ /*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME
+ + nSubframeIdx*SLOTNUM_PER_SUBFRAME
+ + nSlotIdx;*/
+ if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
+ return;
+
+ p_timer_ctx = &p_xran_dev_ctx->cb_timer_ctx[p_xran_dev_ctx->timer_put++ % MAX_CB_TIMER_CTX];
+ if (p_xran_dev_ctx->timer_put >= MAX_CB_TIMER_CTX)
+ p_xran_dev_ctx->timer_put = 0;
+
+ rx_tti = p_timer_ctx->tti_to_process;
+
+ for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) {
+ if(p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] == 0){
+ if(p_xran_dev_ctx->pCallback[cc_id]) {
+ struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id];
+ if(pTag) {
+ //pTag->cellId = cc_id;
+ pTag->slotiId = rx_tti;
+ pTag->symbol = XRAN_HALF_CB_SYM;
+ status = XRAN_STATUS_SUCCESS;
+
+ p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status);
+ }
+ }
+ } else {
+ p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] = 0;
+ }
+ }
+
+ if(p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]){
+ if(p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX] <= 0){
+ p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX](p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]);
+ }else{
+ p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX]--;
+ }
+ }
+
+ MLogXRANTask(PID_UP_UL_HALF_DEAD_LINE_CB, t1, MLogXRANTick());
+}
+
+void
+rx_ul_deadline_three_fourths_cb(struct rte_timer *tim, void *arg)
+{
+ long t1 = MLogXRANTick();
+ struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
+ xran_status_t status;
+ /* half of RX for current TTI as measured against current OTA time */
+ int32_t rx_tti;
+ int32_t cc_id;
+ //uint32_t nFrameIdx;
+ //uint32_t nSubframeIdx;
+ //uint32_t nSlotIdx;
+ //uint64_t nSecond;
struct xran_timer_ctx* p_timer_ctx = NULL;
/*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME
if(pTag) {
//pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
- pTag->symbol = 0; /* last 7 sym means full slot of Symb */
+ pTag->symbol = XRAN_THREE_FOURTHS_CB_SYM;
status = XRAN_STATUS_SUCCESS;
p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status);
}
}
- MLogTask(PID_UP_UL_HALF_DEAD_LINE_CB, t1, MLogTick());
+ MLogXRANTask(PID_UP_UL_THREE_FOURTHS_DEAD_LINE_CB, t1, MLogXRANTick());
}
void
rx_ul_deadline_full_cb(struct rte_timer *tim, void *arg)
{
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
xran_status_t status = 0;
int32_t rx_tti = 0;// = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT);
int32_t cc_id = 0;
- uint32_t nFrameIdx;
- uint32_t nSubframeIdx;
- uint32_t nSlotIdx;
- uint64_t nSecond;
+ //uint32_t nFrameIdx;
+ //uint32_t nSubframeIdx;
+ //uint32_t nSlotIdx;
+ //uint64_t nSecond;
struct xran_timer_ctx* p_timer_ctx = NULL;
if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
if(pTag) {
//pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
- pTag->symbol = 7; /* last 7 sym means full slot of Symb */
+ pTag->symbol = XRAN_FULL_CB_SYM; /* last 7 sym means full slot of Symb */
status = XRAN_STATUS_SUCCESS;
p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status);
}
if(pTag) {
//pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
- pTag->symbol = 7; /* last 7 sym means full slot of Symb */
+ pTag->symbol = XRAN_FULL_CB_SYM; /* last 7 sym means full slot of Symb */
p_xran_dev_ctx->pPrachCallback[cc_id](p_xran_dev_ctx->pPrachCallbackTag[cc_id], status);
}
}
+ if(p_xran_dev_ctx->enableSrsCp)
+ {
if(p_xran_dev_ctx->pSrsCallback[cc_id]){
struct xran_cb_tag *pTag = p_xran_dev_ctx->pSrsCallbackTag[cc_id];
if(pTag) {
//pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
- pTag->symbol = 7; /* last 7 sym means full slot of Symb */
+ pTag->symbol = XRAN_FULL_CB_SYM; /* last 7 sym means full slot of Symb */
p_xran_dev_ctx->pSrsCallback[cc_id](p_xran_dev_ctx->pSrsCallbackTag[cc_id], status);
}
}
}
+ }
/* user call backs if any */
if(p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX]){
}
}
- MLogTask(PID_UP_UL_FULL_DEAD_LINE_CB, t1, MLogTick());
+ MLogXRANTask(PID_UP_UL_FULL_DEAD_LINE_CB, t1, MLogXRANTick());
}
void
rx_ul_user_sym_cb(struct rte_timer *tim, void *arg)
{
- long t1 = MLogTick();
+ long t1 = MLogXRANTick();
struct xran_device_ctx * p_dev_ctx = NULL;
struct cb_user_per_sym_ctx *p_sym_cb_ctx = (struct cb_user_per_sym_ctx *)arg;
- xran_status_t status = 0;
int32_t rx_tti = 0; //(int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT);
- int32_t cc_id = 0;
- uint32_t nFrameIdx;
- uint32_t nSubframeIdx;
- uint32_t nSlotIdx;
- uint64_t nSecond;
uint32_t interval, ota_sym_idx = 0;
uint8_t nNumerology = 0;
struct xran_timer_ctx* p_timer_ctx = NULL;
p_sym_cb_ctx->symCb(p_sym_cb_ctx->symCbParam, p_sym_cb_ctx->symCbTimeInfo);
}
- MLogTask(PID_UP_UL_USER_DEAD_LINE_CB, t1, MLogTick());
+ MLogXRANTask(PID_UP_UL_USER_DEAD_LINE_CB, t1, MLogXRANTick());
}
-void
-tx_cp_ul_cb(struct rte_timer *tim, void *arg)
+int32_t
+xran_prepare_cp_ul_slot(uint16_t xran_port_id, uint32_t nSlotIdx, uint32_t nCcStart, uint32_t nCcNum, uint32_t nSymMask, uint32_t nAntStart,
+ uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
{
- long t1 = MLogTick();
+ int32_t ret = XRAN_STATUS_SUCCESS;
+ long t1 = MLogXRANTick();
int tti, buf_id;
- int ret;
uint32_t slot_id, subframe_id, frame_id;
int32_t cc_id;
- int ant_id, prach_port_id;
+ int ant_id, port_id;
uint16_t occasionid;
uint16_t beam_id;
uint8_t num_eAxc, num_CCPorts;
uint8_t ctx_id;
void *pHandle;
- int num_list;
+ uint32_t interval;
+ uint8_t PortId;
- struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
- if(!p_xran_dev_ctx)
+ //struct xran_timer_ctx *pTCtx;
+ struct xran_buffer_list *pBufList;
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx_by_id(xran_port_id);
+ if(unlikely(!p_xran_dev_ctx))
{
print_err("Null xRAN context!!\n");
- return;
+ return ret;
}
- struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
- struct xran_timer_ctx *pTCtx = &p_xran_dev_ctx->timer_ctx[0];
- uint32_t interval = p_xran_dev_ctx->interval_us_local;
- uint8_t PortId = p_xran_dev_ctx->xran_port_id;
- tti = pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process;
- buf_id = tti % XRAN_N_FE_BUF_LEN;
- slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval));
- subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
- frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
- if (tti == 0) {
- //Wrap around to next second
- frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
- }
- ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME(interval)) % XRAN_MAX_SECTIONDB_CTX;
+ if(first_call && p_xran_dev_ctx->enableCP)
+ {
+ pHandle = p_xran_dev_ctx;
+ //pTCtx = &p_xran_dev_ctx->timer_ctx[0];
+ interval = p_xran_dev_ctx->interval_us_local;
+ PortId = p_xran_dev_ctx->xran_port_id;
+ tti = nSlotIdx; //pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process;
+
+ buf_id = tti % XRAN_N_FE_BUF_LEN;
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
+ slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval));
+ subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
+ frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
+
+ /* Wrap around to next second */
+ if(tti == 0)
+ frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
+ if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_A)
+ num_eAxc = xran_get_num_eAxc(pHandle);
+ else
+ num_eAxc = xran_get_num_eAxcUl(pHandle);
+ num_CCPorts = xran_get_num_cc(pHandle);
- pHandle = p_xran_dev_ctx;
- if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_A)
+ print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id);
+
+ /* General Uplink */
+#if defined(__INTEL_COMPILER)
+#pragma vector always
+#endif
+ for(ant_id = nAntStart; (ant_id < (nAntStart + nAntNum) && ant_id < num_eAxc); ++ant_id) {
+ for(cc_id = nCcStart; (cc_id < (nCcStart + nCcNum) && cc_id < num_CCPorts); cc_id++) {
+ /* start new section information list */
+ xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, ant_id, ctx_id);
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1)
+ {
+ pBufList = &(p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList); /* To shorten reference */
+ if(pBufList->pBuffers && pBufList->pBuffers->pData)
+ {
+ ret = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_UL, tti, cc_id,
+ (struct xran_prb_map *)(pBufList->pBuffers->pData), NULL,
+ p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
+ }
+ }
+ }
+ } /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */
+
+ /* PRACH */
+ if(p_xran_dev_ctx->enablePrach)
+ {
+ struct xran_prach_cp_config *pPrachCPConfig = NULL;
+ //check for dss enable and fill based on technology select the p_xran_dev_ctx->PrachCPConfig NR/LTE.
+ if(p_xran_dev_ctx->dssEnable){
+ int i = tti % p_xran_dev_ctx->dssPeriod;
+ if(p_xran_dev_ctx->technology[i]==1) {
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfigLTE);
+ }
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+ uint32_t is_prach_slot = xran_is_prach_slot(PortId, subframe_id, slot_id);
+
+ if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0])
+ && (is_prach_slot==1))
+ {
+ for(ant_id = 0; ant_id < num_eAxc; ant_id++)
+ {
+ port_id = ant_id + pPrachCPConfig->eAxC_offset;
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ /* start new section information list */
+ xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, port_id, ctx_id);
+ for(occasionid = 0; occasionid < pPrachCPConfig->occassionsInPrachSlot; occasionid++)
+ {
+ struct xran_cp_gen_params params;
+ struct xran_section_gen_info sect_geninfo[8];
+ struct xran_section_info sectInfo[8];
+ for(int secId=0;secId<8;secId++)
+ sect_geninfo[secId].info = §Info[secId];
+ struct rte_mbuf *mbuf = xran_ethdi_mbuf_alloc();
+ uint8_t seqid = xran_get_cp_seqid(pHandle, XRAN_DIR_UL, cc_id, port_id);
+
+ beam_id = xran_get_beamid(pHandle, XRAN_DIR_UL, cc_id, port_id, slot_id);
+ ret = generate_cpmsg_prach(pHandle, ¶ms, sect_geninfo, mbuf, p_xran_dev_ctx,
+ frame_id, subframe_id, slot_id, tti,
+ beam_id, cc_id, port_id, occasionid, seqid);
+ if(ret == XRAN_STATUS_SUCCESS)
+ send_cpmsg(pHandle, mbuf, ¶ms, sect_geninfo,
+ cc_id, port_id, seqid);
+ }
+ }
+ }
+ }
+ } /* if(p_xran_dev_ctx->enablePrach) */
+
+ /* SRS */
+ if(p_xran_dev_ctx->enableSrsCp)
+ {
+ struct xran_srs_config *pSrsCfg = &(p_xran_dev_ctx->srs_cfg);
+
+ for(ant_id = 0; ant_id < xran_get_num_ant_elm(pHandle); ant_id++)
+ {
+ port_id = ant_id + pSrsCfg->eAxC_offset;
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ /* start new section information list */
+ xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, port_id, ctx_id);
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ {
+ pBufList = &(p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList); /* To shorten reference */
+ if(pBufList->pBuffers && pBufList->pBuffers->pData)
+ {
+ ret = xran_cp_create_and_send_section(pHandle, port_id, XRAN_DIR_UL, tti, cc_id,
+ (struct xran_prb_map *)(pBufList->pBuffers->pData), NULL,
+ p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
+ }
+ }
+ }
+ }
+ } /* if(p_xran_dev_ctx->enableSrs) */
+
+ MLogXRANTask(PID_CP_UL_CB, t1, MLogXRANTick());
+ } /* if(p_xran_dev_ctx->enableCP) */
+
+ return ret;
+}
+
+
+void
+tx_cp_ul_cb(struct rte_timer *tim, void *arg)
+{
+ long t1 = MLogXRANTick();
+ int tti, buf_id;
+ int ret;
+ uint32_t slot_id, subframe_id, frame_id;
+ int32_t cc_id;
+ int ant_id, port_id;
+ uint16_t occasionid = 0;
+ uint16_t beam_id;
+ uint8_t num_eAxc, num_CCPorts;
+ uint8_t ctx_id;
+
+ void *pHandle;
+ uint32_t interval;
+ uint8_t PortId;
+
+ struct xran_timer_ctx *pTCtx;
+ struct xran_buffer_list *pBufList;
+ struct xran_device_ctx *p_xran_dev_ctx;
+
+ if(unlikely(!arg))
+ {
+ print_err("Null xRAN context!!\n");
+ return;
+ }
+
+ p_xran_dev_ctx = (struct xran_device_ctx *)arg;
+
+ if (p_xran_dev_ctx->fh_init.io_cfg.bbu_offload)
+ return;
+
+ /* */
+ if(first_call && p_xran_dev_ctx->enableCP)
+ {
+ pHandle = p_xran_dev_ctx;
+ pTCtx = &p_xran_dev_ctx->timer_ctx[0];
+ interval = p_xran_dev_ctx->interval_us_local;
+ PortId = p_xran_dev_ctx->xran_port_id;
+ tti = pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process;
+
+ buf_id = tti % XRAN_N_FE_BUF_LEN;
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
+ slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval));
+ subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
+ frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
+
+ /* Wrap around to next second */
+ if(tti == 0)
+ frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
+ if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_A)
num_eAxc = xran_get_num_eAxc(pHandle);
else
num_eAxc = xran_get_num_eAxcUl(pHandle);
num_CCPorts = xran_get_num_cc(pHandle);
- if(first_call && p_xran_dev_ctx->enableCP) {
-
print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id);
- for(ant_id = 0; ant_id < num_eAxc; ++ant_id) {
- for(cc_id = 0; cc_id < num_CCPorts; cc_id++) {
- if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1
- /* || xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_SP) == 1*/ ) {
+ /* General Uplink */
+ for(ant_id = 0; ant_id < num_eAxc; ant_id++)
+ {
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
/* start new section information list */
xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, ant_id, ctx_id);
- if(p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers){
- if(p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData){
- num_list = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_UL, tti, cc_id,
- (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData,
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1)
+ {
+ pBufList = &(p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList); /* To shorten reference */
+ if(pBufList->pBuffers && pBufList->pBuffers->pData)
+ {
+ ret = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_UL, tti, cc_id,
+ (struct xran_prb_map *)(pBufList->pBuffers->pData), NULL,
p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
}
}
}
+ } /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */
+
+ /* PRACH */
+ if(p_xran_dev_ctx->enablePrach)
+ {
+ struct xran_prach_cp_config *pPrachCPConfig = NULL;
+ //check for dss enable and fill based on technology select the p_xran_dev_ctx->PrachCPConfig NR/LTE.
+ if(p_xran_dev_ctx->dssEnable){
+ int i = tti % p_xran_dev_ctx->dssPeriod;
+ if(p_xran_dev_ctx->technology[i]==1) {
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfigLTE);
+ }
}
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
}
- if(p_xran_dev_ctx->enablePrach) {
uint32_t is_prach_slot = xran_is_prach_slot(PortId, subframe_id, slot_id);
- if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0]) && (is_prach_slot==1)) { //is prach slot
- for(ant_id = 0; ant_id < num_eAxc; ++ant_id) {
- for(cc_id = 0; cc_id < num_CCPorts; cc_id++) {
- for (occasionid = 0; occasionid < pPrachCPConfig->occassionsInPrachSlot; occasionid++) {
+
+ if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0])
+ && (is_prach_slot==1))
+ {
+ for(ant_id = 0; ant_id < num_eAxc; ant_id++)
+ {
+ port_id = ant_id + pPrachCPConfig->eAxC_offset;
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ /* start new section information list */
+ xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, port_id, ctx_id);
+#ifndef FCN_ADAPT
+//for FCN only send C-P for first occasion
+ for(occasionid = 0; occasionid < pPrachCPConfig->occassionsInPrachSlot; occasionid++)
+#endif
+ {
struct xran_cp_gen_params params;
struct xran_section_gen_info sect_geninfo[8];
+ struct xran_section_info sectInfo[8];
+ for(int secId=0;secId<8;secId++)
+ sect_geninfo[secId].info = §Info[secId];
+
struct rte_mbuf *mbuf = xran_ethdi_mbuf_alloc();
- prach_port_id = ant_id + num_eAxc;
- /* start new section information list */
- xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, prach_port_id, ctx_id);
+ uint8_t seqid = xran_get_cp_seqid(pHandle, XRAN_DIR_UL, cc_id, port_id);
- beam_id = xran_get_beamid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id, slot_id);
+ beam_id = xran_get_beamid(pHandle, XRAN_DIR_UL, cc_id, port_id, slot_id);
ret = generate_cpmsg_prach(pHandle, ¶ms, sect_geninfo, mbuf, p_xran_dev_ctx,
- frame_id, subframe_id, slot_id,
- beam_id, cc_id, prach_port_id, occasionid,
- xran_get_cp_seqid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id));
+ frame_id, subframe_id, slot_id, tti,
+ beam_id, cc_id, port_id, occasionid, seqid);
if (ret == XRAN_STATUS_SUCCESS)
send_cpmsg(pHandle, mbuf, ¶ms, sect_geninfo,
- cc_id, prach_port_id, xran_get_cp_seqid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id));
+ cc_id, port_id, seqid);
+ }
+ }
}
}
+ } /* if(p_xran_dev_ctx->enablePrach) */
+
+ /* SRS */
+ if(p_xran_dev_ctx->enableSrsCp)
+ {
+ struct xran_srs_config *pSrsCfg = &(p_xran_dev_ctx->srs_cfg);
+
+ for(ant_id = 0; ant_id < xran_get_num_ant_elm(pHandle); ant_id++)
+ {
+ port_id = ant_id + pSrsCfg->eAxC_offset;
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ /* start new section information list */
+ xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, port_id, ctx_id);
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ {
+ pBufList = &(p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList); /* To shorten reference */
+ if(pBufList->pBuffers && pBufList->pBuffers->pData)
+ {
+ ret = xran_cp_create_and_send_section(pHandle, port_id, XRAN_DIR_UL, tti, cc_id,
+ (struct xran_prb_map *)(pBufList->pBuffers->pData), NULL,
+ p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
}
}
}
- } /* if(p_xran_dev_ctx->enableCP) */
+ }
+ } /* if(p_xran_dev_ctx->enableSrs) */
- MLogTask(PID_CP_UL_CB, t1, MLogTick());
+ MLogXRANTask(PID_CP_UL_CB, t1, MLogXRANTick());
+ } /* if(p_xran_dev_ctx->enableCP) */
}
void
{
int res = 0;
cpu_set_t cpuset;
- int32_t do_reset = 0;
- uint64_t t1 = 0;
- uint64_t delta;
- int32_t result1,i,j;
-
+ int32_t result1;
uint32_t xran_port_id = 0;
static int owdm_init_done = 0;
-
struct sched_param sched_param;
struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *) args ;
uint64_t tWake = 0, tWakePrev = 0, tUsed = 0;
- struct cb_elem_entry * cb_elm = NULL;
-
struct xran_device_ctx * p_dev_ctx_run = NULL;
/* ToS = Top of Second start +- 1.5us */
struct timespec ts;
CPU_ZERO(&cpuset);
CPU_SET(p_dev_ctx->fh_init.io_cfg.timing_core, &cpuset);
- if (result1 = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset))
+ if ((result1 = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset)))
{
printf("pthread_setaffinity_np failed: coreId = 2, result1 = %d\n",result1);
}
tWakePrev = tWake;
tUsed = 0;
- delta = poll_next_tick(interval_us*1000L/N_SYM_PER_SLOT, &tUsed);
+ int64_t delta = poll_next_tick(interval_us*1000L/N_SYM_PER_SLOT, &tUsed);
if (XRAN_STOPPED == xran_if_current_state)
break;
+ if (delta > 3E5 && tUsed > 0)//300us about 9 symbols
+ {
+ print_err("poll_next_tick too long, delta:%ld(ns), tUsed:%ld(tick)", delta, tUsed);
+ }
+
if (likely(XRAN_RUNNING == xran_if_current_state)) {
for(xran_port_id = 0; xran_port_id < XRAN_PORTS_NUM; xran_port_id++ ) {
p_dev_ctx_run = xran_dev_get_ctx_by_id(xran_port_id);
int32_t handle_ecpri_ethertype(struct rte_mbuf* pkt_q[], uint16_t xport_id, struct xran_eaxc_info *p_cid, uint16_t num)
{
- struct rte_mbuf* pkt, * pkt0;
+ struct rte_mbuf *pkt;
uint16_t i;
struct rte_ether_hdr* eth_hdr;
struct xran_ecpri_hdr* ecpri_hdr;
- union xran_ecpri_cmn_hdr* ecpri_cmn;
unsigned long t1;
int32_t ret = MBUF_FREE;
uint32_t ret_data[MBUFS_CNT] = { MBUFS_CNT * MBUF_FREE };
{
for (i = 0; i < MBUFS_CNT; i++)
{
- ret_data[i] == MBUF_FREE;
+ ret_data[i] = MBUF_FREE;
}
if (p_dev_ctx->fh_init.io_cfg.id == O_DU || p_dev_ctx->fh_init.io_cfg.id == O_RU)
for (i = 0; i < num_control; i++)
{
- t1 = MLogTick();
+ t1 = MLogXRANTick();
if (p_dev_ctx->fh_init.io_cfg.id == O_RU)
{
ret = process_cplane(pkt_control[i], (void*)p_dev_ctx);
{
print_err("O-DU recevied C-Plane message!");
}
- MLogTask(PID_PROCESS_CP_PKT, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_CP_PKT, t1, MLogXRANTick());
}
for (i = 0; i < num_meas; i++)
{
- t1 = MLogTick();
+
+ /*if(p_dev_ctx->fh_init.io_cfg.id == O_RU)
+ printf("Got delay_meas_pkt xport_id %d p_dev_ctx %08"PRIx64" %d\n", xport_id,(int64_t*)p_dev_ctx, num_meas) ;*/
+ t1 = MLogXRANTick();
+ if(xran_if_current_state != XRAN_RUNNING)
ret = process_delay_meas(pkt_meas[i], (void*)p_dev_ctx, xport_id);
- // printf("Got delay_meas_pkt xport_id %d p_dev_ctx %08"PRIx64"\n", xport_id,(int64_t*)p_dev_ctx) ;
+ else
+ ret = MBUF_FREE;
if (ret == MBUF_FREE)
rte_pktmbuf_free(pkt_meas[i]);
- MLogTask(PID_PROCESS_DELAY_MEAS_PKT, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_DELAY_MEAS_PKT, t1, MLogXRANTick());
}
}
int32_t
xran_packet_and_dpdk_timer_thread(void *args)
{
- struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
+ //struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
uint64_t prev_tsc = 0;
uint64_t cur_tsc = rte_rdtsc();
uint64_t diff_tsc = cur_tsc - prev_tsc;
- cpu_set_t cpuset;
struct sched_param sched_param;
int res = 0;
printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid());
int32_t i;
int32_t j;
int32_t o_xu_id = 0;
-
struct xran_io_cfg *p_io_cfg = NULL;
struct xran_device_ctx * p_xran_dev_ctx = NULL;
-
int32_t lcore_id = 0;
- char filename[64];
-
const char *version = rte_version();
if (version == NULL)
print_err("fh_init xran_ports= %d is wrong [%d]\n", p_xran_fh_init->xran_ports, ret);
return ret;
}
-
+ mlogxranenable = p_xran_fh_init->mlogxranenable;
p_io_cfg = (struct xran_io_cfg *)&p_xran_fh_init->io_cfg;
if ((ret = xran_dev_create_ctx(p_xran_fh_init->xran_ports)) < 0) {
xran_sector_get_instances (uint32_t xran_port, void * pDevHandle, uint16_t nNumInstances,
xran_cc_handle_t * pSectorInstanceHandles)
{
- xran_status_t nStatus = XRAN_STATUS_FAIL;
struct xran_device_ctx *pDev = (struct xran_device_ctx *)pDevHandle;
XranSectorHandleInfo *pCcHandle = NULL;
int32_t i = 0;
xran_transport_callback_fn pCallback,
void *pCallbackTag)
{
- int j, i = 0, z, k;
+ int j, i = 0, z;
XranSectorHandleInfo* pXranCc = NULL;
struct xran_device_ctx * p_xran_dev_ctx = NULL;
p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pDstCpBuffer[z][j];
else
memset(&p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pDstCpBuffer[z][j]));
-
}
}
return XRAN_STATUS_SUCCESS;
}
+int32_t xran_5g_bfw_config(void * pHandle,
+ struct xran_buffer_list *pSrcRxCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN],
+ struct xran_buffer_list *pSrcTxCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN],
+ xran_transport_callback_fn pCallback,
+ void *pCallbackTag){
+ int j, i = 0, z;
+ XranSectorHandleInfo* pXranCc = NULL;
+ struct xran_device_ctx * p_xran_dev_ctx = NULL;
+
+ if(NULL == pHandle) {
+ printf("Handle is NULL!\n");
+ return XRAN_STATUS_FAIL;
+ }
+ pXranCc = (XranSectorHandleInfo*) pHandle;
+ p_xran_dev_ctx = xran_dev_get_ctx_by_id(pXranCc->nXranPort);
+ if (p_xran_dev_ctx == NULL) {
+ printf ("p_xran_dev_ctx is NULL\n");
+ return XRAN_STATUS_FAIL;
+ }
+
+ i = pXranCc->nIndex;
+
+ for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ /* C-plane RX - RU */
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFrontHaulRxPrbMapBuffers[j][i][z][0];
+
+ if(pSrcRxCpBuffer[z][j])
+ p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pSrcRxCpBuffer[z][j];
+ else
+ memset(&p_xran_dev_ctx->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pSrcRxCpBuffer[z][j]));
+
+ /* C-plane TX - RU */
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFrontHaulTxPrbMapBuffers[j][i][z][0];
+
+ if(pSrcTxCpBuffer[z][j])
+ p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pSrcTxCpBuffer[z][j];
+ else
+ memset(&p_xran_dev_ctx->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pSrcTxCpBuffer[z][j]));
+ }
+ }
+ return XRAN_STATUS_SUCCESS;
+}
+
int32_t
xran_5g_prach_req (void * pHandle,
struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN],
i = pXranCc->nIndex;
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < XRAN_MAX_PRACH_ANT_NUM; z++){
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
- p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR; // ant number.
+ p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_PRACH_ANT_NUM; // ant number.
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHPrachRxBuffers[j][i][z][0];
if(pDstBuffer[z][j])
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHPrachRxBuffersDecomp[j][i][z][0];
if(pDstBufferDecomp[z][j])
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList = *pDstBufferDecomp[z][j];
-
}
}
xran_pkt_gen_process_ring(struct rte_ring *r)
{
assert(r);
- int32_t retval = 0;
struct rte_mbuf *mbufs[16];
int i;
uint32_t remaining;
const uint16_t dequeued = rte_ring_dequeue_burst(r, (void **)mbufs,
RTE_DIM(mbufs), &remaining);
+
if (!dequeued)
return 0;
- t1 = MLogTick();
+ t1 = MLogXRANTick();
for (i = 0; i < dequeued; ++i) {
struct cp_up_tx_desc * p_tx_desc = (struct cp_up_tx_desc *)rte_pktmbuf_mtod(mbufs[i], struct cp_up_tx_desc *);
- retval = xran_process_tx_sym_cp_on_opt(p_tx_desc->pHandle,
+ xran_process_tx_sym_cp_on_opt(p_tx_desc->pHandle,
p_tx_desc->ctx_id,
p_tx_desc->tti,
- p_tx_desc->cc_id,
- p_tx_desc->ant_id,
+ p_tx_desc->start_cc,
+ p_tx_desc->cc_num,
+ p_tx_desc->start_ant,
+ p_tx_desc->ant_num,
p_tx_desc->frame_id,
p_tx_desc->subframe_id,
p_tx_desc->slot_id,
xran_pkt_gen_desc_free(p_tx_desc);
if (XRAN_STOPPED == xran_if_current_state){
- MLogTask(PID_PROCESS_TX_SYM, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_TX_SYM, t1, MLogXRANTick());
return -1;
}
}
if(p_io_cfg->io_sleep)
nanosleep(&sleeptime,NULL);
- MLogTask(PID_PROCESS_TX_SYM, t1, MLogTick());
+ MLogXRANTask(PID_PROCESS_TX_SYM, t1, MLogXRANTick());
return remaining;
}
return 0;
}
+int32_t xran_fh_rx_and_up_tx_processing(void *port_mask)
+{
+ int32_t ret_val=0;
+
+ ret_val = ring_processing_func((void *)0);
+ if(ret_val != 0)
+ return ret_val;
+
+ ret_val = xran_dl_pkt_ring_processing_func(port_mask);
+ if(ret_val != 0)
+ return ret_val;
+
+ return 0;
+}
/** Function to peforms serves of DPDK times */
int32_t
xran_processing_timer_only_func(void* args)
ring_processing_func_per_port(void* args)
{
struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
- int16_t retPoll = 0;
int32_t i;
- uint64_t t1, t2;
uint16_t port_id = (uint16_t)((uint64_t)args & 0xFFFF);
queueid_t qi;
uint32_t worker_num_cores = 0;
uint32_t icx_cpu = 0;
int32_t core_map[2*sizeof(uint64_t)*8];
- uint32_t xran_port_mask = 0;
+ uint64_t xran_port_mask = 0;
struct xran_ethdi_ctx *eth_ctx = xran_ethdi_get_ctx();
struct xran_device_ctx *p_dev = NULL;
struct xran_fh_init *fh_init = NULL;
struct xran_fh_config *fh_cfg = NULL;
struct xran_worker_th_ctx* pThCtx = NULL;
+ void *worker_ports=NULL;
p_dev = xran_dev_get_ctx_by_id(0);
if(p_dev == NULL) {
printf("O-RU eAxC %d\n", fh_cfg->neAxc);
for (i = 0; i < fh_init->xran_ports; i++){
- xran_port_mask |= 1<<i;
+ xran_port_mask |= 1L<<i;
}
for (i = 0; i < fh_init->xran_ports; i++) {
print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
return XRAN_STATUS_FAIL;
}
- } else if (fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_B && fh_init->xran_ports == 1) {
+ } else if ((fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_B && fh_init->xran_ports == 1) || fh_init->io_cfg.bbu_offload) {
switch(total_num_cores) {
case 1: /** only timing core */
print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
eth_ctx->time_wrk_cfg.arg = NULL;
eth_ctx->time_wrk_cfg.state = 1;
+ if (p_dev->fh_init.io_cfg.bbu_offload)
+ p_dev->tx_sym_gen_func = xran_process_tx_sym_cp_on_ring;
+ else
p_dev->tx_sym_gen_func = xran_process_tx_sym_cp_on_opt;
pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
eth_ctx->pkt_wrk_cfg[0].arg = pThCtx;
break;
case 3:
- if(icx_cpu) {
+ if(1) {
/* timing core */
eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks;
eth_ctx->time_wrk_cfg.arg = NULL;
}
break;
case 4:
- if(icx_cpu) {
+ if(1) {
/* timing core */
eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks;
eth_ctx->time_wrk_cfg.arg = NULL;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(((1<<1) | (1<<2) |(1<<0)) & xran_port_mask);
+ pThCtx->task_arg = (void*)(((1L<<1) | (1L<<2) |(1L<<0)) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ pThCtx->task_arg = (void*)((1L<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
}
break;
case 5:
- if(icx_cpu) {
+ if(1) {
/* timing core */
eth_ctx->time_wrk_cfg.f = xran_eth_rx_tasks;
eth_ctx->time_wrk_cfg.arg = NULL;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(((1<<1) | (1<<2) |(1<<0)) & xran_port_mask);
+ pThCtx->task_arg = (void*)(((1L<<1) | (1L<<2) |(1L<<0)) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ pThCtx->task_arg = (void*)((1L<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ pThCtx->task_arg = (void*)((1L<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(((1<<1) | (1<<2) |(1<<0)) & xran_port_mask);
+ pThCtx->task_arg = (void*)(((1L<<1) | (1L<<2) |(1L<<0)) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ pThCtx->task_arg = (void*)((1L<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ pThCtx->task_arg = (void*)((1L<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
} else if (fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_B && fh_init->xran_ports > 1) {
switch(total_num_cores) {
case 1:
+ print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
+ return XRAN_STATUS_FAIL;
+ break;
+
case 2:
+ if(fh_init->xran_ports == 2)
+ worker_ports = (void *)((1L<<0 | 1L<<1) & xran_port_mask);
+ else if(fh_init->xran_ports == 3)
+ worker_ports = (void *)((1L<<0 | 1L<<1 | 1L<<2) & xran_port_mask);
+ else if(fh_init->xran_ports == 4)
+ worker_ports = (void *)((1L<<0 | 1L<<1 | 1L<<2 | 1L<<3) & xran_port_mask);
+ else
+ {
print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
return XRAN_STATUS_FAIL;
+ }
+
+ eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks;
+ eth_ctx->time_wrk_cfg.arg = NULL;
+ eth_ctx->time_wrk_cfg.state = 1;
+
+ /* p_dev->tx_sym_gen_func = xran_process_tx_sym_cp_on_opt; */
+
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 0;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_fh_rx_and_up_tx_processing;
+ pThCtx->task_arg = worker_ports;
+ eth_ctx->pkt_wrk_cfg[0].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[0].arg = pThCtx;
+
+ for (i = 1; i < fh_init->xran_ports; i++) {
+ struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i);
+ if(p_dev_update == NULL) {
+ print_err("p_dev_update\n");
+ return XRAN_STATUS_FAIL;
+ }
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id;
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id;
+ printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]);
+ printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]);
+ }
break;
case 3:
if(icx_cpu) {
pThCtx->task_arg = (void*)xran_port_mask;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
- } else {
+ }
+ else /* csx cpu */
+ {
+ if(fh_init->xran_ports == 3)
+ worker_ports = (void *)(1L<<2 & xran_port_mask);
+ else if(fh_init->xran_ports == 4)
+ worker_ports = (void *)((1L<<2 | 1L<<3) & xran_port_mask);
+ else{
print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
return XRAN_STATUS_FAIL;
}
+ /* timing core */
+ eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks;
+ eth_ctx->time_wrk_cfg.arg = NULL;
+ eth_ctx->time_wrk_cfg.state = 1;
+
+ /* workers */
+ /** 0 **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 0;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_dl_pkt_ring_processing_func;
+ pThCtx->task_arg = (void *)((1L<<0|1L<<1) & xran_port_mask);
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ for (i = 1; i < fh_init->xran_ports; i++) {
+ struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i);
+ if(p_dev_update == NULL) {
+ print_err("p_dev_update\n");
+ return XRAN_STATUS_FAIL;
+ }
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id;
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id;
+ printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]);
+ printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]);
+ }
+
+ /** 1 - CP GEN **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 1;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_fh_rx_and_up_tx_processing;
+ pThCtx->task_arg = worker_ports;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+ }
+
break;
+
case 4:
- if(icx_cpu) {
+ if(1) {
/* timing core */
eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks;
eth_ctx->time_wrk_cfg.arg = NULL;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(((1<<1) | (1<<2)) & xran_port_mask);
+ pThCtx->task_arg = (void*)(((1L<<1) | (1L<<2)) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ pThCtx->task_arg = (void*)((1L<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]);
printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]);
}
- } else {
+ }
+ else {
print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
return XRAN_STATUS_FAIL;
}
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(1<<0);
+ pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_up_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(1<<1);
+ pThCtx->task_arg = (void*)((1<<1) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_up_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(1<<2);
+ pThCtx->task_arg = (void*)((1<<2) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+
+ if(eth_ctx->io_cfg.id == O_DU && 0 == fh_init->dlCpProcBurst) {
+ for (i = 1; i < fh_init->xran_ports; i++) {
+ struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i);
+ if(p_dev_update == NULL) {
+ print_err("p_dev_update\n");
+ return XRAN_STATUS_FAIL;
+ }
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = i+1;
+ printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]);
+ }
+ }
+
break;
case 6:
if(eth_ctx->io_cfg.id == O_DU){
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(1<<0);
+ pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(1<<1);
+ pThCtx->task_arg = (void*)((1<<1) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
pThCtx->task_func = xran_dl_pkt_ring_processing_func;
- pThCtx->task_arg = (void*)(1<<2);
+ pThCtx->task_arg = (void*)((1<<2) & xran_port_mask);
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
} else {
pThCtx->worker_core_id = core_map[pThCtx->worker_id];
snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_tx", core_map[pThCtx->worker_id]);
pThCtx->task_func = process_dpdk_io_tx;
- pThCtx->task_arg = (void*)2;
+ pThCtx->task_arg = NULL;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
}
break;
- default:
- print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
- return XRAN_STATUS_FAIL;
- }
- } else {
- print_err("unsupported configuration\n");
- return XRAN_STATUS_FAIL;
- }
+ case 7:
+ /*** O_RU specific config */
+ if((fh_init->xran_ports == 4) && (eth_ctx->io_cfg.id == O_RU))
+ {
+ /*** O_RU specific config */
+ /* timing core */
+ eth_ctx->time_wrk_cfg.f = NULL;
+ eth_ctx->time_wrk_cfg.arg = NULL;
+ eth_ctx->time_wrk_cfg.state = 1;
- nWorkerCore = 1LL;
- if(eth_ctx->io_cfg.pkt_proc_core) {
- for (i = 0; i < coreNum && i < 64; i++) {
- if (nWorkerCore & (uint64_t)eth_ctx->io_cfg.pkt_proc_core) {
- xran_core_used[xran_num_cores_used++] = i;
- if (rte_eal_remote_launch(eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f, eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].arg, i))
- rte_panic("eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f() failed to start\n");
- eth_ctx->pkt_wrk_cfg[i].state = 1;
- if(eth_ctx->pkt_proc_core_id == 0)
+ /* workers */
+ /** 0 Eth RX */
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 0;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_rx", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = process_dpdk_io_rx;
+ pThCtx->task_arg = NULL;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** 1 FH RX and BBDEV */
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 1;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p0", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = ring_processing_func_per_port;
+ pThCtx->task_arg = (void*)0;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** 2 FH RX and BBDEV */
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 2;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p1", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = ring_processing_func_per_port;
+ pThCtx->task_arg = (void*)1;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** 3 FH RX and BBDEV */
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 3;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p2", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = ring_processing_func_per_port;
+ pThCtx->task_arg = (void*)2;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** 4 FH RX and BBDEV */
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 4;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p3", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = ring_processing_func_per_port;
+ pThCtx->task_arg = (void*)3;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** FH TX and BBDEV */
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 5;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_tx", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = process_dpdk_io_tx;
+ pThCtx->task_arg = NULL;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ } /* -- if xran->ports == 4 -- */
+ else if(eth_ctx->io_cfg.id == O_DU){
+ if(fh_init->xran_ports == 3)
+ worker_ports = (void *)((1<<2) & xran_port_mask);
+ else if(fh_init->xran_ports == 4)
+ worker_ports = (void *)((1<<3) & xran_port_mask);
+ /* timing core */
+ eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks;
+ eth_ctx->time_wrk_cfg.arg = NULL;
+ eth_ctx->time_wrk_cfg.state = 1;
+
+ /* workers */
+ /** 0 **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 0;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = ring_processing_func;
+ pThCtx->task_arg = NULL;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ for (i = 2; i < fh_init->xran_ports; i++) {
+ struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i);
+ if(p_dev_update == NULL) {
+ print_err("p_dev_update\n");
+ return XRAN_STATUS_FAIL;
+ }
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id;
+ printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]);
+ }
+
+ /** 1 - CP GEN **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 1;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_processing_timer_only_func;
+ pThCtx->task_arg = NULL;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** 2 UP GEN **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 2;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_dl_pkt_ring_processing_func;
+ pThCtx->task_arg = (void*)((1<<0) & xran_port_mask);
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ for (i = (fh_init->xran_ports-1); i < fh_init->xran_ports; i++) {
+ struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i);
+ if(p_dev_update == NULL) {
+ print_err("p_dev_update\n");
+ return XRAN_STATUS_FAIL;
+ }
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id;
+ printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]);
+ }
+
+ /** 3 UP GEN **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 3;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_dl_pkt_ring_processing_func;
+ pThCtx->task_arg = (void*)((1<<1) & xran_port_mask);
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ for (i = (fh_init->xran_ports - 2); i < (fh_init->xran_ports - 1); i++) {
+ struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i);
+ if(p_dev_update == NULL) {
+ print_err("p_dev_update\n");
+ return XRAN_STATUS_FAIL;
+ }
+ p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id;
+ printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]);
+ }
+
+ /** 4 UP GEN **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 4;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_dl_pkt_ring_processing_func;
+ pThCtx->task_arg = (void*)((1<<2) & xran_port_mask);
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+
+ /** 5 UP GEN **/
+ pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64);
+ if(pThCtx == NULL){
+ print_err("pThCtx allocation error\n");
+ return XRAN_STATUS_FAIL;
+ }
+ memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx));
+ pThCtx->worker_id = 5;
+ pThCtx->worker_core_id = core_map[pThCtx->worker_id];
+ snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]);
+ pThCtx->task_func = xran_dl_pkt_ring_processing_func;
+ pThCtx->task_arg = worker_ports;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread;
+ eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx;
+ }
+ else{
+ print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
+ return XRAN_STATUS_FAIL;
+ }
+ break;
+
+ default:
+ print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores);
+ return XRAN_STATUS_FAIL;
+ }
+ } else {
+ print_err("unsupported configuration\n");
+ return XRAN_STATUS_FAIL;
+ }
+
+ nWorkerCore = 1LL;
+ if(eth_ctx->io_cfg.pkt_proc_core) {
+ for (i = 0; i < coreNum && i < 64; i++) {
+ if (nWorkerCore & (uint64_t)eth_ctx->io_cfg.pkt_proc_core) {
+ xran_core_used[xran_num_cores_used++] = i;
+ if (rte_eal_remote_launch(eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f, eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].arg, i))
+ rte_panic("eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f() failed to start\n");
+ eth_ctx->pkt_wrk_cfg[i].state = 1;
+ if(eth_ctx->pkt_proc_core_id == 0)
eth_ctx->pkt_proc_core_id = i;
printf("spawn worker %d core %d\n",eth_ctx->num_workers, i);
eth_ctx->worker_core[eth_ctx->num_workers++] = i;
int32_t ret = XRAN_STATUS_SUCCESS;
int32_t i;
uint8_t nNumerology = 0;
- int32_t lcore_id = 0;
struct xran_device_ctx *p_xran_dev_ctx = NULL;
struct xran_fh_config *pFhCfg = NULL;
struct xran_fh_init *fh_init = NULL;
if(pConf->dpdk_port < XRAN_PORTS_NUM) {
p_xran_dev_ctx = xran_dev_get_ctx_by_id(pConf->dpdk_port);
} else {
- print_err("@0x%08p [ru %d ] pConf->dpdk_port > XRAN_PORTS_NUM\n", pConf, pConf->dpdk_port);
+ print_err("@0x%p [ru %d ] pConf->dpdk_port > XRAN_PORTS_NUM\n", pConf, pConf->dpdk_port);
return XRAN_STATUS_FAIL;
}
p_xran_dev_ctx->enableCP = pConf->enableCP;
p_xran_dev_ctx->enablePrach = pConf->prachEnable;
p_xran_dev_ctx->enableSrs = pConf->srsEnable;
+ p_xran_dev_ctx->enableSrsCp = pConf->srsEnableCp;
+ p_xran_dev_ctx->nSrsDelaySym = pConf->SrsDelaySym;
p_xran_dev_ctx->puschMaskEnable = pConf->puschMaskEnable;
p_xran_dev_ctx->puschMaskSlot = pConf->puschMaskSlot;
p_xran_dev_ctx->DynamicSectionEna = pConf->DynamicSectionEna;
+ p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable = pConf->RunSlotPrbMapBySymbolEnable;
+ p_xran_dev_ctx->dssEnable = pConf->dssEnable;
+ p_xran_dev_ctx->dssPeriod = pConf->dssPeriod;
+ for(i=0; i<pConf->dssPeriod; i++) {
+ p_xran_dev_ctx->technology[i] = pConf->technology[i];
+ }
if(pConf->GPS_Alpha || pConf->GPS_Beta ){
offset_sec = pConf->GPS_Beta / 100; /* resolution of beta is 10ms */
}
/* setup PRACH configuration for C-Plane */
+ if(pConf->dssEnable){
+ if((ret = xran_init_prach(pConf, p_xran_dev_ctx, XRAN_RAN_5GNR))< 0)
+ return ret;
+ if((ret = xran_init_prach_lte(pConf, p_xran_dev_ctx))< 0)
+ return ret;
+ }
+ else{
if(pConf->ru_conf.xranTech == XRAN_RAN_5GNR) {
- if((ret = xran_init_prach(pConf, p_xran_dev_ctx))< 0){
+ if((ret = xran_init_prach(pConf, p_xran_dev_ctx, XRAN_RAN_5GNR))< 0){
return ret;
}
} else if (pConf->ru_conf.xranTech == XRAN_RAN_LTE) {
return ret;
}
}
+ }
if((ret = xran_init_srs(pConf, p_xran_dev_ctx))< 0){
return ret;
p_xran_dev_ctx->tx_sym_gen_func = xran_process_tx_sym_cp_on_dispatch_opt;
}
+ if (p_xran_dev_ctx->fh_init.io_cfg.bbu_offload)
+ p_xran_dev_ctx->tx_sym_gen_func = xran_process_tx_sym_cp_on_ring;
+ printf("bbu_offload %d\n", p_xran_dev_ctx->fh_init.io_cfg.bbu_offload);
if(pConf->dpdk_port == 0) {
/* create all thread on open of port 0 */
xran_num_cores_used = 0;
/* ToS = Top of Second start +- 1.5us */
struct timespec ts;
char buff[100];
-
+ int i;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ struct xran_prb_map * prbMap0 = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[0][0][0].sBufferList.pBuffers->pData;
+ for(i = 0; i < XRAN_MAX_SECTIONS_PER_SLOT && i < prbMap0->nPrbElm; i++)
+ {
+ p_xran_dev_ctx->numSetBFWs_arr[i] = prbMap0->prbMap[i].bf_weight.numSetBFWs;
+ }
+
if(xran_get_if_state() == XRAN_RUNNING) {
print_err("Already STARTED!!");
return (-1);
{
return timing_set_debug_stop(value, count);
}
+
+
+int32_t xran_get_num_prb_elm(struct xran_prb_map* p_PrbMapIn, uint32_t mtu)
+{
+ int32_t i,j = 0;
+ int16_t iqwidth = p_PrbMapIn->prbMap[0].iqWidth;
+ struct xran_prb_elm *p_prb_elm_src;
+ int32_t nRBremain;
+ // int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr);
+ // int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqwidth);
+ int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr) - sizeof(struct data_section_hdr);
+ int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/(XRAN_PAYLOAD_1_RB_SZ(iqwidth)+sizeof(struct data_section_hdr));
+ uint32_t nRBSize=0;
+
+ if (mtu==9600)
+ nmaxRB--; //for some reason when mtu is 9600, only 195 RB can be sent, not 196
+
+ for (i = 0;i < p_PrbMapIn->nPrbElm; i++)
+ {
+ p_prb_elm_src = &p_PrbMapIn->prbMap[i];
+ if (p_prb_elm_src->nRBSize <= nmaxRB) //no fragmentation needed
+ {
+ j++;
+ }
+ else
+ {
+ nRBremain = p_prb_elm_src->nRBSize - nmaxRB;
+ j++;
+ while (nRBremain > 0)
+ {
+ nRBSize = RTE_MIN(nmaxRB, nRBremain);
+ nRBremain -= nRBSize;
+ j++;
+ }
+ }
+ }
+
+ return j;
+}
+
+
+int32_t xran_init_PrbMap_from_cfg(struct xran_prb_map* p_PrbMapIn, struct xran_prb_map* p_PrbMapOut, uint32_t mtu)
+{
+ int32_t i,j = 0;
+ int16_t iqwidth = p_PrbMapIn->prbMap[0].iqWidth;
+ struct xran_prb_elm *p_prb_elm_src, *p_prb_elm_dst;
+ int32_t nRBStart_tmp, nRBremain;
+ // int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr);
+ // int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqwidth);
+ int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr) - sizeof(struct data_section_hdr);
+ int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/(XRAN_PAYLOAD_1_RB_SZ(iqwidth)+sizeof(struct data_section_hdr));
+
+ if (mtu==9600)
+ nmaxRB--; //for some reason when mtu is 9600, only 195 RB can be sent, not 196
+
+ memcpy(p_PrbMapOut, p_PrbMapIn, sizeof(struct xran_prb_map));
+ for (i = 0;i < p_PrbMapIn->nPrbElm; i++)
+ {
+ p_prb_elm_src = &p_PrbMapIn->prbMap[i];
+ p_prb_elm_dst = &p_PrbMapOut->prbMap[j];
+ memcpy(p_prb_elm_dst, p_prb_elm_src, sizeof(struct xran_prb_elm));
+
+ // int32_t nStartSymb, nEndSymb, numSymb, nRBStart, nRBEnd, nRBSize;
+ // nStartSymb = p_prb_elm_src->nStartSymb;
+ // nEndSymb = nStartSymb + p_prb_elm_src->numSymb;
+ if (p_prb_elm_src->nRBSize <= nmaxRB) //no fragmentation needed
+ {
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->UP_nRBSize = p_prb_elm_src->nRBSize;
+ p_prb_elm_dst->UP_nRBStart = p_prb_elm_src->nRBStart;
+ p_prb_elm_dst->nSectId = i;
+ j++;
+ }
+ else
+ {
+ nRBStart_tmp = p_prb_elm_src->nRBStart + nmaxRB;
+ nRBremain = p_prb_elm_src->nRBSize - nmaxRB;
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->UP_nRBSize = nmaxRB;
+ p_prb_elm_dst->UP_nRBStart = p_prb_elm_src->nRBStart;
+ p_prb_elm_dst->nSectId = i;
+ j++;
+ while (nRBremain > 0)
+ {
+ p_prb_elm_dst = &p_PrbMapOut->prbMap[j];
+ memcpy(p_prb_elm_dst, p_prb_elm_src, sizeof(struct xran_prb_elm));
+ p_prb_elm_dst->IsNewSect = 0;
+ p_prb_elm_dst->UP_nRBSize = RTE_MIN(nmaxRB, nRBremain);
+ p_prb_elm_dst->UP_nRBStart = nRBStart_tmp;
+ nRBremain -= p_prb_elm_dst->UP_nRBSize;
+ nRBStart_tmp += p_prb_elm_dst->UP_nRBSize;
+ p_prb_elm_dst->nSectId = i;
+ j++;
+ }
+ }
+ }
+
+ p_PrbMapOut->nPrbElm = j;
+ return 0;
+}
+
+
+int32_t xran_init_PrbMap_from_cfg_for_rx(struct xran_prb_map* p_PrbMapIn, struct xran_prb_map* p_PrbMapOut, uint32_t mtu)
+{
+ int32_t i,j = 0;
+ int16_t iqwidth = p_PrbMapIn->prbMap[0].iqWidth;
+ struct xran_prb_elm *p_prb_elm_src, *p_prb_elm_dst;
+ int32_t nRBStart_tmp, nRBremain;
+ // int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr);
+ // int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqwidth);
+ int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr) - sizeof(struct data_section_hdr);
+ int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/(XRAN_PAYLOAD_1_RB_SZ(iqwidth)+sizeof(struct data_section_hdr));
+
+ if (mtu==9600)
+ nmaxRB--; //for some reason when mtu is 9600, only 195 RB can be sent, not 196
+ nmaxRB *= XRAN_MAX_FRAGMENT;
+
+ memcpy(p_PrbMapOut, p_PrbMapIn, sizeof(struct xran_prb_map));
+ for (i = 0;i < p_PrbMapIn->nPrbElm; i++)
+ {
+ p_prb_elm_src = &p_PrbMapIn->prbMap[i];
+ p_prb_elm_dst = &p_PrbMapOut->prbMap[j];
+ memcpy(p_prb_elm_dst, p_prb_elm_src, sizeof(struct xran_prb_elm));
+
+ if (p_prb_elm_src->nRBSize <= nmaxRB) //no fragmentation needed
+ {
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->UP_nRBSize = p_prb_elm_src->nRBSize;
+ p_prb_elm_dst->UP_nRBStart = p_prb_elm_src->nRBStart;
+ p_prb_elm_dst->nSectId = j;
+ j++;
+ }
+ else
+ {
+ nRBStart_tmp = p_prb_elm_src->nRBStart + nmaxRB;
+ nRBremain = p_prb_elm_src->nRBSize - nmaxRB;
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->nRBSize = nmaxRB;
+ p_prb_elm_dst->UP_nRBSize = nmaxRB;
+ p_prb_elm_dst->UP_nRBStart = p_prb_elm_src->nRBStart;
+ p_prb_elm_dst->nSectId = j;
+ j++;
+ while (nRBremain > 0)
+ {
+ p_prb_elm_dst = &p_PrbMapOut->prbMap[j];
+ memcpy(p_prb_elm_dst, p_prb_elm_src, sizeof(struct xran_prb_elm));
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->nRBSize = RTE_MIN(nmaxRB, nRBremain);
+ p_prb_elm_dst->nRBStart = nRBStart_tmp;
+ p_prb_elm_dst->UP_nRBSize = RTE_MIN(nmaxRB, nRBremain);
+ p_prb_elm_dst->UP_nRBStart = nRBStart_tmp;
+ nRBremain -= p_prb_elm_dst->UP_nRBSize;
+ nRBStart_tmp += p_prb_elm_dst->UP_nRBSize;
+ p_prb_elm_dst->nSectId = j;
+ j++;
+ }
+ }
+ }
+
+ p_PrbMapOut->nPrbElm = j;
+ return 0;
+}
+
+
+int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, struct xran_prb_map* p_PrbMapOut, uint32_t mtu, uint32_t xran_max_prb)
+{
+ int32_t i = 0, j = 0, nPrbElm = 0;
+ int16_t iqwidth = p_PrbMapIn->prbMap[0].iqWidth;
+ struct xran_prb_elm *p_prb_elm_src, *p_prb_elm_dst;
+ struct xran_prb_elm prbMapTemp[XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ int32_t nRBStart_tmp, nRBremain, nStartSymb, nEndSymb, nRBStart, nRBEnd, nRBSize;
+ // int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr);
+ // int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqwidth);
+ int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr) - sizeof(struct data_section_hdr);
+ int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/(XRAN_PAYLOAD_1_RB_SZ(iqwidth)+sizeof(struct data_section_hdr));
+ if (mtu==9600)
+ nmaxRB--; //for some reason when mtu is 9600, only 195 RB can be sent, not 196
+
+
+ memcpy(p_PrbMapOut, p_PrbMapIn, sizeof(struct xran_prb_map));
+ for(i = 0; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++)
+ {
+ p_prb_elm_dst = &prbMapTemp[i];
+ // nRBStart = 273;
+ nRBStart = xran_max_prb;
+ nRBEnd = 0;
+
+ for(j = 0; j < p_PrbMapIn->nPrbElm; j++)
+ {
+ p_prb_elm_src = &(p_PrbMapIn->prbMap[j]);
+ nStartSymb = p_prb_elm_src->nStartSymb;
+ nEndSymb = nStartSymb + p_prb_elm_src->numSymb;
+
+ if((i >= nStartSymb) && (i < nEndSymb))
+ {
+ if(nRBStart > p_prb_elm_src->nRBStart)
+ {
+ nRBStart = p_prb_elm_src->nRBStart;
+ }
+ if(nRBEnd < (p_prb_elm_src->nRBStart + p_prb_elm_src->nRBSize))
+ {
+ nRBEnd = (p_prb_elm_src->nRBStart + p_prb_elm_src->nRBSize);
+ }
+
+ p_prb_elm_dst->nBeamIndex = p_prb_elm_src->nBeamIndex;
+ p_prb_elm_dst->bf_weight_update = p_prb_elm_src->bf_weight_update;
+ p_prb_elm_dst->compMethod = p_prb_elm_src->compMethod;
+ p_prb_elm_dst->iqWidth = p_prb_elm_src->iqWidth;
+ p_prb_elm_dst->ScaleFactor = p_prb_elm_src->ScaleFactor;
+ p_prb_elm_dst->reMask = p_prb_elm_src->reMask;
+ p_prb_elm_dst->BeamFormingType = p_prb_elm_src->BeamFormingType;
+ }
+ }
+
+ if(nRBEnd < nRBStart)
+ {
+ p_prb_elm_dst->nRBStart = 0;
+ p_prb_elm_dst->nRBSize = 0;
+ p_prb_elm_dst->nStartSymb = i;
+ p_prb_elm_dst->numSymb = 1;
+ }
+ else
+ {
+ p_prb_elm_dst->nRBStart = nRBStart;
+ p_prb_elm_dst->nRBSize = nRBEnd - nRBStart;
+ p_prb_elm_dst->nStartSymb = i;
+ p_prb_elm_dst->numSymb = 1;
+ }
+ }
+
+ for(i = 0; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++)
+ {
+ if((prbMapTemp[i].nRBSize != 0))
+ {
+ nRBStart = prbMapTemp[i].nRBStart;
+ nRBSize = prbMapTemp[i].nRBSize;
+ prbMapTemp[nPrbElm].nRBStart = prbMapTemp[i].nRBStart;
+ prbMapTemp[nPrbElm].nRBSize = prbMapTemp[i].nRBSize;
+ prbMapTemp[nPrbElm].nStartSymb = prbMapTemp[i].nStartSymb;
+ prbMapTemp[nPrbElm].nBeamIndex = prbMapTemp[i].nBeamIndex;
+ prbMapTemp[nPrbElm].bf_weight_update = prbMapTemp[i].bf_weight_update;
+ prbMapTemp[nPrbElm].compMethod = prbMapTemp[i].compMethod;
+ prbMapTemp[nPrbElm].iqWidth = prbMapTemp[i].iqWidth;
+ prbMapTemp[nPrbElm].ScaleFactor = prbMapTemp[i].ScaleFactor;
+ prbMapTemp[nPrbElm].reMask = prbMapTemp[i].reMask;
+ prbMapTemp[nPrbElm].BeamFormingType = prbMapTemp[i].BeamFormingType;
+ i++;
+ break;
+ }
+ }
+
+ for(; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++)
+ {
+ if((nRBStart == prbMapTemp[i].nRBStart) && (nRBSize == prbMapTemp[i].nRBSize))
+ {
+ prbMapTemp[nPrbElm].numSymb++;
+ }
+ else
+ {
+ nPrbElm++;
+ prbMapTemp[nPrbElm].nStartSymb = prbMapTemp[i].nStartSymb;
+ prbMapTemp[nPrbElm].nRBStart = prbMapTemp[i].nRBStart;
+ prbMapTemp[nPrbElm].nRBSize = prbMapTemp[i].nRBSize;
+ prbMapTemp[nPrbElm].nBeamIndex = prbMapTemp[i].nBeamIndex;
+ prbMapTemp[nPrbElm].bf_weight_update = prbMapTemp[i].bf_weight_update;
+ prbMapTemp[nPrbElm].compMethod = prbMapTemp[i].compMethod;
+ prbMapTemp[nPrbElm].iqWidth = prbMapTemp[i].iqWidth;
+ prbMapTemp[nPrbElm].ScaleFactor = prbMapTemp[i].ScaleFactor;
+ prbMapTemp[nPrbElm].reMask = prbMapTemp[i].reMask;
+ prbMapTemp[nPrbElm].BeamFormingType = prbMapTemp[i].BeamFormingType;
+
+ nRBStart = prbMapTemp[i].nRBStart;
+ nRBSize = prbMapTemp[i].nRBSize;
+ }
+ }
+
+ for(i = 0; i < nPrbElm; i++)
+ {
+ if(prbMapTemp[i].nRBSize == 0)
+ prbMapTemp[i].nRBSize = 1;
+ }
+
+ if(prbMapTemp[nPrbElm].nRBSize != 0)
+ nPrbElm++;
+
+
+ j = 0;
+
+ for (i = 0;i < nPrbElm; i++)
+ {
+ p_prb_elm_src = &prbMapTemp[i];
+ p_prb_elm_dst = &p_PrbMapOut->prbMap[j];
+ memcpy(p_prb_elm_dst, p_prb_elm_src, sizeof(struct xran_prb_elm));
+ if (p_prb_elm_src->nRBSize <= nmaxRB) //no fragmentation needed
+ {
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->UP_nRBSize = p_prb_elm_src->nRBSize;
+ p_prb_elm_dst->UP_nRBStart = p_prb_elm_src->nRBStart;
+ p_prb_elm_dst->nSectId = i;
+ j++;
+ }
+ else
+ {
+ nRBStart_tmp = p_prb_elm_src->nRBStart + nmaxRB;
+ nRBremain = p_prb_elm_src->nRBSize - nmaxRB;
+ p_prb_elm_dst->IsNewSect = 1;
+ p_prb_elm_dst->UP_nRBSize = nmaxRB;
+ p_prb_elm_dst->UP_nRBStart = p_prb_elm_src->nRBStart;
+ p_prb_elm_dst->nSectId = i;
+ j++;
+ while (nRBremain > 0)
+ {
+ p_prb_elm_dst = &p_PrbMapOut->prbMap[j];
+ memcpy(p_prb_elm_dst, p_prb_elm_src, sizeof(struct xran_prb_elm));
+ p_prb_elm_dst->IsNewSect = 0;
+ p_prb_elm_dst->UP_nRBSize = RTE_MIN(nmaxRB, nRBremain);
+ p_prb_elm_dst->UP_nRBStart = nRBStart_tmp;
+ nRBremain -= p_prb_elm_dst->UP_nRBSize;
+ nRBStart_tmp += p_prb_elm_dst->UP_nRBSize;
+ p_prb_elm_dst->nSectId = i;
+ j++;
+ }
+ }
+ }
+
+ p_PrbMapOut->nPrbElm = j;
+
+ return 0;
+}
+
+inline void MLogXRANTask(uint32_t taskid, uint64_t ticksstart, uint64_t ticksstop)
+{
+ if (mlogxranenable)
+ {
+ MLogTask(taskid, ticksstart, ticksstop);
+ }
+ return;
+}
+
+inline uint64_t MLogXRANTick(void)
+{
+ if (mlogxranenable)
+ return MLogTick();
+ else
+ return 0;
+}
+
+
extern uint16_t xran_max_frame;
static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */
-
uint32_t xran_schedule_to_worker(enum xran_job_type_id job_type_id, struct xran_device_ctx * p_xran_dev_ctx);
uint16_t xran_getSfnSecStart(void);
void tx_cp_dl_cb(struct rte_timer *tim, void *arg);
void rx_ul_deadline_full_cb(struct rte_timer *tim, void *arg);
void rx_ul_user_sym_cb(struct rte_timer *tim, void *arg);
void rx_ul_deadline_half_cb(struct rte_timer *tim, void *arg);
+void rx_ul_deadline_one_fourths_cb(struct rte_timer *tim, void *arg);
+void rx_ul_deadline_three_fourths_cb(struct rte_timer *tim, void *arg);
+void rx_ul_static_srs_cb(struct rte_timer *tim, void *arg);
+int32_t xran_fh_rx_and_up_tx_processing(void *port_mask);
#ifdef __cplusplus
}
int32_t
xran_bm_init (void * pHandle, uint32_t * pPoolIndex, uint32_t nNumberOfBuffers, uint32_t nBufferSize)
{
+ //printf("nNumberOfBuffers=%u\n", nNumberOfBuffers);
+ if(nNumberOfBuffers == 280)
+ nNumberOfBuffers = 560;
+
XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle;
uint32_t nAllocBufferSize;
return -1;
}
- printf("%s: [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d\n", pool_name,
- pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize);
+ printf("%s: [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d socket_id %d\n", pool_name,
+ pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, rte_socket_id());
pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex] = rte_pktmbuf_pool_create(pool_name, nNumberOfBuffers,
- MBUF_CACHE, 0, nAllocBufferSize, rte_socket_id());
+ /*MBUF_CACHE*/0, 0, nAllocBufferSize, rte_socket_id());
+
if(pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex] == NULL){
- rte_panic("rte_pktmbuf_pool_create failed [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d errno %s\n",
- pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, rte_strerror(rte_errno));
+ rte_panic("rte_pktmbuf_pool_create failed [poolName=%s, handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d errno %s\n",
+ pool_name, pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, rte_strerror(rte_errno));
return -1;
}
-
+ //printf("press enter (RTE_MEMPOOL_NAMESIZE=%u)\n", RTE_MEMPOOL_NAMESIZE);
+ //getchar();
pXranCc->bufferPoolElmSz[pXranCc->nBufferPoolIndex] = nBufferSize;
pXranCc->bufferPoolNumElm[pXranCc->nBufferPoolIndex] = nNumberOfBuffers;
}
int32_t
-xran_bm_free_buffer(void * pHandle, void *pData, void *pCtrl)
+xran_bm_allocate_ring(void * pHandle, const char *rng_name_prefix, uint16_t cc_id, uint16_t buff_id, uint16_t ant_id, uint16_t symb_id, void **ppRing)
{
+ int32_t ret = 0;
XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle;
+ uint32_t xran_port_id;
+ char ring_name[32] = "";
+ struct rte_ring *ring = NULL;
+ ssize_t r_size;
+
+ if(pHandle){
+ xran_port_id = pXranCc->nXranPort;
+ *ppRing = NULL;
+ snprintf(ring_name, RTE_DIM(ring_name), "%srb%dp%dcc%dant%dsym%d", rng_name_prefix, buff_id, xran_port_id, cc_id, ant_id, symb_id);
+ print_dbg("%s\n", ring_name);
+ r_size = rte_ring_get_memsize(XRAN_MAX_MEM_IF_RING_SIZE);
+ ring = (struct rte_ring *)xran_malloc(r_size);
+ if(ring == NULL) {
+ print_err("[%srb%dp%dcc%dant%dsym%d] ring alloc failed \n", rng_name_prefix, buff_id, xran_port_id, cc_id, ant_id, symb_id);
+ return -1;
+ }
+ ret = rte_ring_init(ring, ring_name, XRAN_MAX_MEM_IF_RING_SIZE, /*RING_F_SC_DEQ*/0);
+ if(ret != 0){
+ print_err("[%srb%dp%dcc%dant%dsym%d] rte_ring_init failed \n", rng_name_prefix, buff_id, xran_port_id, cc_id, ant_id, symb_id);
+ return -1;
+ }
+
+ if(ring) {
+ *ppRing = (void *)ring;
+ }else {
+ print_err("[%srb%dp%dcc%dant%dsym%d] ring alloc failed \n", rng_name_prefix, buff_id, xran_port_id, cc_id, ant_id, symb_id);
+ return -1;
+ }
+ } else {
+ print_err("pHandle failed \n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int32_t
+xran_bm_free_buffer(void * pHandle, void *pData, void *pCtrl)
+{
+ //XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle;
if(pCtrl)
rte_pktmbuf_free(pCtrl);
#include "xran_fh_o_du.h"
-
#ifdef __cplusplus
}
#endif
#include "xran_dev.h"
#include "xran_frame_struct.h"
#include "xran_printf.h"
-#include "xran_app_frag.h"
#include "xran_rx_proc.h"
#include "xran_cp_proc.h"
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
uint8_t symb_id_offset;
uint32_t tti = 0;
- xran_status_t status;
- void *pHandle = NULL;
+ uint32_t ttt_det = 0;
+ //xran_status_t status;
struct rte_mbuf *mb;
uint32_t interval = p_xran_dev_ctx->interval_us_local;
tti = frame_id * SLOTS_PER_SYSTEMFRAME(interval) + subframe_id * SLOTNUM_PER_SUBFRAME(interval) + slot_id;
- status = tti << 16 | symb_id;
+ //status = tti << 16 | symb_id;
+
+
+ struct xran_prach_cp_config *pPrachCPConfig;
+ uint32_t StartUsedFirstSym;
+ if(p_xran_dev_ctx->dssEnable){
+ int i = tti % p_xran_dev_ctx->dssPeriod;
+ if(p_xran_dev_ctx->technology[i]==1) {
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfigLTE);
+ }
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+
+
+ if (1500 == p_xran_dev_ctx->fh_init.mtu && pPrachCPConfig->filterIdx == XRAN_FILTERINDEX_PRACH_012)
+ {
+ /*one prach for more then one pkg*/
+ StartUsedFirstSym = 1;
+ }
+ else{
+ StartUsedFirstSym = 0;
+ }
+
if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < XRAN_MAX_ANTENNA_NR && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT){
+ uint8_t numerology = xran_get_conf_numerology(p_xran_dev_ctx);
+ if (numerology > 0 && pPrachCPConfig->filterIdx == XRAN_FILTERINDEX_PRACH_012) ttt_det = (1<<numerology) - 1;
+ else ttt_det = 0;
+
+ if (1 == StartUsedFirstSym)
+ {
+ uint8_t compMeth = p_xran_dev_ctx->fh_cfg.ru_conf.compMeth;
+ uint8_t iqWidth = p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth;
+ uint32_t iqLenPrePrb,dataOffset,dataLen;
+ uint8_t * pdata;
+ symb_id_offset = 0;
+ if (XRAN_COMPMETHOD_NONE == compMeth)
+ {
+ iqLenPrePrb = 48;
+ }
+ else
+ {
+ iqLenPrePrb = 3*iqWidth+1;
+ }
+ dataOffset = start_prbu*iqLenPrePrb;
+ dataLen = num_prbu*iqLenPrePrb;
+
+ if(iq_data_start && size) {
+ pdata = p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[(tti + ttt_det)% XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData + dataOffset;
+ mb = p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[(tti + ttt_det)% XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl;
+ if(mb)
+ rte_pktmbuf_free(mb);
+
+ if(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) {
+ int idx = 0;
+ uint16_t *psrc = (uint16_t *)iq_data_start;
+ uint16_t *pdst = (uint16_t *)pdata;
+ for (idx = 0; idx < dataLen; idx++){
+ pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]);
+ }
+ //*mb_free = MBUF_FREE;
+ }
+ else{
+ memcpy(pdata,iq_data_start,dataLen);
+ }
+
+ p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[(tti + ttt_det) % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl = mbuf;
+ *mb_free = MBUF_KEEP;
+ }
+ else {
+ //print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size);
+ print_err("iq_data_start %p size %d\n", iq_data_start, size);
+ }
+
+ }
+ else
+ {
symb_id_offset = symb_id - p_xran_dev_ctx->prach_start_symbol[CC_ID]; //make the storing of prach packets to start from 0 for easy of processing within PHY
// pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData;
if(iq_data_start && size) {
- mb = p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl;
+ mb = p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[(tti + ttt_det) % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl;
if(mb)
rte_pktmbuf_free(mb);
//*mb_free = MBUF_FREE;
}
- p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData = iq_data_start;
- p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl = mbuf;
-
+ p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[(tti + ttt_det) % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData = iq_data_start;
+ p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[(tti + ttt_det) % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl = mbuf;
*mb_free = MBUF_KEEP;
}
else {
//print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size);
print_err("iq_data_start %p size %d\n", iq_data_start, size);
}
+
+ }
+
} else {
print_err("TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id);
}
char *pos = NULL;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
uint32_t tti = 0;
- xran_status_t status;
- void *pHandle = NULL;
struct rte_mbuf *mb = NULL;
struct xran_prb_map * pRbMap = NULL;
struct xran_prb_elm * prbMapElm = NULL;
tti = frame_id * SLOTS_PER_SYSTEMFRAME(interval) + subframe_id * SLOTNUM_PER_SUBFRAME(interval) + slot_id;
- status = tti << 16 | symb_id;
-
if(CC_ID != 0)
rte_panic("CC_ID != 0");
- if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < p_xran_dev_ctx->fh_cfg.nAntElmTRx && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT) {
+
+ if(CC_ID < XRAN_MAX_SECTOR_NR
+ && Ant_ID < p_xran_dev_ctx->fh_cfg.nAntElmTRx
+ && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT)
+ {
+ if (0 == p_xran_dev_ctx->enableSrsCp)
+ {
+
+ struct xran_section_desc *p_sec_desc = NULL;
pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData;
pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData;
- if(pRbMap){
+
+
+ if(pRbMap && pRbMap->nPrbElm > 0)
+ {
+ prbMapElm = &pRbMap->prbMap[0];
+ if (symb_id < prbMapElm->nStartSymb || symb_id >= (prbMapElm->nStartSymb + prbMapElm->numSymb))
+ {
+ print_err("%dnot srs symbole, srs sym start is %d,num is %d\n", symb_id,prbMapElm->nStartSymb,prbMapElm->numSymb);
+ *mb_free = MBUF_FREE;
+ return size;
+ }
+ sec_desc_idx = prbMapElm->nSecDesc[0];
+ p_sec_desc = &(prbMapElm->sec_desc[0][0]);
+ if(sec_desc_idx >= XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_FRAGMENT)
+ {
+ print_err("sec_desc_idx %d is more then %d\n", sec_desc_idx,XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_FRAGMENT);
+ *mb_free = MBUF_FREE;
+ return size;
+ }
+
+ pos += start_prbu * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits);
+ if(pos && iq_data_start && size)
+ {
+ if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER)
+ {
+ rte_panic("XRAN_CPU_LE_BYTE_ORDER is not supported 0x16%lx\n", (long)mb);
+ }
+ else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER))
+ {
+ p_sec_desc += sec_desc_idx;
+ if(p_sec_desc)
+ {
+ mb = p_sec_desc->pCtrl;
+ if(mb)
+ {
+ rte_pktmbuf_free(mb);
+ }
+ p_sec_desc->pData = iq_data_start;
+ p_sec_desc->pCtrl = mbuf;
+ p_sec_desc->start_prbu = start_prbu;
+ p_sec_desc->num_prbu = num_prbu;
+ p_sec_desc->iq_buffer_len = size;
+ p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf);
+ prbMapElm->nSecDesc[0] += 1;
+ }
+ else
+ {
+ print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx);
+ *mb_free = MBUF_FREE;
+ return size;
+ }
+ *mb_free = MBUF_KEEP;
+ } /* else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)) */
+ } /* if(pos && iq_data_start && size) */
+ else
+ {
+ print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size);
+ }
+
+ }
+ else
+ {
+ print_err("pRbMap==NULL\n");
+ *mb_free = MBUF_FREE;
+ return size;
+ }
+
+ }
+ else
+ {
+ pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData;
+ pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData;
+ if(pRbMap)
+ {
prbMapElm = &pRbMap->prbMap[sect_id];
- if(sect_id >= pRbMap->nPrbElm) {
+ if(sect_id >= pRbMap->nPrbElm)
+ {
print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm);
*mb_free = MBUF_FREE;
return size;
}
- } else {
+ }
+ else
+ {
print_err("pRbMap==NULL\n");
*mb_free = MBUF_FREE;
return size;
}
+
pos += start_prbu * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits);
- if(pos && iq_data_start && size){
- if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) {
+ if(pos && iq_data_start && size)
+ {
+ if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER)
+ {
int idx = 0;
uint16_t *psrc = (uint16_t *)iq_data_start;
uint16_t *pdst = (uint16_t *)pos;
rte_panic("XRAN_CPU_LE_BYTE_ORDER is not supported 0x16%lx\n", (long)mb);
/* network byte (be) order of IQ to CPU byte order (le) */
- for (idx = 0; idx < size/sizeof(int16_t); idx++){
+ for (idx = 0; idx < size/sizeof(int16_t); idx++)
+ {
pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]);
}
- } else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){
- /*if (pRbMap->nPrbElm == 1){
+ }
+ else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER))
+ {
+ /*if (pRbMap->nPrbElm == 1)
+ {
if (likely (p_xran_dev_ctx->fh_init.mtu >=
p_xran_dev_ctx->fh_cfg.nULRBs * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits)))
{
p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData = iq_data_start;
p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl = mbuf;
*mb_free = MBUF_KEEP;
- } else {
+ }
+ else
+ {
// packet can be fragmented copy RBs
memcpy(pos, iq_data_start, size);
*mb_free = MBUF_FREE;
}
- } else */{
+ }
+ else */
+ {
struct xran_section_desc *p_sec_desc = NULL;
prbMapElm = &pRbMap->prbMap[sect_id];
- sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id];
+ // sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id];
+ sec_desc_idx = prbMapElm->nSecDesc[symb_id];
- if (sec_desc_idx < XRAN_MAX_FRAGMENT) {
- p_sec_desc = prbMapElm->p_sec_desc[symb_id][sec_desc_idx];
- } else {
- print_err("sect_id %d: sec_desc_idx %d tti %u ant %d symb_id %d sec_desc_idx %d\n", sect_id, sec_desc_idx, tti, Ant_ID, symb_id, sec_desc_idx);
+ if (sec_desc_idx < XRAN_MAX_FRAGMENT)
+ {
+ p_sec_desc = &prbMapElm->sec_desc[symb_id][sec_desc_idx];
+ }
+ else
+ {
+ print_err("[p %d]sect_id %d: sec_desc_idx %d tti %u ant %d symb_id %d sec_desc_idx %d\n", p_xran_dev_ctx->xran_port_id, sect_id, sec_desc_idx, tti, Ant_ID, symb_id, sec_desc_idx);
prbMapElm->nSecDesc[symb_id] = 0;
*mb_free = MBUF_FREE;
return size;
}
- if(p_sec_desc){
+ if(p_sec_desc)
+ {
mb = p_sec_desc->pCtrl;
- if(mb){
+ if(mb)
+ {
rte_pktmbuf_free(mb);
}
p_sec_desc->pData = iq_data_start;
p_sec_desc->num_prbu = num_prbu;
p_sec_desc->iq_buffer_len = size;
p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf);
- //prbMapElm->nSecDesc[symb_id] += 1;
- } else {
+ prbMapElm->nSecDesc[symb_id] += 1;
+ }
+ else
+ {
print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx);
*mb_free = MBUF_FREE;
return size;
}
*mb_free = MBUF_KEEP;
}
- }
- } else {
+ } /* else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)) */
+ } /* if(pos && iq_data_start && size) */
+ else
+ {
print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size);
}
- } else {
+ }
+ } /* if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < p_xran_dev_ctx->fh_cfg.nAntElmTRx && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT) */
+ else
+ {
print_err("o-xu%d: TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",p_xran_dev_ctx->xran_port_id, tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id);
}
char *pos = NULL;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg;
uint32_t tti = 0;
- xran_status_t status;
- void *pHandle = NULL;
+ //xran_status_t status;
struct rte_mbuf *mb = NULL;
struct xran_prb_map * pRbMap = NULL;
struct xran_prb_elm * prbMapElm = NULL;
uint16_t iq_sample_size_bits = 16;
- uint16_t sec_desc_idx;
+ uint16_t sec_desc_idx, prb_elem_id=0;
uint32_t interval = p_xran_dev_ctx->interval_us_local;
+ uint16_t i=0, total_sections=0;
if(expect_comp)
iq_sample_size_bits = iqWidth;
tti = frame_id * SLOTS_PER_SYSTEMFRAME(interval) + subframe_id * SLOTNUM_PER_SUBFRAME(interval) + slot_id;
- status = tti << 16 | symb_id;
+ //status = tti << 16 | symb_id;
if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < XRAN_MAX_ANTENNA_NR && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT){
pos = (char*) p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData;
pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData;
if(pRbMap){
- prbMapElm = &pRbMap->prbMap[sect_id];
- if(sect_id >= pRbMap->nPrbElm) {
- print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm);
+ /** Get the prb_elem_id */
+ total_sections=0;
+ if(pRbMap->prbMap[0].bf_weight.extType == 1)
+ {
+ for(i=0 ; i < pRbMap->nPrbElm ; i++)
+ {
+ total_sections += pRbMap->prbMap[i].bf_weight.numSetBFWs;
+ if(total_sections >= (sect_id + 1))
+ {
+ prb_elem_id = i;
+ break;
+ }
+ }
+ }
+ else
+ {
+ prb_elem_id = sect_id;
+ }
+
+ prbMapElm = &pRbMap->prbMap[prb_elem_id];
+ if(prb_elem_id >= pRbMap->nPrbElm) {
+ print_err("sect id %d prb_elem_id %d !=pRbMap->nPrbElm %d\n",sect_id, prb_elem_id,pRbMap->nPrbElm);
*mb_free = MBUF_FREE;
return size;
}
pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]);
}
} else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){
- if (pRbMap->nPrbElm == 1){
- prbMapElm = &pRbMap->prbMap[0];
- if (likely (p_xran_dev_ctx->fh_init.mtu >=
- prbMapElm->nRBSize * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits)))
- {
- /* no fragmentation */
- struct xran_section_desc *p_sec_desc = NULL;
- sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id];
- p_sec_desc = prbMapElm->p_sec_desc[symb_id][sec_desc_idx];
-
- if(p_sec_desc){
- mb = p_sec_desc->pCtrl;
- if(mb){
- rte_pktmbuf_free(mb);
- }
- p_sec_desc->pData = iq_data_start;
- p_sec_desc->pCtrl = mbuf;
- p_sec_desc->start_prbu = start_prbu;
- p_sec_desc->num_prbu = num_prbu;
- p_sec_desc->iq_buffer_len = size;
- p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf);
- } else {
- print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx);
- *mb_free = MBUF_FREE;
- return size;
- }
- *mb_free = MBUF_KEEP;
- } else {
- /* packet can be fragmented copy RBs */
- memcpy(pos, iq_data_start, size);
- *mb_free = MBUF_FREE;
- }
- } else {
struct xran_section_desc *p_sec_desc = NULL;
- prbMapElm = &pRbMap->prbMap[sect_id];
- sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id];
+ prbMapElm = &pRbMap->prbMap[prb_elem_id];
+ sec_desc_idx = prbMapElm->nSecDesc[symb_id];
if (sec_desc_idx < XRAN_MAX_FRAGMENT) {
- p_sec_desc = prbMapElm->p_sec_desc[symb_id][sec_desc_idx];
+ p_sec_desc = &prbMapElm->sec_desc[symb_id][sec_desc_idx];
} else {
- print_err("sect_id %d: sec_desc_idx %d tti %u ant %d symb_id %d sec_desc_idx %d\n", sect_id, sec_desc_idx, tti, Ant_ID, symb_id, sec_desc_idx);
+ print_err("[p: %d] sect_id %d: sec_desc_idx %d tti %u ant %d symb_id %d sec_desc_idx %d\n",p_xran_dev_ctx->xran_port_id,
+ sect_id, sec_desc_idx, tti, Ant_ID, symb_id, sec_desc_idx);
prbMapElm->nSecDesc[symb_id] = 0;
*mb_free = MBUF_FREE;
return size;
p_sec_desc->num_prbu = num_prbu;
p_sec_desc->iq_buffer_len = size;
p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf);
- //prbMapElm->nSecDesc[symb_id] += 1;
+ prbMapElm->nSecDesc[symb_id] += 1;
} else {
print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx);
*mb_free = MBUF_FREE;
return size;
}
*mb_free = MBUF_KEEP;
- }
+
}
} else {
print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size);
} else {
print_err("o-xu%d: TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",p_xran_dev_ctx->xran_port_id, tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id);
}
-
return size;
}
}
struct dirent *entry = NULL;
- while (entry = readdir(dir)) {
+ while ((entry = readdir(dir))) {
long pid = atol(entry->d_name);
if (0 == pid)
continue;
struct xran_common_counters* pCnt = &p_xran_dev_ctx->fh_counters;
long target_time;
- long delta;
+ long delta, tm_threshold_high, tm_threshold_low;//Update tm threhsolds
static int counter = 0;
static long sym_acc = 0;
static long sym_cnt = 0;
if(unlikely(p_xran_dev_ctx->offset_sec || p_xran_dev_ctx->offset_nsec))
timing_adjust_gps_second(p_cur_time);
delta = (p_cur_time->tv_sec * NSEC_PER_SEC + p_cur_time->tv_nsec) - target_time;
- if(delta > 0 || (delta < 0 && abs(delta) < THRESHOLD)) {
+ tm_threshold_high = interval_ns * N_SYM_PER_SLOT * 2;//2 slots
+ tm_threshold_low = interval_ns * 2; //2 symbols
+ //add tm exception handling
+ if (unlikely(labs(delta) > tm_threshold_low)) {
+ print_dbg("poll_next_tick exceed 2 symbols threshold with delta:%ld(ns), used_tick:%ld(tick) \n", delta, used_tick);
+ pCnt->timer_missed_sym++;
+ if(unlikely(labs(delta) > tm_threshold_high)) {
+ print_dbg("poll_next_tick exceed 2 slots threshold, stop xran! delta:%ld(ns), used_tick:%ld(tick) \n", delta, used_tick);
+ //xran_if_current_state = XRAN_STOPPED;
+ pCnt->timer_missed_slot++;
+ }
+ }
+ if(delta > 0 || (delta < 0 && labs(delta) < THRESHOLD)) {
if (debugStop &&(debugStopCount > 0) && (pCnt->tx_counter >= debugStopCount)){
uint64_t t1;
printf("STOP:[%ld.%09ld], debugStopCount %d, tx_counter %ld\n", p_cur_time->tv_sec, p_cur_time->tv_nsec, debugStopCount, pCnt->tx_counter);
for (i=1; i < p_xran_dev_ctx->fh_init.xran_ports; i++)
{
struct xran_device_ctx * p_other_ctx = xran_dev_get_ctx_by_id(i);
+ if(p_other_ctx)
xran_lib_ota_sym_idx[i] = xran_lib_ota_sym_idx[0] >> (numerlogy - xran_get_conf_numerology(p_other_ctx));
}
/* adjust to sym boundary */
if(debugStop && delta < interval_ns*10)
MLogTask(PID_TIME_SYSTIME_POLL, (p_last_time->tv_sec * NSEC_PER_SEC + p_last_time->tv_nsec), (p_cur_time->tv_sec * NSEC_PER_SEC + p_cur_time->tv_nsec));
#else
- MLogTask(PID_TIME_SYSTIME_POLL, last_tick, curr_tick);
+ MLogXRANTask(PID_TIME_SYSTIME_POLL, last_tick, curr_tick);
last_tick = curr_tick;
#endif
uint32_t payloadlen;
struct xran_ecpri_hdr *tmp;
-
tmp = (struct xran_ecpri_hdr *)rte_pktmbuf_append(mbuf, sizeof(struct xran_ecpri_hdr));
if(unlikely(tmp == NULL)) {
print_err("Fail to allocate the space for eCPRI hedaer!");
#include <rte_memzone.h>
#include <rte_mbuf.h>
#include <rte_ring.h>
+#include <rte_ethdev.h>
#include "xran_fh_o_du.h"
#include "xran_dev.h"
#include "xran_frame_struct.h"
#include "xran_printf.h"
-#include "xran_app_frag.h"
#include "xran_tx_proc.h"
#include "xran_cp_proc.h"
XRAN_IN_NEXT_PERIOD
};
+extern int32_t first_call;
struct rte_mbuf *
xran_attach_up_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len,
int32_t n_bytes;
int32_t prep_bytes;
int16_t nPktSize;
- uint32_t off;
-
iqWidth = (iqWidth==0) ? 16 : iqWidth;
switch(compMeth) {
RU_Port_ID,
seq_id,
staticEn,
- do_copy);
+ do_copy,
+ 1,
+ section_id,
+ 0);
if (prep_bytes <= 0)
errx(1, "failed preparing symbol");
char *p_sec_iq = NULL;
void *mb = NULL;
void *send_mb = NULL;
- int prb_num = 0;
- uint16_t iq_sample_size_bits = 16;
- uint16_t vf_id = 0;
+ // int prb_num = 0;
+ uint16_t vf_id = 0 , num_sections = 0, curr_sect_id = 0 ;
struct xran_prb_map *prb_map = NULL;
- uint8_t num_ant_elm = 0;
+ //uint8_t num_ant_elm = 0;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)pHandle;
if (p_xran_dev_ctx == NULL)
return retval;
struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters;
- struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
- struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
+ //struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ //struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
- num_ant_elm = xran_get_num_ant_elm(pHandle);
+ //num_ant_elm = xran_get_num_ant_elm(pHandle);
enum xran_pkt_dir direction;
enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC;
struct rte_mbuf_ext_shared_info * p_share_data = NULL;
if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
direction = XRAN_DIR_DL; /* O-DU */
- prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
+ //prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
} else {
direction = XRAN_DIR_UL; /* RU */
- prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
+ //prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
}
if(xran_fs_get_slot_type(PortId, cc_id, tti, ((p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)? XRAN_SLOT_TYPE_DL : XRAN_SLOT_TYPE_UL)) == 1
int32_t elmIdx = 0;
for (elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++){
//print_err("tti is %d, cc_id is %d, ant_id is %d, prb_map->nPrbElm id - %d", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_id, prb_map->nPrbElm);
- uint16_t sec_id = elmIdx;
struct xran_prb_elm * prb_map_elm = &prb_map->prbMap[elmIdx];
struct xran_section_desc * p_sec_desc = NULL;
+ uint16_t sec_id = prb_map_elm->nSectId;
p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sec_id];
+ if(unlikely(sym_id < prb_map_elm->nStartSymb || sym_id >= (prb_map_elm->nStartSymb + prb_map_elm->numSymb)))
+ continue;
+
if(prb_map_elm == NULL){
rte_panic("p_sec_desc == NULL\n");
}
- p_sec_desc = prb_map_elm->p_sec_desc[sym_id][0];
+ p_sec_desc = &prb_map_elm->sec_desc[sym_id][0];
p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset);
xran_get_upul_seqid(pHandle, cc_id, ant_id);
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU
+ && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B)
+ {
+ num_sections = (prb_map_elm->bf_weight.extType == 1) ? prb_map_elm->bf_weight.numSetBFWs : 1 ;
+ if (prb_map_elm->bf_weight.extType != 1)
+ curr_sect_id = sec_id;
+ }
+ else
+ num_sections = 1;
/* first all PRBs */
- int32_t num_bytes = prepare_symbol_ex(direction, sec_id,
+ prepare_symbol_ex(direction, curr_sect_id,
send_mb,
(uint8_t *)p_sec_iq,
prb_map_elm->compMethod,
prb_map_elm->iqWidth,
p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
frame_id, subframe_id, slot_id, sym_id,
- prb_map_elm->nRBStart, prb_map_elm->nRBSize,
+ prb_map_elm->UP_nRBStart, prb_map_elm->UP_nRBSize,
cc_id, ant_id,
seq_id,
- 0,
- staticEn);
+ 0,
+ staticEn,
+ num_sections,
+ p_sec_desc->iq_buffer_offset);
+
+ curr_sect_id += num_sections;
rte_mbuf_sanity_check((struct rte_mbuf *)send_mb, 0);
pCnt->tx_counter++;
pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)send_mb);
p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)send_mb, ETHER_TYPE_ECPRI, vf_id);
- }
+ } /* for (elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++) */
} else {
printf("(%d %d %d %d) prb_map == NULL\n", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_id, sym_id);
}
- if(p_xran_dev_ctx->enablePrach
- && (p_xran_dev_ctx->fh_init.io_cfg.id == O_RU)) { /* Only RU needs to send PRACH I/Q */
- uint32_t is_prach_slot = xran_is_prach_slot(PortId, subframe_id, slot_id);
-
- if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0])
- && (is_prach_slot == 1)
- && (sym_id >= p_xran_dev_ctx->prach_start_symbol[cc_id])
- && (sym_id <= p_xran_dev_ctx->prach_last_symbol[cc_id])) {
- int prach_port_id = ant_id + pPrachCPConfig->eAxC_offset;
- int compMethod, parm_size;
- uint8_t symb_id_offset = sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id];
-
- compMethod = p_xran_dev_ctx->fh_cfg.ru_conf.compMeth_PRACH;
- switch(compMethod) {
- case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
- case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
- default:
- parm_size = 0;
- }
- pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[symb_id_offset].pData;
- //pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id]) * pPrachCPConfig->numPrbc * N_SC_PER_PRB * 4;
- /*pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id])
- * (3*p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth + parm_size)
- * pPrachCPConfig->numPrbc;*/
- mb = NULL;//(void*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pCtrl;
-
- send_symbol_ex(pHandle,
- direction,
- xran_alloc_sectionid(pHandle, direction, cc_id, prach_port_id, slot_id),
- (struct rte_mbuf *)mb,
- (uint8_t *)pos,
- compMethod,
- p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth_PRACH,
- p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
- frame_id, subframe_id, slot_id, sym_id,
- pPrachCPConfig->startPrbc, pPrachCPConfig->numPrbc,
- cc_id, prach_port_id,
- xran_get_upul_seqid(pHandle, cc_id, prach_port_id));
- retval = 1;
- }
- } /* if(p_xran_dev_ctx->enablePrach ..... */
} /* RU mode or C-Plane is not used */
}
-
return retval;
}
-
-int32_t
-xran_process_tx_srs_cp_off(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id)
+int32_t xran_process_tx_prach_cp_off(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id)
{
int32_t retval = 0;
char *pos = NULL;
- char *p_sec_iq = NULL;
void *mb = NULL;
- void *send_mb = NULL;
- int prb_num = 0;
- uint16_t iq_sample_size_bits = 16;
-
- struct xran_prb_map *prb_map = NULL;
- uint8_t num_ant_elm = 0;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)pHandle;
- struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters;
- struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
- struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
+ if (p_xran_dev_ctx == NULL)
+ return retval;
- num_ant_elm = xran_get_num_ant_elm(pHandle);
- enum xran_pkt_dir direction;
+ struct xran_prach_cp_config *pPrachCPConfig;
+ if(p_xran_dev_ctx->dssEnable){
+ int i = tti % p_xran_dev_ctx->dssPeriod;
+ if(p_xran_dev_ctx->technology[i]==1) {
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfigLTE);
+ }
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
- struct rte_mbuf *eth_oran_hdr = NULL;
- char *ext_buff = NULL;
- uint16_t ext_buff_len = 0;
- struct rte_mbuf *tmp = NULL;
- rte_iova_t ext_buff_iova = 0;
- int32_t ant_elm_eAxC_id = ant_id + p_srs_cfg->eAxC_offset;
- uint32_t vf_id = 0;
- enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC;
+ enum xran_pkt_dir direction = XRAN_DIR_UL;
+ uint8_t PortId = p_xran_dev_ctx->xran_port_id;
- if (p_xran_dev_ctx != NULL)
- {
- if(p_xran_dev_ctx->xran_port_id >= XRAN_PORTS_NUM)
+ if(PortId >= XRAN_PORTS_NUM)
rte_panic("incorrect PORT ID\n");
- struct rte_mbuf_ext_shared_info * p_share_data = NULL;
- if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
- direction = XRAN_DIR_DL; /* O-DU */
- prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
- rte_panic("incorrect O_DU\n");
- } else {
- direction = XRAN_DIR_UL; /* RU */
- prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
- }
+ if(p_xran_dev_ctx->enablePrach
+ && (p_xran_dev_ctx->fh_init.io_cfg.id == O_RU) && (ant_id < XRAN_MAX_PRACH_ANT_NUM)){
+ if(xran_fs_get_symbol_type(PortId, cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_UL
+ || xran_fs_get_symbol_type(PortId, cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD) { /* Only RU needs to send PRACH I/Q */
- staticEn = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+ uint32_t is_prach_slot = xran_is_prach_slot(PortId, subframe_id, slot_id);
+ if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0])
+ && (is_prach_slot == 1)
+ && (sym_id >= p_xran_dev_ctx->prach_start_symbol[cc_id])
+ && (sym_id <= p_xran_dev_ctx->prach_last_symbol[cc_id])) {
+ int prach_port_id = ant_id + pPrachCPConfig->eAxC_offset;
+ int compMethod;
+ //int parm_size;
+ uint8_t symb_id_offset = sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id];
-#if 1
- if (tti % 5 == 3) {
- {
-#else
- if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_UL) == 1
- || xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_FDD) == 1) {
- if(xran_fs_get_symbol_type(cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_UL
- || xran_fs_get_symbol_type(cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD) {
+ compMethod = p_xran_dev_ctx->fh_cfg.ru_conf.compMeth_PRACH;
+#if 0
+ switch(compMethod) {
+ case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
+ case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
+ default:
+ parm_size = 0;
+ }
#endif
- pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
- mb = (void*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
- prb_map = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers->pData;
- vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, ant_elm_eAxC_id);
-
- if(prb_map) {
- int32_t elmIdx = 0;
- for (elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++) {
- uint16_t sec_id = elmIdx;
- struct xran_prb_elm * prb_map_elm = &prb_map->prbMap[elmIdx];
- struct xran_section_desc * p_sec_desc = NULL;
-
- if(prb_map_elm == NULL) {
- rte_panic("p_sec_desc == NULL\n");
+ pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[symb_id_offset].pData;
+ //pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id]) * pPrachCPConfig->numPrbc * N_SC_PER_PRB * 4;
+ /*pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id])
+ * (3*p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth + parm_size)
+ * pPrachCPConfig->numPrbc;*/
+ mb = NULL;//(void*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pCtrl;
+
+ struct xran_prach_cp_config *pPrachCPConfig;
+ if(p_xran_dev_ctx->dssEnable){
+ int i = tti % p_xran_dev_ctx->dssPeriod;
+ if(p_xran_dev_ctx->technology[i]==1) {
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
}
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfigLTE);
+ }
+ }
+ else{
+ pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ }
+
+
+ if (1500 == p_xran_dev_ctx->fh_init.mtu && pPrachCPConfig->filterIdx == XRAN_FILTERINDEX_PRACH_012)
+ {
+ pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pData;
+ mb = (void*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pCtrl;
+ /*one prach for more then one pkg*/
+ send_symbol_mult_section_ex(pHandle,
+ direction,
+ xran_alloc_sectionid(pHandle, direction, cc_id, prach_port_id, subframe_id, slot_id),
+ (struct rte_mbuf *)mb,
+ (uint8_t *)pos,
+ compMethod,
+ p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth,
+ p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
+ frame_id, subframe_id, slot_id, sym_id,
+ pPrachCPConfig->startPrbc, pPrachCPConfig->numPrbc,
+ cc_id, prach_port_id,
+ 0);
+ }
+ else{
+ send_symbol_ex(pHandle,
+ direction,
+ xran_alloc_sectionid(pHandle, direction, cc_id, prach_port_id, subframe_id, slot_id),
+ (struct rte_mbuf *)mb,
+ (uint8_t *)pos,
+ compMethod,
+ p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth_PRACH,
+ p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
+ frame_id, subframe_id, slot_id, sym_id,
+ pPrachCPConfig->startPrbc, pPrachCPConfig->numPrbc,
+ cc_id, prach_port_id,
+ xran_get_upul_seqid(pHandle, cc_id, prach_port_id));
+ }
+ retval = 1;
+ }
+ } /* if(p_xran_dev_ctx->enablePrach ..... */
+ }
+ return retval;
+}
+int32_t
+xran_process_tx_srs_cp_off(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id,
+ uint32_t frame_id, uint32_t subframe_id, uint32_t slot_id)
+{
+ int32_t retval = 0;
+ char *pos = NULL;
+ char *p_sec_iq = NULL;
+ void *mb = NULL;
+ char *ext_buff = NULL;
+ uint16_t ext_buff_len = 0 , num_sections=0 , section_id=0;
+ int32_t antElm_eAxC_id;
+ uint32_t vf_id = 0;
+ int32_t elmIdx;
+ uint32_t sym_id;
+ enum xran_pkt_dir direction;
+ enum xran_comp_hdr_type staticEn;
- /* skip, if not scheduled */
- if(sym_id < prb_map_elm->nStartSymb || sym_id >= prb_map_elm->nStartSymb + prb_map_elm->numSymb)
- return 0;
+ rte_iova_t ext_buff_iova = 0;
+ struct rte_mbuf *tmp = NULL;
+ struct xran_prb_map *prb_map = NULL;
+ struct xran_device_ctx * p_xran_dev_ctx;
+ struct xran_common_counters *pCnt;
+ //struct xran_prach_cp_config *pPrachCPConfig;
+ struct xran_srs_config *p_srs_cfg;
+ struct rte_mbuf *eth_oran_hdr = NULL;
+ struct rte_mbuf_ext_shared_info *p_share_data = NULL;
- p_share_data = &p_xran_dev_ctx->srs_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id];
- p_sec_desc = prb_map_elm->p_sec_desc[sym_id][0];
- p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset);
- /* calculate offset for external buffer */
- ext_buff_len = p_sec_desc->iq_buffer_len;
- ext_buff = p_sec_iq - (RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
- sizeof (struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr));
+ p_xran_dev_ctx = (struct xran_device_ctx *)pHandle;
+ if(p_xran_dev_ctx == NULL)
+ {
+ print_err("dev_ctx is NULL. ctx_id=%d, tti=%d, cc_id=%d, ant_id=%d, frame_id=%d, subframe_id=%d, slot_id=%d\n",
+ ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id);
+ return 0;
+ }
- ext_buff_len += RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
- sizeof (struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr) + 18;
+ if(p_xran_dev_ctx->xran_port_id >= XRAN_PORTS_NUM)
+ rte_panic("incorrect PORT ID\n");
- if ((prb_map_elm->compMethod != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)){
- ext_buff -= sizeof (struct data_section_compression_hdr);
- ext_buff_len += sizeof (struct data_section_compression_hdr);
- }
+ pCnt = &p_xran_dev_ctx->fh_counters;
+ //pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
+ p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
-// eth_oran_hdr = rte_pktmbuf_alloc(_eth_mbuf_pool_small);
- eth_oran_hdr = xran_ethdi_mbuf_indir_alloc();
+ /* Only O-RU sends SRS U-Plane */
+ direction = XRAN_DIR_UL;
+ staticEn = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+ antElm_eAxC_id = ant_id + p_srs_cfg->eAxC_offset;
- if (unlikely (( eth_oran_hdr) == NULL)) {
- rte_panic("Failed rte_pktmbuf_alloc\n");
- }
+ prb_map = (struct xran_prb_map *)p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers->pData;
+ if(prb_map)
+ {
+ for(elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++)
+ {
+ struct xran_prb_elm *prb_map_elm = &prb_map->prbMap[elmIdx];
+ struct xran_section_desc * p_sec_desc = NULL;
- p_share_data->free_cb = extbuf_free_callback;
- p_share_data->fcb_opaque = NULL;
- rte_mbuf_ext_refcnt_set(p_share_data, 1);
+ if(prb_map_elm == NULL)
+ rte_panic("p_sec_desc == NULL\n");
- ext_buff_iova = rte_mempool_virt2iova(mb);
- if (unlikely (( ext_buff_iova) == 0)) {
- rte_panic("Failed rte_mem_virt2iova \n");
- }
+ sym_id = prb_map->prbMap[elmIdx].nStartSymb;
+ pos = (char*)p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
+ mb = (void*)p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
- if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) {
- rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
- }
- rte_pktmbuf_attach_extbuf(eth_oran_hdr,
- ext_buff,
- ext_buff_iova + RTE_PTR_DIFF(ext_buff , mb),
- ext_buff_len,
- p_share_data);
+ p_share_data = &p_xran_dev_ctx->srs_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id];
+ p_sec_desc = &prb_map_elm->sec_desc[sym_id][0];
+ p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset);
- rte_pktmbuf_reset_headroom(eth_oran_hdr);
+ /* calculate offset for external buffer */
+ ext_buff_len = p_sec_desc->iq_buffer_len;
- tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct rte_ether_hdr));
- if (unlikely (( tmp) == NULL)) {
- rte_panic("Failed rte_pktmbuf_prepend \n");
- }
- send_mb = eth_oran_hdr;
+ ext_buff = p_sec_iq - (RTE_PKTMBUF_HEADROOM +
+ sizeof (struct xran_ecpri_hdr) +
+ sizeof (struct radio_app_common_hdr) +
+ sizeof(struct data_section_hdr));
- uint8_t seq_id = (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ?
- xran_get_updl_seqid(pHandle, cc_id, ant_elm_eAxC_id) :
- xran_get_upul_seqid(pHandle, cc_id, ant_elm_eAxC_id);
- /* first all PRBs */
- int32_t num_bytes = prepare_symbol_ex(direction, sec_id,
- send_mb,
- (uint8_t *)p_sec_iq,
- prb_map_elm->compMethod,
- prb_map_elm->iqWidth,
- p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
- frame_id, subframe_id, slot_id, sym_id,
- prb_map_elm->nRBStart, prb_map_elm->nRBSize,
- cc_id, ant_elm_eAxC_id,
- seq_id,
- 0,
- staticEn);
+ ext_buff_len += RTE_PKTMBUF_HEADROOM +
+ sizeof (struct xran_ecpri_hdr) +
+ sizeof (struct radio_app_common_hdr) +
+ sizeof(struct data_section_hdr) + 18;
- rte_mbuf_sanity_check((struct rte_mbuf *)send_mb, 0);
- pCnt->tx_counter++;
- pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)send_mb);
- p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)send_mb, ETHER_TYPE_ECPRI, vf_id);
- }
- } else {
- printf("(%d %d %d %d) prb_map == NULL\n", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_elm_eAxC_id, sym_id);
+ if((prb_map_elm->compMethod != XRAN_COMPMETHOD_NONE)
+ && (staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
+ {
+ ext_buff -= sizeof (struct data_section_compression_hdr);
+ ext_buff_len += sizeof (struct data_section_compression_hdr);
}
- }
- }
+
+ eth_oran_hdr = xran_ethdi_mbuf_indir_alloc();
+ if(unlikely(eth_oran_hdr == NULL))
+ rte_panic("Failed rte_pktmbuf_alloc\n");
+
+ p_share_data->free_cb = extbuf_free_callback;
+ p_share_data->fcb_opaque = NULL;
+ rte_mbuf_ext_refcnt_set(p_share_data, 1);
+
+ ext_buff_iova = rte_mempool_virt2iova(mb);
+ if(unlikely(ext_buff_iova == 0 || ext_buff_iova == RTE_BAD_IOVA))
+ rte_panic("Failed rte_mem_virt2iova : %lu\n", ext_buff_iova);
+
+ rte_pktmbuf_attach_extbuf(eth_oran_hdr,
+ ext_buff,
+ ext_buff_iova + RTE_PTR_DIFF(ext_buff , mb),
+ ext_buff_len,
+ p_share_data);
+
+ rte_pktmbuf_reset_headroom(eth_oran_hdr);
+
+ tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct rte_ether_hdr));
+ if(unlikely(tmp == NULL))
+ rte_panic("Failed rte_pktmbuf_prepend \n");
+
+ uint8_t seq_id = xran_get_upul_seqid(pHandle, cc_id, antElm_eAxC_id);
+
+ num_sections = (prb_map_elm->bf_weight.extType == 1) ? prb_map_elm->bf_weight.numSetBFWs : 1 ;
+
+ prepare_symbol_ex(direction, prb_map_elm->nSectId,
+ (void *)eth_oran_hdr, (uint8_t *)p_sec_iq,
+ prb_map_elm->compMethod, prb_map_elm->iqWidth,
+ p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
+ frame_id, subframe_id, slot_id, sym_id,
+ prb_map_elm->UP_nRBStart, prb_map_elm->UP_nRBSize,
+ cc_id, antElm_eAxC_id,
+ seq_id,
+ 0,
+ staticEn,
+ num_sections,
+ 0);
+
+ section_id += num_sections;
+
+ rte_mbuf_sanity_check(eth_oran_hdr, 0);
+
+ vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, antElm_eAxC_id);
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(eth_oran_hdr);
+ p_xran_dev_ctx->send_upmbuf2ring(eth_oran_hdr, ETHER_TYPE_ECPRI, vf_id);
+ } /* for(elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++) */
+ } /* if(prb_map) */
+ else
+ {
+ printf("(%d %d %d) prb_map == NULL\n", tti % XRAN_N_FE_BUF_LEN, cc_id, antElm_eAxC_id);
}
return retval;
return mb_oran_hdr_ext;
}
-int32_t xran_process_tx_sym_cp_on_dispatch_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id,
+int32_t xran_process_tx_sym_cp_on_dispatch_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db)
{
p_desc->pHandle = pHandle;
p_desc->ctx_id = ctx_id;
p_desc->tti = tti;
- p_desc->cc_id = num_cc;
- p_desc->ant_id = num_ant;
+ p_desc->start_cc = start_cc;
+ p_desc->cc_num = num_cc;
+ p_desc->start_ant = start_ant;
+ p_desc->ant_num = num_ant;
p_desc->frame_id = frame_id;
p_desc->subframe_id = subframe_id;
p_desc->slot_id = slot_id;
p_desc->sym_id = sym_id;
p_desc->compType = (uint32_t)compType;
- p_desc->direction = (uint32_t)direction;
+ p_desc->direction = (uint32_t)direction;
p_desc->xran_port_id = xran_port_id;
p_desc->p_sec_db = (void*)p_sec_db;
}
int32_t
-xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
+xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id, uint32_t subframe_id,
uint32_t slot_id, uint32_t sym_id)
{
int32_t retval = 0;
p_desc->pHandle = pHandle;
p_desc->ctx_id = ctx_id;
p_desc->tti = tti;
- p_desc->cc_id = cc_id;
- p_desc->ant_id = ant_id;
+ p_desc->start_cc = start_cc;
+ p_desc->cc_num = num_cc;
+ p_desc->start_ant = start_ant;
+ p_desc->ant_num = num_ant;
p_desc->frame_id = frame_id;
p_desc->subframe_id = subframe_id;
p_desc->slot_id = slot_id;
}
int32_t
-xran_process_tx_sym_cp_on(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
+xran_process_tx_sym_cp_on(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t cc_id, int32_t start_ant, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
uint32_t slot_id, uint32_t sym_id)
{
int32_t retval = 0;
-
- struct rte_mbuf *eth_oran_hdr = NULL;
- char *ext_buff = NULL;
uint16_t ext_buff_len = 0;
- struct rte_mbuf *tmp = NULL;
- rte_iova_t ext_buff_iova = 0;
char *pos = NULL;
char *p_sec_iq = NULL;
void *mb = NULL;
struct rte_mbuf *to_free_mbuf = NULL;
- int prb_num = 0;
+ //int prb_num = 0;
uint16_t iq_sample_size_bits = 16;
uint32_t next = 0;
int32_t num_sections = 0;
uint16_t len = 0;
int16_t len2 = 0;
uint16_t i = 0;
-
- uint64_t t1;
struct mbuf_table loc_tx_mbufs;
struct xran_up_pkt_gen_params loc_xp;
{
compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
+ direction = XRAN_DIR_DL; /* O-DU */
+ //prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
+ } else {
+ direction = XRAN_DIR_UL; /* RU */
+ //prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
+ }
- if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
- direction = XRAN_DIR_DL; /* O-DU */
- prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
- } else {
- direction = XRAN_DIR_UL; /* RU */
- prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
- }
-
- vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, ant_id);
- next = 0;
- num_sections = xran_cp_getsize_section_info(pHandle, direction, cc_id, ant_id, ctx_id);
- /* iterate C-Plane configuration to generate corresponding U-Plane */
- if(num_sections)
- prepare_sf_slot_sym(direction, frame_id, subframe_id, slot_id, sym_id, &loc_xp);
+ vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, ant_id);
+ next = 0;
+ num_sections = xran_cp_getsize_section_info(pHandle, direction, cc_id, ant_id, ctx_id);
+ /* iterate C-Plane configuration to generate corresponding U-Plane */
+ if(num_sections)
+ prepare_sf_slot_sym(direction, frame_id, subframe_id, slot_id, sym_id, &loc_xp);
- loc_tx_mbufs.len = 0;
- while(next < num_sections) {
- sectinfo = xran_cp_iterate_section_info(pHandle, direction, cc_id, ant_id, ctx_id, &next);
+ loc_tx_mbufs.len = 0;
+ while(next < num_sections) {
+ sectinfo = xran_cp_iterate_section_info(pHandle, direction, cc_id, ant_id, ctx_id, &next);
- if(sectinfo == NULL)
- break;
+ if(sectinfo == NULL)
+ break;
- if(sectinfo->type != XRAN_CP_SECTIONTYPE_1) { /* only supports type 1 */
- print_err("Invalid section type in section DB - %d", sectinfo->type);
- continue;
- }
+ if(sectinfo->type != XRAN_CP_SECTIONTYPE_1) { /* only supports type 1 */
+ print_err("Invalid section type in section DB - %d", sectinfo->type);
+ continue;
+ }
- /* skip, if not scheduled */
- if(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol)
- continue;
+ /* skip, if not scheduled */
+ if(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol)
+ continue;
- if(sectinfo->compMeth)
- iq_sample_size_bits = sectinfo->iqWidth;
+ if(sectinfo->compMeth)
+ iq_sample_size_bits = sectinfo->iqWidth;
- print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next,
- sectinfo->type, sectinfo->id, sectinfo->startPrbc,
- sectinfo->numPrbc,sectinfo->startSymId, sectinfo->numSymbol);
+ print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next,
+ sectinfo->type, sectinfo->id, sectinfo->startPrbc,
+ sectinfo->numPrbc,sectinfo->startSymId, sectinfo->numSymbol);
- p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sectinfo->id];
+ p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sectinfo->id];
- len = loc_tx_mbufs.len;
- len2 = 0;
- i = 0;
+ len = loc_tx_mbufs.len;
+ len2 = 0;
+ i = 0;
- //Added for Klocworks
- if (len >= MBUF_TABLE_SIZE) {
- len = MBUF_TABLE_SIZE - 1;
- rte_panic("len >= MBUF_TABLE_SIZE\n");
- }
+ //Added for Klocworks
+ if (len >= MBUF_TABLE_SIZE) {
+ len = MBUF_TABLE_SIZE - 1;
+ rte_panic("len >= MBUF_TABLE_SIZE\n");
+ }
- to_free_mbuf = p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][sectinfo->id];
- pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
- mb = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
+ to_free_mbuf = p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][sectinfo->id];
+ pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
+ mb = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
- if(mb == NULL) {
- rte_panic("mb == NULL\n");
- }
+ if(mb == NULL) {
+ rte_panic("mb == NULL\n");
+ }
- p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset);
- ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len;
+ p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset);
+ ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len;
- mb = xran_attach_up_ext_buf(vf_id, (int8_t *)mb, (int8_t *) p_sec_iq,
- (uint16_t) ext_buff_len,
- p_share_data, (enum xran_compression_method) sectinfo->compMeth, compType);
- p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][sectinfo->id] = mb;
- rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */
+ mb = xran_attach_up_ext_buf(vf_id, (int8_t *)mb, (int8_t *) p_sec_iq,
+ (uint16_t) ext_buff_len,
+ p_share_data, (enum xran_compression_method) sectinfo->compMeth, compType);
+ p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][sectinfo->id] = mb;
+ rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */
- if(to_free_mbuf) {
- rte_pktmbuf_free(to_free_mbuf);
- }
+ if(to_free_mbuf) {
+ rte_pktmbuf_free(to_free_mbuf);
+ }
- /* first all PRBs */
- prepare_symbol_opt(direction, sectinfo->id,
- mb,
- (struct rb_map *)p_sec_iq,
- sectinfo->compMeth,
- sectinfo->iqWidth,
- p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
- sectinfo->startPrbc,
- sectinfo->numPrbc,
- cc_id,
- ant_id,
- xran_get_updl_seqid(pHandle, cc_id, ant_id),
- 0,
- &loc_xp,
- compType);
-
- /* if we don't need to do any fragmentation */
- if (likely (p_xran_dev_ctx->fh_init.mtu >=
- sectinfo->numPrbc * (3*iq_sample_size_bits + 1))) {
- /* no fragmentation */
- loc_tx_mbufs.m_table[len] = mb;
- len2 = 1;
- } else {
- /* fragmentation */
- uint8_t * seq_num = xran_get_updl_seqid_addr(pHandle, cc_id, ant_id);
- if(seq_num)
- (*seq_num)--;
- else
- rte_panic("pointer to seq number is NULL [CC %d Ant %d]\n", cc_id, ant_id);
-
- len2 = xran_app_fragment_packet(mb,
- &loc_tx_mbufs.m_table[len],
- (uint16_t)(MBUF_TABLE_SIZE - len),
- p_xran_dev_ctx->fh_init.mtu,
- p_xran_dev_ctx->direct_pool,
- p_xran_dev_ctx->indirect_pool,
- sectinfo->startPrbc,
- sectinfo->numPrbc,
- seq_num,
+ /* first all PRBs */
+ prepare_symbol_opt(direction, sectinfo->id,
+ mb,
+ (struct rb_map *)p_sec_iq,
+ sectinfo->compMeth,
sectinfo->iqWidth,
- ((sectinfo->iqWidth == 16)||(compType==XRAN_COMP_HDR_TYPE_STATIC)) ? 0 : 1);
-
- /* Free input packet */
- rte_pktmbuf_free(mb);
-
- /* If we fail to fragment the packet */
- if (unlikely (len2 < 0)){
- print_err("len2= %d\n", len2);
+ p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder,
+ sectinfo->startPrbc,
+ sectinfo->numPrbc,
+ cc_id,
+ ant_id,
+ xran_get_updl_seqid(pHandle, cc_id, ant_id),
+ 0,
+ &loc_xp,
+ compType);
+
+ /* if we don't need to do any fragmentation */
+ if (likely (p_xran_dev_ctx->fh_init.mtu >=
+ sectinfo->numPrbc * (3*iq_sample_size_bits + 1))) {
+ /* no fragmentation */
+ loc_tx_mbufs.m_table[len] = mb;
+ len2 = 1;
+ } else {
+ /* current code should not go to fragmentation as it should be taken care of by section allocation already */
+ print_err("should not go to fragmentation mtu %d packet size %d\n", p_xran_dev_ctx->fh_init.mtu, sectinfo->numPrbc * (3*iq_sample_size_bits + 1));
return 0;
}
- }
- if(len2 > 1){
- for (i = len; i < len + len2; i ++) {
- struct rte_mbuf *m;
- m = loc_tx_mbufs.m_table[i];
- struct rte_ether_hdr *eth_hdr = (struct rte_ether_hdr *)
- rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr));
- if (eth_hdr == NULL) {
- rte_panic("No headroom in mbuf.\n");
+ if(len2 > 1){
+ for (i = len; i < len + len2; i ++) {
+ struct rte_mbuf *m;
+ m = loc_tx_mbufs.m_table[i];
+ struct rte_ether_hdr *eth_hdr = (struct rte_ether_hdr *)
+ rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr));
+ if (eth_hdr == NULL) {
+ rte_panic("No headroom in mbuf.\n");
+ }
}
}
- }
- len += len2;
- if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM)) {
- rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n");
- }
- loc_tx_mbufs.len = len;
- } /* while(section) */
+ len += len2;
+ if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM)) {
+ rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n");
+ }
+ loc_tx_mbufs.len = len;
+ } /* while(section) */
- /* Transmit packets */
- xran_send_burst(p_xran_dev_ctx, &loc_tx_mbufs, vf_id);
- loc_tx_mbufs.len = 0;
- retval = 1;
+ /* Transmit packets */
+ xran_send_burst(p_xran_dev_ctx, &loc_tx_mbufs, vf_id);
+ loc_tx_mbufs.len = 0;
+ retval = 1;
}
return retval;
}
-//#define TRANSMIT_BURST
-//#define ENABLE_DEBUG_COREDUMP
-
-#define ETHER_TYPE_ECPRI_BE (0xFEAE)
-
-int32_t xran_process_tx_sym_cp_on_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id,
- uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
- uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db)
+int32_t
+xran_prepare_up_dl_sym(uint16_t xran_port_id, uint32_t nSlotIdx, uint32_t nCcStart, uint32_t nCcNum, uint32_t nSymMask, uint32_t nAntStart,
+ uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
{
- uint8_t seq_id = 0;
- int32_t cc_id = 0, ant_id = 0;
- char* ext_buff = NULL;
- uint16_t ext_buff_len = 0;
- rte_iova_t ext_buff_iova = 0;
- char* pos = NULL;
- char* p_sec_iq = NULL;
- void* mb = NULL, *mb_base = NULL;
- struct rte_mbuf* to_free_mbuf = NULL;
- uint16_t iq_sample_size_bits = 16;
- uint32_t next = 0;
- int32_t num_sections = 0, total_sections = 0;
- uint16_t len = 0, len2 = 0, len_frag = 0;
- char* pStart = 0;
- uint16_t cid = 0;
- uint8_t compMeth = 0;
- uint8_t iqWidth = 0;
- int parm_size = 0;
- int32_t n_bytes = 0, elm_bytes = 0;
- uint16_t section_id;
- uint16_t prb_num = 0;
- uint16_t prb_start = 0;
- int16_t nPktSize = 0;
- uint16_t ecpri_payl_size = 0;
-#ifdef TRANSMIT_BURST
- struct mbuf_table loc_tx_mbufs;
+ int32_t retval = 0;
+ uint32_t tti=0;
+ uint32_t numSlotMu1 = 5;
+#if XRAN_MLOG_VAR
+ uint32_t mlogVar[15];
+ uint32_t mlogVarCnt = 0;
#endif
- struct mbuf_table loc_tx_mbufs_fragmented;
- struct xran_up_pkt_gen_params xp;
- struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx();
- struct xran_section_info* sectinfo = NULL;
- struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle;
- uint16_t vf_id = 0;
- struct rte_mbuf_ext_shared_info* p_share_data = NULL;
- struct xran_sectioninfo_db* ptr_sect_elm = NULL;
- struct rte_mbuf* mb_oran_hdr_ext = NULL;
- struct rte_mempool_objhdr* iova_hdr = NULL;
- struct xran_eaxcid_config* conf = &(p_xran_dev_ctx->eAxc_id_cfg);
- struct rte_ether_hdr* ether_hdr = NULL;
- struct xran_ecpri_hdr* ecpri_hdr = NULL;
- struct radio_app_common_hdr* app_hdr = NULL;
- struct data_section_hdr* section_hdr = NULL;
- struct data_section_compression_hdr* compression_hdr = NULL;
- const int16_t ccid_pos = conf->bit_ccId;
- const int16_t ccid_mask = conf->mask_ccId;
- const int16_t antid_pos = conf->bit_ruPortId;
- const int16_t antid_mask = conf->mask_ruPortId;
-
- const int16_t rte_ether_hdr_size = sizeof(struct rte_ether_hdr);
- const int16_t rte_mempool_objhdr_size = sizeof(struct rte_mempool_objhdr);
- uint16_t comp_head_upd = 0;
+ unsigned long t1 = MLogXRANTick();
- const int16_t total_header_size = (RTE_PKTMBUF_HEADROOM +
- sizeof(struct xran_ecpri_hdr) +
- sizeof(struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr));
+ void *pHandle = NULL;
+ int32_t ant_id = 0;
+ int32_t cc_id = 0;
+ uint8_t num_eAxc = 0;
+ uint8_t num_eAxc_prach = 0;
+ uint8_t num_eAxAntElm = 0;
+ uint8_t num_CCPorts = 0;
+ uint32_t frame_id = 0;
+ uint32_t subframe_id = 0;
+ uint32_t slot_id = 0;
+ uint32_t sym_id = 0;
+ uint32_t sym_idx_to_send = 0;
+ uint32_t idxSym;
+ uint8_t ctx_id;
+ enum xran_in_period inPeriod;
+ uint32_t interval;
+ uint8_t PortId;
+ struct xran_device_ctx * p_xran_dev_ctx = NULL;
- uint16_t* __restrict pSrc = NULL;
- uint16_t* __restrict pDst = NULL;
+ p_xran_dev_ctx = xran_dev_get_ctx_by_id(xran_port_id);
- const enum xran_input_byte_order iq_buf_byte_order = p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder;
+ if(p_xran_dev_ctx == NULL)
+ return 0;
- /* radio app header */
- xp.app_params.data_feature.value = 0x10;
- xp.app_params.data_feature.data_direction = direction;
- xp.app_params.frame_id = frame_id;
- xp.app_params.sf_slot_sym.subframe_id = subframe_id;
- xp.app_params.sf_slot_sym.slot_id = slot_id;
- xp.app_params.sf_slot_sym.symb_id = sym_id;
- /* convert to network byte order */
- xp.app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp.app_params.sf_slot_sym.value);
+ if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
+ return 0;
+ interval = p_xran_dev_ctx->interval_us_local;
+ PortId = p_xran_dev_ctx->xran_port_id;
- for (cc_id = 0; cc_id < num_cc; cc_id++)
- {
- for (ant_id = 0; ant_id < num_ant; ant_id++)
- {
- ptr_sect_elm = p_sec_db->p_sectiondb_elm[ctx_id][direction][cc_id][ant_id];
- if (unlikely(ptr_sect_elm == NULL))
- return (0);
- num_sections = ptr_sect_elm->cur_index;
+ pHandle = p_xran_dev_ctx;
- /* iterate C-Plane configuration to generate corresponding U-Plane */
- vf_id = p_xran_dev_ctx->map2vf[direction][cc_id][ant_id][XRAN_UP_VF];
- pos = (char*)p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
- mb_base = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
- if (unlikely(mb_base == NULL))
+ for (idxSym = nSymStart; idxSym < (nSymStart + nSymNum) && idxSym < XRAN_NUM_OF_SYMBOL_PER_SLOT; idxSym++) {
+ t1 = MLogXRANTick();
+ if(((1 << idxSym) & nSymMask) ) {
+ sym_idx_to_send = nSlotIdx*XRAN_NUM_OF_SYMBOL_PER_SLOT + idxSym;
+ XranOffsetSym(p_xran_dev_ctx->sym_up, sym_idx_to_send, XRAN_NUM_OF_SYMBOL_PER_SLOT*SLOTNUM_PER_SUBFRAME(interval)*1000, &inPeriod);
+ tti = XranGetTtiNum(sym_idx_to_send, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+ slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval));
+ subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
+
+ uint16_t sfnSecStart = xran_getSfnSecStart();
+ if(unlikely(inPeriod == XRAN_IN_NEXT_PERIOD))
{
- rte_panic("mb == NULL\n");
+ // For DU
+ sfnSecStart = (sfnSecStart + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
}
-
- cid = ((cc_id << ccid_pos) & ccid_mask) | ((ant_id << antid_pos) & antid_mask);
- cid = rte_cpu_to_be_16(cid);
- iq_sample_size_bits = 16;
-
-#ifdef TRANSMIT_BURST
- loc_tx_mbufs.len = 0;
-#endif
- loc_tx_mbufs_fragmented.len = 0;
- len_frag = 0;
-#pragma loop_count min=1, max=16
- for (next=0; next< num_sections; next++)
+ else if(unlikely(inPeriod == XRAN_IN_PREV_PERIOD))
{
- sectinfo = &ptr_sect_elm->list[next];
-
- if (unlikely(sectinfo == NULL))
- break;
- if (unlikely(sectinfo->type != XRAN_CP_SECTIONTYPE_1))
- { /* only supports type 1 */
- print_err("Invalid section type in section DB - %d", sectinfo->type);
- continue;
+ // For RU
+ if (sfnSecStart >= NUM_OF_FRAMES_PER_SECOND)
+ {
+ sfnSecStart -= NUM_OF_FRAMES_PER_SECOND;
+ }
+ else
+ {
+ sfnSecStart += NUM_OF_FRAMES_PER_SFN_PERIOD - NUM_OF_FRAMES_PER_SECOND;
}
- /* skip, if not scheduled */
- if (unlikely(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol))
- continue;
+ }
+ frame_id = XranGetFrameNum(tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
+ // ORAN frameId, 8 bits, [0, 255]
+ frame_id = (frame_id & 0xff);
- compMeth = sectinfo->compMeth;
- iqWidth = sectinfo->iqWidth;
- section_id = sectinfo->id;
- prb_start = sectinfo->startPrbc;
- prb_num = sectinfo->numPrbc;
- seq_id = xran_updl_seq_id_num[xran_port_id][cc_id][ant_id]++;
- len2 = 0;
+ sym_id = XranGetSymNum(sym_idx_to_send, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
- if (compMeth)
- iq_sample_size_bits = iqWidth;
+ print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id);
- comp_head_upd = ((compMeth != XRAN_COMPMETHOD_NONE) && (compType == XRAN_COMP_HDR_TYPE_DYNAMIC));
+#if XRAN_MLOG_VAR
+ mlogVarCnt = 0;
+ mlogVar[mlogVarCnt++] = 0xAAAAAAAA;
+ mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx[PortId];
+ mlogVar[mlogVarCnt++] = idxSym;
+ mlogVar[mlogVarCnt++] = abs(p_xran_dev_ctx->sym_up);
+ mlogVar[mlogVarCnt++] = tti;
+ mlogVar[mlogVarCnt++] = frame_id;
+ mlogVar[mlogVarCnt++] = subframe_id;
+ mlogVar[mlogVarCnt++] = slot_id;
+ mlogVar[mlogVarCnt++] = sym_id;
+ mlogVar[mlogVarCnt++] = PortId;
+ MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
+#endif
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU
+ && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B)
+ {
+ num_eAxc = xran_get_num_eAxcUl(pHandle);
+ }
+ else
+ {
+ num_eAxc = xran_get_num_eAxc(pHandle);
+ }
- print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next,
- sectinfo->type, sectinfo->id, sectinfo->startPrbc,
- sectinfo->numPrbc, sectinfo->startSymId, sectinfo->numSymbol);
+ num_eAxc_prach = ((num_eAxc > XRAN_MAX_PRACH_ANT_NUM)? XRAN_MAX_PRACH_ANT_NUM : num_eAxc);
+ num_CCPorts = xran_get_num_cc(pHandle);
- p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][section_id];
- p_share_data->free_cb = extbuf_free_callback;
- p_share_data->fcb_opaque = NULL;
- rte_mbuf_ext_refcnt_set(p_share_data, 1);
+ /* U-Plane */
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU && p_xran_dev_ctx->enableCP) {
+ enum xran_comp_hdr_type compType;
+ enum xran_pkt_dir direction;
+ //uint32_t prb_num;
+ uint32_t loc_ret = 1;
+ uint16_t xran_port_id;
+ PSECTION_DB_TYPE p_sec_db = NULL;
-#ifdef TRANSMIT_BURST
- len = loc_tx_mbufs.len;
- //Added for Klocworks
- if (unlikely(len >= MBUF_TABLE_SIZE))
+ compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)
{
- len = MBUF_TABLE_SIZE - 1;
- rte_panic("len >= MBUF_TABLE_SIZE\n");
+ direction = XRAN_DIR_DL; /* O-DU */
+ //prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
+ }
+ else
+ {
+ direction = XRAN_DIR_UL; /* RU */
+ //prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
}
-#endif
- p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset);
- ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len;
- ext_buff = p_sec_iq - total_header_size;
- ext_buff_len += (total_header_size + 18);
+ if(unlikely(p_xran_dev_ctx->xran_port_id > XRAN_PORTS_NUM))
+ {
+ print_err("Invalid Port id - %d", p_xran_dev_ctx->xran_port_id);
+ loc_ret = 0;
+ }
- if (comp_head_upd)
+ if(unlikely(ctx_id > XRAN_MAX_SECTIONDB_CTX))
{
- ext_buff -= sizeof(struct data_section_compression_hdr);
- ext_buff_len += sizeof(struct data_section_compression_hdr);
+ print_err("Invalid Context id - %d", ctx_id);
+ loc_ret = 0;
}
- mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]);
- if (unlikely((mb_oran_hdr_ext) == NULL))
+ if(unlikely(direction > XRAN_DIR_MAX))
{
- rte_panic("[core %d]Failed rte_pktmbuf_alloc on vf %d\n", rte_lcore_id(), vf_id);
+ print_err("Invalid direction - %d", direction);
+ loc_ret = 0;
}
- iova_hdr = (struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size);
- ext_buff_iova = iova_hdr->iova;
+ if(unlikely(num_CCPorts > XRAN_COMPONENT_CARRIERS_MAX))
+ {
+ print_err("Invalid CC id - %d", num_CCPorts);
+ loc_ret = 0;
+ }
-#ifdef ENABLE_DEBUG_COREDUMP
- if (unlikely(ext_buff_iova == 0))
+ if(unlikely(num_eAxc > (XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR)))
{
- rte_panic("Failed rte_mem_virt2iova\n");
+ print_err("Invalid eAxC id - %d", num_eAxc);
+ loc_ret = 0;
}
- if (unlikely(((rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA))
+
+ xran_port_id = p_xran_dev_ctx->xran_port_id;
+ p_sec_db = p_sectiondb[p_xran_dev_ctx->xran_port_id];
+ if(unlikely(p_sec_db == NULL))
{
- rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
+ print_err("p_sec_db == NULL\n");
+ loc_ret = 0;
+ }
+
+ if (loc_ret) {
+ retval = xran_process_tx_sym_cp_on_opt(pHandle, ctx_id, tti,
+ nCcStart, nCcNum, nAntStart, nAntNum, frame_id, subframe_id, slot_id, idxSym,
+ compType, direction, xran_port_id, p_sec_db);
+ } else {
+ print_err("loc_ret %d\n", loc_ret);
+ retval = 0;
}
+ } else {
+ for (ant_id = 0; ant_id < num_eAxc; ant_id++) {
+ for (cc_id = 0; cc_id < num_CCPorts; cc_id++) {
+ //struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
+ if(p_xran_dev_ctx->puschMaskEnable)
+ {
+ if((tti % numSlotMu1) != p_xran_dev_ctx->puschMaskSlot)
+ retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0);
+ }
+ else
+ retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0);
+
+ if(p_xran_dev_ctx->enablePrach && (ant_id < num_eAxc_prach) )
+ {
+ retval = xran_process_tx_prach_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id);
+ }
+ }
+ }
+ }
+
+ /* SRS U-Plane, only for O-RU emulation with Cat B */
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU
+ && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B
+ && p_xran_dev_ctx->enableSrs
+ && ((p_xran_dev_ctx->srs_cfg.symbMask >> idxSym)&1))
+ {
+ struct xran_srs_config *pSrsCfg = &(p_xran_dev_ctx->srs_cfg);
+
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ /* check special frame */
+ if((xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ || (xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1))
+ {
+ if(((tti % p_xran_dev_ctx->fh_cfg.frame_conf.nTddPeriod) == pSrsCfg->slot)
+ && (p_xran_dev_ctx->ndm_srs_scheduled == 0))
+ {
+ int elmIdx;
+ struct xran_prb_map *prb_map;
+ prb_map = (struct xran_prb_map *)p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][0].sBufferList.pBuffers->pData;
+
+ /* if PRB map is present in first antenna, assume SRS might be scheduled. */
+ if(prb_map && prb_map->nPrbElm)
+ {
+ /* NDM U-Plane is not enabled */
+ if(pSrsCfg->ndm_offset == 0)
+ {
+
+ if (prb_map->nPrbElm > 0)
+ {
+ /* Check symbol range in PRB Map */
+ if(sym_id >= prb_map->prbMap[0].nStartSymb
+ && sym_id < (prb_map->prbMap[0].nStartSymb + prb_map->prbMap[0].numSymb))
+ for(ant_id=0; ant_id < xran_get_num_ant_elm(pHandle); ant_id++)
+ xran_process_tx_srs_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id);
+ }
+
+ }
+ /* NDM U-Plane is enabled, SRS U-Planes will be transmitted after ndm_offset (in slots) */
+ else
+ {
+ p_xran_dev_ctx->ndm_srs_scheduled = 1;
+ p_xran_dev_ctx->ndm_srs_tti = tti;
+ p_xran_dev_ctx->ndm_srs_txtti = (tti + pSrsCfg->ndm_offset)%2000;
+ p_xran_dev_ctx->ndm_srs_schedperiod = pSrsCfg->slot;
+ }
+ }
+ }
+ }
+ /* check SRS NDM UP has been scheduled in non special slots */
+ else if(p_xran_dev_ctx->ndm_srs_scheduled
+ && p_xran_dev_ctx->ndm_srs_txtti == tti)
+ {
+ int ndm_step;
+ uint32_t srs_tti, srsFrame, srsSubframe, srsSlot;
+ uint8_t srsCtx;
+
+ srs_tti = p_xran_dev_ctx->ndm_srs_tti;
+ num_eAxAntElm = xran_get_num_ant_elm(pHandle);
+ ndm_step = num_eAxAntElm / pSrsCfg->ndm_txduration;
+
+ srsSlot = XranGetSlotNum(srs_tti, SLOTNUM_PER_SUBFRAME(interval));
+ srsSubframe = XranGetSubFrameNum(srs_tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
+ srsFrame = XranGetFrameNum(srs_tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
+ srsFrame = (srsFrame & 0xff);
+ srsCtx = srs_tti % XRAN_MAX_SECTIONDB_CTX;
+
+ if(sym_id < pSrsCfg->ndm_txduration)
+ {
+ for(ant_id=sym_id*ndm_step; ant_id < (sym_id+1)*ndm_step; ant_id++)
+ xran_process_tx_srs_cp_off(pHandle, srsCtx, srs_tti, cc_id, ant_id, srsFrame, srsSubframe, srsSlot);
+ }
+ else
+ {
+ p_xran_dev_ctx->ndm_srs_scheduled = 0;
+ p_xran_dev_ctx->ndm_srs_tti = 0;
+ p_xran_dev_ctx->ndm_srs_txtti = 0;
+ p_xran_dev_ctx->ndm_srs_schedperiod = 0;
+ }
+ }
+ }
+ }
+ }
+ MLogXRANTask(PID_DISPATCH_TX_SYM, t1, MLogXRANTick());
+ }
+
+ return retval;
+}
+
+
+static inline uint16_t
+xran_tx_sym_from_ring(struct xran_device_ctx* p_xran_dev_ctx, struct rte_ring *r, uint16_t vf_id)
+{
+ struct rte_mbuf *mbufs[XRAN_MAX_MEM_IF_RING_SIZE];
+ uint16_t dequeued, sent = 0;
+ uint32_t remaining;
+ //long t1 = MLogXRANTick();
+
+ dequeued = rte_ring_dequeue_burst(r, (void **)mbufs, XRAN_MAX_MEM_IF_RING_SIZE,
+ &remaining);
+ if (!dequeued)
+ return 0; /* Nothing to send. */
+
+ while (1) {
+ //sent += p_xran_dev_ctx->send_upmbuf2ring(mbufs[sent], ETHER_TYPE_ECPRI, vf_id);
+ sent += rte_eth_tx_burst(vf_id, 0, &mbufs[sent], dequeued - sent);
+ if (sent == dequeued){
+ // MLogXRANTask(PID_REQUEUE_TX_SYM, t1, MLogXRANTick());
+ return remaining;
+ }
+ }
+}
+
+int32_t
+xran_process_tx_sym_cp_on_ring(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
+ uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
+ uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db)
+{
+ struct rte_ring *ring = NULL;
+ struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle;
+ int32_t cc_id = 0;
+ int32_t ant_id = 0;
+ uint16_t vf_id = 0;
+
+ for (cc_id = start_cc; cc_id < (start_cc + num_cc); cc_id++) {
+ for (ant_id = start_ant; ant_id < (start_ant + num_ant); ant_id++) {
+ vf_id = p_xran_dev_ctx->map2vf[direction][cc_id][ant_id][XRAN_UP_VF];
+ ring = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pRing;
+ xran_tx_sym_from_ring(p_xran_dev_ctx, ring, vf_id);
+ }
+ }
+ return 0;
+}
+
+//#define TRANSMIT_BURST
+//#define ENABLE_DEBUG_COREDUMP
+
+#define ETHER_TYPE_ECPRI_BE (0xFEAE)
+
+int32_t
+xran_process_tx_sym_cp_on_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
+ uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
+ uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db)
+{
+ struct xran_up_pkt_gen_params *pxp;
+ struct data_section_hdr *pDataSec;
+ char* ext_buff;
+ void *mb_base;
+ struct rte_ring *ring;
+ char* pStart;
+ struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx();
+ struct xran_section_info* sectinfo;
+ struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle;
+ struct rte_mbuf_ext_shared_info* p_share_data;
+ struct xran_sectioninfo_db* ptr_sect_elm = NULL;
+ struct rte_mbuf* mb_oran_hdr_ext = NULL;
+ struct xran_ecpri_hdr* ecpri_hdr = NULL;
+ //uint16_t* __restrict pSrc = NULL;
+ uint16_t* __restrict pDst = NULL;
+
+ uint16_t next;
+ uint16_t ext_buff_len = 0;
+ uint16_t iq_sample_size_bytes=0;
+ uint16_t num_sections = 0, total_sections = 0;
+ uint16_t n_bytes;
+ uint16_t elm_bytes = 0;
+ uint16_t section_id;
+ uint16_t nPktSize=0;
+ uint16_t cid;
+ uint16_t vf_id;
+ const int16_t rte_mempool_objhdr_size = sizeof(struct rte_mempool_objhdr);
+ uint8_t seq_id = 0;
+ uint8_t cc_id, ant_id;
+
+#ifdef TRANSMIT_BURST
+ uint16_t len = 0;
+#endif
+ //uint16_t len2 = 0, len_frag = 0;
+ uint8_t compMeth;
+ uint8_t iqWidth;
+ uint8_t parm_size;
+#ifdef TRANSMIT_BURST
+ struct mbuf_table loc_tx_mbufs;
+ struct mbuf_table loc_tx_mbufs_fragmented = {0};
#endif
- mb_oran_hdr_ext->buf_addr = ext_buff;
- mb_oran_hdr_ext->buf_iova = ext_buff_iova + RTE_PTR_DIFF(ext_buff, mb_base);
- mb_oran_hdr_ext->buf_len = ext_buff_len;
- mb_oran_hdr_ext->ol_flags |= EXT_ATTACHED_MBUF;
- mb_oran_hdr_ext->shinfo = p_share_data;
- mb_oran_hdr_ext->data_off = (uint16_t)RTE_MIN((uint16_t)RTE_PKTMBUF_HEADROOM, (uint16_t)mb_oran_hdr_ext->buf_len) - rte_ether_hdr_size;
- mb_oran_hdr_ext->data_len = (uint16_t)(mb_oran_hdr_ext->data_len + rte_ether_hdr_size);
- mb_oran_hdr_ext->pkt_len = mb_oran_hdr_ext->pkt_len + rte_ether_hdr_size;
- mb_oran_hdr_ext->port = eth_ctx->io_cfg.port[vf_id];
-
- mb = (void*)mb_oran_hdr_ext;
-
- to_free_mbuf = p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id];
- p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id] = mb;
- rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */
- if (to_free_mbuf)
+ uint8_t fragNeeded=0;
+
+ const uint8_t rte_ether_hdr_size = sizeof(struct rte_ether_hdr);
+ uint8_t comp_head_upd = 0;
+
+ const uint8_t total_header_size = (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct radio_app_common_hdr) +
+ sizeof(struct data_section_hdr));
+
+
+ for (cc_id = start_cc; cc_id < (start_cc + num_cc); cc_id++)
+ {
+ for (ant_id = start_ant; ant_id < (start_ant + num_ant); ant_id++)
+ {
+ ptr_sect_elm = p_sec_db->p_sectiondb_elm[ctx_id][direction][cc_id][ant_id];
+ if (unlikely(ptr_sect_elm == NULL)){
+ rte_panic("ptr_sect_elm == NULL\n");
+ return (0);
+ }
+
+ if(0!=ptr_sect_elm->cur_index)
+ {
+ num_sections = ptr_sect_elm->cur_index;
+ /* iterate C-Plane configuration to generate corresponding U-Plane */
+ vf_id = p_xran_dev_ctx->map2vf[direction][cc_id][ant_id][XRAN_UP_VF];
+ mb_base = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
+ ring = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pRing;
+ if (unlikely(mb_base == NULL))
{
- rte_pktmbuf_free(to_free_mbuf);
+ rte_panic("mb == NULL\n");
}
+ cid = ((cc_id << p_xran_dev_ctx->eAxc_id_cfg.bit_ccId) & p_xran_dev_ctx->eAxc_id_cfg.mask_ccId) | ((ant_id << p_xran_dev_ctx->eAxc_id_cfg.bit_ruPortId) & p_xran_dev_ctx->eAxc_id_cfg.mask_ruPortId);
+ cid = rte_cpu_to_be_16(cid);
+
+#ifdef TRANSMIT_BURST
+ loc_tx_mbufs.len = 0;
+#endif
+ //len_frag = 0;
+#pragma loop_count min=1, max=16
+ for (next=0; next< num_sections; next++)
+ {
+ sectinfo = &ptr_sect_elm->list[next];
- pStart = (char*)((char*)mb_oran_hdr_ext->buf_addr + mb_oran_hdr_ext->data_off);
+ if (unlikely(sectinfo == NULL)) {
+ print_err("sectinfo == NULL\n");
+ break;
+ }
+ if (unlikely(sectinfo->type != XRAN_CP_SECTIONTYPE_1))
+ { /* only supports type 1 */
+ print_err("Invalid section type in section DB - %d", sectinfo->type);
+ continue;
+ }
+ /* skip, if not scheduled */
+ if (unlikely(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol))
+ continue;
+
+ compMeth = sectinfo->compMeth;
+ iqWidth = sectinfo->iqWidth;
+ section_id = sectinfo->id;
+
+ comp_head_upd = ((compMeth != XRAN_COMPMETHOD_NONE) && (compType == XRAN_COMP_HDR_TYPE_DYNAMIC));
+
+ if(sectinfo->prbElemBegin || p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable)
+ {
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)
+ seq_id = xran_updl_seq_id_num[xran_port_id][cc_id][ant_id]++;
+ else
+ seq_id = xran_upul_seq_id_num[xran_port_id][cc_id][ant_id]++;
+ iq_sample_size_bytes = 18 + sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct radio_app_common_hdr);
+ }
+
+
+ if (compMeth)
+ {
+ iq_sample_size_bytes += sizeof(struct data_section_hdr) ;
+
+ if (comp_head_upd)
+ {
+ iq_sample_size_bytes += sizeof(struct data_section_compression_hdr);
+ }
+
+ iq_sample_size_bytes += sectinfo->numPrbc*(iqWidth*3 + 1);
+ }
- ether_hdr = (struct rte_ether_hdr*)pStart;
+ print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next,
+ sectinfo->type, sectinfo->id, sectinfo->startPrbc,
+ sectinfo->numPrbc, sectinfo->startSymId, sectinfo->numSymbol);
- /* Fill in the ethernet header. */
+
+#ifdef TRANSMIT_BURST
+ len = loc_tx_mbufs.len;
+ //Added for Klocworks
+ if (unlikely(len >= MBUF_TABLE_SIZE))
+ {
+ len = MBUF_TABLE_SIZE - 1;
+ rte_panic("len >= MBUF_TABLE_SIZE\n");
+ }
+#endif
+ if(sectinfo->prbElemBegin || p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable)
+ {
+ p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][section_id];
+ p_share_data->free_cb = extbuf_free_callback;
+ p_share_data->fcb_opaque = NULL;
+ rte_mbuf_ext_refcnt_set(p_share_data, 1);
+
+ /* Create ethernet + eCPRI + radio app header */
+ ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len;
+
+ ext_buff = ((char*)p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData + sectinfo->sec_desc[sym_id].iq_buffer_offset) - total_header_size;
+ ext_buff_len += (total_header_size + 18);
+
+ if (comp_head_upd)
+ {
+ ext_buff -= sizeof(struct data_section_compression_hdr);
+ ext_buff_len += sizeof(struct data_section_compression_hdr);
+ }
+
+ mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]);
+ if (unlikely((mb_oran_hdr_ext) == NULL))
+ {
+ rte_panic("[core %d]Failed rte_pktmbuf_alloc on vf %d\n", rte_lcore_id(), vf_id);
+ }
+
+#ifdef ENABLE_DEBUG_COREDUMP
+ if (unlikely((struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size)->iova == 0))
+ {
+ rte_panic("Failed rte_mem_virt2iova\n");
+ }
+ if (unlikely(((rte_iova_t)(struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size)->iova) == RTE_BAD_IOVA))
+ {
+ rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
+ }
+#endif
+ mb_oran_hdr_ext->buf_addr = ext_buff;
+ mb_oran_hdr_ext->buf_iova = ((struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size))->iova + RTE_PTR_DIFF(ext_buff, mb_base);
+ mb_oran_hdr_ext->buf_len = ext_buff_len;
+ mb_oran_hdr_ext->ol_flags |= EXT_ATTACHED_MBUF;
+ mb_oran_hdr_ext->shinfo = p_share_data;
+ mb_oran_hdr_ext->data_off = (uint16_t)RTE_MIN((uint16_t)RTE_PKTMBUF_HEADROOM, (uint16_t)mb_oran_hdr_ext->buf_len) - rte_ether_hdr_size;
+ mb_oran_hdr_ext->data_len = (uint16_t)(mb_oran_hdr_ext->data_len + rte_ether_hdr_size);
+ mb_oran_hdr_ext->pkt_len = mb_oran_hdr_ext->pkt_len + rte_ether_hdr_size;
+ mb_oran_hdr_ext->port = eth_ctx->io_cfg.port[vf_id];
+
+ p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id] = (void*)mb_oran_hdr_ext;
+ rte_pktmbuf_refcnt_update((void*)mb_oran_hdr_ext, 1); /* make sure eth won't free our mbuf */
+ if (p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id])
+ {
+ rte_pktmbuf_free(p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id]);
+ }
+
+ pStart = (char*)((char*)mb_oran_hdr_ext->buf_addr + mb_oran_hdr_ext->data_off);
+
+ /* Fill in the ethernet header. */
#ifndef TRANSMIT_BURST
- rte_eth_macaddr_get(mb_oran_hdr_ext->port, ðer_hdr->s_addr); /* set source addr */
- ether_hdr->d_addr = eth_ctx->entities[vf_id][ID_O_RU]; /* set dst addr */
- ether_hdr->ether_type = ETHER_TYPE_ECPRI_BE; /* ethertype */
+ rte_eth_macaddr_get(mb_oran_hdr_ext->port, &((struct rte_ether_hdr*)pStart)->s_addr); /* set source addr */
+ ((struct rte_ether_hdr*)pStart)->d_addr = eth_ctx->entities[vf_id][ID_O_RU]; /* set dst addr */
+ ((struct rte_ether_hdr*)pStart)->ether_type = ETHER_TYPE_ECPRI_BE; /* ethertype */
#endif
- iqWidth = (iqWidth == 0) ? 16 : iqWidth;
- switch (compMeth)
- {
+ nPktSize = sizeof(struct rte_ether_hdr)
+ + sizeof(struct xran_ecpri_hdr)
+ + sizeof(struct radio_app_common_hdr) ;
+
+ ecpri_hdr = (struct xran_ecpri_hdr*)(pStart + sizeof(struct rte_ether_hdr));
+
+ ecpri_hdr->cmnhdr.data.data_num_1 = 0x0;
+ ecpri_hdr->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER;
+ ecpri_hdr->cmnhdr.bits.ecpri_mesg_type = ECPRI_IQ_DATA;
+
+ /* one to one lls-CU to RU only and band sector is the same */
+ ecpri_hdr->ecpri_xtc_id = cid;
+
+ /* no transport layer fragmentation supported */
+ ecpri_hdr->ecpri_seq_id.data.data_num_1 = 0x8000;
+ ecpri_hdr->ecpri_seq_id.bits.seq_id = seq_id;
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size = sizeof(struct radio_app_common_hdr) + XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size();;;
+
+ } /* if(sectinfo->prbElemBegin) */
+
+ /* Prepare U-Plane section hdr */
+ iqWidth = (iqWidth == 0) ? 16 : iqWidth;
+ switch (compMeth)
+ {
case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
default:
parm_size = 0;
- }
- n_bytes = (3 * iqWidth + parm_size) * prb_num;
- n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN);
-
- nPktSize = sizeof(struct rte_ether_hdr)
- + sizeof(struct xran_ecpri_hdr)
- + sizeof(struct radio_app_common_hdr)
- + sizeof(struct data_section_hdr)
- + n_bytes;
-
- if (comp_head_upd)
- nPktSize += sizeof(struct data_section_compression_hdr);
-
- xp.sec_hdr.fields.sect_id = section_id;
- xp.sec_hdr.fields.num_prbu = (uint8_t)XRAN_CONVERT_NUMPRBC(prb_num);
- xp.sec_hdr.fields.start_prbu = (uint8_t)prb_start;
- xp.sec_hdr.fields.sym_inc = 0;
- xp.sec_hdr.fields.rb = 0;
- /* network byte order */
- xp.sec_hdr.fields.all_bits = rte_cpu_to_be_32(xp.sec_hdr.fields.all_bits);
+ }
- /* compression */
- xp.compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth;
- xp.compr_hdr_param.ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth);
- xp.compr_hdr_param.rsrvd = 0;
-
- ecpri_hdr = (struct xran_ecpri_hdr*)(pStart + sizeof(struct rte_ether_hdr));
-
- ecpri_payl_size = n_bytes
- + sizeof(struct data_section_hdr)
- + sizeof(struct radio_app_common_hdr)
- + XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size();
-
- if (comp_head_upd)
- ecpri_payl_size += sizeof(struct data_section_compression_hdr);
-
- ecpri_hdr->cmnhdr.data.data_num_1 = 0x0;
- ecpri_hdr->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER;
- ecpri_hdr->cmnhdr.bits.ecpri_mesg_type = ECPRI_IQ_DATA;
- ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(ecpri_payl_size);
-
- /* one to one lls-CU to RU only and band sector is the same */
- ecpri_hdr->ecpri_xtc_id = cid;
-
- /* no transport layer fragmentation supported */
- ecpri_hdr->ecpri_seq_id.data.data_num_1 = 0x8000;
- ecpri_hdr->ecpri_seq_id.bits.seq_id = seq_id;
-
- pSrc = (uint16_t*)&(xp.app_params);
- pDst = (uint16_t*)(pStart + sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr));
- *pDst++ = *pSrc++;
- *pDst++ = *pSrc++;
- *pDst++ = *pSrc++;
- *pDst++ = *pSrc++;
- if (comp_head_upd)
- {
- *pDst++ = *pSrc++;
- }
+ n_bytes = (3 * iqWidth + parm_size) * sectinfo->numPrbc; //Dont understand this
+ n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN);
- rte_pktmbuf_pkt_len(mb_oran_hdr_ext) = nPktSize;
- rte_pktmbuf_data_len(mb_oran_hdr_ext) = nPktSize;
+ /* Ethernet & eCPRI added already */
+ nPktSize += sizeof(struct data_section_hdr) + n_bytes;
- elm_bytes += nPktSize;
+ if (comp_head_upd)
+ nPktSize += sizeof(struct data_section_compression_hdr);
- /* Restore fragmentation support in this code version */
- /* if we don't need to do any fragmentation */
- if (likely(p_xran_dev_ctx->fh_init.mtu >= sectinfo->numPrbc * (3 * iq_sample_size_bits + 1)))
- {
- /* no fragmentation */
- len2 = 1;
-#ifdef TRANSMIT_BURST
- loc_tx_mbufs.m_table[len++] = mb;
- if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM))
+ if(likely((ecpri_hdr!=NULL)))
{
- rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n");
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size += sizeof(struct data_section_hdr) + n_bytes ;
+
+ if (comp_head_upd)
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size += sizeof(struct data_section_compression_hdr);
}
- loc_tx_mbufs.len = len;
-#else
- xran_enqueue_mbuf(mb_oran_hdr_ext, eth_ctx->tx_ring[vf_id]);
-#endif
- }
- else
- {
- /* fragmentation */
- /* only burst transmission mode is supported for fragmented packets*/
- uint8_t* p_seq_num = &xran_updl_seq_id_num[xran_port_id][cc_id][ant_id];
- (*p_seq_num)--;
-
- len2 = xran_app_fragment_packet(mb_oran_hdr_ext,
- &loc_tx_mbufs_fragmented.m_table[len_frag],
- (uint16_t)(MBUF_TABLE_SIZE - len_frag),
- p_xran_dev_ctx->fh_init.mtu,
- p_xran_dev_ctx->direct_pool,
- p_xran_dev_ctx->indirect_pool,
- prb_start,
- prb_num,
- p_seq_num,
- iqWidth,
- ((iqWidth == 16) || (compType == XRAN_COMP_HDR_TYPE_STATIC)) ? 0 : 1);
-
- /* Free input packet */
- rte_pktmbuf_free(mb_oran_hdr_ext);
-
- /* If we fail to fragment the packet */
- if (unlikely(len2 < 0))
+ else
{
- print_err("len2= %d\n", len2);
- continue;
+ print_err("ecpri_hdr should not be NULL\n");
+ }
+ //ecpri_hdr->cmnhdr.bits.ecpri_payl_size += ecpri_payl_size;
+
+ /* compression */
+
+ if(sectinfo->prbElemBegin || p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable)
+ {
+ pDst = (uint16_t*)(pStart + sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr));
+ pxp = (struct xran_up_pkt_gen_params *)pDst;
+ /* radio app header */
+ pxp->app_params.data_feature.value = 0x10;
+ pxp->app_params.data_feature.data_direction = direction;
+ pxp->app_params.frame_id = frame_id;
+ pxp->app_params.sf_slot_sym.subframe_id = subframe_id;
+ pxp->app_params.sf_slot_sym.slot_id = slot_id;
+ pxp->app_params.sf_slot_sym.symb_id = sym_id;
+ /* convert to network byte order */
+ pxp->app_params.sf_slot_sym.value = rte_cpu_to_be_16(pxp->app_params.sf_slot_sym.value);
+ pDst += 2;
+ }
+
+ pDataSec = (struct data_section_hdr *)pDst;
+ if(pDataSec){
+ pDataSec->fields.sect_id = section_id;
+ pDataSec->fields.num_prbu = (uint8_t)XRAN_CONVERT_NUMPRBC(sectinfo->numPrbc);
+ pDataSec->fields.start_prbu = (sectinfo->startPrbc & 0x03ff);
+ pDataSec->fields.sym_inc = 0;
+ pDataSec->fields.rb = 0;
+ /* network byte order */
+ pDataSec->fields.all_bits = rte_cpu_to_be_32(pDataSec->fields.all_bits);
+ pDst += 2;
}
- if (unlikely(len2 > 1))
+ else
+ {
+ print_err("pDataSec is NULL idx = %u num_sections = %u\n", next, num_sections);
+ // return 0;
+ }
+
+ if (comp_head_upd)
+ {
+ if(pDst == NULL){
+ print_err("pDst == NULL\n");
+ return 0;
+ }
+ ((struct data_section_compression_hdr *)pDst)->ud_comp_hdr.ud_comp_meth = compMeth;
+ ((struct data_section_compression_hdr *)pDst)->ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth);
+ ((struct data_section_compression_hdr *)pDst)->rsrvd = 0;
+ pDst++;
+ }
+
+ //Increment by IQ data len
+ pDst = (uint16_t *)((uint8_t *)pDst + n_bytes) ;
+ if(mb_oran_hdr_ext){
+ rte_pktmbuf_pkt_len(mb_oran_hdr_ext) = nPktSize;
+ rte_pktmbuf_data_len(mb_oran_hdr_ext) = nPktSize;
+ }
+
+ if(sectinfo->prbElemEnd || p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable) /* Transmit the packet */
{
- for (int32_t i = len_frag; i < len_frag + len2; i++)
+ if(likely((ecpri_hdr!=NULL)))
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(ecpri_hdr->cmnhdr.bits.ecpri_payl_size);
+ else
+ print_err("ecpri_hdr should not be NULL\n");
+ /* if we don't need to do any fragmentation */
+ if (likely(p_xran_dev_ctx->fh_init.mtu >= (iq_sample_size_bytes)))
{
- struct rte_mbuf* m;
- m = loc_tx_mbufs_fragmented.m_table[i];
- struct rte_ether_hdr* eth_hdr = (struct rte_ether_hdr*)
- rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr));
- if (eth_hdr == NULL)
+ /* no fragmentation */
+ //len2 = 1;
+#ifdef TRANSMIT_BURST
+ loc_tx_mbufs.m_table[len++] = (void*)mb_oran_hdr_ext;
+ if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM))
{
- rte_panic("No headroom in mbuf.\n");
+ rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n");
+ }
+ loc_tx_mbufs.len = len;
+#else
+
+ if(p_xran_dev_ctx->fh_init.io_cfg.bbu_offload){
+ rte_ring_enqueue(ring, mb_oran_hdr_ext);
+ } else {
+ xran_enqueue_mbuf(mb_oran_hdr_ext, eth_ctx->tx_ring[vf_id]);
}
+#endif
}
- }
+ else
+ {
+ /* current code should not go to fragmentation as it should be taken care of by section allocation already */
+ // print_err("should not go into fragmentation mtu %d packet size %d\n", p_xran_dev_ctx->fh_init.mtu, sectinfo->numPrbc * (3*iq_sample_size_bits + 1));
+ return 0;
+ }
+ elm_bytes += nPktSize;
+ } /* if(prbElemEnd) */
+ }/* section loop */
+ } /* if ptr_sect_elm->cur_index */
- len_frag += len2;
- if (unlikely(len_frag > XRAN_MAX_PKT_BURST_PER_SYM)) {
- rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n");
- }
- loc_tx_mbufs_fragmented.len = len_frag;
- }
- } /* section loop */
total_sections += num_sections;
/* Transmit packets */
{
for (int32_t i = 0; i < loc_tx_mbufs.len; i++)
{
- p_xran_dev_ctx->send_upmbuf2ring(loc_tx_mbufs.m_table[i], ETHER_TYPE_ECPRI, vf_id);
+ if(p_xran_dev_ctx->fh_init.io_cfg.bbu_offload){
+ rte_ring_enqueue(ring, loc_tx_mbufs_fragmented.m_table[i]);
+ } else {
+ p_xran_dev_ctx->send_upmbuf2ring(loc_tx_mbufs.m_table[i], ETHER_TYPE_ECPRI, vf_id);
+ }
}
loc_tx_mbufs.len = 0;
}
#endif
/* Transmit fragmented packets */
- if (unlikely(loc_tx_mbufs_fragmented.len))
+ if (unlikely(fragNeeded))
{
+#if 0 /* There is no logic populating loc_tx_mbufs_fragmented. hence disabling this code */
for (int32_t i = 0; i < loc_tx_mbufs_fragmented.len; i++)
{
- p_xran_dev_ctx->send_upmbuf2ring(loc_tx_mbufs_fragmented.m_table[i], ETHER_TYPE_ECPRI, vf_id);
+ if(p_xran_dev_ctx->fh_init.io_cfg.bbu_offload){
+ rte_ring_enqueue(ring, loc_tx_mbufs_fragmented.m_table[i]);
+ } else {
+ p_xran_dev_ctx->send_upmbuf2ring(loc_tx_mbufs_fragmented.m_table[i], ETHER_TYPE_ECPRI, vf_id);
+ }
}
- loc_tx_mbufs_fragmented.len = 0;
+#endif
}
} /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */
} /* for(ant_id = 0; ant_id < num_eAxc; ant_id++) */
return 1;
}
+int32_t
+xran_process_tx_srs_cp_on(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
+ uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
+ uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db)
+{
+ struct xran_up_pkt_gen_params *pxp;
+ struct data_section_hdr *pDataSec;
+ int32_t antElm_eAxC_id = 0;// = ant_id + p_srs_cfg->eAxC_offset;
+
+ struct xran_srs_config *p_srs_cfg;
+
+ char* ext_buff;
+ void *mb_base;
+ char* pStart;
+ struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx();
+ struct xran_section_info* sectinfo;
+ struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle;
+ p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
+ struct rte_mbuf_ext_shared_info* p_share_data;
+ struct xran_sectioninfo_db* ptr_sect_elm = NULL;
+ struct rte_mbuf* mb_oran_hdr_ext = NULL;
+ struct xran_ecpri_hdr* ecpri_hdr = NULL;
+ uint16_t* __restrict pDst = NULL;
+
+ uint16_t next;
+ uint16_t ext_buff_len = 0;
+ uint16_t iq_sample_size_bytes=0;
+ uint16_t num_sections = 0, total_sections = 0;
+ uint16_t n_bytes;
+ uint16_t elm_bytes = 0;
+ uint16_t section_id;
+ uint16_t nPktSize=0;
+ uint16_t cid;
+ uint16_t vf_id;
+ const int16_t rte_mempool_objhdr_size = sizeof(struct rte_mempool_objhdr);
+ uint8_t seq_id = 0;
+ uint8_t cc_id, ant_id;
+ uint8_t compMeth;
+ uint8_t iqWidth;
+ uint8_t parm_size;
+
+ const uint8_t rte_ether_hdr_size = sizeof(struct rte_ether_hdr);
+ uint8_t comp_head_upd = 0;
+
+ const uint8_t total_header_size = (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct radio_app_common_hdr) +
+ sizeof(struct data_section_hdr));
+
+ for (cc_id = start_cc; cc_id < (start_cc + num_cc); cc_id++)
+ {
+ for (ant_id = start_ant; ant_id < (start_ant + num_ant); ant_id++)
+ {
+ antElm_eAxC_id = ant_id + p_srs_cfg->eAxC_offset;
+ ptr_sect_elm = p_sec_db->p_sectiondb_elm[ctx_id][direction][cc_id][antElm_eAxC_id];
+
+ if (unlikely(ptr_sect_elm == NULL)){
+ printf("ant_id = %d ctx_id = %d,start_ant = %d, num_ant = %d, antElm_eAxC_id = %d\n",ant_id,ctx_id,start_ant,num_ant,antElm_eAxC_id);
+ rte_panic("ptr_sect_elm == NULL\n");
+ return (0);
+ }
+ if(0!=ptr_sect_elm->cur_index)
+ {
+ num_sections = ptr_sect_elm->cur_index;
+ /* iterate C-Plane configuration to generate corresponding U-Plane */
+ vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, antElm_eAxC_id);//p_xran_dev_ctx->map2vf[direction][cc_id][antElm_eAxC_id][XRAN_UP_VF];
+ mb_base = p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
+ if (unlikely(mb_base == NULL))
+ {
+ rte_panic("mb == NULL\n");
+ }
+ cid = ((cc_id << p_xran_dev_ctx->eAxc_id_cfg.bit_ccId) & p_xran_dev_ctx->eAxc_id_cfg.mask_ccId) | ((antElm_eAxC_id << p_xran_dev_ctx->eAxc_id_cfg.bit_ruPortId) & p_xran_dev_ctx->eAxc_id_cfg.mask_ruPortId);
+ cid = rte_cpu_to_be_16(cid);
+#pragma loop_count min=1, max=16
+ for (next=0; next< num_sections; next++)
+ {
+ sectinfo = &ptr_sect_elm->list[next];
+
+ if (unlikely(sectinfo == NULL)) {
+ print_err("sectinfo == NULL\n");
+ break;
+ }
+ if (unlikely(sectinfo->type != XRAN_CP_SECTIONTYPE_1))
+ { /* only supports type 1 */
+ print_err("Invalid section type in section DB - %d", sectinfo->type);
+ continue;
+ }
+ /* skip, if not scheduled */
+ if (unlikely(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol))
+ continue;
+ compMeth = sectinfo->compMeth;
+ iqWidth = sectinfo->iqWidth;
+ section_id = sectinfo->id;
+
+ comp_head_upd = ((compMeth != XRAN_COMPMETHOD_NONE) && (compType == XRAN_COMP_HDR_TYPE_DYNAMIC));
+
+ if(sectinfo->prbElemBegin)
+ {
+ seq_id = xran_get_upul_seqid(pHandle, cc_id, antElm_eAxC_id);
+ iq_sample_size_bytes = 18 + sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct radio_app_common_hdr);
+ }
+
+ if (compMeth)
+ {
+ iq_sample_size_bytes += sizeof(struct data_section_hdr) ;
+
+ if (comp_head_upd)
+ {
+ iq_sample_size_bytes += sizeof(struct data_section_compression_hdr);
+ }
+
+ iq_sample_size_bytes += sectinfo->numPrbc*(iqWidth*3 + 1);
+ }
+
+ print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next,
+ sectinfo->type, sectinfo->id, sectinfo->startPrbc,
+ sectinfo->numPrbc, sectinfo->startSymId, sectinfo->numSymbol);
+
+ if(sectinfo->prbElemBegin)
+ {
+ p_share_data = &p_xran_dev_ctx->srs_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id];
+ p_share_data->free_cb = extbuf_free_callback;
+ p_share_data->fcb_opaque = NULL;
+ rte_mbuf_ext_refcnt_set(p_share_data, 1);
+
+ /* Create ethernet + eCPRI + radio app header */
+ ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len;
+
+ ext_buff = ((char*)p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData + sectinfo->sec_desc[sym_id].iq_buffer_offset) - total_header_size;
+ ext_buff_len += (total_header_size + 18);
+
+ if (comp_head_upd)
+ {
+ ext_buff -= sizeof(struct data_section_compression_hdr);
+ ext_buff_len += sizeof(struct data_section_compression_hdr);
+ }
+
+ mb_oran_hdr_ext = xran_ethdi_mbuf_indir_alloc();
+ if (unlikely((mb_oran_hdr_ext) == NULL))
+ {
+ rte_panic("[core %d]Failed rte_pktmbuf_alloc on vf %d\n", rte_lcore_id(), vf_id);
+ }
+
+#ifdef ENABLE_DEBUG_COREDUMP
+ if (unlikely((struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size)->iova == 0))
+ {
+ rte_panic("Failed rte_mem_virt2iova\n");
+ }
+ if (unlikely(((rte_iova_t)(struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size)->iova) == RTE_BAD_IOVA))
+ {
+ rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
+ }
+#endif
+ mb_oran_hdr_ext->buf_addr = ext_buff;
+ mb_oran_hdr_ext->buf_iova = ((struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size))->iova + RTE_PTR_DIFF(ext_buff, mb_base);
+ mb_oran_hdr_ext->buf_len = ext_buff_len;
+ mb_oran_hdr_ext->ol_flags |= EXT_ATTACHED_MBUF;
+ mb_oran_hdr_ext->shinfo = p_share_data;
+ mb_oran_hdr_ext->data_off = (uint16_t)RTE_MIN((uint16_t)RTE_PKTMBUF_HEADROOM, (uint16_t)mb_oran_hdr_ext->buf_len) - rte_ether_hdr_size;
+ mb_oran_hdr_ext->data_len = (uint16_t)(mb_oran_hdr_ext->data_len + rte_ether_hdr_size);
+ mb_oran_hdr_ext->pkt_len = mb_oran_hdr_ext->pkt_len + rte_ether_hdr_size;
+ mb_oran_hdr_ext->port = eth_ctx->io_cfg.port[vf_id];
+ pStart = (char*)((char*)mb_oran_hdr_ext->buf_addr + mb_oran_hdr_ext->data_off);
+
+ /* Fill in the ethernet header. */
+ rte_eth_macaddr_get(mb_oran_hdr_ext->port, &((struct rte_ether_hdr*)pStart)->s_addr); /* set source addr */
+ ((struct rte_ether_hdr*)pStart)->d_addr = eth_ctx->entities[vf_id][ID_O_RU]; /* set dst addr */
+ ((struct rte_ether_hdr*)pStart)->ether_type = ETHER_TYPE_ECPRI_BE; /* ethertype */
+
+ nPktSize = sizeof(struct rte_ether_hdr)
+ + sizeof(struct xran_ecpri_hdr)
+ + sizeof(struct radio_app_common_hdr) ;
+
+ ecpri_hdr = (struct xran_ecpri_hdr*)(pStart + sizeof(struct rte_ether_hdr));
+
+ ecpri_hdr->cmnhdr.data.data_num_1 = 0x0;
+ ecpri_hdr->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER;
+ ecpri_hdr->cmnhdr.bits.ecpri_mesg_type = ECPRI_IQ_DATA;
+
+ /* one to one lls-CU to RU only and band sector is the same */
+ ecpri_hdr->ecpri_xtc_id = cid;
+
+ /* no transport layer fragmentation supported */
+ ecpri_hdr->ecpri_seq_id.data.data_num_1 = 0x8000;
+ ecpri_hdr->ecpri_seq_id.bits.seq_id = seq_id;
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size = sizeof(struct radio_app_common_hdr) + XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size();;;
+
+ } /* if(sectinfo->prbElemBegin) */
+
+ /* Prepare U-Plane section hdr */
+ iqWidth = (iqWidth == 0) ? 16 : iqWidth;
+ switch (compMeth)
+ {
+ case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break;
+ case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break;
+ default:
+ parm_size = 0;
+ }
+
+ n_bytes = (3 * iqWidth + parm_size) * sectinfo->numPrbc;
+ n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN);
+
+ /* Ethernet & eCPRI added already */
+ nPktSize += sizeof(struct data_section_hdr) + n_bytes;
+
+ if (comp_head_upd)
+ nPktSize += sizeof(struct data_section_compression_hdr);
+
+ if(likely((ecpri_hdr!=NULL)))
+ {
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size += sizeof(struct data_section_hdr) + n_bytes ;
+
+ if (comp_head_upd)
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size += sizeof(struct data_section_compression_hdr);
+ }
+ else
+ {
+ print_err("ecpri_hdr should not be NULL\n");
+ }
+
+ if(sectinfo->prbElemBegin)
+ {
+ pDst = (uint16_t*)(pStart + sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr));
+ pxp = (struct xran_up_pkt_gen_params *)pDst;
+ /* radio app header */
+ pxp->app_params.data_feature.value = 0x10;
+ pxp->app_params.data_feature.data_direction = direction;
+ pxp->app_params.frame_id = frame_id;
+ pxp->app_params.sf_slot_sym.subframe_id = subframe_id;
+ pxp->app_params.sf_slot_sym.slot_id = slot_id;
+ pxp->app_params.sf_slot_sym.symb_id = sym_id;
+ /* convert to network byte order */
+ pxp->app_params.sf_slot_sym.value = rte_cpu_to_be_16(pxp->app_params.sf_slot_sym.value);
+ pDst += 2;
+ }
+
+ pDataSec = (struct data_section_hdr *)pDst;
+ if(pDataSec){
+ pDataSec->fields.sect_id = section_id;
+ pDataSec->fields.num_prbu = (uint8_t)XRAN_CONVERT_NUMPRBC(sectinfo->numPrbc);
+ pDataSec->fields.start_prbu = (sectinfo->startPrbc & 0x03ff);
+ pDataSec->fields.sym_inc = 0;
+ pDataSec->fields.rb = 0;
+ /* network byte order */
+ pDataSec->fields.all_bits = rte_cpu_to_be_32(pDataSec->fields.all_bits);
+ pDst += 2;
+ }
+ else
+ {
+ print_err("pDataSec is NULL idx = %u num_sections = %u\n", next, num_sections);
+ // return 0;
+ }
+
+ if (comp_head_upd)
+ {
+ if(pDst == NULL){
+ print_err("pDst == NULL\n");
+ return 0;
+ }
+ ((struct data_section_compression_hdr *)pDst)->ud_comp_hdr.ud_comp_meth = compMeth;
+ ((struct data_section_compression_hdr *)pDst)->ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth);
+ ((struct data_section_compression_hdr *)pDst)->rsrvd = 0;
+ pDst++;
+ }
+
+ //Increment by IQ data len
+ pDst = (uint16_t *)((uint8_t *)pDst + n_bytes) ;
+ if(mb_oran_hdr_ext){
+ rte_pktmbuf_pkt_len(mb_oran_hdr_ext) = nPktSize;
+ rte_pktmbuf_data_len(mb_oran_hdr_ext) = nPktSize;
+ }
+
+ if(sectinfo->prbElemEnd) /* Transmit the packet */
+ {
+ if(likely((ecpri_hdr!=NULL)))
+ ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(ecpri_hdr->cmnhdr.bits.ecpri_payl_size);
+ else
+ print_err("ecpri_hdr should not be NULL\n");
+ /* if we don't need to do any fragmentation */
+ if (likely(p_xran_dev_ctx->fh_init.mtu >= (iq_sample_size_bytes)))
+ {
+ p_xran_dev_ctx->send_upmbuf2ring(mb_oran_hdr_ext, ETHER_TYPE_ECPRI, vf_id);
+ }
+ else
+ {
+ return 0;
+ }
+ elm_bytes += nPktSize;
+ } /* if(prbElemEnd) */
+ }/* section loop */
+ } /* if ptr_sect_elm->cur_index */
+ total_sections += num_sections;
+ } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */
+ } /* for(ant_id = 0; ant_id < num_eAxc; ant_id++) */
+
+ struct xran_common_counters* pCnt = &p_xran_dev_ctx->fh_counters;
+ pCnt->tx_counter += total_sections;
+ pCnt->tx_bytes_counter += elm_bytes;
+ return 1;
+}
+
+
int32_t xran_process_tx_sym(void *arg)
{
uint32_t mlogVar[15];
uint32_t mlogVarCnt = 0;
#endif
- unsigned long t1 = MLogTick();
+ unsigned long t1 = MLogXRANTick();
void *pHandle = NULL;
int32_t ant_id = 0;
int32_t cc_id = 0;
uint8_t num_eAxc = 0;
+ uint8_t num_eAxc_prach = 0;
uint8_t num_eAxAntElm = 0;
uint8_t num_CCPorts = 0;
uint32_t frame_id = 0;
uint32_t slot_id = 0;
uint32_t sym_id = 0;
uint32_t sym_idx = 0;
-
uint8_t ctx_id;
struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *) arg;
enum xran_in_period inPeriod;
subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
uint16_t sfnSecStart = xran_getSfnSecStart();
- if (unlikely(inPeriod == XRAN_IN_NEXT_PERIOD))
+ if(unlikely(inPeriod == XRAN_IN_NEXT_PERIOD))
{
// For DU
sfnSecStart = (sfnSecStart + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
}
- else if (unlikely(inPeriod == XRAN_IN_PREV_PERIOD))
+ else if(unlikely(inPeriod == XRAN_IN_PREV_PERIOD))
{
// For RU
if (sfnSecStart >= NUM_OF_FRAMES_PER_SECOND)
frame_id = (frame_id & 0xff);
sym_id = XranGetSymNum(sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT);
- ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME(interval)) % XRAN_MAX_SECTIONDB_CTX;
+ ctx_id = tti % XRAN_MAX_SECTIONDB_CTX;
print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id);
MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
#endif
- if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B) {
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU
+ && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B)
+ {
num_eAxc = xran_get_num_eAxcUl(pHandle);
- } else {
+ }
+ else
+ {
num_eAxc = xran_get_num_eAxc(pHandle);
}
+ num_eAxc_prach = ((num_eAxc > XRAN_MAX_PRACH_ANT_NUM)? XRAN_MAX_PRACH_ANT_NUM : num_eAxc);
num_CCPorts = xran_get_num_cc(pHandle);
/* U-Plane */
if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU && p_xran_dev_ctx->enableCP)
{
- if(p_xran_dev_ctx->tx_sym_gen_func) {
+ if(p_xran_dev_ctx->tx_sym_gen_func)
+ {
enum xran_comp_hdr_type compType;
- enum xran_pkt_dir direction;
- uint32_t prb_num, loc_ret = 1;
+ uint8_t loc_ret = 1;
uint16_t xran_port_id;
PSECTION_DB_TYPE p_sec_db = NULL;
compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
- if (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
- direction = XRAN_DIR_DL; /* O-DU */
- prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs;
- }
- else {
- direction = XRAN_DIR_UL; /* RU */
- prb_num = p_xran_dev_ctx->fh_cfg.nULRBs;
- }
-
- if (unlikely(p_xran_dev_ctx->xran_port_id > XRAN_PORTS_NUM)) {
+ if(unlikely(p_xran_dev_ctx->xran_port_id > XRAN_PORTS_NUM))
+ {
print_err("Invalid Port id - %d", p_xran_dev_ctx->xran_port_id);
loc_ret = 0;
}
- if (unlikely(ctx_id > XRAN_MAX_SECTIONDB_CTX)) {
+ if(unlikely(ctx_id > XRAN_MAX_SECTIONDB_CTX))
+ {
print_err("Invalid Context id - %d", ctx_id);
loc_ret = 0;
}
- if (unlikely(direction > XRAN_DIR_MAX)) {
- print_err("Invalid direction - %d", direction);
- loc_ret = 0;
- }
-
- if (unlikely(num_CCPorts > XRAN_COMPONENT_CARRIERS_MAX)) {
+ if(unlikely(num_CCPorts > XRAN_COMPONENT_CARRIERS_MAX))
+ {
print_err("Invalid CC id - %d", num_CCPorts);
loc_ret = 0;
}
- if (unlikely(num_eAxc > (XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR))) {
+ if(unlikely(num_eAxc > (XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR)))
+ {
print_err("Invalid eAxC id - %d", num_eAxc);
loc_ret = 0;
}
xran_port_id = p_xran_dev_ctx->xran_port_id;
- p_sec_db = p_sectiondb[p_xran_dev_ctx->xran_port_id];
+ p_sec_db = p_sectiondb[xran_port_id];
- if (loc_ret)
- {
- retval = p_xran_dev_ctx->tx_sym_gen_func(pHandle, ctx_id, tti, num_CCPorts, num_eAxc, frame_id, subframe_id, slot_id, sym_id,
- compType, direction, xran_port_id, p_sec_db);
+ if (loc_ret) {
+ p_xran_dev_ctx->tx_sym_gen_func(pHandle, ctx_id, tti,
+ 0, num_CCPorts, 0, num_eAxc, frame_id, subframe_id, slot_id, sym_id,
+ compType, XRAN_DIR_DL, xran_port_id, p_sec_db);
}
else
{
rte_panic("p_xran_dev_ctx->tx_sym_gen_func== NULL\n");
}
}
- else
+ else if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU && p_xran_dev_ctx->enableCP)
{
- for (ant_id = 0; ant_id < num_eAxc; ant_id++)
- {
- for (cc_id = 0; cc_id < num_CCPorts; cc_id++)
- {
- struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
+ if(first_call) {
+ enum xran_comp_hdr_type compType;
+ uint16_t xran_port_id;
+ PSECTION_DB_TYPE p_sec_db = NULL;
- if(p_xran_dev_ctx->puschMaskEnable)
- {
- if((tti % numSlotMu1 == p_xran_dev_ctx->puschMaskSlot))
- ;
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1
+ || xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1
+ || xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_FDD) == 1){
+
+ if(xran_fs_get_symbol_type(PortId, cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_UL
+ || xran_fs_get_symbol_type(PortId, cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD){
+
+ uint8_t loc_ret = 1;
+ compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+ if(unlikely(p_xran_dev_ctx->xran_port_id > XRAN_PORTS_NUM))
+ {
+ print_err("Invalid Port id - %d", p_xran_dev_ctx->xran_port_id);
+ loc_ret = 0;
+ }
+
+ if(unlikely(ctx_id > XRAN_MAX_SECTIONDB_CTX))
+ {
+ print_err("Invalid Context id - %d", ctx_id);
+ loc_ret = 0;
+ }
+
+ if(unlikely(num_CCPorts > XRAN_COMPONENT_CARRIERS_MAX))
+ {
+ print_err("Invalid CC id - %d", num_CCPorts);
+ loc_ret = 0;
+ }
+
+ if(unlikely(num_eAxc > (XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR)))
+ {
+ print_err("Invalid eAxC id - %d", num_eAxc);
+ loc_ret = 0;
+ }
+
+ xran_port_id = p_xran_dev_ctx->xran_port_id;
+ p_sec_db = p_sectiondb[xran_port_id];
+
+ if (loc_ret) {
+ xran_process_tx_sym_cp_on_opt(pHandle, ctx_id, tti,
+ 0, num_CCPorts, 0, num_eAxc, frame_id, subframe_id, slot_id, sym_id,
+ compType, XRAN_DIR_UL, xran_port_id, p_sec_db);
+ }
else
- retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0);
+ {
+ retval = 0;
+ }
}
- else
- retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0);
+ }
+
+ if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_B
+ && p_xran_dev_ctx->enableSrs
+ && ((p_xran_dev_ctx->srs_cfg.symbMask >> sym_id)&1))
+ {
+ xran_port_id = p_xran_dev_ctx->xran_port_id;
+ p_sec_db = p_sectiondb[xran_port_id];
+ compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType;
+ struct xran_srs_config *pSrsCfg = &(p_xran_dev_ctx->srs_cfg);
+ struct xran_prb_map *prb_map;
+ /* check special frame */
+ if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ {
+ if(((tti % p_xran_dev_ctx->fh_cfg.frame_conf.nTddPeriod) == pSrsCfg->slot)
+ && (p_xran_dev_ctx->ndm_srs_scheduled == 0))
+ {
- if(p_xran_dev_ctx->enableSrs && (p_srs_cfg->symbMask & (1 << sym_id)))
+ prb_map = (struct xran_prb_map *)p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][0].sBufferList.pBuffers->pData;
+ /* NDM U-Plane is not enabled */
+ if(pSrsCfg->ndm_offset == 0)
+ {
+ retval = xran_process_tx_srs_cp_on(pHandle, ctx_id, tti,
+ 0, num_CCPorts, 0, xran_get_num_ant_elm(pHandle), frame_id, subframe_id, slot_id, sym_id,
+ compType, XRAN_DIR_UL, xran_port_id, p_sec_db);
+ }
+ /* NDM U-Plane is enabled, SRS U-Planes will be transmitted after ndm_offset (in slots) */
+ else
+ {
+ p_xran_dev_ctx->ndm_srs_scheduled = 1;
+ p_xran_dev_ctx->ndm_srs_tti = tti;
+ p_xran_dev_ctx->ndm_srs_txtti = (tti + pSrsCfg->ndm_offset)%2000;
+ p_xran_dev_ctx->ndm_srs_schedperiod = pSrsCfg->slot;
+ }
+ }
+ }
+ /* check SRS NDM UP has been scheduled in non special slots */
+ else if(p_xran_dev_ctx->ndm_srs_scheduled
+ && p_xran_dev_ctx->ndm_srs_txtti == tti)
{
- retval = xran_process_tx_srs_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id);
+ prb_map = (struct xran_prb_map *)p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][0].sBufferList.pBuffers->pData;
+ xran_port_id = p_xran_dev_ctx->xran_port_id;
+ p_sec_db = p_sectiondb[xran_port_id];
+ int ndm_step;
+ uint32_t srs_tti, srsFrame, srsSubframe, srsSlot, srs_sym;
+ uint8_t srsCtx;
+ if(prb_map && prb_map->nPrbElm)
+ {
+ srs_sym = prb_map->prbMap[0].nStartSymb;
+
+ srs_tti = p_xran_dev_ctx->ndm_srs_tti;
+ num_eAxAntElm = xran_get_num_ant_elm(pHandle);
+ ndm_step = num_eAxAntElm / pSrsCfg->ndm_txduration;
+
+ srsSlot = XranGetSlotNum(srs_tti, SLOTNUM_PER_SUBFRAME(interval));
+ srsSubframe = XranGetSubFrameNum(srs_tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
+ srsFrame = XranGetFrameNum(srs_tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
+ srsFrame = (srsFrame & 0xff);
+ srsCtx = srs_tti % XRAN_MAX_SECTIONDB_CTX;
+
+ if(sym_id < pSrsCfg->ndm_txduration)
+ {
+ retval = xran_process_tx_srs_cp_on(pHandle, srsCtx, srs_tti,
+ 0, num_CCPorts, sym_id*ndm_step, ndm_step, srsFrame, srsSubframe, srsSlot, srs_sym,
+ compType, XRAN_DIR_UL, xran_port_id, p_sec_db);
+ }
+ else
+ {
+ p_xran_dev_ctx->ndm_srs_scheduled = 0;
+ p_xran_dev_ctx->ndm_srs_tti = 0;
+ p_xran_dev_ctx->ndm_srs_txtti = 0;
+ p_xran_dev_ctx->ndm_srs_schedperiod = 0;
+ }
+ }
}
}
}
}
+ else {
+ if(first_call) {
+ for (ant_id = 0; ant_id < num_eAxc; ant_id++)
+ {
+ for (cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ //struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
+ if(p_xran_dev_ctx->puschMaskEnable)
+ {
+ if((tti % numSlotMu1) != p_xran_dev_ctx->puschMaskSlot)
+ retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0);
+ }
+ else
+ retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0);
+
+ if(p_xran_dev_ctx->enablePrach && (ant_id < num_eAxc_prach) )
+ {
+ retval = xran_process_tx_prach_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id);
+ }
+ }
+ }
+
+ if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_B
+ && p_xran_dev_ctx->enableSrs
+ && ((p_xran_dev_ctx->srs_cfg.symbMask >> sym_id)&1))
+ {
+ struct xran_srs_config *pSrsCfg = &(p_xran_dev_ctx->srs_cfg);
+
+ for(cc_id = 0; cc_id < num_CCPorts; cc_id++)
+ {
+ /* check special frame */
+ if((xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1)
+ ||(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1))
+ {
+ if(((tti % p_xran_dev_ctx->fh_cfg.frame_conf.nTddPeriod) == pSrsCfg->slot)
+ && (p_xran_dev_ctx->ndm_srs_scheduled == 0))
+ {
+ int elmIdx;
+ struct xran_prb_map *prb_map;
+ prb_map = (struct xran_prb_map *)p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][0].sBufferList.pBuffers->pData;
- if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU && p_xran_dev_ctx->enableSrs && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B) {
- num_eAxAntElm = xran_get_num_ant_elm(pHandle);
- struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
- for(num_eAxc = 0; ant_id < num_eAxAntElm; ant_id++) {
- for(cc_id = 0; cc_id < num_CCPorts; cc_id++) {
- if( p_srs_cfg->symbMask & (1 << sym_id)) {
- retval = xran_process_tx_srs_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id);
+ /* if PRB map is present in first antenna, assume SRS might be scheduled. */
+ if(prb_map && prb_map->nPrbElm)
+ {
+ /* NDM U-Plane is not enabled */
+ if(pSrsCfg->ndm_offset == 0)
+ {
+
+ if (prb_map->nPrbElm > 0)
+ {
+ if(sym_id >= prb_map->prbMap[0].nStartSymb
+ && sym_id < (prb_map->prbMap[0].nStartSymb + prb_map->prbMap[0].numSymb))
+ for(ant_id=0; ant_id < xran_get_num_ant_elm(pHandle); ant_id++)
+ xran_process_tx_srs_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id);
+ }
+
+ }
+ /* NDM U-Plane is enabled, SRS U-Planes will be transmitted after ndm_offset (in slots) */
+ else
+ {
+ p_xran_dev_ctx->ndm_srs_scheduled = 1;
+ p_xran_dev_ctx->ndm_srs_tti = tti;
+ p_xran_dev_ctx->ndm_srs_txtti = (tti + pSrsCfg->ndm_offset)%2000;
+ p_xran_dev_ctx->ndm_srs_schedperiod = pSrsCfg->slot;
+ }
+ }
+ }
+ }
+ /* check SRS NDM UP has been scheduled in non special slots */
+ /*NDM feature enables the spread of SRS packets
+ Non delay measurement SRS PDSCH PUSCH delay measure it*/
+ else if(p_xran_dev_ctx->ndm_srs_scheduled
+ && p_xran_dev_ctx->ndm_srs_txtti == tti)
+ {
+ int ndm_step;
+ uint32_t srs_tti, srsFrame, srsSubframe, srsSlot;
+ uint8_t srsCtx;
+
+ srs_tti = p_xran_dev_ctx->ndm_srs_tti;
+ num_eAxAntElm = xran_get_num_ant_elm(pHandle);
+ ndm_step = num_eAxAntElm / pSrsCfg->ndm_txduration;
+
+ srsSlot = XranGetSlotNum(srs_tti, SLOTNUM_PER_SUBFRAME(interval));
+ srsSubframe = XranGetSubFrameNum(srs_tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME);
+ srsFrame = XranGetFrameNum(srs_tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval));
+ srsFrame = (srsFrame & 0xff);
+ srsCtx = srs_tti % XRAN_MAX_SECTIONDB_CTX;
+
+ if(sym_id < pSrsCfg->ndm_txduration)
+ {
+ for(ant_id=sym_id*ndm_step; ant_id < (sym_id+1)*ndm_step; ant_id++)
+ xran_process_tx_srs_cp_off(pHandle, srsCtx, srs_tti, cc_id, ant_id, srsFrame, srsSubframe, srsSlot);
+ }
+ else
+ {
+ p_xran_dev_ctx->ndm_srs_scheduled = 0;
+ p_xran_dev_ctx->ndm_srs_tti = 0;
+ p_xran_dev_ctx->ndm_srs_txtti = 0;
+ p_xran_dev_ctx->ndm_srs_schedperiod = 0;
+ }
+ }
}
}
}
}
- MLogTask(PID_DISPATCH_TX_SYM, t1, MLogTick());
+ MLogXRANTask(PID_DISPATCH_TX_SYM, t1, MLogXRANTick());
return retval;
}
void *pHandle;
uint8_t ctx_id;
uint32_t tti;
- int32_t cc_id;
- int32_t ant_id;
+ int32_t start_cc;
+ int32_t cc_num;
+ int32_t start_ant;
+ int32_t ant_num;
uint32_t frame_id;
uint32_t subframe_id;
uint32_t slot_id;
int32_t xran_pkt_gen_desc_free(struct cp_up_tx_desc *p_desc);
uint16_t xran_getSfnSecStart(void);
-int32_t xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
+int32_t xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t cc_id, int32_t start_ant, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
uint32_t slot_id, uint32_t sym_id);
-int32_t xran_process_tx_sym_cp_on(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
+int32_t xran_process_tx_sym_cp_on(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t cc_id, int32_t start_ant, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
uint32_t slot_id, uint32_t sym_id);
-int32_t xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
+int32_t xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t cc_id, int32_t start_ant, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
uint32_t slot_id, uint32_t sym_id);
-int32_t xran_process_tx_sym_cp_on_dispatch_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id,
+int32_t xran_process_tx_sym_cp_on_dispatch_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
+ uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
+ uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db);
+
+int32_t xran_process_tx_sym_cp_on_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
+ uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
+ uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db);
+
+int32_t xran_process_tx_sym_cp_on_ring(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t start_cc, int32_t num_cc, int32_t start_ant, int32_t num_ant, uint32_t frame_id,
uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction,
uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db);
-int32_t xran_process_tx_sym_cp_on_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id, uint32_t subframe_id,
- uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction, uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db);
extern int rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr* mac_addr);
extern PSECTION_DB_TYPE p_sectiondb[XRAN_PORTS_NUM];
#include "xran_mlog_lnx.h"
#include "xran_common.h"
+
+#if 0
/**
* @brief Builds eCPRI header in xRAN packet
*
return 0;
}
+#endif
/**
* @brief Builds eCPRI header in xRAN packet
*
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
struct xran_ecpri_hdr *ecpri_hdr = (struct xran_ecpri_hdr *)(pChar + sizeof(struct rte_ether_hdr));
+
uint16_t ecpri_payl_size = payl_size
- + sizeof(struct data_section_hdr)
+ sizeof(struct radio_app_common_hdr)
+ XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size();
- if ((comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
- ecpri_payl_size += sizeof(struct data_section_compression_hdr);
if (NULL == ecpri_hdr)
return 1;
*
* @param mbuf Initialized rte_mbuf packet
* @param sec_hdr Section header structure to be set in mbuf packet
+ * @param offset Offset to create the section header
* @return int 0 on success, non zero on failure
*/
static inline int build_section_hdr(
struct rte_mbuf *mbuf,
- const struct data_section_hdr *sec_hdr)
+ const struct data_section_hdr *sec_hdr,
+ uint32_t offset)
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
- struct data_section_hdr *section_hdr = (struct data_section_hdr *)
- (pChar + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr));
+ struct data_section_hdr *section_hdr = (struct data_section_hdr *)(pChar + offset);
if (NULL == section_hdr)
return 1;
- memcpy(section_hdr, sec_hdr, sizeof(struct data_section_hdr));
+ memcpy(section_hdr, &sec_hdr->fields.all_bits, sizeof(struct data_section_hdr));
return 0;
}
+
+#if 0
/**
* @brief Function for appending IQ samples data to the mbuf.
*
return iq_bytes_to_send;
}
+#endif
/**
* @brief Builds compression header in xRAN packet
* @param mbuf Initialized rte_mbuf packet
* @param compression_hdr Section compression header structure
* to be set in mbuf packet
+ * @param offset mbuf data offset to create compression header
* @return int 0 on success, non zero on failure
*/
static inline int build_compression_hdr(
struct rte_mbuf *mbuf,
- const struct data_section_compression_hdr *compr_hdr)
+ const struct data_section_compression_hdr *compr_hdr,
+ uint32_t offset)
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
- struct data_section_compression_hdr *compression_hdr = (struct data_section_compression_hdr *)
- (pChar + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr)
- + sizeof(struct data_section_hdr));
+ struct data_section_compression_hdr *compression_hdr =
+ (struct data_section_compression_hdr *)(pChar + offset);
if (NULL == compression_hdr)
return 1;
return 0;
}
+#if 0
/**
* @brief Appends compression parameter in xRAN packet
*
return 0;
}
-
+#endif
/**
* @brief Function for extracting all IQ samples from xRAN packet
* holding a single data section
* @param iq_data_offset IQ data bytes already sent.
* @param alignment Size of IQ data alignment.
* @param pkt_gen_params Struct with parameters used for building packet
+ * @param num_sections Number of data sections to be created
* @return int Number of bytes that have been appended
to the packet within all appended sections.
*/
uint8_t Ant_ID,
uint8_t seq_id,
enum xran_comp_hdr_type staticEn,
- uint32_t do_copy)
+ uint32_t do_copy,
+ uint16_t num_sections,
+ uint16_t section_id_start,
+ uint16_t iq_offset)
{
- int offset;
+ uint32_t offset=0 , ret_val=0;
+ uint16_t idx , iq_len=0;
+ const void *iq_data;
+ uint16_t iq_n_section_size; //All data_section + compression hdrs + iq
+
+ iq_n_section_size = iq_data_num_bytes + num_sections*sizeof(struct data_section_hdr);
+
+ if ((params[0].compr_hdr_param.ud_comp_hdr.ud_comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
+{
+ iq_n_section_size += num_sections*sizeof(struct data_section_compression_hdr);
+ }
if(xran_build_ecpri_hdr_ex(mbuf,
ECPRI_IQ_DATA,
- iq_data_num_bytes,
+ (int)iq_n_section_size,
CC_ID,
Ant_ID,
seq_id,
- params->compr_hdr_param.ud_comp_hdr.ud_comp_meth,
+ params[0].compr_hdr_param.ud_comp_hdr.ud_comp_meth,
staticEn)){
print_err("xran_build_ecpri_hdr_ex return 0\n");
return 0;
}
- if (build_application_layer(mbuf, &(params->app_params)) != 0){
+ if (build_application_layer(mbuf, &(params[0].app_params)) != 0){
print_err("build_application_layer return != 0\n");
return 0;
}
- if (build_section_hdr(mbuf, &(params->sec_hdr)) != 0){
+ offset = sizeof(struct rte_ether_hdr)
+ + sizeof(struct xran_ecpri_hdr)
+ + sizeof(struct radio_app_common_hdr);
+ for(idx=0 ; idx < num_sections ; idx++)
+ {
+ if (build_section_hdr(mbuf, &(params[idx].sec_hdr),offset) != 0){
print_err("build_section_hdr return != 0\n");
return 0;
}
-
- offset = sizeof(struct rte_ether_hdr)
- + sizeof(struct xran_ecpri_hdr)
- + sizeof(struct radio_app_common_hdr)
- + sizeof(struct data_section_hdr);
- if ((params->compr_hdr_param.ud_comp_hdr.ud_comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) {
- if (build_compression_hdr(mbuf, &(params->compr_hdr_param)) !=0)
+ offset += sizeof(struct data_section_hdr);
+ if ((params[idx].compr_hdr_param.ud_comp_hdr.ud_comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) {
+ if (build_compression_hdr(mbuf, &(params[idx].compr_hdr_param),offset) !=0)
return 0;
+
offset += sizeof(struct data_section_compression_hdr);
}
- return (do_copy ? append_iq_samples_ex(mbuf, offset, iq_data_start, iq_data_num_bytes, iq_buf_byte_order, do_copy) : iq_data_num_bytes);
+
+ /** IQ buffer contains space for data section/compression hdr in case of multiple sections.*/
+ iq_data = (const void *)((uint8_t *)iq_data_start
+ + idx*(sizeof(struct data_section_hdr) + iq_data_num_bytes/num_sections));
+
+ if ((params[idx].compr_hdr_param.ud_comp_hdr.ud_comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC))
+ iq_data = (const void *)((uint8_t *)iq_data + idx*sizeof(struct data_section_compression_hdr));
+
+ //ret_val = (do_copy ? append_iq_samples_ex(mbuf, offset, iq_data_start, iq_data_num_bytes/num_sections, iq_buf_byte_order, do_copy) : iq_data_num_bytes/num_sections);
+ ret_val = iq_data_num_bytes/num_sections;
+
+ if(!ret_val)
+ return ret_val;
+
+ iq_len += ret_val;
+ offset += ret_val;
+ }
+ return iq_len;
}
/*******************************************************************************
*
- * Copyright (c) 2020 Intel.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
+ * <COPYRIGHT_TAG>
*
*******************************************************************************/
parallelization_factor = factor;
}
+ /*!
+ \brief Run the given function and return the mean run time and stddev.
+ \param [in] function Function to benchmark.
+ \param [in] args Function's arguments.
+ \return std::pair where the first element is mean and the second one is standard deviation.
+ */
+ template <typename F, typename ... Args>
+ std::pair<double, double> run_benchmark(F function, Args ... args)
+ {
+ std::vector<long> results((unsigned long) BenchmarkParameters::repetition);
+
+ for(unsigned int outer_loop = 0; outer_loop < BenchmarkParameters::repetition; outer_loop++) {
+ const auto start_time = __rdtsc();
+ for (unsigned int inner_loop = 0; inner_loop < BenchmarkParameters::loop; inner_loop++) {
+ function(args ...);
+ }
+ const auto end_time = __rdtsc();
+ results.push_back(end_time - start_time);
+ }
+
+ return calculate_statistics(results);
+ };
+
/*!
\brief Run performance test case for a given function.
\param [in] isa Used Instruction Set.
const double stddev);
};
-/*!
- \brief Run the given function and return the mean run time and stddev.
- \param [in] function Function to benchmark.
- \param [in] args Function's arguments.
- \return std::pair where the first element is mean and the second one is standard deviation.
-*/
-template <typename F, typename ... Args>
-std::pair<double, double> run_benchmark(F function, Args ... args)
-{
- std::vector<long> results((unsigned long) BenchmarkParameters::repetition);
-
- for(unsigned int outer_loop = 0; outer_loop < BenchmarkParameters::repetition; outer_loop++) {
- const auto start_time = __rdtsc();
- for (unsigned int inner_loop = 0; inner_loop < BenchmarkParameters::loop; inner_loop++) {
- function(args ...);
- }
- const auto end_time = __rdtsc();
- results.push_back(end_time - start_time);
- }
-
- return calculate_statistics(results);
-};
-
/*!
\brief Assert elements of two arrays. It calls ASSERT_EQ for each element of the array.
\param [in] reference Array with reference values.
\param [in] size Size of the array.
*/
template <typename T>
-void assert_array_eq(const T* reference, const T* actual, const int size)
+inline void assert_array_eq(const T* reference, const T* actual, const int size)
{
for(int index = 0; index < size ; index++)
{
\param [in] precision Precision fo the comparision used by ASSERT_NEAR.
*/
template <typename T>
-void assert_array_near(const T* reference, const T* actual, const int size, const double precision)
+inline void assert_array_near(const T* reference, const T* actual, const int size, const double precision)
{
for(int index = 0; index < size ; index++)
{
}
template <>
-void assert_array_near<complex_float>(const complex_float* reference, const complex_float* actual, const int size, const double precision)
+inline void assert_array_near<complex_float>(const complex_float* reference, const complex_float* actual, const int size, const double precision)
{
for(int index = 0; index < size ; index++)
{
\param [in] precision Precision for the comparison used by ASSERT_GT.
*/
template<typename T>
-void assert_avg_greater_complex(const T* reference, const T* actual, const int size, const double precision)
+inline void assert_avg_greater_complex(const T* reference, const T* actual, const int size, const double precision)
{
float mseDB, MSE;
double avgMSEDB = 0.0;
\return Pointer to the allocated memory.
*/
template <typename T>
-T* aligned_malloc(const int size, const unsigned alignment)
+inline T* aligned_malloc(const int size, const unsigned alignment)
{
#ifdef _BBLIB_DPDK_
return (T*) rte_malloc(NULL, sizeof(T) * size, alignment);
\param [in] ptr Pointer to the allocated memory.
*/
template <typename T>
-void aligned_free(T* ptr)
+inline void aligned_free(T* ptr)
{
#ifdef _BBLIB_DPDK_
rte_free((void*)ptr);
\return Pointer to the allocated memory with random data.
*/
template <typename T, typename U>
-T* generate_random_numbers(const long size, const unsigned alignment, U& distribution)
+inline T* generate_random_numbers(const long size, const unsigned alignment, U& distribution)
{
auto array = (T*) aligned_malloc<char>(size * sizeof(T), alignment);
\return Pointer to the allocated memory with random data.
*/
template <typename T>
-T* generate_random_data(const long size, const unsigned alignment)
+inline T* generate_random_data(const long size, const unsigned alignment)
{
std::uniform_int_distribution<> random(0, 255);
\return Pointer to the allocated memory with random data.
*/
template <typename T>
-T* generate_random_int_numbers(const long size, const unsigned alignment, const T lo_range,
+inline T* generate_random_int_numbers(const long size, const unsigned alignment, const T lo_range,
const T up_range)
{
std::uniform_int_distribution<T> random(lo_range, up_range);
\return Pointer to the allocated memory with random data.
*/
template <typename T>
-T* generate_random_real_numbers(const long size, const unsigned alignment, const T lo_range,
+inline T* generate_random_real_numbers(const long size, const unsigned alignment, const T lo_range,
const T up_range)
{
std::uniform_real_distribution<T> distribution(lo_range, up_range);
// include at least decoding support for them even without such
// support. An example of a small decoder for half-precision
// floating-point numbers in the C language is shown in Fig. 3.
- const int half = (v.at(current_idx + 1) << 8) + v.at(current_idx + 2);
- const int exp = (half >> 10) & 0x1f;
- const int mant = half & 0x3ff;
+ const int int16_t = (v.at(current_idx + 1) << 8) + v.at(current_idx + 2);
+ const int exp = (int16_t >> 10) & 0x1f;
+ const int mant = int16_t & 0x3ff;
double val;
if (exp == 0)
{
? std::numeric_limits<double>::infinity()
: std::numeric_limits<double>::quiet_NaN();
}
- return (half & 0x8000) != 0 ? -val : val;
+ return (int16_t & 0x8000) != 0 ? -val : val;
}
case 0xfa: // Single-Precision Float (four-byte IEEE 754)
/*******************************************************************************
*
- * Copyright (c) 2020 Intel.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
+ * <COPYRIGHT_TAG>
*
*******************************************************************************/
#include "common.hpp"
#include "xran_fh_o_du.h"
+#include "xran_fh_o_ru.h"
#include "xran_common.h"
#include "xran_frame_struct.h"
XRANFTHTX_SEC_DESC_OUT,
XRANFTHRX_IN,
XRANFTHRX_PRB_MAP_IN,
+ XRANCP_PRB_MAP_IN_RX,
+ XRANCP_PRB_MAP_IN_TX,
XRANFTHTX_SEC_DESC_IN,
XRANFTHRACH_IN,
MAX_SW_XRAN_INTERFACE_NUM
struct xran_io_buf_ctrl sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
struct xran_io_buf_ctrl sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
+ struct xran_io_buf_ctrl sFHCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ struct xran_io_buf_ctrl sFHCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
/* buffers lists */
struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ struct xran_flat_buffer sFrontHaulCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ struct xran_flat_buffer sFrontHaulCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
/* Cat B SRS buffers */
struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
int init_memory(uint32_t o_xu_id)
{
xran_status_t status;
- int32_t i, j, k, z, m;
+ uint32_t i, j, k, z, m;
SWXRANInterfaceTypeEnum eInterfaceType;
void *ptr;
void *mb;
struct bbu_xran_io_if *psBbuIo = (struct bbu_xran_io_if*)&m_gsXranIoIf;
struct xran_io_shared_ctrl *psIoCtrl = (struct xran_io_shared_ctrl *)&psBbuIo->ioCtrl[o_xu_id];
- uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul());
- uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr);
+ uint32_t xran_max_antenna_nr = (uint32_t)RTE_MAX((uint32_t)get_num_eaxc(), (uint32_t)get_num_eaxc_ul());
+ uint32_t xran_max_ant_array_elm_nr = (uint32_t)RTE_MAX((uint32_t)get_num_antelmtrx(), (uint32_t)xran_max_antenna_nr);
std::cout << "XRAN front haul xran_mm_init" << std::endl;
/* initialize maximum instances to have flexibility for the tests */
/* initialize maximum supported CC to have flexibility on the test */
- int32_t nSectorNum = 6;//XRAN_MAX_SECTOR_NR;
+ uint32_t nSectorNum = 6;//XRAN_MAX_SECTOR_NR;
k = o_xu_id;
psBbuIo->nInstanceNum[k] = nSectorNum;
}
/* C-plane DL */
- eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],
- &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SLOT*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc));
- if(XRAN_STATUS_SUCCESS != status) {
- std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
- return (-1);
- }
eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],
&psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],
}
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
- void *sd_ptr;
- void *sd_mb;
- int elm_id;
+
struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
//memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map));
- for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SLOT; elm_id++){
- struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
- for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
- for(m = 0; m < XRAN_MAX_FRAGMENT; m++){
- status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT], &sd_ptr, &sd_mb);
+ }
+ }
+ /* C-plane */
+ eInterfaceType = XRANCP_PRB_MAP_IN_RX;
+ status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],
+ &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ sizeof(struct xran_prb_map));
if(XRAN_STATUS_SUCCESS != status){
- std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;
- return (-1);
+ rte_panic("Failed at xran_bm_init, status %d\n", status);
}
- pPrbElem->p_sec_desc[k][m] = (struct xran_section_desc *)sd_ptr;
+
+ for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
+ for(z = 0; z < xran_max_antenna_nr; z++){
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulCpRxPrbMapBbuIoBufCtrl[j][i][z];
+
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
+ status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
+ if(XRAN_STATUS_SUCCESS != status) {
+ rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
}
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
+ psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
+ struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
}
}
+
+
+ /* C-plane Tx */
+ eInterfaceType = XRANCP_PRB_MAP_IN_TX;
+ status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],
+ &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ sizeof(struct xran_prb_map));
+ if(XRAN_STATUS_SUCCESS != status) {
+ rte_panic("Failed at xran_bm_init, status %d\n", status);
+ }
+
+ for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
+ for(z = 0; z < xran_max_antenna_nr; z++){
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulCpTxPrbMapBbuIoBufCtrl[j][i][z];
+
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
+ status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],&ptr, &mb);
+ if(XRAN_STATUS_SUCCESS != status) {
+ rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
+ }
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
+ psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
+ struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
}
}
}
}
}
- eInterfaceType = XRANFTHTX_SEC_DESC_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],
- &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SLOT*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc));
- if(XRAN_STATUS_SUCCESS != status) {
- std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
- return (-1);
- }
eInterfaceType = XRANFTHRX_PRB_MAP_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i],
&psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],
}
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
- void *sd_ptr;
- void *sd_mb;
- int elm_id;
struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
//memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map));
- for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SLOT; elm_id++){
- struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
- for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
- for(m = 0; m < XRAN_MAX_FRAGMENT; m++){
- status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN], &sd_ptr, &sd_mb);
- if(XRAN_STATUS_SUCCESS != status){
- std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;
- return (-1);
- }
- pPrbElem->p_sec_desc[k][m] = (struct xran_section_desc *)sd_ptr;
- }
- }
- }
}
}
}
m_xranInit.eAxCId_conf.mask_ruPortId = get_eaxcid_mask(bitnum_ruport, m_xranInit.eAxCId_conf.bit_ruPortId);
m_xranInit.totalBfWeights = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "totalBfWeights");
- m_xranInit.filePrefix = "wls";
+ m_xranInit.filePrefix = (char *)"wls";
m_bSub6 = get_globalcfg<bool>(XRAN_UT_KEY_GLOBALCFG_RU, "sub6");
std::stringstream slotcfgname;
slotcfgname << "slot" << i;
std::vector<int> slotcfg = get_globalcfg_array<int>(slotcfg_key, slotcfgname.str());
- for(int j=0; j < slotcfg.size(); j++) {
+ for(int j=0; j < (int)slotcfg.size(); j++) {
m_xranConf.frame_conf.sSlotConfig[i].nSymbolType[j] = slotcfg[j];
}
m_xranConf.frame_conf.sSlotConfig[i].reserved[0] = 0;
int Init(uint32_t o_xu_id, struct xran_fh_config *pCfg = nullptr)
{
xran_status_t status;
- int32_t nSectorNum;
+ uint32_t nSectorNum;
int32_t i, j, k, z;
void *ptr;
void *mb;
uint16_t *u16dptr;
uint8_t *u8dptr;
SWXRANInterfaceTypeEnum eInterfaceType;
- int32_t cc_id, ant_id, sym_id, tti;
+ uint32_t cc_id, ant_id, sym_id, tti;
int32_t flowId;
char *pos = NULL;
struct xran_prb_map *pRbMap = NULL;
+ struct xran_prb_map tmppRbMap;
struct bbu_xran_io_if *psBbuIo = (struct bbu_xran_io_if*)&m_gsXranIoIf;
struct xran_io_shared_ctrl *psIoCtrl = (struct xran_io_shared_ctrl *)&psBbuIo->ioCtrl[o_xu_id];
iq_bfw_buffer_size_dl = (m_nSlots * N_SYM_PER_SLOT * get_num_antelmtrx() * get_num_dlrbs() * 4L);
iq_bfw_buffer_size_ul = (m_nSlots * N_SYM_PER_SLOT * get_num_antelmtrx() * get_num_ulrbs() * 4L);
- for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(get_num_cc() * get_num_eaxc()); i++) {
+ for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (get_num_cc() * get_num_eaxc()); i++) {
p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl);
tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl;
if(p_tx_dl_bfw_buffer[i] == NULL)
int iPrb;
char *dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
struct xran_prb_elm* p_prbMap = NULL;
- int num_antelm;
+ // int num_antelm;
pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;
pRbMap->prbMap[0].bf_weight_update = 1;
- num_antelm = get_num_antelmtrx();
+ // num_antelm = get_num_antelmtrx();
#if 0
/* populate beam weights to C-plane for each elm */
pRbMap->bf_weight.nAntElmTRx = num_antelm;
}
#endif
} /* else if(get_rucategory() == XRAN_CATEGORY_B) */
+ memcpy(&tmppRbMap, pRbMap, sizeof(struct xran_prb_map));
+ xran_init_PrbMap_from_cfg(&tmppRbMap, pRbMap, m_xranInit.mtu);
} /* if(pRbMap) */
else {
std::cout << "DL pRbMap ==NULL" << std::endl;
}
+ if(get_rucategory() == XRAN_CATEGORY_B){
+ pRbMap = (struct xran_prb_map *)psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap) {
+ pRbMap->dir = XRAN_DIR_DL;
+ pRbMap->xran_port = 0;
+ pRbMap->band_id = 0;
+ pRbMap->cc_id = cc_id;
+ pRbMap->ru_port_id = ant_id;
+ pRbMap->tti_id = tti;
+ pRbMap->start_sym_id = 0;
+
+ pRbMap->nPrbElm = 1;
+ pRbMap->prbMap[0].nRBStart = 0;
+ pRbMap->prbMap[0].nRBSize = get_num_dlrbs();
+ pRbMap->prbMap[0].nStartSymb = 0;
+ pRbMap->prbMap[0].numSymb = 14;
+ pRbMap->prbMap[0].nBeamIndex = 0;
+ pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
+ uint32_t idxElm;
+ int iPrb;
+ char *dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
+ struct xran_prb_elm* p_prbMap = NULL;
+ int num_antelm;
+
+ pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;
+ pRbMap->prbMap[0].bf_weight_update = 1;
+
+ num_antelm = get_num_antelmtrx();
+#if 1
+ /* populate beam weights to C-plane for each elm */
+ // pRbMap->bf_weight.nAntElmTRx = num_antelm;
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
+ p_prbMap = &pRbMap->prbMap[idxElm];
+ for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++) {
+ /* copy BF W IQs for 1 PRB of */
+ p_prbMap->bf_weight.nAntElmTRx = num_antelm;
+ // memcpy(&p_prbMap->bf_weight.p_ext_section[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4);
+ }
+ }
+#endif
+ } /* if(pRbMap) */
+ else {
+ std::cout << "Cp DL pRbMap ==NULL" << std::endl;
+ }
+
+ pRbMap = (struct xran_prb_map *)psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
+ if(pRbMap) {
+ pRbMap->dir = XRAN_DIR_DL;
+ pRbMap->xran_port = 0;
+ pRbMap->band_id = 0;
+ pRbMap->cc_id = cc_id;
+ pRbMap->ru_port_id = ant_id;
+ pRbMap->tti_id = tti;
+ pRbMap->start_sym_id = 0;
+
+ pRbMap->nPrbElm = 1;
+ pRbMap->prbMap[0].nRBStart = 0;
+ pRbMap->prbMap[0].nRBSize = get_num_dlrbs();
+ pRbMap->prbMap[0].nStartSymb = 0;
+ pRbMap->prbMap[0].numSymb = 14;
+ pRbMap->prbMap[0].nBeamIndex = 0;
+ pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
+ int idxElm;
+ int iPrb;
+ char *dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
+ struct xran_prb_elm* p_prbMap = NULL;
+ // int num_antelm;
+
+ pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;
+ pRbMap->prbMap[0].bf_weight_update = 1;
+
+ // num_antelm = get_num_antelmtrx();
+#if 0
+ /* populate beam weights to C-plane for each elm */
+ pRbMap->bf_weight.nAntElmTRx = num_antelm;
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
+ p_prbMap = &pRbMap->prbMap[idxElm];
+ for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++) {
+ /* copy BF W IQs for 1 PRB of */
+ memcpy(&pRbMap->bf_weight.weight[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4);
+ }
+ }
+#endif
+ } /* if(pRbMap) */
+ else {
+ std::cout << "Cp UL pRbMap ==NULL" << std::endl;
+ }
+ }
+
+
/* C-plane UL */
pRbMap = (struct xran_prb_map *)psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
if(pRbMap) {
int iPrb;
char *ul_bfw_pos = ((char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId];
struct xran_prb_elm* p_prbMap = NULL;
- int num_antelm;
+ // int num_antelm;
pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;
pRbMap->prbMap[0].bf_weight_update = 1;
- num_antelm = get_num_antelmtrx();
+ // num_antelm = get_num_antelmtrx();
#if 0
/* populate beam weights to C-plane for each elm */
pRbMap->bf_weight.nAntElmTRx = num_antelm;
}
#endif
} /* else if(get_rucategory() == XRAN_CATEGORY_B) */
-
+ memcpy(&tmppRbMap, pRbMap, sizeof(struct xran_prb_map));
+ xran_init_PrbMap_from_cfg(&tmppRbMap, pRbMap, m_xranInit.mtu);
} /* if(pRbMap) */
else {
std::cout << "UL: pRbMap ==NULL" << std::endl;
int i;
if(get_rucategory() == XRAN_CATEGORY_B) {
- for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(get_num_cc() * get_num_eaxc()); i++) {
+ for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (get_num_cc() * get_num_eaxc()); i++) {
if(p_tx_dl_bfw_buffer[i]) {
free(p_tx_dl_bfw_buffer[i]);
- p_tx_dl_bfw_buffer[i] == NULL;
+ p_tx_dl_bfw_buffer[i] = NULL;
}
if(p_tx_ul_bfw_buffer[i]) {
free(p_tx_ul_bfw_buffer[i]);
- p_tx_ul_bfw_buffer[i] == NULL;
+ p_tx_ul_bfw_buffer[i] = NULL;
}
}
}
void Open(uint32_t o_xu_id, xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up,
- void *fh_rx_callback, void *fh_rx_prach_callback, void *fh_srs_callback)
+ void *fh_rx_callback, void *fh_bfw_callback, void *fh_rx_prach_callback, void *fh_srs_callback)
{
struct xran_fh_config *pXranConf;
int32_t nSectorNum;
struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
struct xran_buffer_list *pFthRxSrsPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
+ struct xran_buffer_list *pFthRxCpPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
+ struct xran_buffer_list *pFthTxCpPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
+
#if 0
xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
xran_reg_physide_cb(xranHandle, physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);
pFthRxPrbMapBuffer[i][z][j] = NULL;
pFthRxRachBuffer[i][z][j] = NULL;
pFthRxRachBufferDecomp[i][z][j] = NULL;
+ pFthRxCpPrbMapBuffer[i][z][j] = NULL;
+ pFthTxCpPrbMapBuffer[i][z][j] = NULL;
}
for(z = 0; z < /*xran_max_ant_array_elm_nr*/XRAN_MAX_ANT_ARRAY_ELM_NR; z++) {
pFthRxSrsBuffer[i][z][j] = NULL;
pFthRxPrbMapBuffer[i][z][j] = &(psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxRachBuffer[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxRachBufferDecomp[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList);
+ pFthRxCpPrbMapBuffer[i][z][j] = &(psIoCtrl->sFHCpRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
+ pFthTxCpPrbMapBuffer[i][z][j] = &(psIoCtrl->sFHCpTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
}
for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR /*xran_max_ant_array_elm_nr && xran_max_ant_array_elm_nr*/; z++) {
pFthRxSrsBuffer[i][z][j] = &(psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList);
pFthTxBuffer[i], pFthTxPrbMapBuffer[i],
pFthRxBuffer[i], pFthRxPrbMapBuffer[i],
(void (*)(void *, xran_status_t))fh_rx_callback, &pFthRxBuffer[i][0]);
+
+ xran_5g_bfw_config(psBbuIo->nInstanceHandle[o_xu_id][i],
+ pFthRxCpPrbMapBuffer[i],
+ pFthTxCpPrbMapBuffer[i],
+ (void (*)(void *, xran_status_t))fh_bfw_callback, &pFthRxCpPrbMapBuffer[i][0]);
+
xran_5g_prach_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxRachBuffer[i],pFthRxRachBufferDecomp[i],
(void (*)(void *, xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i]);
}
slotcfgname << "slot" << i;
std::vector<int> slotcfg = get_globalcfg_array<int>(cfgname, slotcfgname.str());
- for(j=0; j < slotcfg.size(); j++)
+ for(j=0; j < (int)slotcfg.size(); j++)
pCfg->sSlotConfig[i].nSymbolType[j] = slotcfg[j];
pCfg->sSlotConfig[i].reserved[0] = 0; pCfg->sSlotConfig[i].reserved[1] = 0;
}
int get_num_eaxc_ul() { return(m_xranConf.neAxcUl); }
int get_num_dlrbs() { return(m_xranConf.nDLRBs); }
int get_num_ulrbs() { return(m_xranConf.nULRBs); }
- int get_num_antelmtrx() { return(m_xranConf.nAntElmTRx); }
+ uint32_t get_num_antelmtrx() { return(m_xranConf.nAntElmTRx); }
bool is_cpenable() { return(m_xranConf.enableCP); };
bool is_prachenable() { return(m_xranConf.prachEnable); };
/*******************************************************************************
*
- * Copyright (c) 2020 Intel.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
+ * <COPYRIGHT_TAG>
*
*******************************************************************************/
#include <rte_config.h>
xranLibWraper *xranlib;
+void
+ut_version_print(void)
+{
+ char sysversion[100];
+ char *compilation_date = (char *)__DATE__;
+ char *compilation_time = (char *)__TIME__;
+ char compiler[100];
+
+ //snprintf(sysversion, 99, "Version: %s", VERSIONX);
+
+#if defined(__clang__)
+ snprintf(compiler, 99, "family clang: %s", __clang_version__);
+#elif defined(__ICC) || defined(__INTEL_COMPILER)
+ snprintf(compiler, 99, "family icc: version %d", __INTEL_COMPILER);
+#elif defined(__INTEL_LLVM_COMPILER)
+ snprintf(compiler, 99, "family icx: version %d", __INTEL_LLVM_COMPILER);
+#elif defined(__GNUC__) || defined(__GNUG__)
+ snprintf(compiler, 99, "family gcc: version %d.%d.%d", __GNUC__, __GNUC_MINOR__,__GNUC_PATCHLEVEL__);
+#endif
+
+ printf("\n\n");
+ printf("===========================================================================================================\n");
+ printf("UNITTESTS VERSION\n");
+ printf("===========================================================================================================\n");
+
+ //printf("%s\n", sysversion);
+ printf("build-date: %s\n", compilation_date);
+ printf("build-time: %s\n", compilation_time);
+ printf("build-with: %s\n", compiler);
+}
+
int main(int argc, char** argv) {
int all_test_ret = 0;
-
+ ut_version_print();
/* Enable xml output by default */
::testing::GTEST_FLAG(output) = "xml:test_results.xml";
if(xranlib != nullptr) {
delete xranlib;
- xranlib == nullptr;
+ xranlib = nullptr;
}
return all_test_ret;
from threading import Timer
import socket
-timeout_sec = 60*3 #3 min max
+timeout_sec = 60*5 #5 min max
nLteNumRbsPerSymF1 = [
# 5MHz 10MHz 15MHz 20 MHz
# values for Jenkins server
vf_addr_o_xu_jenkins = [
- #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c
- ["0000:19:02.0,0000:19:0a.0", "0000:19:02.1,0000:19:0a.1", "0000:19:02.2,0000:19:0a.2" ], #O-DU
- ["0000:af:02.0,0000:af:0a.0", "0000:af:02.1,0000:af:0a.1", "0000:af:02.2,0000:af:0a.2" ], #O-RU
+ #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c vf_addr_o_xu_d
+ ["0000:18:01.0,0000:18:01.1", "0000:18:09.0,0000:18:09.1", "0000:18:11.0,0000:18:11.1", "0000:18:19.0,0000:18:19.1" ], #O-DU
+ ["0000:af:01.0,0000:af:01.1", "0000:af:09.0,0000:af:09.1", "0000:af:11.0,0000:af:11.1", "0000:af:19.0,0000:af:19.1" ], #O-RU
]
vf_addr_o_xu_sc12 = [ # 2x2x25G with loopback FVL0:port0 to FVL1:port 0 FVL0:port1 to FVL1:port 1
#vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c
- ["0000:88:02.0,0000:88:0a.0", "0000:88:02.1,0000:88:0a.1", "0000:88:02.2,0000:88:0a.2" ], #O-DU
- ["0000:86:02.0,0000:86:0a.0", "0000:86:02.1,0000:86:0a.1", "0000:86:02.2,0000:86:0a.2" ], #O-RU
+ ["0000:88:02.0,0000:88:0a.0", "0000:88:02.1,0000:88:0a.1", "0000:88:02.2,0000:88:0a.2", "0000:88:02.3,0000:88:0a.3" ], #O-DU
+ ["0000:86:02.0,0000:86:0a.0", "0000:86:02.1,0000:86:0a.1", "0000:86:02.2,0000:86:0a.2", "0000:86:02.3,0000:86:0a.3" ], #O-RU
]
vf_addr_o_xu_sc12_cvl = [
#vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c
- ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:22:01.0,0000:22:09.0" ], #O-DU
- ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:1a:01.0,0000:1a:09.0" ], #O-RU
+ ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:1b:01.0,0000:1b:09.0", "0000:1b:11.0,0000:1b:19.0" ], #O-DU
+ ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:1a:01.0,0000:1a:09.0", "0000:1a:11.0,0000:1a:19.0" ], #O-RU
]
vf_addr_o_xu_scs1_30 = [
- ["0000:65:01.0,0000:65:01.1,0000:65:01.2,0000:65:01.3", "0000:65:01.4,0000:65:01.5,0000:65:01.6,0000:65:01.7", "0000:65:02.0,0000:65:02.1,0000:65:02.2,0000:65:02.3" ], #O-DU
- ["0000:65:09.0,0000:65:09.1,0000:65:09.2,0000:65:09.3", "0000:65:09.4,0000:65:09.5,0000:65:09.6,0000:65:09.7", "0000:65:0a.0,0000:65:0a.1,0000:65:0a.2,0000:65:0a.3" ], #O-RU
+ ["0000:65:01.0,0000:65:01.1,0000:65:01.2,0000:65:01.3", "0000:65:01.4,0000:65:01.5,0000:65:01.6,0000:65:01.7", "0000:65:02.0,0000:65:02.1,0000:65:02.2,0000:65:02.3", "0000:65:02.4,0000:65:02.5,0000:65:02.6,0000:65:02.7" ], #O-DU
+ ["0000:65:09.0,0000:65:09.1,0000:65:09.2,0000:65:09.3", "0000:65:09.4,0000:65:09.5,0000:65:09.6,0000:65:09.7", "0000:65:0a.0,0000:65:0a.1,0000:65:0a.2,0000:65:0a.3", "0000:65:0a.4,0000:65:0a.5,0000:65:0a.6,0000:65:0a.7" ], #O-RU
]
vf_addr_o_xu_scs1_repo = [
- ["0000:18:01.0,0000:18:01.1,0000:18:01.2,0000:18:01.3", "0000:18:01.4,0000:18:01.5,0000:18:01.6,0000:18:01.7", "0000:18:02.0,0000:18:02.1,0000:18:02.2,0000:18:02.3" ], #O-DU
- ["0000:18:11.0,0000:18:11.1,0000:18:11.2,0000:18:11.3", "0000:18:11.4,0000:18:11.5,0000:18:11.6,0000:18:11.7", "0000:18:12.0,0000:18:12.1,0000:18:12.2,0000:18:12.3" ], #O-RU
+ ["0000:18:01.0,0000:18:01.1,0000:18:01.2,0000:18:01.3", "0000:18:01.4,0000:18:01.5,0000:18:01.6,0000:18:01.7", "0000:18:02.0,0000:18:02.1,0000:18:02.2,0000:18:02.3", "0000:18:02.4,0000:18:02.5,0000:18:02.6,0000:18:02.7" ], #O-DU
+ ["0000:18:11.0,0000:18:11.1,0000:18:11.2,0000:18:11.3", "0000:18:11.4,0000:18:11.5,0000:18:11.6,0000:18:11.7", "0000:18:12.0,0000:18:12.1,0000:18:12.2,0000:18:12.3", "0000:18:12.4,0000:18:12.5,0000:18:12.6,0000:18:12.7" ], #O-RU
]
vf_addr_o_xu_icelake_scs1_1 = [
- #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c
- ["0000:51:01.0,0000:51:09.0", "0000:51:11.0,0000:51:19.0", "0000:18:01.0,0000:18:09.0" ], #O-DU
- ["0000:17:01.0,0000:17:09.0", "0000:17:11.0,0000:17:19.0", "0000:65:01.0,0000:65:09.0" ], #O-RU
+ #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c vf_addr_o_xu_d
+ ["0000:51:01.0,0000:51:09.0", "0000:51:11.0,0000:51:19.0", "0000:18:01.0,0000:18:09.0", "0000:18:01.1,0000:18:09.1" ], #O-DU
+ ["0000:17:01.0,0000:17:09.0", "0000:17:11.0,0000:17:19.0", "0000:65:01.0,0000:65:09.0", "0000:65:01.1,0000:65:09.1" ], #O-RU
]
vf_addr_o_xu_icx_npg_scs1_coyote4 = [
- #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c
- ["0000:51:01.0,0000:51:09.0", "0000:51:11.0,0000:51:19.0", "0000:54:01.0,0000:54:11.0" ], #O-DU
- ["0000:17:01.0,0000:17:09.0", "0000:17:11.0,0000:17:19.0", "0000:65:01.0,0000:65:09.0" ], #O-RU
+ #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c vf_addr_o_xu_d
+ ["0000:51:01.0,0000:51:09.0", "0000:51:11.0,0000:51:19.0", "0000:51:11.1,0000:51:19.1", "0000:51:01.1,0000:51:09.1" ], #O-DU
+ ["0000:17:01.0,0000:17:09.0", "0000:17:11.0,0000:17:19.0", "0000:17:11.1,0000:17:19.1", "0000:17:01.1,0000:17:09.1" ], #O-RU
]
vf_addr_o_xu_scs1_35 = [
- ["0000:88:01.0,0000:88:01.1,0000:88:01.2,0000:88:01.3", "0000:88:01.4,0000:88:01.5,0000:88:01.6,0000:88:01.7", "0000:88:02.0,0000:88:02.1,0000:88:02.2,0000:88:02.3" ], #O-DU
- ["0000:88:11.0,0000:88:11.1,0000:88:11.2,0000:88:11.3", "0000:88:11.4,0000:88:11.5,0000:88:11.6,0000:88:11.7", "0000:88:12.0,0000:88:12.1,0000:88:12.2,0000:88:12.3" ], #O-RU
+ ["0000:86:01.0,0000:86:01.1,0000:86:01.2,0000:86:01.3", "0000:86:01.4,0000:86:01.5,0000:86:01.6,0000:86:01.7", "0000:86:02.0,0000:86:02.1,0000:86:02.2,0000:86:02.3", "0000:86:02.4,0000:86:02.5,0000:86:02.6,0000:86:02.7" ], #O-DU
+ ["0000:86:11.0,0000:86:11.1,0000:86:11.2,0000:86:11.3", "0000:86:11.4,0000:86:11.5,0000:86:11.6,0000:86:11.7", "0000:86:12.0,0000:86:12.1,0000:86:12.2,0000:86:12.3", "0000:86:12.4,0000:86:12.5,0000:86:12.6,0000:86:12.7" ], #O-RU
]
vf_addr_o_xu_csl_npg_scs1_33 = [
#vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c
- ["0000:1a:01.0,0000:1a:01.1", "0000:1a:01.2,0000:1a:01.3", "0000:1a:01.4,0000:1a:01.5" ], #O-DU
- ["0000:1a:11.0,0000:1a:11.1", "0000:1a:11.2,0000:1a:11.3", "0000:1a:11.4,0000:1a:11.5" ], #O-RU
+ ["0000:1a:01.0,0000:1a:01.1", "0000:1a:01.2,0000:1a:01.3", "0000:1a:01.4,0000:1a:01.5", "0000:1a:01.6,0000:1a:01.7" ], #O-DU
+ ["0000:1a:11.0,0000:1a:11.1", "0000:1a:11.2,0000:1a:11.3", "0000:1a:11.4,0000:1a:11.5", "0000:1a:11.6,0000:1a:11.7" ], #O-RU
+]
+
+vf_addr_o_xu_skx_5gnr_sd6 = [
+ #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c vf_addr_o_xu_d
+ ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:af:11.1,0000:af:19.1", "0000:af:01.1,0000:af:09.1"], #O-DU
+ ["0000:18:01.0,0000:18:09.0", "0000:18:11.0,0000:18:19.0", "0000:18:11.1,0000:18:19.1", "0000:18:01.1,0000:18:09.1"], #O-RU
]
+
# table of all test cases
# (ran, cat, mu, bw, test case, "test case description")
#Cat A
NR_test_cases_A = [(0, 0, 0, 5, 0, "NR_Sub6_Cat_A_5MHz_1_Cell_0"),
+ (0, 0, 0, 10, 12, "NR_Sub6_Cat_A_10MHz_12_Cell_12"),
+ (0, 0, 0, 20, 12, "NR_Sub6_Cat_A_20MHz_12_Cell_12"),
+ (0, 0, 0, 20, 20, "NR_Sub6_Cat_A_20MHz_1_Cell_owd_req_resp"),
+ (0, 0, 1, 100, 0, "NR_Sub6_Cat_A_100MHz_1_Cell_0"),
+ (0, 0, 3, 100, 7, "NR_mmWave_Cat_A_100MHz_1_Cell_0_sc"),
+]
+
+NR_test_cases_A_ext = [(0, 0, 0, 5, 0, "NR_Sub6_Cat_A_5MHz_1_Cell_0"),
(0, 0, 0, 10, 0, "NR_Sub6_Cat_A_10MHz_1_Cell_0"),
(0, 0, 0, 10, 12, "NR_Sub6_Cat_A_10MHz_12_Cell_12"),
(0, 0, 0, 20, 0, "NR_Sub6_Cat_A_20MHz_1_Cell_0"),
(0, 0, 3, 100, 7, "NR_mmWave_Cat_A_100MHz_1_Cell_0_sc"),
]
+j_test_cases_A = [(0, 0, 1, 100, 204,"NR_Sub6_Cat_A_100MHz_4_O_RU_2Ant"),
+ (0, 0, 1, 100, 404,"NR_Sub6_Cat_A_100MHz_4_O_RU_4Ant")
+]
+
+j_test_cases_A_ext = [(0, 0, 1, 100, 201,"NR_Sub6_Cat_A_100MHz_1_O_RU_2Ant"),
+ (0, 0, 1, 100, 202,"NR_Sub6_Cat_A_100MHz_2_O_RU_2Ant"),
+ (0, 0, 1, 100, 203,"NR_Sub6_Cat_A_100MHz_3_O_RU_2Ant"),
+ (0, 0, 1, 100, 204,"NR_Sub6_Cat_A_100MHz_4_O_RU_2Ant"),
+ (0, 0, 1, 100, 401,"NR_Sub6_Cat_A_100MHz_1_O_RU_4Ant"),
+ (0, 0, 1, 100, 402,"NR_Sub6_Cat_A_100MHz_2_O_RU_4Ant"),
+ (0, 0, 1, 100, 403,"NR_Sub6_Cat_A_100MHz_3_O_RU_4Ant"),
+ (0, 0, 1, 100, 404,"NR_Sub6_Cat_A_100MHz_4_O_RU_4Ant")
+]
+
+
LTE_test_cases_A = [(1, 0, 0, 5, 0, "LTE_Cat_A_5Hz_1_Cell_0"),
(1, 0, 0, 10, 0, "LTE_Cat_A_10Hz_1_Cell_0"),
(1, 0, 0, 20, 0, "LTE_Cat_A_20Hz_1_Cell_0"),
]
+DSS_test_cases_A = [(2, 0, 0, 20, 10, "DSS_Cat_A_20MHz_FDD_1_Cell"),
+ (2, 0, 0, 20, 11, "DSS_Cat_A_20MHz_TDD_1_Cell"),
+ (2, 0, 0, 20, 60, "DSS_Cat_A_20MHz_FDD_6_Cell"),
+ (2, 0, 0, 20, 61, "DSS_Cat_A_20MHz_TDD_6_Cell"),
+ (2, 0, 0, 10, 10, "DSS_Cat_A_10MHz_FDD_1_Cell"),
+ (2, 0, 0, 10, 11, "DSS_Cat_A_10MHz_TDD_1_Cell"),
+ (2, 0, 0, 10, 60, "DSS_Cat_A_10MHz_FDD_6_Cell"),
+ (2, 0, 0, 10, 61, "DSS_Cat_A_10MHz_TDD_6_Cell"),
+ (2, 0, 0, 5, 10, "DSS_Cat_A_5MHz_FDD_1_Cell"),
+ (2, 0, 0, 5, 11, "DSS_Cat_A_5MHz_TDD_1_Cell"),
+ (2, 0, 0, 5, 60, "DSS_Cat_A_5MHz_FDD_6_Cell"),
+ (2, 0, 0, 5, 61, "DSS_Cat_A_5MHz_TDD_6_Cell"),
+]
+
#Cat B
NR_test_cases_B = [(0, 1, 1, 100, 0, "NR_Sub6_Cat_B_100MHz_1_Cell_0"),
- (0, 1, 1, 100, 2, "NR_Sub6_Cat_B_100MHz_1_Cell_2"),
+ (0, 1, 1, 100, 216, "NR_Sub6_Cat_B_100MHz_1_Cell_216"),
+]
+
+NR_test_cases_B_ext = [(0, 1, 1, 100, 0, "NR_Sub6_Cat_B_100MHz_1_Cell_0"),
(0, 1, 1, 100, 1, "NR_Sub6_Cat_B_100MHz_1_Cell_1"),
+ (0, 1, 1, 100, 2, "NR_Sub6_Cat_B_100MHz_1_Cell_1_ext1"),
(0, 1, 1, 100, 101, "NR_Sub6_Cat_B_100MHz_1_Cell_101"),
(0, 1, 1, 100, 102, "NR_Sub6_Cat_B_100MHz_1_Cell_102"),
(0, 1, 1, 100, 103, "NR_Sub6_Cat_B_100MHz_1_Cell_103"),
(0, 1, 1, 100, 214, "NR_Sub6_Cat_B_100MHz_1_Cell_214"),
(0, 1, 1, 100, 215, "NR_Sub6_Cat_B_100MHz_1_Cell_215"),
(0, 1, 1, 100, 216, "NR_Sub6_Cat_B_100MHz_1_Cell_216"),
- #(0, 1, 1, 100, 401, "NR_Sub6_Cat_B_100MHz_1_Cell_401") 25G not enough
]
-LTE_test_cases_B = [(1, 1, 0, 5, 0, "LTE_Cat_B_5MHz_1_Cell_0"),
+LTE_test_cases_B = [(1, 1, 0, 20, 0, "LTE_Cat_B_20MHz_1_Cell_0"),
+]
+
+LTE_test_cases_B_ext = [(1, 1, 0, 5, 0, "LTE_Cat_B_5MHz_1_Cell_0"),
(1, 1, 0, 10, 0, "LTE_Cat_B_10MHz_1_Cell_0"),
(1, 1, 0, 20, 0, "LTE_Cat_B_20MHz_1_Cell_0"),
(1, 1, 0, 5, 1, "LTE_Cat_B_5Hz_1_Cell_0_sc"),
]
+
V_test_cases_B = [
+ # (0, 1, 1, 100, 301, "NR_Sub6_Cat_B_100MHz_1_Cell_301"),
+ (0, 1, 1, 100, 602, "NR_Sub6_Cat_B_100MHz_1_Cell_602_sc"),
+]
+
+V_test_cases_B_ext = [
(0, 1, 1, 100, 301, "NR_Sub6_Cat_B_100MHz_1_Cell_301"),
(0, 1, 1, 100, 302, "NR_Sub6_Cat_B_100MHz_1_Cell_302"),
(0, 1, 1, 100, 303, "NR_Sub6_Cat_B_100MHz_1_Cell_303"),
(0, 1, 1, 100, 602, "NR_Sub6_Cat_B_100MHz_1_Cell_602_sc"),
]
+
V_test_cases_B_2xUL = [
+ # (0, 1, 1, 100, 311, "NR_Sub6_Cat_B_100MHz_1_Cell_311"),
+ (0, 1, 1, 100, 612, "NR_Sub6_Cat_B_100MHz_1_Cell_612_sc"),
+
+]
+
+V_test_cases_B_2xUL_ext = [
(0, 1, 1, 100, 311, "NR_Sub6_Cat_B_100MHz_1_Cell_311"),
(0, 1, 1, 100, 312, "NR_Sub6_Cat_B_100MHz_1_Cell_312"),
(0, 1, 1, 100, 313, "NR_Sub6_Cat_B_100MHz_1_Cell_313"),
(0, 1, 1, 100, 3511, "NR_Sub6_Cat_B_100MHz_1_Cell_3511")
]
-all_test_cases = NR_test_cases_A + LTE_test_cases_A + LTE_test_cases_B + NR_test_cases_B + V_test_cases_B + V_test_cases_B_2xUL
+
+J_test_cases_B_4Cells = [
+ (0, 1, 1, 100, 1421, "NR_Sub6_Cat_B_100MHz_1_Cell_DL4UL2"),
+ (0, 1, 1, 100, 4424, "NR_Sub6_Cat_B_100MHz_4_Cell_DL4UL2")
+]
+
+J_test_cases_B_4Cells_ext = [
+ (0, 1, 1, 100, 1421, "NR_Sub6_Cat_B_100MHz_1_Cell_DL4UL2"),
+ (0, 1, 1, 100, 2422, "NR_Sub6_Cat_B_100MHz_2_Cell_DL4UL2"),
+ (0, 1, 1, 100, 3423, "NR_Sub6_Cat_B_100MHz_3_Cell_DL4UL2"),
+ (0, 1, 1, 100, 4424, "NR_Sub6_Cat_B_100MHz_4_Cell_DL4UL2")
+]
+
+Ext1_test_cases_B_4Cells = [
+ (0, 1, 1, 100, 142, "NR_Sub6_Cat_B_100MHz_ext1_1_Cell_DL4UL2"),
+ (0, 1, 1, 100, 242, "NR_Sub6_Cat_B_100MHz_ext1_2_Cell_DL4UL2"),
+ (0, 1, 1, 100, 342, "NR_Sub6_Cat_B_100MHz_ext1_3_Cell_DL4UL2"),
+ (0, 1, 1, 100, 442, "NR_Sub6_Cat_B_100MHz_ext1_4_Cell_DL4UL2")
+]
+
+all_test_cases = []
+
+#reduced duration test cycle
+all_test_cases_short = NR_test_cases_A + LTE_test_cases_A + j_test_cases_A + LTE_test_cases_B + NR_test_cases_B + V_test_cases_B + V_test_cases_B_2xUL + J_test_cases_B_4Cells
+
+all_test_cases_long = NR_test_cases_A_ext + LTE_test_cases_A + j_test_cases_A_ext + DSS_test_cases_A + LTE_test_cases_B_ext + NR_test_cases_B_ext + V_test_cases_B_ext + V_test_cases_B_2xUL_ext + J_test_cases_B_4Cells_ext + Ext1_test_cases_B_4Cells
dic_dir = dict({0:'DL', 1:'UL'})
dic_xu = dict({0:'o-du', 1:'o-ru'})
-dic_ran_tech = dict({0:'5g_nr', 1:'lte'})
+dic_ran_tech = dict({0:'5g_nr', 1:'lte', 2:'dss'})
def init_logger(console_level, logfile_level):
"""Initializes console and logfile logger with given logging levels"""
# Parser configuration
parser = argparse.ArgumentParser(description="Run test cases: category numerology bandwidth test_num")
- parser.add_argument("--rem_o_ru_host", type=str, default="", help="remot host to run O-RU", metavar="root@10.10.10.1", dest="rem_o_ru_host")
- parser.add_argument("--ran", type=int, default=0, help="Radio Access Tehcnology 0 (5G NR) or 1 (LTE)", metavar="ran", dest="rantech")
+ parser.add_argument("--rem_o_ru_host", type=str, default="", help="remote host to run O-RU", metavar="root@10.10.10.1", dest="rem_o_ru_host")
+ parser.add_argument("--ran", type=int, default=0, help="Radio Access Technology 0 (5G NR) , 1 (LTE) or 2 DSS (5G NR and LTE)", metavar="ran", dest="rantech")
parser.add_argument("--cat", type=int, default=0, help="Category: 0 (A) or 1 (B)", metavar="cat", dest="category")
parser.add_argument("--mu", type=int, default=0, help="numerology [0,1,3]", metavar="num", dest="numerology")
parser.add_argument("--bw", type=int, default=20, help="bandwidth [5,10,20,100]", metavar="bw", dest="bandwidth")
#print(PrbElemContent,"RBStart: ", xRBStart, "RBSize: ",xRBSize, list(range(xRBStart, xRBStart + xRBSize)))
prb_map = prb_map + list(range(xRBStart*12, xRBStart*12 + xRBSize*12))
else:
- nPrbElm = 0;
+ nPrbElm = 0
elif direction == 1:
#UL
elif direction == 2:
#UL
if 'nPrbElemSrs' in globals():
- nPrbElm = nPrbElemUl
+ nPrbElm = nPrbElemSrs
for i in range(0, nPrbElm):
elm = str('PrbElemSrs'+str(i))
#print(elm)
return prb_map
+def get_bfw_map(direction):
+ bfw_map = []
+ bfwElemContent = []
+ if direction == 0:
+ #DL
+ if 'nPrbElemDl' in globals():
+ nPrbElm = nPrbElemDl
+ numsetBFW_total = 0
+ for i in range(0, nPrbElm):
+ elm = str('ExtBfwDl'+str(i))
+ #print(elm)
+ if elm in globals():
+ bfwElemContent.insert(i,list(globals()[elm]))
+ numBundPrb = bfwElemContent[i][0]
+ numsetBFW = bfwElemContent[i][1]
+ bfw_map = bfw_map + list(range(antElmTRx*numsetBFW_total, antElmTRx*numsetBFW_total + numsetBFW*antElmTRx))
+ numsetBFW_total += numsetBFW
+ else:
+ nPrbElm = 0
+ if nPrbElm == 0 :
+ bfw_map = list(range(0, (nPrbElm-1)*numsetBFW*antElmTRx))
+
+ return bfw_map, numsetBFW_total
+
def check_for_string_present_in_file(file_name, search_string):
res = 1
with open(file_name, 'r') as read_obj:
def compare_results(o_xu_id, rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction):
res = 0
re_map = []
- if rantech==1:
+ if rantech==2:
+ if mu == 0:
+ nDlRB = nLteNumRbsPerSymF1[mu][nRChBwOptions.get(str(nDLBandwidth))]
+ nUlRB = nLteNumRbsPerSymF1[mu][nRChBwOptions.get(str(nULBandwidth))]
+ else:
+ print("Incorrect arguments\n")
+ res = -1
+ return res
+ elif rantech==1:
if mu == 0:
nDlRB = nLteNumRbsPerSymF1[mu][nRChBwOptions.get(str(nDLBandwidth))]
nUlRB = nLteNumRbsPerSymF1[mu][nRChBwOptions.get(str(nULBandwidth))]
else:
comp = 0
- if 'srsEanble' in globals():
- srs_enb = srsEanble
+ if 'srsEnable' in globals():
+ srs_enb = srsEnable
else:
srs_enb = 0
- if 'rachEanble' in globals():
- rach = rachEanble
+ if 'rachEnable' in globals():
+ rach = rachEnable
else:
rach = 0
+ if 'extType' in globals():
+ ext_type = extType
+ else:
+ ext_type = 0
+
print("O-RU {} compare results: {} [compression {}]\n".format(o_xu_id, dic_dir.get(direction), comp))
#if cat == 1:
- # print("WARNING: Skip checking IQs and BF Weights for CAT B for now\n");
+ # print("WARNING: Skip checking IQs and BF Weights for CAT B for now\n")
# return res
#get slot config
print(len(tst))
print(len(ref))
- file_tst.close();
- file_ref.close();
+ file_tst.close()
+ file_ref.close()
print(numSlots)
print(len(tst))
print(len(ref))
- file_tst.close();
- file_ref.close();
+ file_tst.close()
+ file_ref.close()
print(numSlots)
except GetOutOfLoops:
return res
+ if ((cat == 1) and (direction == 0) and (ext_type == 1)): #Cat B, DL and Extension type = 1
+ try:
+ if (direction == 0) & (cat == 1): #DL
+ flowId = ccNum*antNum
+ if direction == 0:
+ bfw_map, numsetBFW_total = get_bfw_map(direction)
+ else:
+ raise Exception('Direction is not supported %d'.format(direction))
+
+ for i in range(0, flowId):
+ #read ref and test files
+ tst = []
+ ref = []
+ if direction == 0:
+ # DL
+ file_tst = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-dl_bfw_log_ue"+str(i)+".txt"
+ file_ref = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-dl_bfw_ue"+str(i)+".txt"
+ else:
+ raise Exception('Direction is not supported %d'.format(direction))
+
+ print("test result :", file_tst)
+ print("test reference:", file_ref)
+ if os.path.exists(file_tst):
+ try:
+ file_tst = open(file_tst, 'r')
+ except OSError:
+ print ("Could not open/read file:", file_tst)
+ sys.exit()
+ else:
+ print(file_tst, "doesn't exist")
+ res = -1
+ return res
+ if os.path.exists(file_ref):
+ try:
+ file_ref = open(file_ref, 'r')
+ except OSError:
+ print ("Could not open/read file:", file_ref)
+ sys.exit()
+ else:
+ print(file_tst, "doesn't exist")
+ res = -1
+ return res
+
+ tst = file_tst.readlines()
+ ref = file_ref.readlines()
+
+ print(len(tst))
+ print(len(ref))
+
+ file_tst.close()
+ file_ref.close()
+
+ print(numSlots)
+
+ for slot_idx in range(0, numSlots):
+ skip_tti = 1
+ if nFrameDuplexType==1:
+ #skip tti if UL slot
+ if direction == 0:
+ #DL
+ for sym_idx in range(0,14):
+ sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx]
+ if(sym_dir == 0):
+ skip_tti = 0
+ break
+ if(skip_tti == 1):
+ continue
+ for line_idx in bfw_map:
+ offset = slot_idx * (nDlRB*antElmTRx) #(slot_idx*numsetBFW_total*antElmTRx) + line_idx
+ try:
+ line_tst = tst[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on tst: ant:[",i,"]:",offset, slot_idx, line_idx, len(tst))
+ raise GetOutOfLoops
+ try:
+ line_ref = ref[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on ref: ant:[",i,"]:",offset, slot_idx, line_idx, len(ref))
+ raise GetOutOfLoops
+
+ if comp == 1:
+ # discard LSB bits as BFP compression is not "bit exact"
+ tst_i_value = int(line_tst.split(" ")[0]) & 0xFF80
+ tst_q_value = int(line_tst.split(" ")[1]) & 0xFF80
+ ref_i_value = int(line_ref.split(" ")[0]) & 0xFF80
+ ref_q_value = int(line_ref.split(" ")[1]) & 0xFF80
+
+ tst_i_act = int(line_tst.split(" ")[0])
+ tst_q_act = int(line_tst.split(" ")[1])
+ ref_i_act = int(line_ref.split(" ")[0])
+ ref_q_act = int(line_ref.split(" ")[1])
+
+ #print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ if (tst_i_value != ref_i_value) or (tst_q_value != ref_q_value) :
+ print("868 Actual:","bfw:[",i,"]:",offset, slot_idx, line_idx,":","tst: ", tst_i_act, " ", tst_q_act, " " , "ref: ", ref_i_act, " ", ref_q_act, " ")
+ print("FAIL:","bfw:[",i,"]:",offset, slot_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ res = -1
+ raise GetOutOfLoops
+ else:
+ #if line_idx == 0:
+ #print("Check:", offset,"[",i,"]", slot_idx, sym_idx,":",line_tst, line_ref)
+ if line_ref != line_tst:
+ print("876 Actual:","bfw:[",i,"]:",offset, slot_idx, line_idx,":","tst: ", tst_i_act, " ", tst_q_act, " " , "ref: ", ref_i_act, " ", ref_q_act, " ")
+ print("FAIL:","bfw:[",i,"]:",offset, slot_idx, line_idx,":","tst:", line_tst, "ref:", line_ref)
+ res = -1
+ raise GetOutOfLoops
+ except GetOutOfLoops:
+ res = 0 # Not treating it as a test case fail criteria for now
+ # return res
+
+ try:
+ if (direction == 0) & (cat == 1): #DL
+ flowId = ccNum*antNumUL
+ if direction == 0:
+ bfw_map, numsetBFW_total = get_bfw_map(direction)
+ else:
+ raise Exception('Direction is not supported %d'.format(direction))
+
+ for i in range(0, flowId):
+ #read ref and test files
+ tst = []
+ ref = []
+ if direction == 0:
+ # DL
+ file_tst = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-ul_bfw_log_ue"+str(i)+".txt"
+ file_ref = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-ul_bfw_ue"+str(i)+".txt"
+ else:
+ raise Exception('Direction is not supported %d'.format(direction))
+
+ print("test result :", file_tst)
+ print("test reference:", file_ref)
+ if os.path.exists(file_tst):
+ try:
+ file_tst = open(file_tst, 'r')
+ except OSError:
+ print ("Could not open/read file:", file_tst)
+ sys.exit()
+ else:
+ print(file_tst, "doesn't exist")
+ res = -1
+ return res
+ if os.path.exists(file_ref):
+ try:
+ file_ref = open(file_ref, 'r')
+ except OSError:
+ print ("Could not open/read file:", file_ref)
+ sys.exit()
+ else:
+ print(file_tst, "doesn't exist")
+ res = -1
+ return res
+
+ tst = file_tst.readlines()
+ ref = file_ref.readlines()
+
+ print(len(tst))
+ print(len(ref))
+
+ file_tst.close()
+ file_ref.close()
+
+ print(numSlots)
+
+ for slot_idx in range(0, numSlots):
+ skip_tti = 1
+ if nFrameDuplexType==1:
+ #skip tti if UL slot
+ if direction == 0:
+ #DL
+ for sym_idx in range(0,14):
+ sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx]
+ if(sym_dir == 1):
+ skip_tti = 0
+ break
+ if(skip_tti == 1):
+ continue
+ for line_idx in bfw_map:
+ offset = slot_idx * (nUlRB*antElmTRx) #(slot_idx*numsetBFW_total*antElmTRx) + line_idx
+ try:
+ line_tst = tst[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on tst: ant:[",i,"]:",offset, slot_idx, line_idx, len(tst))
+ raise GetOutOfLoops
+ try:
+ line_ref = ref[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on ref: ant:[",i,"]:",offset, slot_idx, line_idx, len(ref))
+ raise GetOutOfLoops
+
+ if comp == 1:
+ # discard LSB bits as BFP compression is not "bit exact"
+ tst_i_value = int(line_tst.split(" ")[0]) & 0xFF80
+ tst_q_value = int(line_tst.split(" ")[1]) & 0xFF80
+ ref_i_value = int(line_ref.split(" ")[0]) & 0xFF80
+ ref_q_value = int(line_ref.split(" ")[1]) & 0xFF80
+
+ #print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ if (tst_i_value != ref_i_value) or (tst_q_value != ref_q_value) :
+ print("FAIL:","bfw:[",i,"]:",offset, slot_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ res = -1
+ raise GetOutOfLoops
+ else:
+ #if line_idx == 0:
+ #print("Check:", offset,"[",i,"]", slot_idx, sym_idx,":",line_tst, line_ref)
+ if line_ref != line_tst:
+ print("FAIL:","bfw:[",i,"]:",offset, slot_idx, line_idx,":","tst:", line_tst, "ref:", line_ref)
+ res = -1
+ raise GetOutOfLoops
+ except GetOutOfLoops:
+ res = 0 # Not treating it as a test case fail criteria for now
+ # return res
+
if (direction == 0) | (cat == 0) | (srs_enb == 0): #DL or Cat A
#done
return res
print("O-RU {} compare results: {} [compression {}]\n".format(o_xu_id, 'SRS', comp))
#srs
- symbMask = srsSym
+ PrbElemContent = []
+ if 'nPrbElemSrs' in globals():
+ for i in range(0, nPrbElemSrs):
+ elm = str('PrbElemSrs'+str(i))
+ #print(elm)
+ if (elm in globals()):
+ PrbElemContent.insert(i,list(globals()[elm]))
+ symbMask = 1 << PrbElemContent[i][2] # start symbol
+ print(symbMask)
+ #print(PrbElemContent,"RBStart: ", xRBStart, "RBSize: ",xRBSize, list(range(xRBStart, xRBStart + xRBSize)))
+ else:
+ print("Cannot find SRS PRB map!")
+ symbMask = 0
+
re_map = get_re_map(nUlRB, 2)
try:
flowId = ccNum*antElmTRx
print(len(tst))
print(len(ref))
- file_tst.close();
- file_ref.close();
+ file_tst.close()
+ file_ref.close()
print(numSlots)
for slot_idx in range(0, numSlots - (1*direction)):
for sym_idx in range(0, 14):
- if symbMask & (1 << sym_idx) and slot_idx%nTddPeriod == 3:
+ if symbMask & (1 << sym_idx) and slot_idx%nTddPeriod == srsSlot:
print("SRS check sym ", slot_idx, sym_idx)
if nFrameDuplexType==1:
#skip sym if TDD
def run_tcase(rem_o_ru_host, rantech, cat, mu, bw, tcase, verbose, xran_path, vf_addr_o_xu):
- if rantech == 1: #LTE
+ if rantech == 2: #LTE and #5G NR
+ if cat == 0:
+ test_config =xran_path+"/app/usecase/dss/mu{0:d}_{1:d}mhz".format(mu, bw)
+ else:
+ print("Incorrect cat argument\n")
+ return -1
+ elif rantech == 1: #LTE
if cat == 1:
test_config =xran_path+"/app/usecase/lte_b/mu{0:d}_{1:d}mhz".format(mu, bw)
elif cat == 0 :
if(tcase > 0) :
test_config = test_config+"/"+str(tcase)
- app = xran_path+"/app/build/sample-app"
+ app = [xran_path+"/app/build/sample-app", xran_path+"/app/build-oru/sample-app-ru"]
logging.debug("run: %s %s", app, test_config)
logging.debug("Started script: master.py, XRAN path %s", xran_path)
test_cfg = []
global oXuOwdmEnabled
oXuOwdmEnabled = 0 #Default is owdm measurements are disabled
+ REM_O_RU_HOST=rem_o_ru_host
+
+ if(os.system('lscpu | grep -q -i AVX512IFMA') == 0):
+ cpu = 'icx'
+ else:
+ cpu = 'csx'
+
+ #O-DU
+ if REM_O_RU_HOST == "":
+
+ if (cpu == 'icx'):
+ if ((os.path.isfile(test_config+"/usecase_du_icx.cfg")) & (os.path.isfile(test_config+"/usecase_ru_icx.cfg"))):
+ test_cfg.append(test_config+"/usecase_du_icx.cfg")
+ test_cfg.append(test_config+"/usecase_ru_icx.cfg")
+ else:
+ test_cfg.append(test_config+"/usecase_du.cfg")
+ test_cfg.append(test_config+"/usecase_ru.cfg")
+ else: #(csx_cpu)
+ if ((os.path.isfile(test_config+"/usecase_du_csx.cfg")) & (os.path.isfile(test_config+"/usecase_ru_csx.cfg"))):
+ test_cfg.append(test_config+"/usecase_du_csx.cfg")
+ test_cfg.append(test_config+"/usecase_ru_csx.cfg")
+ else:
+ test_cfg.append(test_config+"/usecase_du.cfg")
+ test_cfg.append(test_config+"/usecase_ru.cfg")
+ else: # O-RU remote always CSX-SP
+ if (cpu == 'icx'):
+ if (os.path.isfile(test_config+"/usecase_du_icx.cfg")):
+ test_cfg.append(test_config+"/usecase_du_icx.cfg")
+ else:
+ test_cfg.append(test_config+"/usecase_du.cfg")
+ if (os.path.isfile(test_config+"/usecase_ru_csx.cfg")):
+ test_cfg.append(test_config+"/usecase_ru_csx.cfg")
+ else:
+ test_cfg.append(test_config+"/usecase_ru.cfg")
+ else: #(csx_cpu)
+ if ((os.path.isfile(test_config+"/usecase_du_csx.cfg")) & (os.path.isfile(test_config+"/usecase_ru_csx.cfg"))):
+ test_cfg.append(test_config+"/usecase_du_csx.cfg")
+ test_cfg.append(test_config+"/usecase_ru_csx.cfg")
+ else:
test_cfg.append(test_config+"/usecase_du.cfg")
test_cfg.append(test_config+"/usecase_ru.cfg")
timer = []
os.system('pkill -9 "sample-app"')
+ os.system('pkill -9 "sample-app-ru"')
os.system('rm -rf ./logs')
usecase_cfg = parse_usecase_cfg(rantech, cat, mu, bw, tcase, xran_path, test_cfg)
- REM_O_RU_HOST=rem_o_ru_host
+
for i in range(2):
log_file_name.append("sampleapp_log_{}_{}_cat_{}_mu{}_{}mhz_tst_{}.log".format(dic_ran_tech.get(rantech), dic_xu.get(i),cat, mu, bw, tcase))
with open(log_file_name[i], "w") as f:
- run_cmd = [app, "--usecasefile", test_cfg[i], "--num_eth_vfs", "6", "--vf_addr_o_xu_a", vf_addr_o_xu[i][0], "--vf_addr_o_xu_b", vf_addr_o_xu[i][1],"--vf_addr_o_xu_c", vf_addr_o_xu[i][2]]
+ run_cmd = [app[i], "--usecasefile", test_cfg[i], "--num_eth_vfs", "8", "--vf_addr_o_xu_a", vf_addr_o_xu[i][0], "--vf_addr_o_xu_b", vf_addr_o_xu[i][1],"--vf_addr_o_xu_c", vf_addr_o_xu[i][2],"--vf_addr_o_xu_d", vf_addr_o_xu[i][3]]
#, stdout=f, stderr=f
if (verbose==1):
if i == 0 or REM_O_RU_HOST == "":
p = subprocess.Popen(run_cmd)
else:
CMD = ' '.join([str(elem) for elem in run_cmd])
- ssh = ["ssh", "%s" % REM_O_RU_HOST, "cd " + xran_path + "/app"+"; hostname; pwd; pkill -9 sample-app; rm -rf ./logs;" + CMD]
+ ssh = ["ssh", "%s" % REM_O_RU_HOST, "cd " + xran_path + "/app"+"; hostname; pwd; pkill -9 sample-app; rm -rf ./logs; ulimit -c unlimited; echo 1 > /proc/sys/kernel/core_uses_pid; " + CMD]
print(ssh)
print("my_cmd: ", ' '.join([str(elem) for elem in ssh]))
p = subprocess.Popen(ssh, shell=False)
p = subprocess.Popen(run_cmd, stdout=f, stderr=f)
else :
CMD = ' '.join([str(elem) for elem in run_cmd])
- ssh = ["ssh", "%s" % REM_O_RU_HOST, "cd " + xran_path + "/app"+"; hostname; pwd; pkill -9 sample-app; rm -rf ./logs; " + CMD]
+ ssh = ["ssh", "%s" % REM_O_RU_HOST, "cd " + xran_path + "/app"+"; hostname; pwd; pkill -9 sample-app; rm -rf ./logs; ulimit -c unlimited; echo 1 > /proc/sys/kernel/core_uses_pid; " + CMD]
p = subprocess.Popen(ssh, shell=False, stdout=f, stderr=f)
#stdout=subprocess.PIPE, stderr=subprocess.PIPE)
p.wait()
except (KeyboardInterrupt, SystemExit):
for i in range(2):
- timer[i].cancel();
- timer[i].cancel();
+ timer[i].cancel()
+ timer[i].cancel()
for pp, ff in processes:
pp.send_signal(signal.SIGINT)
pp.wait()
f.close()
for i in range(2):
- timer[i].cancel();
- timer[i].cancel();
+ timer[i].cancel()
+ timer[i].cancel()
logging.info("O-DU and O-RU are done\n")
def main():
test_results = []
- test_executed_total = 0
run_total = 0
test_fail_cnt = 0
test_pass_cnt = 0
options = parse_args(sys.argv[1:])
rem_o_ru_host = options.rem_o_ru_host
+ all_test_cases = all_test_cases_long
if host_name == "sc12-xran-sub6":
if rem_o_ru_host:
vf_addr_o_xu = vf_addr_o_xu_sc12_cvl
vf_addr_o_xu = vf_addr_o_xu_scs1_35
elif host_name == "csl-npg-scs1-33":
vf_addr_o_xu = vf_addr_o_xu_csl_npg_scs1_33
+ elif host_name == "skx-5gnr-sd6":
+ vf_addr_o_xu = vf_addr_o_xu_skx_5gnr_sd6
else:
vf_addr_o_xu = vf_addr_o_xu_jenkins
+ all_test_cases = all_test_cases_short
- print(vf_addr_o_xu[0][0],vf_addr_o_xu[0][1],vf_addr_o_xu[0][2])
- print(vf_addr_o_xu[1][0],vf_addr_o_xu[1][1],vf_addr_o_xu[1][2])
+ print(vf_addr_o_xu[0][0],vf_addr_o_xu[0][1],vf_addr_o_xu[0][2],vf_addr_o_xu[0][3])
+ print(vf_addr_o_xu[1][0],vf_addr_o_xu[1][1],vf_addr_o_xu[1][2],vf_addr_o_xu[1][3])
# Parse input arguments
if len(sys.argv) == 1 or (len(sys.argv) == 3 and rem_o_ru_host):
##############################################################
# Tools configuration
##############################################################
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
CC := icc
CXX := icpc
CPP := icpc
AS := as
AR := ar
LD := icc
+else ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ CC := icx
+ CXX := icpx
+ CPP := icpx
+ AS := as
+ AR := llvm-ar
+ LD := icx
+else
+ $(error "Please define WIRELESS_SDK_TOOLCHAIN environment variable")
+endif
+
OBJDUMP := objdump
ifeq ($(SHELL),cmd.exe)
CP := cp -f
RM := rm -rf
endif
+TARGET_PROCESSOR =
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ ifeq ($(WIRELESS_SDK_TARGET_ISA),sse)
+ TARGET_PROCESSOR := -xSSE4.2
+ else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx2)
+ TARGET_PROCESSOR := -xCORE-AVX2
+ else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx512)
+ TARGET_PROCESSOR := -xCORE-AVX512
+ else ifeq ($(WIRELESS_SDK_TARGET_ISA),snc)
+ TARGET_PROCESSOR := -xicelake-server
+ else ifeq ($(WIRELESS_SDK_TARGET_ISA),spr)
+ TARGET_PROCESSOR := -march=sapphirerapids
+ endif
+
+ ifeq ($(TARGET_PROCESSOR),)
+ $(error "Please define valid WIRELESS_SDK_TARGET_ISA environment variable $(WIRELESS_SDK_TARGET_ISA)")
+ endif
+endif
ifeq ($(RTE_SDK),)
$(error "Please define RTE_SDK environment variable")
MLOG_DIR=$(XRAN_DIR)/../mlog
endif
-RTE_TARGET ?= x86_64-native-linuxapp-icc
-
RTE_LIBS = $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --static --libs libdpdk)
RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk)
-
# Where to find user code.
COMMON_TEST_DIR = $(XRAN_DIR)/test/common
USER_DIR = $(XRAN_DIR)/lib/src
# Flags passed to the preprocessor.
# Set Google Test's header directory as a system directory, such that
# the compiler doesn't generate warnings in Google Test headers.
-CPPFLAGS += -isystem $(GTEST_ROOT)/include
+CPPFLAGS += -isystem $(GTEST_ROOT)/include -Wno-unused-variable
# Flags passed to the C++ compiler.
-CXXFLAGS += -g -std=c++14 -Wall -Wextra -pthread -mcmodel=large -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I $(COMMON_TEST_DIR) -I$(RTE_INC)
+CXXFLAGS += -g -std=c++14 -pthread -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -mcmodel=large -Wno-unused-variable -fPIC \
+ -falign-functions=16 $(TARGET_PROCESSOR) -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I $(COMMON_TEST_DIR) -I$(RTE_INC)
+
+
# All tests produced by this Makefile. Remember to add new tests you
# created to the list.
-g \
-Wall \
-Wimplicit-function-declaration \
- -wd1786 \
-mcmodel=large \
+ -Wno-unused-variable \
+ -Wno-unused-parameter \
+ $(TARGET_PROCESSOR) \
-I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I$(RTE_INC)
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
+CXXFLAGS += -Wall -Wextra
+CFLAGS += -wd1786 -restrict
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+CFLAGS += -mintrinsic-promote -Wno-intrinsic-promote -Wno-error -Wno-unused-but-set-variable
+endif
+
+
C_SRC = \
$(USER_ETH)/ethdi.c \
$(USER_ETH)/ethernet.c \
$(USER_DIR)/xran_common.c \
$(USER_DIR)/xran_ul_tables.c \
$(USER_DIR)/xran_frame_struct.c \
- $(USER_DIR)/xran_app_frag.c \
$(USER_DIR)/xran_dev.c \
$(USER_DIR)/xran_rx_proc.c \
$(USER_DIR)/xran_tx_proc.c \
CPPFLAGS += -I$(USER_DIR) -I$(USER_API)
#-qopt-report=5 -qopt-matmul -qopt-report-phase=all
-CPP_COMP := -O3 -DNDEBUG -xcore-avx512 -fPIE -restrict -fasm-blocks
-CPP_COMP_SNC := -O3 -DNDEBUG -march=icelake-server -fPIE -restrict -fasm-blocks
+CPP_COMP := -O3 -DNDEBUG -xcore-avx512 -fPIE -fasm-blocks
+CPP_COMP_SNC := -O3 -DNDEBUG -march=icelake-server -fPIE -fasm-blocks
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
+CPP_COMP += -fp-model fast=2 -no-prec-div -no-prec-sqrt -fast-transcendentals -restrict
+CPP_COMP_SNC += -fp-model fast=2 -no-prec-div -no-prec-sqrt -fast-transcendentals -restrict
+endif
+
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+CPP_COMP += -fp-model fast -mintrinsic-promote -Wno-intrinsic-promote -Wno-error -Wno-unused-variable
+CPP_COMP_SNC += -fp-model fast -mintrinsic-promote -Wno-intrinsic-promote -Wno-error -Wno-unused-variable
+endif
CPP_COMP := $(CPP_COMP)
CPP_COMP_SNC := $(CPP_COMP_SNC)
$(TESTS) : $(CC_OBJS) $(CPP_OBJS) $(CPP_SNC_OBJS) $(C_OBJS) $(GTEST_ROOT)/libgtest.a
@echo "[LD] $@"
- $(CXX) $(CPPFLAGS) $(CXXFLAGS) -L$(MLOG_DIR)/bin -Wl, $(RTE_LIBS) -lpthread -lnuma $^ -o $@
+ @$(CXX) $(CPPFLAGS) $(CXXFLAGS) -L$(MLOG_DIR)/bin -Wl, $(RTE_LIBS) -lpthread -lnuma -Wl,-lstdc++ $^ -o $@
/* wrapper function for performace tests to reset mbuf */
int xran_ut_prepare_cp(struct xran_cp_gen_params *params,
- uint8_t cc_id, uint8_t ant_id, uint8_t seq_id)
+ uint8_t cc_id, uint8_t ant_id, uint8_t seq_id, uint16_t start_sect_id)
{
- register int ret;
- register struct rte_mbuf *mbuf;
+ int ret;
+ struct rte_mbuf *mbuf;
mbuf = xran_ethdi_mbuf_alloc();
if(mbuf == NULL) {
return (-1);
}
- ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, ant_id, seq_id);
+ ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, ant_id, seq_id, start_sect_id);
rte_pktmbuf_free(mbuf);
return (ret);
int m_numSections;
struct rte_mbuf *m_pTestBuffer = nullptr;
+ struct xran_fh_config *m_fh_cfg;
+ struct xran_srs_config *m_srs_cfg;
+ struct xran_device_ctx m_xran_dev_ctx;
struct xran_cp_gen_params m_params;
struct xran_recv_packet_info m_pktInfo;
struct xran_cp_recv_params m_result;
+ struct xran_prb_elm *m_prb_ele = nullptr;
struct xran_sectionext1_info m_temp_ext1[XRAN_MAX_PRBS];
uint8_t m_scs;
uint16_t m_cpLength;
+ uint32_t mb_free = MBUF_FREE;
+
struct sectinfo *m_sections;
struct extcfginfo *m_extcfgs;
int m_nextcfgs;
m_dirStr = get_input_parameter<std::string>("direction");
+ memset(&m_xran_dev_ctx, 0, sizeof(struct xran_device_ctx));
+ m_srs_cfg = &m_xran_dev_ctx.srs_cfg;
+ m_fh_cfg = &m_xran_dev_ctx.fh_cfg;
+
if(!m_dirStr.compare("DL")) m_dir = XRAN_DIR_DL;
else if(!m_dirStr.compare("UL")) m_dir = XRAN_DIR_UL;
else FAIL() << "Invalid direction!";
m_compMethod = get_input_parameter<uint8_t>("comp_method");
m_iqWidth = get_input_parameter<uint8_t>("iq_width");
+ m_xran_dev_ctx.interval_us_local = get_input_parameter<uint8_t>("interval");
+ m_srs_cfg->eAxC_offset = XRAN_MAX_ANTENNA_NR;//m_antId + 4;
+ m_fh_cfg->neAxc = m_antId + 1;
+
switch(m_sectionType) {
case XRAN_CP_SECTIONTYPE_1:
m_filterIndex = XRAN_FILTERINDEX_STANDARD;
ext_type = get_input_parameter<int>("extensions", i, "type");
switch(ext_type) {
case XRAN_CP_SECTIONEXTCMD_1:
+ {
/* if section extension type 1 is present, then ignore other extensions */
if(i != 0 && m_nextcfgs != 1) {
std::cout << "### Extension 1 configuration, ignore other extensions !!\n" << std::endl;
m_extcfgs[i].u.ext1.bfwCompMeth = get_input_parameter<uint8_t> ("extensions", i, "bfwCompMeth");
m_extcfgs[i].u.ext1.bfwIqWidth = get_input_parameter<uint8_t> ("extensions", i, "bfwIqWidth");
m_antElmTRx = get_input_parameter<uint8_t> ("extensions", i, "antelm_trx");
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ p_xran_dev_ctx->numSetBFWs_arr[0] = m_numSections;
break;
-
+ }
case XRAN_CP_SECTIONEXTCMD_2:
m_extcfgs[i].u.ext2.bfAzPtWidth = get_input_parameter<uint8_t>("extensions", i, "bfAzPtWidth") & 0x7;
m_extcfgs[i].u.ext2.bfAzPt = get_input_parameter<uint8_t>("extensions", i, "bfAzPt") & 0xf;
m_extcfgs[i].u.ext6.symbolMask = get_input_parameter<uint16_t>("extensions", i, "symbolMask");
break;
+ case XRAN_CP_SECTIONEXTCMD_9:
+ {
+ m_extcfgs[i].u.ext9.technology = get_input_parameter<uint8_t> ("extensions", i, "technology");
+ m_xran_dev_ctx.dssPeriod = 1;
+ }
+ break;
case XRAN_CP_SECTIONEXTCMD_10:
m_extcfgs[i].u.ext10.numPortc = get_input_parameter<uint8_t> ("extensions", i, "numPortc");
m_extcfgs[i].u.ext10.beamGrpType= get_input_parameter<uint8_t> ("extensions", i, "beamGrpType");
m_pTestBuffer = nullptr;
}
+ if(m_prb_ele){
+ xran_free(m_prb_ele);
+ m_prb_ele = nullptr;
+ }
+
if(m_pBfwIQ_ext){
xran_free(m_pBfwIQ_ext);
m_pBfwIQ_ext = nullptr;
for(sect_num=0; sect_num < m_numSections; sect_num++) {
numext = 0;
- for(i=0; i < m_sections[sect_num].exts.size(); i++) {
+ for(i=0; i < (int)(m_sections[sect_num].exts.size()); i++) {
ext_id = m_sections[sect_num].exts[i];
if(ext_id >= m_nextcfgs) {
m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext6);
m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext6;
break;
+ case XRAN_CP_SECTIONEXTCMD_9:
+ m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext9);
+ m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext9;
+ break;
case XRAN_CP_SECTIONEXTCMD_10:
m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext10);
m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext10;
if(numext) {
m_params.sections[sect_num].exDataSize = numext;
- m_params.sections[sect_num].info.ef = 1;
+ m_params.sections[sect_num].info->ef = 1;
}
else {
m_params.sections[sect_num].exDataSize = 0;
- m_params.sections[sect_num].info.ef = 0;
+ m_params.sections[sect_num].info->ef = 0;
}
} /* for(sect_num=0; sect_num < m_numSections; sect_num++) */
}
for(numsec=0; numsec < m_numSections; numsec++) {
- m_params.sections[numsec].info.type = m_params.sectionType;
- m_params.sections[numsec].info.startSymId = m_params.hdr.startSymId;
- m_params.sections[numsec].info.iqWidth = m_params.hdr.iqWidth;
- m_params.sections[numsec].info.compMeth = m_params.hdr.compMeth;
- m_params.sections[numsec].info.id = m_sections[numsec].sectionId;
- m_params.sections[numsec].info.rb = m_sections[numsec].rb;
- m_params.sections[numsec].info.symInc = m_sections[numsec].symInc;
- m_params.sections[numsec].info.startPrbc = m_sections[numsec].startPrbc;
- m_params.sections[numsec].info.numPrbc = m_sections[numsec].numPrbc;
- m_params.sections[numsec].info.reMask = m_sections[numsec].reMask;
- m_params.sections[numsec].info.numSymbol = m_sections[numsec].numSymbol;
- m_params.sections[numsec].info.beamId = m_sections[numsec].beamId;
+ m_params.sections[numsec].info = new struct xran_section_info;
+ m_params.sections[numsec].info->type = m_params.sectionType;
+ m_params.sections[numsec].info->startSymId = m_params.hdr.startSymId;
+ m_params.sections[numsec].info->iqWidth = m_params.hdr.iqWidth;
+ m_params.sections[numsec].info->compMeth = m_params.hdr.compMeth;
+ m_params.sections[numsec].info->id = m_sections[numsec].sectionId;
+ m_params.sections[numsec].info->rb = m_sections[numsec].rb;
+ m_params.sections[numsec].info->symInc = m_sections[numsec].symInc;
+ m_params.sections[numsec].info->startPrbc = m_sections[numsec].startPrbc;
+ m_params.sections[numsec].info->numPrbc = m_sections[numsec].numPrbc;
+ m_params.sections[numsec].info->reMask = m_sections[numsec].reMask;
+ m_params.sections[numsec].info->numSymbol = m_sections[numsec].numSymbol;
+ m_params.sections[numsec].info->beamId = m_sections[numsec].beamId;
switch(m_sectionType) {
case XRAN_CP_SECTIONTYPE_1:
break;
case XRAN_CP_SECTIONTYPE_3:
- m_params.sections[numsec].info.freqOffset = m_sections[numsec].freqOffset;
+ m_params.sections[numsec].info->freqOffset = m_sections[numsec].freqOffset;
break;
default:
default:
FAIL() << "Invalid Section Type - " << m_sectionType << "\n";
}
-
+ // printf("m_result.numSections = %d , m_params.numSections = %d\n",m_result.numSections,i,m_params.numSections);
ASSERT_TRUE(m_result.numSections == m_params.numSections);
for(i=0; i < m_result.numSections; i++) {
- EXPECT_TRUE(m_result.sections[i].info.id == m_params.sections[i].info.id);
- EXPECT_TRUE(m_result.sections[i].info.rb == m_params.sections[i].info.rb);
- EXPECT_TRUE(m_result.sections[i].info.symInc == m_params.sections[i].info.symInc);
- EXPECT_TRUE(m_result.sections[i].info.startPrbc == m_params.sections[i].info.startPrbc);
- if(m_params.sections[i].info.numPrbc > 255)
+ // printf("m_result.sections[%d].info.id = %d , m_params.sections[%d].info.id = %d\n",i,m_result.sections[i].info.id,i,m_params.sections[i].info.id);
+ EXPECT_TRUE(m_result.sections[i].info.id == m_params.sections[i].info->id);
+ EXPECT_TRUE(m_result.sections[i].info.rb == m_params.sections[i].info->rb);
+ EXPECT_TRUE(m_result.sections[i].info.symInc == m_params.sections[i].info->symInc);
+ EXPECT_TRUE(m_result.sections[i].info.startPrbc == m_params.sections[i].info->startPrbc);
+ if(m_params.sections[i].info->numPrbc > 255)
EXPECT_TRUE(m_result.sections[i].info.numPrbc == 0);
else
- EXPECT_TRUE(m_result.sections[i].info.numPrbc == m_params.sections[i].info.numPrbc);
- EXPECT_TRUE(m_result.sections[i].info.numSymbol == m_params.sections[i].info.numSymbol);
- EXPECT_TRUE(m_result.sections[i].info.reMask == m_params.sections[i].info.reMask);
- EXPECT_TRUE(m_result.sections[i].info.beamId == m_params.sections[i].info.beamId);
- EXPECT_TRUE(m_result.sections[i].info.ef == m_params.sections[i].info.ef);
+ EXPECT_TRUE(m_result.sections[i].info.numPrbc == m_params.sections[i].info->numPrbc);
+ EXPECT_TRUE(m_result.sections[i].info.numSymbol == m_params.sections[i].info->numSymbol);
+ EXPECT_TRUE(m_result.sections[i].info.reMask == m_params.sections[i].info->reMask);
+ EXPECT_TRUE(m_result.sections[i].info.beamId == m_params.sections[i].info->beamId);
+ EXPECT_TRUE(m_result.sections[i].info.ef == m_params.sections[i].info->ef);
switch(m_sectionType) {
case XRAN_CP_SECTIONTYPE_1:
break;
case XRAN_CP_SECTIONTYPE_3:
- EXPECT_TRUE(m_result.sections[i].info.freqOffset == m_params.sections[i].info.freqOffset);
+ EXPECT_TRUE(m_result.sections[i].info.freqOffset == m_params.sections[i].info->freqOffset);
break;
default:
FAIL() << "Invalid Section Type - " << m_sectionType << "\n";
}
- if(m_params.sections[i].info.ef) {
+ if(m_params.sections[i].info->ef) {
//printf("[%d] %d == %d\n",i, m_result.sections[i].exDataSize, m_params.sections[i].exDataSize);
EXPECT_TRUE(m_result.sections[i].numExts == m_params.sections[i].exDataSize);
- for(j=0; j < m_params.sections[i].exDataSize; j++) {
+ for(j=0; j < (int)m_params.sections[i].exDataSize; j++) {
EXPECT_TRUE(m_result.sections[i].exts[j].type == m_params.sections[i].exData[j].type);
switch(m_params.sections[i].exData[j].type) {
EXPECT_TRUE(ext6_result->symbolMask == ext6_params->symbolMask);
}
break;
+ case XRAN_CP_SECTIONEXTCMD_9:
+ {
+ struct xran_sectionext9_info *ext9_params, *ext9_result;
+
+ ext9_params = (struct xran_sectionext9_info *)m_params.sections[i].exData[j].data;
+ ext9_result = &m_result.sections[i].exts[j].u.ext9;
+ EXPECT_TRUE(ext9_result->technology == ext9_params->technology);
+ }
+ break;
case XRAN_CP_SECTIONEXTCMD_10:
{
struct xran_sectionext10_info *ext10_params, *ext10_result;
}
}
}
+ if(m_params.sections[i].info != NULL)
+ delete m_params.sections[i].info;
}
return;
int32_t nAntElm = 64;
int8_t iqWidth = 9;
int8_t compMethod = XRAN_COMPMETHOD_BLKFLOAT;
+ int numSections = 0;
int8_t *p_ext1_dst = NULL;
int8_t *bfw_payload = NULL;
- int32_t expected_len = ((nAntElm/16*4*iqWidth)+1)*nRbs + /* bfwCompParam + IQ = */
- sizeof(struct xran_cp_radioapp_section_ext1)*nRbs; /* ext1 Headers */
+ // int32_t expected_len = ((nAntElm/16*4*iqWidth)+1)*nRbs + /* bfwCompParam + IQ = */
+ // sizeof(struct xran_cp_radioapp_section_ext1)*nRbs; /* ext1 Headers */
int16_t ext_len = 9600;
int16_t ext_sec_total = 0;
struct xran_section_gen_info* loc_pSectGenInfo = m_params.sections;
struct xran_sectionext1_info m_prep_ext1;
struct xran_cp_radioapp_section_ext1 *p_ext1;
+ struct xran_cp_radioapp_section1 *p_section1;
struct rte_mbuf_ext_shared_info share_data;
struct rte_mbuf *mbuf = NULL;
+ struct xran_sectionext1_info ext1;
nAntElm = m_antElmTRx;
- nRbs = m_params.sections[0].info.numPrbc;
+ nRbs = m_params.sections[0].info->numPrbc;
iqWidth = m_extcfgs[0].u.ext1.bfwIqWidth;
compMethod = m_extcfgs[0].u.ext1.bfwCompMeth;
+ numSections = m_numSections;
+#if 0
switch(compMethod) {
case XRAN_BFWCOMPMETHOD_NONE:
- expected_len = (3+1)*nRbs + nAntElm*nRbs*4;
+ // expected_len = (3+1)*nRbs + nAntElm*nRbs*4;
+ expected_len = sizeof(struct xran_cp_radioapp_section1)*numSections + \
+ sizeof(struct xran_cp_radioapp_section_ext1)*numSections + \
+ nAntElm*numSections*4;
break;
case XRAN_BFWCOMPMETHOD_BLKFLOAT:
- expected_len = ((nAntElm/16*4*iqWidth)+1)*nRbs + /* bfwCompParam + IQ = */
- sizeof(struct xran_cp_radioapp_section_ext1)*nRbs; /* ext1 Headers */
+ expected_len = ((nAntElm/16*iqWidth)+1)*numSections*4 + /* bfwCompParam + IQ = */
+ sizeof(struct xran_cp_radioapp_section1)*numSections + \
+ sizeof(struct xran_cp_radioapp_section_ext1)*numSections; /* ext1 Headers */
break;
default:
FAIL() << "Unsupported Compression Method - " << compMethod << std::endl;
}
+#endif
- if(loc_pSectGenInfo->info.type == XRAN_CP_SECTIONTYPE_1) {
- /* extType 1 only with Section 1 for now */
-
+ if(loc_pSectGenInfo->info->type == XRAN_CP_SECTIONTYPE_1) {
ext_buf = ext_buf_init = (int8_t*) xran_malloc(ext_len);
if (ext_buf) {
ptr = m_p_bfw_iq_src;
ext_buf += (RTE_PKTMBUF_HEADROOM +
sizeof (struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_common_header) +
- sizeof(struct xran_cp_radioapp_section1));
+ sizeof(struct xran_cp_radioapp_common_header));
ext_len -= (RTE_PKTMBUF_HEADROOM +
sizeof(struct xran_ecpri_hdr) +
- sizeof(struct xran_cp_radioapp_common_header) +
- sizeof(struct xran_cp_radioapp_section1));
+ sizeof(struct xran_cp_radioapp_common_header));
+ m_prb_ele = (xran_prb_elm *) xran_malloc(sizeof(struct xran_prb_elm));
+
+ m_prb_ele->bf_weight.bfwIqWidth = iqWidth;
+ m_prb_ele->bf_weight.bfwCompMeth = compMethod;
+ m_prb_ele->bf_weight.numSetBFWs = numSections;
+ m_prb_ele->bf_weight.nAntElmTRx = nAntElm;
ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
ext_len,
m_p_bfw_iq_src,
- nRbs,
- nAntElm,
- iqWidth,
- compMethod);
+ m_prb_ele);
- ASSERT_TRUE(ext_sec_total == expected_len);
+ // ASSERT_TRUE(ext_sec_total == expected_len);
p_ext1_dst = ext_buf;
memset(&m_temp_ext1[0], 0, sizeof (struct xran_sectionext1_info)*XRAN_MAX_PRBS);
idRb = 0;
do {
- p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst;
+ p_section1 = (struct xran_cp_radioapp_section1 *)p_ext1_dst;
+ p_ext1 = (struct xran_cp_radioapp_section_ext1 *)(p_section1+1);
bfw_payload = (int8_t*)(p_ext1+1);
- p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+ m_pSectGenInfo[idRb].info->id = idRb;
- m_temp_ext1[idRb].bfwNumber = nAntElm;
- m_temp_ext1[idRb].bfwIqWidth = iqWidth;
- m_temp_ext1[idRb].bfwCompMeth = compMethod;
+ m_pSectGenInfo[idRb].exData[0].type = XRAN_CP_SECTIONEXTCMD_1;
+ m_pSectGenInfo[idRb].exData[0].len = sizeof(ext1);
- if(compMethod == XRAN_BFWCOMPMETHOD_BLKFLOAT) {
- m_temp_ext1[idRb].bfwCompParam.exponent = *bfw_payload++ & 0xF;
- }
- m_temp_ext1[idRb].p_bfwIQ = (int16_t*)bfw_payload;
- m_temp_ext1[idRb].bfwIQ_sz = p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+ m_pSectGenInfo[idRb].info->ef = 1;
+ m_pSectGenInfo[idRb].exDataSize = 1;
- loc_pSectGenInfo->exData[idRb].type = XRAN_CP_SECTIONEXTCMD_1;
- loc_pSectGenInfo->exData[idRb].len = sizeof(m_temp_ext1[idRb]);
- loc_pSectGenInfo->exData[idRb].data = &m_temp_ext1[idRb];
+ p_ext1_dst += sizeof(struct xran_cp_radioapp_section1) /*+ sizeof(struct xran_cp_radioapp_section_ext1)*/ + p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+ m_temp_ext1[0].bfwNumber = nAntElm;
+ m_temp_ext1[0].bfwIqWidth = iqWidth;
+ m_temp_ext1[0].bfwCompMeth = compMethod;
+ m_temp_ext1[0].p_bfwIQ = (int8_t*)bfw_payload;
+ m_temp_ext1[0].bfwIQ_sz = p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+ if(compMethod == XRAN_BFWCOMPMETHOD_BLKFLOAT) {
+ m_temp_ext1[0].bfwCompParam.exponent = *bfw_payload++ & 0xF;
+ }
+ m_pSectGenInfo[idRb].exData[0].data = &m_temp_ext1[0];
idRb++;
- } while(p_ext1->ef != XRAN_EF_F_LAST);
+ } while(idRb < numSections); /*p_ext1->ef != XRAN_EF_F_LAST);*/
- ASSERT_TRUE(idRb == nRbs);
+ ASSERT_TRUE(idRb == numSections);
mbuf = xran_attach_cp_ext_buf(0, ext_buf_init, ext_buf, ext_sec_total, &share_data);
-
- /* Update section information */
- memset(&m_prep_ext1, 0, sizeof (struct xran_sectionext1_info));
- m_prep_ext1.bfwNumber = nAntElm;
- m_prep_ext1.bfwIqWidth = iqWidth;
- m_prep_ext1.bfwCompMeth = compMethod;
- m_prep_ext1.p_bfwIQ = (int16_t*)ext_buf;
- m_prep_ext1.bfwIQ_sz = ext_sec_total;
-
-
- loc_pSectGenInfo->exData[0].type = XRAN_CP_SECTIONEXTCMD_1;
- loc_pSectGenInfo->exData[0].len = sizeof(m_prep_ext1);
- loc_pSectGenInfo->exData[0].data = &m_prep_ext1;
-
- loc_pSectGenInfo->info.ef = 1;
- loc_pSectGenInfo->exDataSize = 1; /* append all extType1 as one shot
- (as generated via xran_cp_populate_section_ext_1)*/
-
- m_params.numSections = 1;
+ m_params.numSections = numSections;
/* Generating C-Plane packet */
- ASSERT_TRUE(xran_prepare_ctrl_pkt(/*m_pTestBuffer*/mbuf, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
-
- /** to match O-RU parsing */
- loc_pSectGenInfo->exDataSize = nRbs;
- loc_pSectGenInfo->exData[0].len = sizeof(m_temp_ext1[0]);
- loc_pSectGenInfo->exData[0].data = &m_temp_ext1[0];
-
- /* Parsing generated packet */
- EXPECT_TRUE(xran_parse_cp_pkt(/*m_pTestBuffer*/mbuf, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS);
+ ASSERT_TRUE(xran_prepare_ctrl_pkt(/*m_pTestBuffer*/mbuf, &m_params, m_ccId, m_antId, m_seqId, 0) == XRAN_STATUS_SUCCESS);
+ EXPECT_TRUE(xran_parse_cp_pkt(/*m_pTestBuffer*/mbuf, &m_result, &m_pktInfo, (void *)&m_xran_dev_ctx, &mb_free) == XRAN_STATUS_SUCCESS);
}
else {
FAIL() << "xran_malloc failed\n";
ASSERT_FALSE(m_pTestBuffer == nullptr);
}
+ xran_cp_init_sectiondb((void *)&m_xran_dev_ctx);
/* Generating C-Plane packet */
- ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
+ ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId, 0) == XRAN_STATUS_SUCCESS);
/* Linearize data in the chain of mbufs to parse generated packet*/
ASSERT_TRUE(rte_pktmbuf_linearize(m_pTestBuffer) == 0);
-
/* Parsing generated packet */
- EXPECT_TRUE(xran_parse_cp_pkt(m_pTestBuffer, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS);
+ EXPECT_TRUE(xran_parse_cp_pkt(m_pTestBuffer, &m_result, &m_pktInfo, (void *)&m_xran_dev_ctx, &mb_free) == XRAN_STATUS_SUCCESS);
/* Verify the result */
verify_sections();
FAIL() << "Invalid Section extension configuration\n";
}
+ xran_cp_init_sectiondb((void *)&m_xran_dev_ctx);
/* using wrapper function to reset mbuf */
performance("C", module_name,
- &xran_ut_prepare_cp, &m_params, m_ccId, m_antId, m_seqId);
+ &xran_ut_prepare_cp, &m_params, m_ccId, m_antId, m_seqId, 0);
}
return;
}
+void utcp_fh_bfw_callback(void *pCallbackTag, xran_status_t status)
+{
+ return;
+}
+
void utcp_fh_srs_callback(void *pCallbackTag, xran_status_t status)
{
return;
{
xranlib->Init(0, &m_xranConf);
xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_bfw_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_cp_dl);
{
xranlib->Init(0, &m_xranConf);
xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_bfw_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_cp_ul);
/* need to disable CP to make U-Plane work without CP */
xranlib->apply_cpenable(false);
xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_bfw_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_up_dl);
/* Enable CP by force to make UP work by CP's section information */
xranlib->apply_cpenable(true);
xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_bfw_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_cpup_dl);
expandedData.dataExpanded = &loc_dataExpandedIn[0];
BlockFloatCompander::ExpandedData expandedDataRes;
expandedDataRes.dataExpanded = &loc_dataExpandedRes[0];
- for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
- for (int tc = 0; tc < sizeof(numRBs)/sizeof(numRBs[0]); tc ++){
+ for (unsigned int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
+ for (unsigned int tc = 0; tc < sizeof(numRBs)/sizeof(numRBs[0]); tc ++){
//printf("[%d]numRBs %d [%d] iqWidth %d\n",tc, numRBs[tc], iq_w_id, iqWidth[iq_w_id]);
// Generate random test data for compression kernel
expandedData.dataExpanded = &loc_dataExpandedIn[0];
BlockFloatCompander::ExpandedData expandedDataRes;
expandedDataRes.dataExpanded = &loc_dataExpandedRes[0];
- for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
- for (int tc = 0; tc < sizeof(numRBs)/sizeof(numRBs[0]); tc ++){
+ for (unsigned int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
+ for (unsigned int tc = 0; tc < sizeof(numRBs)/sizeof(numRBs[0]); tc ++){
//printf("[%d]numRBs %d [%d] iqWidth %d\n",tc, numRBs[tc], iq_w_id, iqWidth[iq_w_id]);
// Generate random test data for compression kernel
BlockFloatCompander::ExpandedData expandedDataRes;
expandedDataRes.dataExpanded = &loc_dataExpandedRes[0];
- for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
- for (int tc = 0; tc < sizeof(antElm)/sizeof(antElm[0]); tc ++){
+ for (unsigned int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
+ for (unsigned int tc = 0; tc < sizeof(antElm)/sizeof(antElm[0]); tc ++){
numDataElements = 2*antElm[tc];
if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52) == 0)
return;
- for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
- for (int tc = 0; tc < sizeof(antElm)/sizeof(antElm[0]); tc ++){
+ for (unsigned int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
+ for (unsigned int tc = 0; tc < sizeof(antElm)/sizeof(antElm[0]); tc ++){
numDataElements = 2*antElm[tc];
"dpdkBasebandFecMode": 0,
"dpdkBasebandDevice": "",
"dpdkMemorySize": 8192,
- "mtu": 1500,
+ "mtu": 9600,
"o_du_macaddr": "00:11:22:33:44:66",
"o_ru_macaddr": "00:11:22:33:44:55",
"cp_vlan_tag": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 6,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 5,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 5,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 1,
"iq_width": 9,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 1,
"iq_width": 9,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"symbol_start": 0,
"comp_method": 0,
"iq_width": 16,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
"fft_size": 10,
"scs": 3,
"cp_length": 0,
+ "interval": 500,
"sections": [
{
"sectionId": 1,
}
]
}
+ },
+ {
+ "name": "DL_SectionType1_SingleSection_Ext9",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 0,
+ "comp_method": 0,
+ "iq_width": 16,
+ "interval": 500,
+ "sections": [
+ {
+ "sectionId": 0,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 273,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0,
+ "exts": [ 0 ]
+ }
+ ],
+ "extensions": [
+ {
+ "name": "ext9",
+ "type": 9,
+ "technology": 1
+ }
+ ]
+ }
}
],
"dpdkBasebandDevice": "none",
"filePrefix": "wls",
"xranCat": 0,
- "mtu": 1500,
+ "mtu": 9600,
"p_o_du_addr": "00:11:22:33:44:66",
"p_o_ru_addr": "00:11:22:33:44:55",
"Tadv_cp_dl": 0,
"antId": 0,
"iqWidth": 16,
"compMeth": 0,
- "fftSize": 10
+ "fftSize": 10,
+ "dssperiod": 1
},
"references": {
"slotId": 0,
"beamId": 0,
"ccId": 0,
- "antId": 0
+ "antId": 0,
+ "dssperiod": 1
},
"references": {
return;
}
+void xran_fh_bfw_callback(void *pCallbackTag, xran_status_t status)
+{
+ rte_pause();
+ return;
+}
+
void xran_fh_srs_callback(void *pCallbackTag, xran_status_t status)
{
rte_pause();
void SetUp() override
{
xranlib->Init(0);
- xranlib->Open(0, nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_rx_prach_callback, (void *)xran_fh_srs_callback);
+ xranlib->Open(0, nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_bfw_callback, (void *)xran_fh_rx_prach_callback, (void *)xran_fh_srs_callback);
}
/* It's called after an execution of the each test case.*/
BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ BbuIoBufCtrlStruct sFHCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ BbuIoBufCtrlStruct sFHCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
/* buffers lists */
struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
int16_t ret = 0;
ret = xran_reg_physide_cb(xranlib->get_xranhandle(), physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
ASSERT_EQ(0,ret);
- ASSERT_EQ(physide_dl_tti_call_back, p_xran_dev_ctx->ttiCb[XRAN_CB_TTI]);
+ ASSERT_EQ((long long)physide_dl_tti_call_back, (long long)p_xran_dev_ctx->ttiCb[XRAN_CB_TTI]);
ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_TTI]);
ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_TTI]);
ret = xran_reg_physide_cb(xranlib->get_xranhandle(), physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);
ASSERT_EQ(0,ret);
- ASSERT_EQ(physide_ul_half_slot_call_back, p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]);
- ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]);
+ ASSERT_EQ((long long)physide_ul_half_slot_call_back, (long long)p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]);
+ ASSERT_EQ((long long)NULL, (long long)p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]);
ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX]);
ret = xran_reg_physide_cb(xranlib->get_xranhandle(), physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX);
ASSERT_EQ(0,ret);
- ASSERT_EQ(physide_ul_full_slot_call_back, p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX]);
+ ASSERT_EQ((long long)physide_ul_full_slot_call_back,(long long) p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX]);
ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_FULL_SLOT_RX]);
ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_FULL_SLOT_RX]);
class PrachCheck : public KernelTests
{
private:
- struct xran_section_gen_info *m_pSectResult = NULL;
+ struct xran_section_recv_info *m_pSectResult = NULL; /*Not used*/
protected:
struct xran_fh_config *m_xranConf;
m_pRUConfig = &m_xranConf->ru_conf;
m_pPrachCPConfig = &m_xran_dev_ctx.PrachCPConfig;
//initialize input parameters
+ m_xran_dev_ctx.dssPeriod = get_input_parameter<uint8_t>("dssperiod");
m_xranConf->frame_conf.nNumerology = get_input_parameter<uint8_t>("Numerology");
m_xranConf->frame_conf.nFrameDuplexType = get_input_parameter<uint8_t>("FrameDuplexType");
m_xranConf->log_level = get_input_parameter<uint32_t>("loglevel");
m_pSectGenInfo = new struct xran_section_gen_info[8];
ASSERT_NE(m_pSectGenInfo, nullptr);
m_params.sections = m_pSectGenInfo;
+ m_params.sections[0].info = new struct xran_section_info;
/* allocating an mbuf for packet generatrion */
m_pTestBuffer = (struct rte_mbuf*)rte_pktmbuf_alloc(_eth_mbuf_pool);
void *pHandle = NULL;
/* Preparing input data for prach config */
- ret = xran_init_prach(m_xranConf, &m_xran_dev_ctx);
+ ret = xran_init_prach(m_xranConf, &m_xran_dev_ctx, XRAN_RAN_5GNR);
ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS);
/* Verify the result */
ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS);
ret = generate_cpmsg_prach(&m_xran_dev_ctx, &m_params, m_pSectGenInfo, m_pTestBuffer, &m_xran_dev_ctx,
- m_frameId, m_subframeId, m_slotId,
+ m_frameId, m_subframeId, m_slotId, 0,
m_beamId, m_ccId, m_antId, 0, 0);
ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS);
/* Verify the result */
EXPECT_EQ(m_params.hdr.cpLength, 0);
EXPECT_EQ(m_params.numSections, 1);
- EXPECT_EQ(m_params.sections[0].info.type, XRAN_CP_SECTIONTYPE_3);
- EXPECT_EQ(m_params.sections[0].info.startSymId, m_startSymId);
- EXPECT_EQ(m_params.sections[0].info.iqWidth, (m_pRUConfig->iqWidth==16)?0:m_pRUConfig->iqWidth);
- EXPECT_EQ(m_params.sections[0].info.compMeth, m_pRUConfig->compMeth);
-
- EXPECT_EQ(m_params.sections[0].info.id, m_id);
- EXPECT_EQ(m_params.sections[0].info.rb, XRAN_RBIND_EVERY);
- EXPECT_EQ(m_params.sections[0].info.symInc, XRAN_SYMBOLNUMBER_NOTINC);
- EXPECT_EQ(m_params.sections[0].info.startPrbc, m_startPrbc);
- EXPECT_EQ(m_params.sections[0].info.numPrbc, m_numPrbc);
- EXPECT_EQ(m_params.sections[0].info.numSymbol, m_numSymbol);
- EXPECT_EQ(m_params.sections[0].info.reMask, 0xfff);
- EXPECT_EQ(m_params.sections[0].info.beamId, m_beamId);
- EXPECT_EQ(m_params.sections[0].info.freqOffset, m_freqOffset);
+ EXPECT_EQ(m_params.sections[0].info->type, XRAN_CP_SECTIONTYPE_3);
+ EXPECT_EQ(m_params.sections[0].info->startSymId, m_startSymId);
+ EXPECT_EQ(m_params.sections[0].info->iqWidth, (m_pRUConfig->iqWidth==16)?0:m_pRUConfig->iqWidth);
+ EXPECT_EQ(m_params.sections[0].info->compMeth, m_pRUConfig->compMeth);
+
+ EXPECT_EQ(m_params.sections[0].info->id, m_id);
+ EXPECT_EQ(m_params.sections[0].info->rb, XRAN_RBIND_EVERY);
+ EXPECT_EQ(m_params.sections[0].info->symInc, XRAN_SYMBOLNUMBER_NOTINC);
+ EXPECT_EQ(m_params.sections[0].info->startPrbc, m_startPrbc);
+ EXPECT_EQ(m_params.sections[0].info->numPrbc, m_numPrbc);
+ EXPECT_EQ(m_params.sections[0].info->numSymbol, m_numSymbol);
+ EXPECT_EQ(m_params.sections[0].info->reMask, 0xfff);
+ EXPECT_EQ(m_params.sections[0].info->beamId, m_beamId);
+ EXPECT_EQ(m_params.sections[0].info->freqOffset, m_freqOffset);
EXPECT_EQ(m_xran_dev_ctx.prach_last_symbol[m_ccId], m_prach_last_symbol);
- EXPECT_EQ(m_params.sections[0].info.ef, 0);
+ EXPECT_EQ(m_params.sections[0].info->ef, 0);
EXPECT_EQ(m_params.sections[0].exDataSize, 0);
+ if(m_params.sections[0].info != NULL)
+ delete[] m_params.sections[0].info;
}
class PrachPerf : public KernelTests
{
- private:
- struct xran_section_gen_info *m_pSectResult = NULL;
+ // private:
+ // struct xran_section_recv_info *m_pSectResult = NULL; /*Not used*/
protected:
struct xran_fh_config m_xranConf;
m_xranConf.frame_conf.nFrameDuplexType = get_input_parameter<uint8_t>("FrameDuplexType");
m_xranConf.log_level = get_input_parameter<uint32_t>("loglevel");
+ m_xran_dev_ctx.dssPeriod = get_input_parameter<uint8_t>("dssperiod");
m_pPRACHConfig->nPrachConfIdx = get_input_parameter<uint8_t>("PrachConfIdx");
m_pPRACHConfig->nPrachFreqStart = get_input_parameter<uint16_t>("PrachFreqStart");
m_pPRACHConfig->nPrachFreqOffset = get_input_parameter<int32_t>("PrachFreqOffset");
m_pSectGenInfo = new struct xran_section_gen_info[8];
ASSERT_NE(m_pSectGenInfo, nullptr);
m_params.sections = m_pSectGenInfo;
+ m_params.sections[0].info = new xran_section_info;
/* allocating an mbuf for packet generatrion */
m_pTestBuffer = (struct rte_mbuf*)rte_pktmbuf_alloc(_eth_mbuf_pool);
mbuf = (struct rte_mbuf*)rte_pktmbuf_alloc(_eth_mbuf_pool);
generate_cpmsg_prach(pxran_lib_ctx, params, sect_geninfo, mbuf, pxran_lib_ctx,
- frame_id, subframe_id, slot_id,
+ frame_id, subframe_id, slot_id, 0,
beam_id, cc_id, prach_port_id, 0, seq_id);
seq_id++;
void *pHandle = NULL;
/* Preparing input data for prach config */
- ret = xran_init_prach(&m_xranConf, &m_xran_dev_ctx);
+ ret = xran_init_prach(&m_xranConf, &m_xran_dev_ctx, XRAN_RAN_5GNR);
ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS);
ret = generate_cpmsg_prach(&m_xran_dev_ctx, &m_params, m_pSectGenInfo, m_pTestBuffer, &m_xran_dev_ctx,
- m_frameId, m_subframeId, m_slotId,
+ m_frameId, m_subframeId, m_slotId, 0,
m_beamId, m_ccId, m_antId, 0, 0);
ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS);
&performance_cp, pHandle, &m_params, m_pSectGenInfo, &m_xran_dev_ctx,
m_frameId, m_subframeId, m_slotId,
m_beamId, m_ccId, m_antId, 0);
+
+ if(m_params.sections[0].info)
+ delete[] m_params.sections[0].info;
}
{
enum xran_pkt_dir direction = XRAN_DIR_DL;
uint16_t section_id = 7;
+ uint16_t num_sections = 1;
enum xran_input_byte_order iq_buf_byte_order = XRAN_CPU_LE_BYTE_ORDER;
uint8_t frame_id = 99;
uint8_t subframe_id = 9;
RU_Port_ID,
seq_id,
do_copy,
- staticEn);
+ staticEn,
+ num_sections,
+ 0);
ASSERT_EQ(prep_bytes, 3168);
{
enum xran_pkt_dir direction = XRAN_DIR_DL;
uint16_t section_id = 7;
+ uint16_t num_sections = 1;
enum xran_input_byte_order iq_buf_byte_order = XRAN_CPU_LE_BYTE_ORDER;
uint8_t frame_id = 99;
uint8_t subframe_id = 9;
enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC;
uint8_t iqWidth = 16;
- int32_t prep_bytes;
- prep_bytes = prepare_symbol_ex(direction,
+ prepare_symbol_ex(direction,
section_id,
test_buffer,
(uint8_t *)iq_offset,
RU_Port_ID,
seq_id,
do_copy,
- staticEn);
+ staticEn,
+ num_sections,
+ 0);
/*union xran_cp_radioapp_section_ext11 *ext11 = NULL;
struct xran_sectionext11_info *params = NULL;
#!/bin/bash
-export DIR_ROOT=/home/
+export DIR_ROOT=$HOME
#set the L1 binary root DIR
export DIR_ROOT_L1_BIN=$DIR_ROOT/FlexRAN
#set the phy root DIR
export DIR_ROOT_PHY=$DIR_ROOT/phy
#set the DPDK root DIR
-#export DIR_ROOT_DPDK=/home/dpdk-19.11
+export DIR_ROOT_DPDK=/$DIR_ROOT/dpdk
#set the GTEST root DIR
#export DIR_ROOT_GTEST=/home/gtest/gtest-1.7.0
export XRAN_DIR=$DIR_ROOT_PHY/fhi_lib
export XRAN_LIB_SO=true
export RTE_TARGET=x86_64-native-linuxapp-icc
-#export RTE_SDK=$DIR_ROOT_DPDK
-#export DESTDIR=""
+export RTE_SDK=$DIR_ROOT_DPDK
+export DESTDIR=$DIR_ROOT_DPDK
+#Uncomment to run tests - it's commented to make builds faster.
#export GTEST_ROOT=$DIR_ROOT_GTEST
export ORAN_5G_FAPI=true
##############################################################
# Tools configuration
##############################################################
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
CC := icc
+ CPP := icpc
AS := as
AR := ar
LD := icc
-OBJDUMP := objdump
-
-ifeq ($(SHELL),cmd.exe)
-MD := mkdir.exe -p
-CP := cp.exe -f
-RM := rm.exe -rf
+else ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ CC := icx
+ CPP := icx
+ AS := as
+ AR := ar
+ LD := icx
else
+ $(error "Please define WIRELESS_SDK_TOOLCHAIN environment variable")
+endif
+
+ifeq ($(WIRELESS_SDK_TARGET_ISA),sse)
+ TARGET_PROCESSOR := -xSSE4.2
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx2)
+ TARGET_PROCESSOR := -xCORE-AVX2
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx512)
+ TARGET_PROCESSOR := -xCORE-AVX512
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),snc)
+ TARGET_PROCESSOR := -xicelake-server
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),spr)
+ TARGET_PROCESSOR := -march=sapphirerapids
+endif
+
+ifeq ($(TARGET_PROCESSOR),)
+ $(error "Please define valid WIRELESS_SDK_TARGET_ISA environment variable $(WIRELESS_SDK_TARGET_ISA)")
+endif
+
+OBJDUMP := objdump
MD := mkdir -p
CP := cp -f
RM := rm -rf
-endif
PROJECT_NAME := libwls
PROJECT_TYPE := lib
$(error "Please define RTE_SDK environment variable")
endif
-ifeq ($(MESON_BUILD),0)
-RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include
-else
-RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk)
-endif
+RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk)
CC_SRC = wls_lib_dpdk.c \
syslib.c
-fPIC \
-Wall \
-Wimplicit-function-declaration \
- -g -O3 -wd1786 -mcmodel=large
+ -g -O3 -mcmodel=large $(TARGET_PROCESSOR)
INC := -I$(RTE_INC)
DEF :=
##############################################################
# Tools configuration
##############################################################
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icc)
CC := icc
+ CPP := icpc
AS := as
AR := ar
LD := icc
-OBJDUMP := objdump
-
-ifeq ($(SHELL),cmd.exe)
-MD := mkdir.exe -p
-CP := cp.exe -f
-RM := rm.exe -rf
+else ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+ CC := icx
+ CPP := icx
+ AS := as
+ AR := ar
+ LD := icx
else
+ $(error "Please define WIRELESS_SDK_TOOLCHAIN environment variable")
+endif
+
+ifeq ($(WIRELESS_SDK_TARGET_ISA),sse)
+ TARGET_PROCESSOR := -xSSE4.2
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx2)
+ TARGET_PROCESSOR := -xCORE-AVX2
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),avx512)
+ TARGET_PROCESSOR := -xCORE-AVX512
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),snc)
+ TARGET_PROCESSOR := -xicelake-server
+else ifeq ($(WIRELESS_SDK_TARGET_ISA),spr)
+ TARGET_PROCESSOR := -march=sapphirerapids
+endif
+
+ifeq ($(TARGET_PROCESSOR),)
+ $(error "Please define valid WIRELESS_SDK_TARGET_ISA environment variable $(WIRELESS_SDK_TARGET_ISA)")
+endif
+
+OBJDUMP := objdump
MD := mkdir -p
CP := cp -f
RM := rm -rf
-endif
PROJECT_NAME := wls_test
PROJECT_TYPE := elf
$(error "Please define RTE_SDK environment variable")
endif
-ifeq ($(MESON_BUILD),0)
-RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include
-RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_mempool_ring -Wl,-lrte_pci -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_net -Wl,-lrte_distributor -Wl,-lrte_reorder -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_jobstats -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lrte_vhost -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_cryptodev -Wl,-lrte_mempool -Wl,-lrte_ring -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_null -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
-RTE_LIBS += -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--no-whole-archive
-else
-RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk)
-RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive
-endif
+RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --static --libs libdpdk) -Wl,--no-whole-archive
+RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk)
CC_SRC = pool.c \
testapp.c
-g \
-Wall \
-Wimplicit-function-declaration \
- -g -O3 -wd1786 -mcmodel=large
+ -g -O3 -mcmodel=large $(TARGET_PROCESSOR)
INC := -I../ -I$(RTE_INC)
DEF :=
LD_FLAGS += $(RTE_LIBS)
+ifeq ($(WIRELESS_SDK_TOOLCHAIN),icx)
+LD_FLAGS += -Wl,-lstdc++
+endif
+
AS_FLAGS :=
AR_FLAGS := rc
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (c) 2019 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
-#include <stdio.h>
-#include <unistd.h>
-#include <sys/mman.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <pthread.h>
-
-#include <sys/ipc.h>
-#include <sys/shm.h>
-
-#include "ttypes.h"
-#include "wls_lib.h"
-#include "wls.h"
-#include "syslib.h"
-
-#define WLS_MAP_SHM 1
-
-#define WLS_PHY_SHM_FILE_NAME "/tmp/phyappshm"
-
-#define HUGE_PAGE_FILE_NAME "/mnt/huge/page"
-
-#define DIV_ROUND_OFFSET(X,Y) ( X/Y + ((X%Y)?1:0) )
-
-#define WLS_LIB_USER_SPACE_CTX_SIZE DMA_MAP_MAX_BLOCK_SIZE
-
-#define PLIB_ERR(x, args...) printf("wls_lib: "x, ## args);
-#define PLIB_INFO(x, args...) printf("wls_lib: "x, ## args);
-
-#ifdef _DEBUG_
-#define PLIB_DEBUG(x, args...) printf("wls_lib debug: "x, ## args);
-#else
-#define PLIB_DEBUG(x, args...) do { } while(0)
-#endif
-
-#ifdef __x86_64__
-#define WLS_LIB_MMAP mmap
-#else
-#define WLS_LIB_MMAP mmap64
-#endif
-
-extern int gethugepagesizes(long pagesizes[], int n_elem);
-extern int hugetlbfs_unlinked_fd(void);
-
-
-static pthread_mutex_t wls_put_lock;
-static pthread_mutex_t wls_get_lock;
-
-static int wls_dev_fd = 0;
-static wls_us_ctx_t* wls_us_ctx = NULL;
-
-static uint64_t wls_kernel_va_to_user_va(void *pWls_us, uint64_t ptr);
-
-int ipc_file = 0;
-
-static int wls_VirtToPhys(void* virtAddr, uint64_t* physAddr)
-{
- int mapFd;
- uint64_t page;
- unsigned int pageSize;
- unsigned long virtualPageNumber;
-
- mapFd = open ("/proc/self/pagemap" , O_RDONLY );
- if (mapFd < 0 )
- {
- PLIB_ERR("Could't open pagemap file\n");
- return -1;
- }
-
- /*get standard page size*/
- pageSize = getpagesize();
-
- virtualPageNumber = (unsigned long) virtAddr / pageSize ;
-
- lseek(mapFd , virtualPageNumber * sizeof(uint64_t) , SEEK_SET );
-
- if(read(mapFd ,&page , sizeof(uint64_t)) < 0 )
- {
- close(mapFd);
- PLIB_ERR("Could't read pagemap file\n");
- return -1;
- }
-
- *physAddr = (( page & 0x007fffffffffffffULL ) * pageSize );
-
- close(mapFd);
-
- return 0;
-}
-
-static void wls_mutex_destroy(pthread_mutex_t* pMutex)
-{
- pthread_mutex_destroy(pMutex);
-}
-
-static void wls_mutex_init(pthread_mutex_t* pMutex)
-{
- pthread_mutexattr_t prior;
- pthread_mutexattr_init(&prior);
- pthread_mutexattr_setprotocol(&prior, PTHREAD_PRIO_INHERIT);
- pthread_mutex_init(pMutex, &prior);
- pthread_mutexattr_destroy(&prior);
-}
-
-static void wls_mutex_lock(pthread_mutex_t* pMutex)
-{
- pthread_mutex_lock(pMutex);
-}
-
-static void wls_mutex_unlock(pthread_mutex_t* pMutex)
-{
- pthread_mutex_unlock(pMutex);
-}
-
-static uint64_t wls_kernel_va_to_user_va(void *pWls_us, uint64_t ptr)
-{
- unsigned long ret = 0;
- wls_us_ctx_t* pUs = (wls_us_ctx_t*)pWls_us;
-
- uint64_t kva = (uint64_t) pUs->wls_us_kernel_va;
- uint64_t uva = (uint64_t) pUs->wls_us_user_space_va;
-
- ret = (uva + (ptr - kva));
-
- PLIB_DEBUG("kva %lx to uva %lx [offset %d]\n",kva, ret, (kva - ret));
- return ret;
-}
-
-static uint64_t wls_kernel_va_to_user_va_dest(void *pWls_us, uint64_t ptr)
-{
- unsigned long ret = 0;
- wls_us_ctx_t* pUs = (wls_us_ctx_t*)pWls_us;
-
- uint64_t kva = (uint64_t) pUs->dst_kernel_va;
- uint64_t uva = (uint64_t) pUs->dst_user_va;
-
- ret = (uva + (ptr - kva));
-
- PLIB_DEBUG("kva %lx to uva %lx [offset %d]\n",kva, ret, (kva - ret));
- return ret;
-}
-
-
-void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWlsMemorySize)
-{
- wls_us_ctx_t* pWls_us = NULL;
- unsigned int ret = 0;
- wls_open_req_t params;
- int i, len;
- char temp[WLS_DEV_SHM_NAME_LEN];
-
-#ifdef __x86_64__
- params.ctx = 64L;
-#else
- params.ctx = 32L;
-#endif
-
- params.ctx_pa = 0;
- params.size = WLS_LIB_USER_SPACE_CTX_SIZE;
-
- if(sizeof(wls_us_ctx_t) >= 64*1024){
- PLIB_ERR("WLS_Open %ld \n", sizeof(wls_us_ctx_t));
- return NULL;
- }
-
- if (!wls_us_ctx) {
- PLIB_INFO("Open %s 0x%08lx\n", ifacename, WLS_IOC_OPEN);
-
- if ((wls_dev_fd = open(ifacename, O_RDWR | O_SYNC)) < 0){
- PLIB_ERR("Open filed [%d]\n", wls_dev_fd);
- return NULL;
- }
- /* allocate block in shared space */
- if((ret = ioctl(wls_dev_fd, WLS_IOC_OPEN, ¶ms)) < 0) {
- PLIB_ERR("Open filed [%d]\n", ret);
- return NULL;
- }
-
- PLIB_DEBUG("params: kernel va 0x%016llx pa 0x%016llx size %ld\n",
- params.ctx, params.ctx_pa, params.size);
-
- if (params.ctx_pa) {
- /* remap to user space the same block */
- pWls_us = (wls_us_ctx_t*) WLS_LIB_MMAP(NULL,
- params.size,
- PROT_READ|PROT_WRITE ,
- MAP_SHARED,
- wls_dev_fd,
- params.ctx_pa);
-
- if( pWls_us == MAP_FAILED ){
- PLIB_ERR("mmap has failed (%d:%s) 0x%016lx [size %d]\n", errno, strerror(errno),params.ctx_pa, params.size);
- return NULL;
- }
-
- PLIB_DEBUG("Local: pWls_us 0x%016p\n", pWls_us);
-
- PLIB_DEBUG("size wls_us_ctx_t %d\n", sizeof(wls_us_ctx_t));
- PLIB_DEBUG(" ul free : off 0x%016lx\n",((unsigned long) &pWls_us->ul_free_block_pq -(unsigned long)pWls_us));
- PLIB_DEBUG(" get_queue: off 0x%016lx\n",((unsigned long) &pWls_us->get_queue -(unsigned long)pWls_us));
- PLIB_DEBUG(" put_queue: off 0x%016lx\n",((unsigned long) &pWls_us->put_queue -(unsigned long)pWls_us));
-
- //memset(pWls_us, 0, params.size);
-
- pWls_us->padding_wls_us_user_space_va = 0LL;
-
- pWls_us->wls_us_user_space_va = pWls_us;
-
- pWls_us->wls_us_kernel_va = (uint64_t) params.ctx;
- pWls_us->wls_us_pa = (uint64_t) params.ctx_pa;
- pWls_us->wls_us_ctx_size = params.size;
-
- PLIB_INFO("User Space Lib Context: us va 0x%016lx kernel va 0x%016lx pa 0x%016lx size %d \n",
- (uintptr_t)pWls_us->wls_us_user_space_va,
- pWls_us->wls_us_kernel_va,
- pWls_us->wls_us_pa,
- pWls_us->wls_us_ctx_size);
-
- wls_mutex_init(&wls_put_lock);
- wls_mutex_init(&wls_get_lock);
-
- pWls_us->mode = mode;
- PLIB_INFO("\nMode %d\n", pWls_us->mode);
-
- PLIB_INFO("\nWLS device %s [%d]\n", ifacename, (int)strlen(ifacename));
- strncpy(temp, ifacename, WLS_DEV_SHM_NAME_LEN - 1);
- len = strlen(ifacename);
- if (len < WLS_DEV_SHM_NAME_LEN - 1)
- strncpy(pWls_us->wls_dev_name, temp, len);
- else
- strncpy(pWls_us->wls_dev_name, temp, WLS_DEV_SHM_NAME_LEN - 1);
- for(i = 0; i < MIN(strlen(pWls_us->wls_dev_name),WLS_DEV_SHM_NAME_LEN); i++)
- if(pWls_us->wls_dev_name[i] != '/')
- pWls_us->wls_shm_name[i] = pWls_us->wls_dev_name[i];
- else
- pWls_us->wls_shm_name[i] = '_';
-
- wls_us_ctx = pWls_us;
- }
- else {
- PLIB_ERR("Open filed: incorrect allocation \n");
- return NULL;
- }
- }
-
- return wls_us_ctx;
-}
-
-int WLS_Ready(void* h)
-{
- int ret = 0;
- wls_event_req_t params;
-
- if (!wls_us_ctx || !wls_dev_fd){
- PLIB_ERR("Library was not opened\n");
- return -1;
- }
-
- params.event_to_wls = WLS_EVENT_IA_READY;
- params.event_param = 0;
-
- /* free block in shared space */
- if((ret = ioctl(wls_dev_fd, WLS_IOC_EVENT, ¶ms)) < 0) {
- PLIB_ERR("Event filed [%d]\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-int WLS_Close(void* h)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t*)h;
- wls_close_req_t params;
- int ret = 0;
-
- if (!wls_us_ctx || !wls_dev_fd){
- PLIB_ERR("Library was not opened\n");
- return -1;
- }
-
- if ((unsigned long)pWls_us != (unsigned long )wls_us_ctx){
- PLIB_ERR("Incorret handle %lx [expected %lx]\n", (unsigned long)pWls_us, (unsigned long )wls_us_ctx);
- return -1;
- }
-
- params.ctx = pWls_us->wls_us_kernel_va;
- params.ctx_pa = pWls_us->wls_us_pa;
- params.size = pWls_us->wls_us_ctx_size;
-
- /* free block in shared space */
- if((ret = ioctl(wls_dev_fd, WLS_IOC_CLOSE, ¶ms)) < 0) {
- PLIB_ERR("Close filed [%d]\n", ret);
- return 0;
- }
-
- /* unmap to user space */
- munmap(pWls_us, pWls_us->wls_us_ctx_size);
-
- wls_mutex_destroy(&wls_put_lock);
- wls_mutex_destroy(&wls_get_lock);
-
- close(wls_dev_fd);
-
- wls_us_ctx = NULL;
- wls_dev_fd = 0;
-
- return 0;
-}
-
-
-void* WLS_Alloc(void* h, unsigned int size)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- long pageSize[1];
- long hugePageSize;
- long nHugePage;
-
- hugepage_tabl_t* pHugePageTlb = &pWls_us->hugepageTbl[0];
-
- void* pvirtAddr = NULL;
- int count;
- int fd;
-
- char shm_file_name[256];
-
- fd = hugetlbfs_unlinked_fd();
-
- if (fd < 0)
- PLIB_ERR("Unable to open temp file in hugetlbfs (%s)", strerror(errno));
-
- gethugepagesizes(pageSize,1);
- hugePageSize = pageSize[0];
-
- PLIB_INFO("hugePageSize on the system is %ld\n", hugePageSize);
-
- /* calculate total number of hugepages */
- nHugePage = DIV_ROUND_OFFSET(size, hugePageSize);
-
- if (nHugePage >= MAX_N_HUGE_PAGES){
- PLIB_INFO("not enough hugepages: need %ld system has %d\n", nHugePage, MAX_N_HUGE_PAGES);
- return NULL;
- }
-
- if(pHugePageTlb == NULL )
- {
- PLIB_INFO("Table memory allocation failed\n");
- return NULL;
- }
-
-#if WLS_MAP_SHM
-{
- snprintf(shm_file_name, WLS_DEV_SHM_NAME_LEN, "%s_%s", WLS_PHY_SHM_FILE_NAME, pWls_us->wls_shm_name);
- PLIB_INFO("shm open %s\n", shm_file_name);
- ipc_file = open(shm_file_name, O_CREAT); // | O_EXCL maybe sometimes in future.. ;-)
- if(ipc_file == -1){
- PLIB_ERR("open failed (%s)\n", strerror(errno) );
- return NULL;
- }
-
- key_t key = ftok(shm_file_name, '4');
- int shm_handle = shmget(key, size, SHM_HUGETLB|SHM_R|SHM_W);
- if(shm_handle == -1){
- PLIB_INFO("Create shared memory\n");
- shm_handle = shmget(key, size, SHM_HUGETLB | IPC_CREAT | SHM_R | SHM_W);
- }
- else
- PLIB_INFO("Attach to shared memory\n");
-
- if(shm_handle == -1){
- PLIB_ERR("shmget has failed (%s) [size %ld]\n", strerror(errno), nHugePage * hugePageSize);
- return NULL;
- }
-
- pvirtAddr = shmat(shm_handle, 0, /*SHM_RND*/0);
-}
-#else
- /* Allocate required number of pages */
- pvirtAddr = mmap(0,(nHugePage * hugePageSize), (PROT_READ|PROT_WRITE), MAP_SHARED, fd,0);
-#endif
- if(pvirtAddr == MAP_FAILED )
- {
- PLIB_ERR("mmap has failed (%s) [size %ld]\n", strerror(errno), nHugePage * hugePageSize);
- return NULL;
- }
-
- PLIB_INFO("pvirtAddr 0x%016lx\n", (unsigned long)pvirtAddr);
-
- for(count = 0 ; count < nHugePage ; count++ )
- {
- /*Incremented virtual address to next hugepage to create table*/
- pHugePageTlb[count].pageVa = ((unsigned char*)pvirtAddr + \
- ( count * hugePageSize ));
- /*Creating dummy page fault in process for each page
- inorder to get pagemap*/
- *(unsigned char*)pHugePageTlb[count].pageVa = 1;
-
- if(wls_VirtToPhys((uint64_t*) pHugePageTlb[count].pageVa,
- &pHugePageTlb[count].pagePa ) == -1)
- {
- munmap(pvirtAddr, (nHugePage * hugePageSize));
- PLIB_ERR("Virtual to physical conversion failed\n");
- return NULL;
- }
-
- //PLIB_INFO("id %d va 0x%016p pa 0x%016llx [%ld]\n", count, (uintptr_t)pHugePageTlb[count].pageVa, (uint64_t) pHugePageTlb[count].pagePa, hugePageSize);
- }
-
- PLIB_INFO("WLS_Alloc: 0x%016lx [%d]\n", (unsigned long)pvirtAddr, size);
-
- close(fd);
-
- pWls_us->HugePageSize = (uint32_t)hugePageSize;
- pWls_us->alloc_buffer = pvirtAddr;
- pWls_us->alloc_size = (uint32_t)(nHugePage * hugePageSize);
-
- if (pWls_us->mode == WLS_MASTER_CLIENT){
- wls_us_ctx_t* pWls_usRem = NULL;
- PLIB_INFO("Connecting to remote peer ...\n");
- while (pWls_us->dst_pa == 0) // wait for slave
- ;
-
- /* remap to user space the same block */
- pWls_usRem = (wls_us_ctx_t*) WLS_LIB_MMAP(NULL,
- sizeof(wls_us_ctx_t),
- PROT_READ|PROT_WRITE ,
- MAP_SHARED,
- wls_dev_fd,
- pWls_us->dst_pa);
-
- if( pWls_us == MAP_FAILED ){
- PLIB_ERR("mmap has failed (%d:%s) 0x%016lx \n", errno, strerror(errno),pWls_us->dst_pa);
- return NULL;
- }
-
- PLIB_INFO("Remote: pWls_us 0x%p\n", pWls_usRem);
-
- PLIB_INFO("size wls_us_ctx_t %ld\n", sizeof(wls_us_ctx_t));
- PLIB_INFO(" ul free : off 0x%016lx\n",((unsigned long) &pWls_usRem->ul_free_block_pq -(unsigned long)pWls_usRem));
- PLIB_INFO(" get_queue: off 0x%016lx\n",((unsigned long) &pWls_usRem->get_queue -(unsigned long)pWls_usRem));
- PLIB_INFO(" put_queue: off 0x%016lx\n",((unsigned long) &pWls_usRem->put_queue -(unsigned long)pWls_usRem));
-
- pWls_us->dst_user_va = (uint64_t) pWls_usRem ;
- }
-
-
- return pvirtAddr;
-}
-
-int WLS_Free(void* h, PVOID pMsg)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- if ((unsigned long)pMsg != (unsigned long)pWls_us->alloc_buffer) {
- PLIB_ERR("incorrect pMsg %lx [expected %lx]\n", (unsigned long)pMsg ,(unsigned long)pWls_us->alloc_buffer);
- return -1;
- }
-
- if (pWls_us->mode == WLS_MASTER_CLIENT){
- if(pWls_us->dst_user_va){
- munmap((void*)pWls_us->dst_user_va, sizeof(wls_us_ctx_t));
- pWls_us->dst_user_va = 0;
- }
- }
-
- PLIB_DEBUG("WLS_Free 0x%016lx", (unsigned long)pMsg);
-#if WLS_MAP_SHM
- shmdt(pMsg);
- close (ipc_file);
-#else
- munmap(pMsg, pWls_us->alloc_size);
-#endif
-
-
-
- return 0;
-}
-
-int WLS_Put(void* h, unsigned long long pMsg, unsigned int MsgSize, unsigned short MsgTypeID, unsigned short Flags)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
- int ret = 0;
-
- if ((unsigned long)h != (unsigned long)wls_us_ctx) {
- PLIB_ERR("Incorrect user space context %lx [%lx]\n", (unsigned long)h, (unsigned long)wls_us_ctx);
- return -1;
- }
-
- if(!WLS_IS_ONE_HUGE_PAGE(pMsg, MsgSize, WLS_HUGE_DEF_PAGE_SIZE)) {
- PLIB_ERR("WLS_Put input error: buffer is crossing 2MB page boundary 0x%016llx size %ld\n", pMsg, (unsigned long)MsgSize);
- }
-
- wls_mutex_lock(&wls_put_lock);
-
- if ((WLS_FLAGS_MASK & Flags)){ // multi block transaction
- if (Flags & WLS_TF_SYN){
- PLIB_DEBUG("WLS_SG_FIRST\n");
- if (WLS_MsgEnqueue(&pWls_us->put_queue, pMsg, MsgSize, MsgTypeID, Flags, wls_kernel_va_to_user_va, (void*)pWls_us))
- {
- PLIB_DEBUG("WLS_Get %lx %d type %d\n",(U64) pMsg, MsgSize, MsgTypeID);
- }
- } else if ((Flags & WLS_TF_SCATTER_GATHER) && !(Flags & WLS_TF_SYN) && !(Flags & WLS_TF_FIN)){
- PLIB_DEBUG("WLS_SG_NEXT\n");
- if (WLS_MsgEnqueue(&pWls_us->put_queue, pMsg, MsgSize, MsgTypeID, Flags, wls_kernel_va_to_user_va, (void*)pWls_us))
- {
- PLIB_DEBUG("WLS_Put %lx %d type %d\n",(U64) pMsg, MsgSize, MsgTypeID);
- }
- } else if (Flags & WLS_TF_FIN) {
- wls_put_req_t params;
- PLIB_DEBUG("WLS_SG_LAST\n");
- params.wls_us_kernel_va = pWls_us->wls_us_kernel_va;
- if (WLS_MsgEnqueue(&pWls_us->put_queue, pMsg, MsgSize, MsgTypeID, Flags, wls_kernel_va_to_user_va, (void*)pWls_us))
- {
- PLIB_DEBUG("WLS_Put %lx %d type %d\n",(U64) pMsg, MsgSize, MsgTypeID);
- }
-
- PLIB_DEBUG("List: call WLS_IOC_PUT\n");
- if((ret = ioctl(wls_dev_fd, WLS_IOC_PUT, ¶ms)) < 0) {
- PLIB_ERR("Put filed [%d]\n", ret);
- wls_mutex_unlock(&wls_put_lock);
- return -1;
- }
- } else
- PLIB_ERR("unsaported flags %x\n", WLS_FLAGS_MASK & Flags);
- } else { // one block transaction
- wls_put_req_t params;
- params.wls_us_kernel_va = pWls_us->wls_us_kernel_va;
- if (WLS_MsgEnqueue(&pWls_us->put_queue, pMsg, MsgSize, MsgTypeID, Flags, wls_kernel_va_to_user_va, (void*)pWls_us))
- {
- PLIB_DEBUG("WLS_Put %lx %d type %d\n",(U64) pMsg, MsgSize, MsgTypeID);
- }
-
- PLIB_DEBUG("One block: call WLS_IOC_PUT\n");
- if((ret = ioctl(wls_dev_fd, WLS_IOC_PUT, ¶ms)) < 0) {
- PLIB_ERR("Put filed [%d]\n", ret);
- wls_mutex_unlock(&wls_put_lock);
- return -1;
- }
- }
- wls_mutex_unlock(&wls_put_lock);
-
- return 0;
-}
-
-int WLS_Check(void* h)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- if ((unsigned long)h != (unsigned long)wls_us_ctx) {
- PLIB_ERR("Incorrect user space context %lx [%lx]\n", (unsigned long)h, (unsigned long)wls_us_ctx);
- return 0;
- }
-
- PLIB_DEBUG("offset get_queue %lx\n",(U64)&pWls_us->get_queue - (U64)pWls_us);
-
- return WLS_GetNumItemsInTheQueue(&pWls_us->get_queue);
-}
-
-
-unsigned long long WLS_Get(void* h, unsigned int *MsgSize, unsigned short *MsgTypeID, unsigned short *Flags)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
- WLS_MSG_HANDLE hMsg;
- uint64_t pMsg = NULL;
-
- if ((unsigned long)h != (unsigned long)wls_us_ctx) {
- PLIB_ERR("Incorrect user space context %lx [%lx]\n", (unsigned long)h, (unsigned long)wls_us_ctx);
- return 0;
- }
-
- PLIB_DEBUG("offset get_queue %lx\n",(U64)&pWls_us->get_queue - (U64)pWls_us);
- wls_mutex_lock(&wls_get_lock);
-
- if (WLS_MsgDequeue(&pWls_us->get_queue, &hMsg, wls_kernel_va_to_user_va, (void*)pWls_us))
- {
- PLIB_DEBUG("WLS_Get %lx %d type %d\n",(U64) hMsg.pIaPaMsg, hMsg.MsgSize, hMsg.TypeID);
- pMsg = hMsg.pIaPaMsg;
- *MsgSize = hMsg.MsgSize;
- *MsgTypeID = hMsg.TypeID;
- *Flags = hMsg.flags;
- }
-
- wls_mutex_unlock(&wls_get_lock);
-
- return pMsg;
-}
-
-int WLS_WakeUp(void* h)
-{
- int ret;
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
- wls_wake_up_req_t params;
-
- if (!wls_us_ctx || !wls_dev_fd){
- PLIB_ERR("Library was not opened\n");
- return -1;
- }
-
- params.ctx = (uint64_t)pWls_us;
- params.wls_us_kernel_va = (uint64_t)pWls_us->wls_us_kernel_va;
-
- PLIB_DEBUG("WLS_WakeUp\n");
-
- if((ret = ioctl(wls_dev_fd, WLS_IOC_WAKE_UP, ¶ms)) < 0) {
- PLIB_ERR("Wake Up filed [%d]\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-int WLS_Wait(void* h)
-{
- int ret;
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
- wls_wait_req_t params;
-
- if (!wls_us_ctx || !wls_dev_fd){
- PLIB_ERR("Library was not opened\n");
- return -1;
- }
-
- params.ctx = (uint64_t)pWls_us;
- params.wls_us_kernel_va = (uint64_t)pWls_us->wls_us_kernel_va;
- params.action = 0;
- params.nMsg = 0;
-
- PLIB_DEBUG("WLS_Wait\n");
-
- if((ret = ioctl(wls_dev_fd, WLS_IOC_WAIT, ¶ms)) < 0) {
- PLIB_ERR("Wait filed [%d]\n", ret);
- return ret;
- }
-
- return params.nMsg;
-}
-
-unsigned long long WLS_WGet(void* h, unsigned int *MsgSize, unsigned short *MsgTypeID, unsigned short *Flags)
-{
- uint64_t pRxMsg = WLS_Get(h, MsgSize, MsgTypeID, Flags);
-
- if (pRxMsg)
- return pRxMsg;
-
- WLS_Wait(h);
- return WLS_Get(h, MsgSize, MsgTypeID, Flags);
-}
-
-unsigned long long WLS_VA2PA(void* h, PVOID pMsg)
-{
- uint64_t ret = 0;
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- unsigned long alloc_base;
- hugepage_tabl_t* pHugePageTlb;
- uint64_t hugePageBase;
- uint64_t hugePageOffet;
- unsigned int count = 0;
-
- uint64_t HugePageMask = ((unsigned long)pWls_us->HugePageSize - 1);
-
- if(pWls_us->alloc_buffer == NULL){
- PLIB_ERR("WLS_VA2PA: nothing was allocated [%ld]\n", ret);
- return (uint64_t)ret;
- }
-
- alloc_base = (unsigned long)pWls_us->alloc_buffer;
-
- pHugePageTlb = &pWls_us->hugepageTbl[0];
-
- hugePageBase = (uint64_t)pMsg & ~HugePageMask;
- hugePageOffet = (uint64_t)pMsg & HugePageMask;
-
- count = (hugePageBase - alloc_base) / pWls_us->HugePageSize;
-
- PLIB_DEBUG("WLS_VA2PA %lx base %llx off %llx count %d\n", (unsigned long)pMsg,
- (uint64_t)hugePageBase, (uint64_t)hugePageOffet, count);
-
- ret = pHugePageTlb[count].pagePa + hugePageOffet;
-
- return (uint64_t) ret;
-}
-
-void* WLS_PA2VA(void* h, unsigned long long pMsg)
-{
- unsigned long ret = NULL;
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- hugepage_tabl_t* pHugePageTlb;
- uint64_t hugePageBase;
- uint64_t hugePageOffet;
- unsigned int count;
- int i;
- uint64_t HugePageMask = ((uint64_t)pWls_us->HugePageSize - 1);
-
- if(pWls_us->alloc_buffer == NULL){
- PLIB_ERR("WLS_PA2VA: nothing was allocated [%ld]\n", ret);
- return (void*)ret;
- }
-
- pHugePageTlb = &pWls_us->hugepageTbl[0];
-
- hugePageBase = (uint64_t)pMsg & ~HugePageMask;
- hugePageOffet = (uint64_t)pMsg & HugePageMask;
-
- count = pWls_us->alloc_size / pWls_us->HugePageSize;
-
- PLIB_DEBUG("WLS_PA2VA %llx base %llx off %llx count %d\n", (uint64_t)pMsg,
- (uint64_t)hugePageBase, (uint64_t)hugePageOffet, count);
-
- for (i = 0; i < count; i++) {
- if (pHugePageTlb[i].pagePa == hugePageBase)
- {
- ret = (unsigned long)pHugePageTlb[i].pageVa;
- ret += hugePageOffet;
- return (void*)ret;
- }
- }
-
- return (void*) (ret);
-}
-
-int WLS_EnqueueBlock(void* h, unsigned long long pMsg)
-{
- int ret = 0;
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- if (!wls_us_ctx || !wls_dev_fd){
- PLIB_ERR("Library was not opened\n");
- return -1;
- }
-
- if(pWls_us->mode == WLS_SLAVE_CLIENT){
- PLIB_ERR("Slave doesn't support memory allocation\n");
- return -1;
- }
-
- if(pMsg == 0){
- PLIB_ERR("WLS_EnqueueBlock: Null\n");
- return -1;
- }
-
- if(pWls_us->dst_kernel_va){
- if (pWls_us->dst_user_va)
- {
- wls_us_ctx_t* pDstWls_us = (wls_us_ctx_t* )pWls_us->dst_user_va;
- ret = SFL_WlsEnqueue(&pDstWls_us->ul_free_block_pq, pMsg, wls_kernel_va_to_user_va_dest, pWls_us);
- if(ret == 1){
- unsigned long* ptr = (unsigned long*)WLS_PA2VA(pWls_us, pMsg);
- if(ptr){
- *ptr = 0xFFFFFFFFFFFFFFFF;
- }
- }
- }
- else
- ret = -1;
- }
- else
- ret = -1;
-
- PLIB_DEBUG("SFL_WlsEnqueue %d\n", ret);
- return ret;
-}
-
-unsigned long long WLS_DequeueBlock(void* h)
-{
- unsigned long long retval = NULL;
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
-
- if(pWls_us->mode == WLS_SLAVE_CLIENT){
- // local
- retval = SFL_WlsDequeue(&pWls_us->ul_free_block_pq, wls_kernel_va_to_user_va, h );
- } else if(pWls_us->dst_kernel_va) {
- // remote
- if (pWls_us->dst_user_va)
- {
- wls_us_ctx_t* pDstWls_us = (wls_us_ctx_t* )pWls_us->dst_user_va;
- retval = SFL_WlsDequeue(&pDstWls_us->ul_free_block_pq, wls_kernel_va_to_user_va_dest, pWls_us);
- if(retval){
- unsigned long* ptr = (unsigned long*)WLS_PA2VA(pWls_us, retval);
- if(ptr){
- if(*ptr != 0xFFFFFFFFFFFFFFFF){
- PLIB_ERR("WLS_EnqueueBlock: incorrect content pa: 0x%016lx: 0x%016lx\n", (unsigned long)retval, *ptr);
- }
- }
- }
- }
- }
-
- return retval;
-}
-
-int WLS_NumBlocks(void* h)
-{
- wls_us_ctx_t* pWls_us = (wls_us_ctx_t* )h;
- int n = 0;
-
- if(pWls_us->mode == WLS_SLAVE_CLIENT){
- // local
- n = SFL_GetNumItemsInTheQueue(&pWls_us->ul_free_block_pq);
- } else if(pWls_us->dst_kernel_va) {
- // remote
- if (pWls_us->dst_user_va)
- {
- wls_us_ctx_t* pDstWls_us = (wls_us_ctx_t* )pWls_us->dst_user_va;
- n = SFL_GetNumItemsInTheQueue(&pDstWls_us->ul_free_block_pq);
- }
- }
-
- return n;
-}
-
-
/* definitions PUT/GET Flags */
#define WLS_TF_SCATTER_GATHER (1 << 15)
-#define WLS_TF_URLLC (1 << 10)
+#define WLS_TF_URLLC (1 << 11)
+#define WLS_TF_LTE (1 << 10)
#define WLS_TF_SYN (1 << 9)
#define WLS_TF_FIN (1 << 8)
#define WLS_FLAGS_MASK (0xFF00)
pthread_mutexattr_init(&attr);
pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED);
- if (ret = pthread_mutex_init(&mng_ctx->mng_mutex, &attr)) {
+ ret = pthread_mutex_init(&mng_ctx->mng_mutex, &attr);
+ if (ret)
+ {
pthread_mutexattr_destroy(&attr);
PLIB_ERR("Failed to initialize mng_mutex %d\n", ret);
return ret;
{
wls_us_ctx_t* pWls_us = NULL;
wls_drv_ctx_t *pWlsDrvCtx;
- int i, len;
+
char temp[WLS_DEV_SHM_NAME_LEN] = {0};
static const struct rte_memzone *mng_memzone;
mng_memzone = (struct rte_memzone *)rte_memzone_lookup(temp);
if (mng_memzone == NULL)
{
- PLIB_ERR("Cannot initialize wls shared memory: %s\n", temp);
- return NULL;
- }
+ PLIB_ERR("Cannot initialize wls shared memory: %s\n", temp);
+ return NULL;
+ }
}
else
{
wls_us_ctx_t* pWls_us = NULL;
wls_us_ctx_t* pWls_us1 = NULL;
wls_drv_ctx_t *pWlsDrvCtx;
- int i, len;
+
char temp[WLS_DEV_SHM_NAME_LEN] = {0};
static const struct rte_memzone *mng_memzone;
int WLS_Free(void* h, PVOID pMsg)
{
wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h;
- wls_drv_ctx_t *pDrv_ctx;
struct rte_memzone *mng_memzone;
mng_memzone = (struct rte_memzone *)rte_memzone_lookup(pWls_us->wls_dev_name);
pWls_us->wls_dev_name, rte_strerror(rte_errno));
return -1;
}
- pDrv_ctx = mng_memzone->addr;
if (pMsg != pWls_us->alloc_buffer) {
PLIB_ERR("incorrect pMsg %p [expected %p]\n", pMsg, pWls_us->alloc_buffer);
{
wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h;
int ret = 0;
- unsigned short nFlags = Flags & (~WLS_TF_URLLC);
+ unsigned short nFlags = Flags & (~(WLS_TF_URLLC | WLS_TF_LTE));
if (wls_check_ctx(h))
return -1;
Code Review / o-du / phy.git / commitdiff
