fapi_5g/source/include/nr5g_fapi_framework.h

   1 /******************************************************************************
   2 *
   3 *   Copyright (c) 2021 Intel.
   4 *
   5 *   Licensed under the Apache License, Version 2.0 (the "License");
   6 *   you may not use this file except in compliance with the License.
   7 *   You may obtain a copy of the License at
   8 *
   9 *       http://www.apache.org/licenses/LICENSE-2.0
  10 *
  11 *   Unless required by applicable law or agreed to in writing, software
  12 *   distributed under the License is distributed on an "AS IS" BASIS,
  13 *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14 *   See the License for the specific language governing permissions and
  15 *   limitations under the License.
  16 *
  17 *******************************************************************************/
  18
  19 /**
  20  * @file This file consist of FAPI internal functions.
  21  *
  22  **/
  23
  24 #ifndef _NR5G_FAPI_FRAMEWORK_H_
  25 #define _NR5G_FAPI_FRAMEWORK_H_
  26
  27 #include <fcntl.h>
  28 #include "fapi_interface.h"
  29 #include "nr5g_fapi_log.h"
  30 #include "nr5g_fapi_internal.h"
  31 #include "nr5g_fapi_std.h"
  32 #include "nr5g_fapi_common_types.h"
  33 #include "nr5g_fapi_config_loader.h"
  34
  35 // FAPI CONFIG.request parameters
  36 typedef struct _nr5g_fapi_phy_config {
  37     uint16_t phy_cell_id;
  38     uint8_t n_nr_of_rx_ant;
  39     uint8_t use_vendor_EpreXSSB;
  40     uint8_t sub_c_common;
  41     uint8_t pad[3];
  42 } nr5g_fapi_phy_config_t,
  43 *pnr5g_fapi_phy_config_t;
  44
  45 typedef struct _nr5g_fapi_rach_info {
  46     uint16_t phy_cell_id;
  47 } nr5g_fapi_rach_info_t;
  48
  49 typedef struct _nr5g_fapi_srs_info {
  50     uint32_t handle;
  51 } nr5g_fapi_srs_info_t;
  52
  53 typedef struct _nr5g_fapi_pusch_info {
  54     uint32_t handle;
  55     uint8_t harq_process_id;
  56     uint8_t ul_cqi;
  57     uint16_t timing_advance;
  58 } nr5g_fapi_pusch_info_t;
  59
  60 typedef struct _nr5g_fapi_pucch_info {
  61     uint32_t handle;
  62     uint8_t pucch_format;
  63 } nr5g_fapi_pucch_info_t;
  64
  65 typedef struct _nr5g_fapi_ul_slot_info {
  66     uint16_t cookie;            //set this to frame_no at UL_TTI.Request and compare the
  67     //same during uplink indications.
  68     uint8_t slot_no;
  69     uint8_t symbol_no;
  70     uint8_t num_ulsch;
  71     uint8_t num_ulcch;
  72     uint8_t num_srs;
  73     uint8_t rach_presence;
  74     nr5g_fapi_rach_info_t rach_info;    //Only One RACH PDU will be reported for RACH.Indication message
  75     nr5g_fapi_srs_info_t srs_info[FAPI_MAX_NUMBER_SRS_PDUS_PER_SLOT];
  76     nr5g_fapi_pucch_info_t pucch_info[FAPI_MAX_NUMBER_UCI_PDUS_PER_SLOT];
  77     nr5g_fapi_pusch_info_t pusch_info[FAPI_MAX_NUMBER_OF_ULSCH_PDUS_PER_SLOT];
  78 } nr5g_fapi_ul_slot_info_t;
  79
  80 typedef struct _nr5g_fapi_stats_info_t {
  81     uint8_t fapi_param_req;
  82     uint8_t fapi_param_res;
  83     uint8_t fapi_config_req;
  84     uint8_t fapi_config_res;
  85     uint8_t fapi_start_req;
  86     uint8_t fapi_stop_req;
  87     uint8_t fapi_stop_ind;
  88     uint8_t fapi_vendor_msg;
  89     uint8_t fapi_vext_shutdown_req;
  90     uint8_t fapi_vext_shutdown_res;
  91 #ifdef DEBUG_MODE
  92     uint8_t fapi_vext_start_res;
  93 #endif
  94     uint64_t fapi_dl_tti_req;
  95     uint64_t fapi_ul_tti_req;
  96     uint64_t fapi_ul_dci_req;
  97     uint64_t fapi_tx_data_req;
  98
  99     uint64_t fapi_slot_ind;
 100     uint64_t fapi_error_ind;
 101     uint64_t fapi_crc_ind;
 102     uint64_t fapi_rx_data_ind;
 103     uint64_t fapi_uci_ind;
 104     uint64_t fapi_srs_ind;
 105     uint64_t fapi_rach_ind;
 106
 107     uint64_t fapi_dl_tti_pdus;
 108     uint64_t fapi_dl_tti_pdcch_pdus;
 109     uint64_t fapi_dl_tti_pdsch_pdus;
 110     uint64_t fapi_dl_tti_csi_rs_pdus;
 111     uint64_t fapi_dl_tti_ssb_pdus;
 112
 113     uint64_t fapi_ul_dci_pdus;
 114
 115     uint64_t fapi_ul_tti_pdus;
 116     uint64_t fapi_ul_tti_prach_pdus;
 117     uint64_t fapi_ul_tti_pusch_pdus;
 118     uint64_t fapi_ul_tti_pucch_pdus;
 119     uint64_t fapi_ul_tti_srs_pdus;
 120     uint64_t fapi_crc_ind_pdus;
 121     uint64_t fapi_rx_data_ind_pdus;
 122     uint64_t fapi_uci_ind_pdus;
 123     uint64_t fapi_srs_ind_pdus;
 124     uint64_t fapi_rach_ind_pdus;
 125 } nr5g_fapi_stats_info_t;
 126
 127 typedef struct _nr5g_iapi_stats_info_t {
 128     uint8_t iapi_param_req;
 129     uint8_t iapi_param_res;
 130     uint8_t iapi_config_req;
 131     uint8_t iapi_config_res;
 132     uint8_t iapi_start_req;
 133     uint8_t iapi_start_res;
 134     uint8_t iapi_stop_req;
 135     uint8_t iapi_stop_ind;
 136     uint8_t iapi_shutdown_req;
 137     uint8_t iapi_shutdown_res;
 138     uint64_t iapi_dl_config_req;
 139     uint64_t iapi_ul_config_req;
 140     uint64_t iapi_ul_dci_req;
 141     uint64_t iapi_tx_req;
 142
 143     uint64_t iapi_slot_ind;
 144     uint64_t iapi_error_ind;
 145     uint64_t iapi_crc_ind;
 146     uint64_t iapi_rx_data_ind;
 147     uint64_t iapi_uci_ind;
 148     uint64_t iapi_srs_ind;
 149     uint64_t iapi_rach_ind;
 150
 151     uint64_t iapi_dl_tti_pdus;
 152     uint64_t iapi_dl_tti_pdcch_pdus;
 153     uint64_t iapi_dl_tti_pdsch_pdus;
 154     uint64_t iapi_dl_tti_csi_rs_pdus;
 155     uint64_t iapi_dl_tti_ssb_pdus;
 156
 157     uint64_t iapi_ul_dci_pdus;
 158
 159     uint64_t iapi_ul_tti_pdus;
 160     uint64_t iapi_ul_tti_prach_pdus;
 161     uint64_t iapi_ul_tti_pusch_pdus;
 162     uint64_t iapi_ul_tti_pucch_pdus;
 163     uint64_t iapi_ul_tti_srs_pdus;
 164     uint64_t iapi_crc_ind_pdus;
 165     uint64_t iapi_rx_data_ind_pdus;
 166     uint64_t iapi_uci_ind_pdus;
 167     uint64_t iapi_srs_ind_pdus;
 168     uint64_t iapi_rach_preambles;
 169 } nr5g_iapi_stats_info_t;
 170
 171 typedef struct _nr5g_fapi_stats_t {
 172     nr5g_fapi_stats_info_t fapi_stats;
 173     nr5g_iapi_stats_info_t iapi_stats;
 174 } nr5g_fapi_stats_t;
 175
 176 // FAPI phy instance structure
 177 typedef struct _nr5g_fapi_phy_instance {
 178     uint8_t phy_id;
 179     uint8_t shutdown_retries;
 180     uint32_t shutdown_test_type;
 181     fapi_states_t state;        // FAPI state
 182     nr5g_fapi_phy_config_t phy_config;  // place holder to store,
 183     // parameters from config request
 184     nr5g_fapi_stats_t stats;
 185     nr5g_fapi_ul_slot_info_t ul_slot_info[FAPI_MAX_SLOT_INFO_URLLC][MAX_UL_SLOT_INFO_COUNT][MAX_UL_SYMBOL_INFO_COUNT];
 186 } nr5g_fapi_phy_instance_t,
 187 *p_nr5g_fapi_phy_instance_t;
 188
 189 typedef struct _nr5g_fapi_urllc_thread_params_t {
 190     void *p_urllc_list_elem;
 191     pthread_mutex_t lock;
 192     sem_t urllc_sem_process;
 193     sem_t urllc_sem_done;
 194 } nr5g_fapi_urllc_thread_params_t;
 195
 196 // Phy Context
 197 typedef struct _nr5g_fapi_phy_context {
 198     uint8_t num_phy_instance;
 199     uint8_t mac2phy_worker_core_id;
 200     uint8_t phy2mac_worker_core_id;
 201     uint8_t urllc_mac2phy_worker_core_id;
 202     uint8_t urllc_phy2mac_worker_core_id;
 203     nr5g_fapi_urllc_thread_params_t urllc_mac2phy_params;
 204     nr5g_fapi_urllc_thread_params_t urllc_phy2mac_params;
 205     bool is_urllc_enabled;
 206     volatile uint64_t process_exit;
 207     nr5g_fapi_phy_instance_t phy_instance[FAPI_MAX_PHY_INSTANCES];
 208 } nr5g_fapi_phy_ctx_t,
 209 *p_nr5g_fapi_phy_ctx_t;
 210
 211 // Function Declarations
 212 p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx(
 213     );
 214 uint8_t nr5g_fapi_framework_init(
 215     );
 216 uint8_t nr5g_fapi_framework_stop(
 217     );
 218 uint8_t nr5g_fapi_framework_finish(
 219     );
 220 uint8_t nr5g_fapi_dpdk_init(
 221     p_nr5g_fapi_cfg_t cfg);
 222 uint8_t nr5g_fapi_dpdk_wait(
 223     p_nr5g_fapi_cfg_t cfg);
 224 void *nr5g_fapi_phy2mac_thread_func(
 225     void *config);
 226 void *nr5g_fapi_mac2phy_thread_func(
 227     void *config);
 228 void *nr5g_fapi_urllc_mac2phy_thread_func(
 229     void *config);
 230 void *nr5g_fapi_urllc_phy2mac_thread_func(
 231     void *config);
 232 nr5g_fapi_ul_slot_info_t *nr5g_fapi_get_ul_slot_info(
 233     bool is_urllc,
 234     uint16_t frame_no,
 235     uint16_t slot_no,
 236     uint8_t symbol_no,
 237     p_nr5g_fapi_phy_instance_t p_phy_instance);
 238 void nr5g_fapi_set_ul_slot_info(
 239     uint16_t frame_no,
 240     uint16_t slot_no,
 241     uint8_t symbol_no,
 242     nr5g_fapi_ul_slot_info_t * p_ul_slot_info);
 243 void nr5g_fapi_init_thread(uint8_t worker_core_id);
 244 void nr5g_fapi_urllc_thread_callback(
 245     void *p_list_elem,
 246     nr5g_fapi_urllc_thread_params_t* urllc_params);
 247 void nr5g_fapi_clean(
 248     p_nr5g_fapi_phy_instance_t p_phy_instance);
 249 #endif                          // _NR5G_FAPI_FRAMEWORK_H_