fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru_tst377.dat

   1 #******************************************************************************
   2 #
   3 #   Copyright (c) 2019 Intel.
   4 #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");
   6 #   you may not use this file except in compliance with the License.
   7 #   You may obtain a copy of the License at
   8 #
   9 #       http://www.apache.org/licenses/LICENSE-2.0
  10 #
  11 #   Unless required by applicable law or agreed to in writing, software
  12 #   distributed under the License is distributed on an "AS IS" BASIS,
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14 #   See the License for the specific language governing permissions and
  15 #   limitations under the License.
  16 #
  17 #******************************************************************************/
  18
  19 #Peak
  20 #4%
  21 #302    TDD     DDDFU: S it's 10:2:2    1       64T64R  100     8       8       37%     100     1200    37%     100     1200    Peak: 4 %
  22
  23
  24 # This is simple configuration file. Use '#' sign for comments
  25 instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
  26 appMode=1 # O-DU(0) | O-RU(1)
  27 xranMode=1 # Category A  (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
  28 ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
  29 antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
  30 antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
  31 antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
  32
  33 #UEs
  34 muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
  35 DlLayersPerUe=1 #number of RX anntennas on DL UE side
  36 UlLayersPerUe=1 #number of TX anntennas on UL UE side
  37
  38
  39 ##Numerology
  40 mu=1 #30Khz Sub Carrier Spacing
  41
  42 ttiPeriod=500 # in us TTI period (30Khz default 500us)
  43
  44 nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
  45 nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
  46 nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
  47 nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
  48 nDLFftSize=4096
  49 nULFftSize=4096
  50
  51 nFrameDuplexType=1 # 0 - FDD 1 - TDD
  52 nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2
  53 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
  54 sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
  55 sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
  56 sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
  57 sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
  58
  59 MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
  60  #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
  61 Gps_Alpha=0     #alpha and beta value as in section 9.7.2 of ORAN spec
  62 Gps_Beta=0
  63
  64 numSlots=20 #number of slots per IQ files
  65 antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin   #CC0
  66 antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin   #CC0
  67 antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin   #CC0
  68 antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin   #CC0
  69 antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin   #CC1
  70 antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin   #CC1
  71 antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin   #CC1
  72 antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin  #CC1
  73 antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin   #CC2
  74 antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin   #CC2
  75 antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
  76 antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
  77 antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
  78 antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
  79 antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
  80 antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
  81
  82 #SlotNumTx0=./avg_txconfig_1.cfg
  83 #SlotNumTx1=./avg_txconfig_1.cfg
  84 #SlotNumTx2=./avg_txconfig_1.cfg
  85 #SlotNumTx3=./avg_txconfig_2.cfg
  86 #SlotNumTx4=./avg_txconfig_0.cfg
  87
  88 #SlotNumTx5=./avg_txconfig_1.cfg
  89 #SlotNumTx6=./avg_txconfig_1.cfg
  90 #SlotNumTx7=./avg_txconfig_1.cfg
  91 #SlotNumTx8=./avg_txconfig_2.cfg
  92 #SlotNumTx9=./avg_txconfig_0.cfg
  93
  94 #SlotNumRx0=./avg_rxconfig_0.cfg
  95 #SlotNumRx1=./avg_rxconfig_0.cfg
  96 #SlotNumRx2=./avg_rxconfig_0.cfg
  97 #SlotNumRx3=./avg_rxconfig_2.cfg
  98 #SlotNumRx4=./avg_rxconfig_1.cfg
  99
 100 #SlotNumRx5=./avg_rxconfig_0.cfg
 101 #SlotNumRx6=./avg_rxconfig_0.cfg
 102 #SlotNumRx7=./avg_rxconfig_0.cfg
 103 #SlotNumRx8=./avg_rxconfig_3.cfg
 104 #SlotNumRx9=./avg_rxconfig_1.cfg
 105
 106
 107 antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin   #CC0
 108 antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin   #CC0
 109 antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin   #CC0
 110 antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin   #CC0
 111 antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin   #CC1
 112 antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin   #CC1
 113 antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin   #CC1
 114 antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin   #CC1
 115 antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin   #CC2
 116 antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin   #CC2
 117 antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin  #CC2
 118 antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin  #CC2
 119 antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin  #CC3
 120 antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin  #CC3
 121 antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin  #CC3
 122 antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin  #CC3
 123
 124 rachEnable=0 # Enable (1)| disable (0) PRACH configuration
 125 prachConfigIndex=189
 126
 127 srsEnable=1 # Enable (1)| disable (0) SRS
 128 srsSym=4 # deprecated
 129 srsSlot=3           # scheduled SRS slot within TDD period
 130 srsNdmOffset=2      # delay offset to start NDM SRS U-Plane
 131 srsNdmTxDuration=4  # TX duration for NDM SRTS U-Plane (numberof of symbols)
 132
 133 antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
 134 antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
 135 antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
 136 antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
 137 antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
 138 antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
 139 antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
 140 antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
 141 antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
 142 antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
 143 antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
 144 antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
 145 antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
 146 antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
 147 antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
 148 antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
 149 antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
 150 antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
 151 antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
 152 antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
 153 antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
 154 antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
 155 antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
 156 antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
 157 antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
 158 antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
 159 antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
 160 antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
 161 antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
 162 antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
 163 antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
 164 antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
 165 antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
 166 antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
 167 antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
 168 antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
 169 antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
 170 antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
 171 antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
 172 antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
 173 antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
 174 antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
 175 antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
 176 antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
 177 antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
 178 antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
 179 antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
 180 antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
 181 antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
 182 antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
 183 antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
 184 antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
 185 antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
 186 antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
 187 antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
 188 antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
 189 antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
 190 antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
 191 antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
 192 antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
 193 antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
 194 antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
 195 antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
 196 antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
 197
 198
 199 srsEnable=1 # Enable (1)| disable (0) SRS
 200 srsSym=1 # (1<<13) symbol used for SRS (def: sym 13)
 201
 202 ###########################################################
 203 ##Section Settings
 204 DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
 205 max_sections_per_slot=12
 206 max_sections_per_symbol=12
 207
 208 nPrbElemDl=6
 209 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
 210 # weight base beams
 211 PrbElemDl0=0,18,0,14,0,1,1,9,1
 212 PrbElemDl1=18,18,0,14,1,1,1,9,1
 213 PrbElemDl2=36,18,0,14,2,1,1,9,1
 214 PrbElemDl3=54,18,0,14,3,1,1,9,1
 215 PrbElemDl4=72,18,0,14,4,1,1,9,1
 216 PrbElemDl5=90,10,0,14,5,1,1,9,1
 217
 218 # Extension Parameters for Beamforming weights
 219 # numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
 220 ExtBfwDl0=2,9,0,0,9,1
 221 ExtBfwDl1=2,9,0,0,9,1
 222 ExtBfwDl2=2,9,0,0,9,1
 223 ExtBfwDl3=2,9,0,0,9,1
 224 ExtBfwDl4=2,9,0,0,9,1
 225 ExtBfwDl5=2,5,0,0,9,1
 226
 227
 228 nPrbElemUl=6
 229 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
 230 # weight base beams
 231 PrbElemUl0=0,18,0,14,0,1,1,9,1
 232 PrbElemUl1=18,18,0,14,1,1,1,9,1
 233 PrbElemUl2=36,18,0,14,2,1,1,9,1
 234 PrbElemUl3=54,18,0,14,3,1,1,9,1
 235 PrbElemUl4=72,18,0,14,4,1,1,9,1
 236 PrbElemUl5=90,10,0,14,5,1,1,9,1
 237
 238 # Extension Parameters for Beamforming weights
 239 # numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
 240 ExtBfwUl0=2,9,0,0,9,1
 241 ExtBfwUl1=2,9,0,0,9,1
 242 ExtBfwUl2=2,9,0,0,9,1
 243 ExtBfwUl3=2,9,0,0,9,1
 244 ExtBfwUl4=2,9,0,0,9,1
 245 ExtBfwUl5=2,5,0,0,9,1
 246
 247
 248 nPrbElemSrs=11
 249 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
 250 PrbElemSrs0=0,30,0,1,0,0,1,9,0
 251 PrbElemSrs1=30,30,0,1,0,0,1,9,0
 252 PrbElemSrs2=60,30,0,1,0,0,1,9,0
 253 PrbElemSrs3=90,30,0,1,0,0,1,9,0
 254 PrbElemSrs4=120,30,0,1,0,0,1,9,0
 255 PrbElemSrs5=150,30,0,1,0,0,1,9,0
 256 PrbElemSrs6=180,30,0,1,0,0,1,9,0
 257 PrbElemSrs7=210,30,0,1,0,0,1,9,0
 258 PrbElemSrs8=240,30,0,1,0,0,1,9,0
 259 PrbElemSrs9=270,30,0,1,0,0,1,9,0
 260 PrbElemSrs10=270,3,0,1,0,0,1,9,0
 261
 262
 263 ###########################################################
 264
 265 ## control of IQ byte order
 266 iqswap=0 #do swap of IQ before send buffer to eth
 267 nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
 268 compression=1 # (1) compression enabled (0) compression disabled
 269
 270 ##Debug
 271 debugStop=1 #stop app on 1pps boundary (gps_second % 30)
 272 debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
 273 bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
 274
 275 CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
 276
 277 ##O-RU Settings
 278 totalBFWeights=64 # Total number of Beamforming Weights on RU
 279
 280 Tadv_cp_dl=25 # in us
 281               # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
 282 #Reception Window C-plane DL
 283 T2a_min_cp_dl=285 # 285.42us
 284 T2a_max_cp_dl=429 # 428.12us
 285
 286 #Reception Window C-plane UL
 287 T2a_min_cp_ul=285 # 285.42us
 288 T2a_max_cp_ul=429 # 428.12us
 289
 290 #Reception Window U-plane
 291 T2a_min_up=71  # 71.35in us
 292 T2a_max_up=428 # 428.12us
 293
 294 #Transmission Window
 295 Ta3_min=20 # in us
 296 Ta3_max=32 # in us
 297
 298 ###########################################################
 299 ##O-DU Settings
 300 #C-plane
 301 #Transmission Window Fast C-plane DL
 302 T1a_min_cp_dl=285
 303 T1a_max_cp_dl=429
 304
 305 ##Transmission Window Fast C-plane UL
 306 T1a_min_cp_ul=285
 307 T1a_max_cp_ul=300
 308
 309 #U-plane
 310 ##Transmission Window
 311 T1a_min_up=96  #71 + 25 us
 312 T1a_max_up=196 #71 + 25 us
 313
 314 #Reception Window
 315 Ta4_min=0  # in us
 316 Ta4_max=75 # in us
 317 ###########################################################
 318