1 /******************************************************************************
3 * Copyright (c) 2020 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * @brief Header file to interface implementation to ORAN FH from Application side
21 * @file app_iof_fh_xran.h
23 * @author Intel Corporation
39 #include "xran_fh_o_du.h"
40 #include "xran_pkt_up.h"
42 #define MAX_PKT_BURST (448+4) /* 4x14x8 */
43 #define N_MAX_BUFFER_SEGMENT MAX_PKT_BURST
45 #define NUM_OF_SUBFRAME_PER_FRAME (10)
47 #define SW_FPGA_TOTAL_BUFFER_LEN 4*1024*1024*1024
48 #define SW_FPGA_SEGMENT_BUFFER_LEN 1*1024*1024*1024
49 #define SW_FPGA_FH_TOTAL_BUFFER_LEN 1*1024*1024*1024
50 #define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192)
52 extern void* app_io_xran_handle;
53 extern struct xran_fh_init app_io_xran_fh_init;
54 extern struct xran_fh_config app_io_xran_fh_config[XRAN_PORTS_NUM];
58 uint32_t phaseFlag :1;
60 uint32_t SULFreShift :1;
67 XRANFTHTX_PRB_MAP_OUT,
68 XRANFTHTX_SEC_DESC_OUT,
71 XRANFTHTX_SEC_DESC_IN,
78 MAX_SW_XRAN_INTERFACE_NUM
79 } SWXRANInterfaceTypeEnum;
81 struct xran_io_buf_ctrl {
82 /* -1-this subframe is not used in current frame format
83 0-this subframe can be transmitted, i.e., data is ready
84 1-this subframe is waiting transmission, i.e., data is not ready
85 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1,
88 int32_t bValid ; // when UL rx, it is subframe index.
90 int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE
91 // -1 means that DL packet to be transmitted is not ready in BS
92 int32_t nSegTransferred; // number of data segments has been transmitted or received
93 struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool
94 struct xran_buffer_list sBufferList;
97 struct xran_io_shared_ctrl {
98 enum xran_input_byte_order byteOrder; /* Order of bytes in int16_t in buffer. Big or little endian */
99 enum xran_input_i_q_order iqOrder; /* order of IQs in the buffer */
102 struct xran_io_buf_ctrl sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
103 struct xran_io_buf_ctrl sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
104 struct xran_io_buf_ctrl sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
105 struct xran_io_buf_ctrl sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
106 struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
107 struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrlDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
110 struct xran_io_buf_ctrl sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
111 struct xran_io_buf_ctrl sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
113 struct xran_io_buf_ctrl sFHCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
114 struct xran_io_buf_ctrl sFHCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
117 struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
118 struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
119 struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
120 struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
121 struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
122 struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
124 struct xran_flat_buffer sFrontHaulCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
125 struct xran_flat_buffer sFrontHaulCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
127 /* Cat B SRS buffers */
128 struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
129 struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
131 // struct xran_flat_buffer sFHCpRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
134 struct bbu_xran_io_if {
135 void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; /**< instance per ORAN port per CC */
136 uint32_t nBufPoolIndex[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; /**< unique buffer pool */
137 uint16_t nInstanceNum[XRAN_PORTS_NUM]; /**< instance is equivalent to CC */
139 uint16_t DynamicSectionEna;
140 uint16_t DynamicSectionEnaUL;
141 uint32_t nPhaseCompFlag;
142 uint32_t xranModCompEna;
143 uint32_t xranCompMethod;
147 int32_t bbu_offload; /**< enable packet handling on BBU cores */
150 int32_t num_cc_per_port[XRAN_PORTS_NUM];
151 int32_t map_cell_id2port[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
153 struct xran_io_shared_ctrl ioCtrl[XRAN_PORTS_NUM]; /**< for each O-RU port */
155 struct xran_cb_tag RxCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
156 struct xran_cb_tag PrachCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
157 struct xran_cb_tag SrsCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
158 struct xran_cb_tag BfwCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];
161 struct bbu_xran_io_if* app_io_xran_if_alloc(void);
162 struct bbu_xran_io_if* app_io_xran_if_get(void);
163 void app_io_xran_if_free(void);
164 struct xran_io_shared_ctrl * app_io_xran_if_ctrl_get(uint32_t o_xu_id);
165 int32_t app_io_xran_sfidx_get(uint8_t nNrOfSlotInSf);
167 int32_t app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg, struct xran_fh_init* p_xran_fh_init);
168 int32_t app_io_xran_iq_content_init(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg);
169 int32_t app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg);
170 int32_t app_io_xran_eAxCid_conf_set(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg);
171 int32_t app_io_xran_fh_config_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init, struct xran_fh_config* p_xran_fh_cfg);
172 int32_t app_io_xran_fh_init_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init);
173 int32_t app_io_xran_buffers_max_sz_set (RuntimeConfig* p_o_xu_cfg);
175 int32_t app_io_xran_dl_post_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask, uint32_t nAntStart, uint32_t nAntNum);
177 int32_t app_io_xran_dl_tti_call_back(void * param);
178 int32_t app_io_xran_ul_half_slot_call_back(void * param);
179 int32_t app_io_xran_ul_full_slot_call_back(void * param);
180 int32_t app_io_xran_ul_custom_sym_call_back(void * param, struct xran_sense_of_time* time);
182 int32_t app_io_xran_map_cellid_to_port(struct bbu_xran_io_if * p_xran_io, uint32_t cell_id, uint32_t *ret_cc_id);
184 int32_t app_io_xran_iq_content_init_cp_tx(uint8_t appMode, struct xran_fh_config *pXranConf,
185 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
186 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
188 int32_t app_io_xran_iq_content_init_cp_rx(uint8_t appMode, struct xran_fh_config *pXranConf,
189 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
190 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
192 int32_t app_io_xran_iq_content_init_up_tx(uint8_t appMode, struct xran_fh_config *pXranConf,
193 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
194 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
196 int32_t app_io_xran_iq_content_init_up_prach(uint8_t appMode, struct xran_fh_config *pXranConf,
197 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
198 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
200 int32_t app_io_xran_iq_content_init_up_srs(uint8_t appMode, struct xran_fh_config *pXranConf,
201 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
202 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
204 int32_t app_io_xran_iq_content_get_up_rx(uint8_t appMode, struct xran_fh_config *pXranConf,
205 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
206 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
208 int32_t app_io_xran_iq_content_get_up_prach(uint8_t appMode, struct xran_fh_config *pXranConf,
209 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
210 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
212 int32_t app_io_xran_iq_content_get_up_srs(uint8_t appMode, struct xran_fh_config *pXranConf,
213 struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq,
214 int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId);
216 void app_io_xran_if_stop(void);
222 #endif /* _APP_IO_FH_H_ */