ENV XRAN_DIR $BUILD_DIR/fhi_lib
###Install required libs
-RUN yum install -y libhugetlbfs-utils libhugetlbfs-devel libhugetlbfs numactl-devel ethtool gcc make module-init-tools kmod patch xz iproute pciutils python vim cmake unzip nano mc iputils-ping libaio libaio-devel net-tools wget zip
+RUN yum update -y && \
+ yum install -y libhugetlbfs-utils libhugetlbfs-devel libhugetlbfs numactl-devel ethtool gcc make module-init-tools kmod patch xz iproute pciutils python vim cmake unzip nano mc iputils-ping libaio libaio-devel net-tools wget zip
###Install some libs to compile DPDK
RUN yum groupinstall -y "Development Tools"
RUN yum install -y ncurses-devel hmaccalc zlib-devel binutils-devel elfutils-libelf-devel bc libstdc++-4.8.5-28.el7_5.1.x86_64 gcc-c++ libstdc++-devel-4.8.5-28.el7_5.1.x86_64 autoconf-2.69-11.el7.noarch
###googletest is required for XRAN unittests build and run
-RUN wget https://github.com/google/googletest/archive/release-1.7.0.tar.gz && \
- cd /opt && tar -zxvf $BUILD_DIR/release-1.7.0.tar.gz
-ENV GTEST_ROOT /opt/googletest-release-1.7.0
-ENV GTEST_DIR /opt/googletest-release-1.7.0
+RUN wget https://github.com/google/googletest/archive/v1.8.x.zip && \
+ cd /opt && unzip $BUILD_DIR/v1.8.x.zip
+ENV GTEST_ROOT /opt/googletest-1.8.x/googletest
+ENV GTEST_DIR /opt/googletest-1.8.x/googletest
RUN cd $GTEST_DIR && \
g++ -isystem ${GTEST_DIR}/include -I${GTEST_DIR} -pthread -c ${GTEST_DIR}/src/gtest-all.cc && \
- ar -rv libgtest.a gtest-all.o && cd build-aux/ && cmake $GTEST_DIR && make && cd .. && ln -s build-aux/libgtest_main.a libgtest_main.a
+ ar -rv libgtest.a gtest-all.o
+
###Before install ISS, please go to Intel site to get a free license: https://software.intel.com/en-us/system-studio/choose-download
COPY $icc_license_file $BUILD_DIR/license.lic
####Download Intel System Studio from Intel website and install ICC
-RUN wget http://registrationcenter-download.intel.com/akdlm/irc_nas/emb/15320/system_studio_2019_update_3_ultimate_edition_offline.tar.gz && \
+RUN wget https://registrationcenter-download.intel.com/akdlm/irc_nas/16242/system_studio_2020_ultimate_edition_offline.tar.gz && \
cd /opt && mkdir intel && cp $BUILD_DIR/license.lic intel/license.lic && \
- tar -zxvf $BUILD_DIR/system_studio_2019_update_3_ultimate_edition_offline.tar.gz && \
- cd system_studio_2019_update_3_ultimate_edition_offline && \
+ tar -zxvf $BUILD_DIR/system_studio_2020_ultimate_edition_offline.tar.gz && \
+ cd system_studio_2020_ultimate_edition_offline/ && \
sed -i "s/ACCEPT_EULA.*/ACCEPT_EULA=accept/" silent.cfg && \
sed -i "s/PSET_INSTALL_DIR.*/PSET_INSTALL_DIR=\/opt\/intel/" silent.cfg && \
sed -i "s/.*ACTIVATION_LICENSE_FILE.*/ACTIVATION_LICENSE_FILE=\/opt\/intel\/license.lic/" silent.cfg && \
./install.sh -s silent.cfg
###Set env for ICC
-RUN source /opt/intel/system_studio_2019/bin/iccvars.sh intel64
-ENV PATH /opt/intel/system_studio_2019/bin/:$PATH
+RUN source /opt/intel/system_studio_2020/bin/iccvars.sh intel64
+ENV PATH /opt/intel/system_studio_2020/bin/:$PATH
####Download and build DPDK
ENV RTE_TARGET x86_64-native-linuxapp-icc
####Install octave. Issue when downloading octave. And the octave will take 500MB space.
RUN yum install https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm -y && \
yum install octave -y
-####Install expect
-RUN yum install -y expect
###Copy XRAN source code into docker image
COPY fhi_lib $BUILD_DIR/fhi_lib
COPY misc $BUILD_DIR/misc
-ENV WIRELESS_SDK_TARGET_ISA avx512
-
-####Download and Build FlexRAN FEC SDK, not needed for run L1
-#RUN cd $BUILD_DIR/ && wget https://software.intel.com/sites/default/files/managed/23/b8/FlexRAN-FEC-SDK-19-04.tar.gz && tar -zxvf #FlexRAN-FEC-SDK-19-04.tar.gz && misc/extract-flexran-fec-sdk.ex && cd FlexRAN-FEC-SDK-19-04/sdk && source #/opt/intel/system_studio_2019/bin/iccvars.sh intel64 && ./create-makefiles-linux.sh && cd build-avx512-icc && #make && make install
-
####Build XRAN lib, unittests, sample app
RUN cd $BUILD_DIR/fhi_lib/ && ./build.sh xclean && ./build.sh && cd app && octave gen_test.m
-####Build wls lib
-COPY wls_lib $BUILD_DIR/wls_lib
-RUN cd $BUILD_DIR/wls_lib && ./build.sh xclean && ./build.sh
-ENV DIR_WIRELESS_WLS $BUILD_DIR/wls_lib
-
-####Clone FlexRAN repo from Github
-RUN cd /opt/o-du && git clone https://github.com/intel/FlexRAN.git
-ENV DIR_WIRELESS=/opt/o-du/FlexRAN/l1/
-
-####Build 5g fapi
-COPY fapi_5g $BUILD_DIR/fapi_5g
-ENV DIR_WIRELESS_ORAN_5G_FAPI $BUILD_DIR/fapi_5g
-ENV DEBUG_MODE true
-RUN cd $BUILD_DIR/fapi_5g/build && ./build.sh xclean && ./build.sh
-
-####Copy other folders/files
-COPY setupenv.sh $BUILD_DIR
-
####Unset network proxy
RUN unset http_proxy https_prox ftp_proxy no_proxy
-####Copy built binaries/libraries into docker images
FROM centos:centos7.7.1908
-ENV TARGET_DIR /opt/o-du/
-COPY --from=builder $TARGET_DIR/phy $TARGET_DIR/phy
-COPY --from=builder $TARGET_DIR/FlexRAN $TARGET_DIR/FlexRAN
-
+ENV TARGET_DIR /opt/o-du/phy
+COPY --from=builder /opt/o-du/phy/fhi_lib $TARGET_DIR/fhi_lib
+COPY --from=builder /opt/o-du/phy/misc $TARGET_DIR/misc
COPY --from=builder /usr/lib64/libnuma* /usr/lib64/
-WORKDIR $TARGET_DIR
+ENV XRAN_DIR $TARGET_DIR/fhi_lib
+WORKDIR $TARGET_DIR/fhi_lib
-LABEL description="ORAN O-DU PHY Applications"
+LABEL description="ORAN Fronthaul Sample Application"
------------
The front haul interface, according to the ORAN Fronthaul specification,
-performs communication between O-RAN |br|
-Distributed Unit (O-DU) and O-RAN
+performs communication between O-RAN Distributed Unit (O-DU) and O-RAN
Radio Unit (O-RU) and consists of multiple HW and SW components.
The logical representation of HW and SW components is shown in Figure 1.
From the hardware perspective, two networking ports are used to
communicate to the Front Haul and Back (Mid) Haul network as well as to
receive PTP synchronization. The system timer is used to provide a
-“sense” of time to the gNB |br|
-application.
+“sense” of time to the gNB application.
From the software perspective, the following components are used:
-- Linux PTP provides synchronization of system timer to GPS time:
+* Linux PTP provides synchronization of system timer to GPS time:
-- Ptp4l is used to synchronize oscillator on Network Interface
- Controller (NIC) to PTP GM.
+ - Ptp4l is used to synchronize oscillator on Network Interface
+ Controller (NIC) to PTP GM.
-- Phc2sys is used to synchronize system timer to oscillator on NIC.
+ - Phc2sys is used to synchronize system timer to oscillator on NIC.
-- DPDK to provide the interface to the Ethernet port.
+* DPDK to provide the interface to the Ethernet port.
-- xRAN library is built on top of DPDK to perform U-plane and C-plane
+* xRAN library is built on top of DPDK to perform U-plane and C-plane
functionality according to the ORAN Fronthaul specification.
-- 5GNR reference PHY uses the xRAN library to access interface to O-RU.
+* 5GNR reference PHY uses the xRAN library to access interface to O-RU.
The interface between the library and PHY is defined to communicate
TTI event, symbol time, C-plane information as well as IQ sample
data.
-- 5G NR PHY communicates with the L2 application using the set of
+* 5G NR PHY communicates with the L2 application using the set of
MAC/PHY APIs and the shared memory interface defined as WLS.
-- L2, in turn, can use Back (Mid) Haul networking port to connect to
+* L2, in turn, can use Back (Mid) Haul networking port to connect to
the CU unit in the context of 3GPP specification.
In this document, we focus on the details of the design and
implementation of the xRAN library with respect to providing Front Haul
-functionality for both mmWave and Sub-6 scenarios
+functionality for both mmWave and Sub-6 scenarios.
The xRAN M-plane is not implemented and is outside of the scope of this
-description. Configuration files are used to |br|
-specify selected M-plane
+description. Configuration files are used to specify selected M-plane
level parameters.
ORAN FH Threads
ORAN FH Thread Performs:
- Symbol base “time event” to the rest of the system based on System
- Clock synchronized to GPS time via PTP
+ Clock synchronized to GPS time via PTP.
-- Baseline polling mode driver performing TX and RX of Ethernet packets
+- Baseline polling mode driver performing TX and RX of Ethernet packets.
- Most of the packet processing such as Transport header, Application
header, Data section header and interactions with the rest of the PHY
Communication between L1 and xRAN layer is performed using a set of
callback functions where L1 assigned callback and xRAN layer executes
those functions at a particular event or time moment. Detailed
-information on callback function |br|
-options and setting as well as design,
+information on callback function options and setting as well as design,
can be found in the sections below.
Sample Application Thread Model
-------------------------------
Configuration of a sample application for both O-DU and O-RU follows the
-model of 5G NR l1app application in the |br|
-section of xRAN only. No BBU or
+model of 5G NR l1app application in the section of xRAN only. No BBU or
FEC related threads are needed as minimal xRAN functionality is used
only.
----------------
Figure 1 corresponds to the O-RU part of the xRAN split. Implementation
-of the RU side of the xRAN protocol is not |br|
-covered in this document.
+of the RU side of the xRAN protocol is not covered in this document.
.. image:: images/eNB-gNB-Architecture-with-O-DU-and-RU.jpg
:width: 600
|br|
Information on specific features of C-Plane and U-plane provided in
-Section 6.0. Configuration of S-plane used on test |br|
-setup for simulation
+Section 6.0. Configuration of S-plane used on test setup for simulation
is provided in Appendix Appendix 2.
Data flow separation is based on VLAN (applicable when layer 2 or layer
-------------------------------------------
The ORAN Fronthaul specification defines the latency model of the front
-haul interface and interaction between O-DU and 0-RU. This
+haul interface and interaction between O-DU and O-RU. This
implementation of the xRAN library supports only the category with fixed
timing advance and Defined Transport method. It determines O-DU transmit
-and receive windows based on pre-defined transport network |br|
-characteristics, and the delay characteristics of the RUs within the
+and receive windows based on pre-defined transport network characteristics, and the delay characteristics of the RUs within the
timing domain.
Table 4 below provides default values used for the implementation of
O-DU – O-RU simulation with mmWave scenario. Table 5 and Table 6 below
provide default values used for the implementation of O-DU – O-RU
-simulation with |br|
-numerology 0 and numerology 1 for Sub6 scenarios.
+simulation with numerology 0 and numerology 1 for Sub6 scenarios.
Configuration can be adjusted via configuration files for sample |br|
application and reference PHY. However, simulation of the different
-range of the settings was not performed, and |bR|
-additional implementation changes might be required as well as testing with actual O-RU. |br|
-The
-parameters for the front haul network are out of scope as a direct
-connection between O-DU and 0-RU is used for simulation.
+range of the settings was not performed, and additional implementation changes might be required as well as testing with actual O-RU. The
+parameters for the front haul network are out of scope as a direct connection between O-DU and 0-RU is used for simulation.
|br|
|br|
synchronize local time to GPS time. Details of the configuration used
are provided in Appendix Appendix 2. Local time is used to get Top of
the Second (ToS) as a 1pps event for SW implementation. Timing event is
-obtained by performing polling of local time using |br|
-clock_gettime(CLOCK_REALTIME,..)
+obtained by performing polling of local time using clock_gettime(CLOCK_REALTIME,..)
All-time intervals are specified with respect to GPS time which
corresponds to OTA time.
-----------
An L1 with a proprietary interface and a testmac supporting the FAPI interface are available through the Open Source Community(OSC) github in binary blob form and with the reference
-files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to |br|
-integrate with the O-DU
+files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to integrate with the O-DU
High to check network functionality are available from the same site.
-The L1 App and Testmac |br|
-repository is at https://github.com/intel/FlexRAN/
+The L1 App and Testmac repository is at https://github.com/intel/FlexRAN/
Requirements
------------
* Only Xeon® series Processor with Intel Architecture are supported and the platform should be |br|
- Intel® Xeon® SkyLake / CascadeLake platforms with at least 2.0 GHz core frequency
-* FPGA/ASIC card for FEC acceleration that's compliance with BBDev framework and interface if you need run high throughput case with HW FEC card assistant.
-* Bios setting steps and options might have difference, however at least you should have the same Bios setting as decribed in the README.me file available at https://github.com/intel/FlexRAN Bios settings section
-* Runing with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization.
+ either Intel® Xeon® SkyLake or CascadeLake with at least 2.0 GHz core frequency.
+* FPGA/ASIC card for FEC acceleration that is compliant with the BBDev framework and interface. Only needed to run high throughput cases with the HW FEC card assistance.
+* Bios setting steps and options may have differences, however at least you should have the same Bios setting as decribed in the README.md file available at https://github.com/intel/FlexRAN Bios settings section.
+* Running with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization.
Dependencies
------------
-* Centos OS 7 (7.5+) (7.7 was used for the L1 and testmac binaries)
+* Centos OS 7 (7.5+) (7.7 was used for the L1 and testmac binaries).
* RT Kernel kernel-rt-3.10.0-1062.12.1.rt56.1042
-* Data Plane Development Kit (DPDK v18.08) with corresponding DPDK patch according to O-RAN FH setup |br|
- configuation section.
+* Data Plane Development Kit (DPDK v19.11) with corresponding DPDK patch according to |br| O-RAN FH setup configuration section.
-* FEC SDK lib which was needed when you run FEC in SW mode, download through: https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules
+* FEC SDK lib which is needed when you run the FEC in SW mode, download through: https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules
-* Intel® C++ Compiler v19.0.3 is used for test application and system integration. Free Intel® C++ Compiler can be gotten through below link with community license, however the version you could get is always latest ICC version, the verification for that version might not be performed yet, please feedback through O-DU Low WIKI page if you meet issue.
+* Intel® C++ Compiler v19.0.3 is used for test application and system integration. Free Intel® C++ Compiler can be gotten through below link with community license, however the version you get is always the latest ICC version, the verification for that version might not have been performed yet, please feedback through O-DU Low WIKI page if you meet any issues.
https://software.intel.com/en-us/system-studio/choose-download
-* Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64) for O-RAN FH Sample App, which is not needed if running sample APP for O-RAN FHI is not performed.
+* Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64) for O-RAN FH Sample App. Only needed to run the sample APP for O-RAN FHI.
A.5 PTP Synchronization
-----------------------
Precision Time Protocol (PTP) provides an efficient way to synchronize
-time on the network nodes. This protocol uses Master-Slave architecture.
-Grandmaster Clock (Master) is a reference clock for the other nodes,
-which adapt their clocks to the master.
+time on the network nodes. This protocol uses Primary-Slave architecture.
+Main Reference Clock (Primary) is a reference clock for the other nodes,
+which adapt their clocks to the Primary.
-Using Physical Hardware Clock (PHC) from the Grandmaster Clock, NIC port
-precision timestamp packets can be served for other network nodes. Slave
-nodes adjust their PHC to the master following the IEEE 1588
+Using Physical Hardware Clock (PHC) from the Main Reference Clock, NIC port
+precision timestamp packets can be served for other network nodes. Secondary
+nodes adjust their PHC to the Primary following the IEEE 1588
specification.
There are existing implementations of PTP protocol that are widely used
----------
This tool handles all PTP traffic on the provided NIC port and updated
-PHC. It also determines the Grandmaster Clock and tracks |br|
-synchronization
+PHC. It also determines the Primary Reference Clock and tracks synchronization
status. This tool can be run as a daemon or as a regular Linux\*
application. When the synchronization is reached, it gives output on the
screen for precision tracking. The configuration file of ptp4l contains
./ptp4l -f ./configs/default.cfg -2 -i <if_name> -m
-The output below shows what the output on non-master node should look
+The output below shows what the output on non-Primary node should look
like when synchronization is started. This means that PHC on this
-machine is synchronized to the master PHC::
+machine is synchronized to the Primary PHC::
ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[1434166.384]: port 1: new foreign master fcaf6a.fffe.029708-1
+ ptp4l[1434166.384]: port 1: new foreign primary fcaf6a.fffe.029708-1
- ptp4l[1434170.352]: selected best master clock fcaf6a.fffe.029708
+ ptp4l[1434170.352]: selected best primary clock fcaf6a.fffe.029708
ptp4l[1434170.352]: updating UTC offset to 37
ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
- ptp4l[1434171.763]: master offset -5873 s0 freq -18397 path delay 2778
+ ptp4l[1434171.763]: primary offset -5873 s0 freq -18397 path delay 2778
- ptp4l[1434172.763]: master offset -6088 s2 freq -18612 path delay 2778
+ ptp4l[1434172.763]: primary offset -6088 s2 freq -18612 path delay 2778
ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on
MASTER_CLOCK_SELECTED
- ptp4l[1434173.763]: master offset -5886 s2 freq -24498 path delay 2732
+ ptp4l[1434173.763]: primary offset -5886 s2 freq -24498 path delay 2732
- ptp4l[1434174.763]: master offset 221 s2 freq -20157 path delay 2728
+ ptp4l[1434174.763]: primary offset 221 s2 freq -20157 path delay 2728
- ptp4l[1434175.763]: master offset 1911 s2 freq -18401 path delay 2724
+ ptp4l[1434175.763]: primary offset 1911 s2 freq -18401 path delay 2724
- ptp4l[1434176.763]: master offset 1774 s2 freq -17964 path delay 2728
+ ptp4l[1434176.763]: primary offset 1774 s2 freq -17964 path delay 2728
- ptp4l[1434177.763]: master offset 1198 s2 freq -18008 path delay 2728
+ ptp4l[1434177.763]: primary offset 1198 s2 freq -18008 path delay 2728
- ptp4l[1434178.763]: master offset 746 s2 freq -18101 path delay 2755
+ ptp4l[1434178.763]: primary offset 746 s2 freq -18101 path delay 2755
- ptp4l[1434179.763]: master offset 218 s2 freq -18405 path delay 2792
+ ptp4l[1434179.763]: primary offset 218 s2 freq -18405 path delay 2792
- ptp4l[1434180.763]: master offset 103 s2 freq -18454 path delay 2792
+ ptp4l[1434180.763]: primary offset 103 s2 freq -18454 path delay 2792
- ptp4l[1434181.763]: master offset -13 s2 freq -18540 path delay 2813
+ ptp4l[1434181.763]: primary offset -13 s2 freq -18540 path delay 2813
- ptp4l[1434182.763]: master offset 9 s2 freq -18521 path delay 2813
+ ptp4l[1434182.763]: primary offset 9 s2 freq -18521 path delay 2813
- ptp4l[1434183.763]: master offset 11 s2 freq -18517 path delay 2813
+ ptp4l[1434183.763]: primary offset 11 s2 freq -18517 path delay 2813
phc2sys
-----------
The PHC clock is independent from the system clock. Synchronizing only
-PHC does not make the system clock exactly the same as the master. The
+PHC does not make the system clock exactly the same as the primary. The
xRAN library requires use of the system clock to determine a common
-point in time on two |br|
-machines (O-DU and RU) to start transmission at the
-same moment and keep time frames defined by ORAN Fronthaul |br|
-specification.
+point in time on two machines (O-DU and RU) to start transmission at the
+same moment and keep time frames defined by ORAN Fronthaul specification.
This application keeps the system clock updated to PHC. It makes it
possible to use POSIX timers as a time reference in xRAN application.
Configuration C3 27 can be simulated for O-DU using a separate server
acting as Fronthaul Network and O-RU at the same time. O-RU server can
-be configured to relay PTP and act as PTP master for O-DU. Settings
-below can be used to |br|
-instantiate this scenario. The difference is that
+be configured to relay PTP and act as PTP primary for O-DU. Settings
+below can be used to instantiate this scenario. The difference is that
on the O-DU side, the Fronthaul port can be used as the source of PTP as
well as for U-plane and C-plane traffic.
# Run time options
-1.Start slave port toward PTP GM::
+1.Start secondary port toward PTP GM::
./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 –m
ptp4l[3904470.275]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[3904471.085]: port 1: new foreign master fcaf6a.fffe.029708-1
+ ptp4l[3904471.085]: port 1: new foreign primary fcaf6a.fffe.029708-1
- ptp4l[3904475.053]: selected best master clock fcaf6a.fffe.029708
+ ptp4l[3904475.053]: selected best primary clock fcaf6a.fffe.029708
ptp4l[3904475.053]: updating UTC offset to 37
ptp4l[3904475.053]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
- ptp4l[3904477.029]: master offset 196 s0 freq -18570 path delay 1109
+ ptp4l[3904477.029]: primary offset 196 s0 freq -18570 path delay 1109
- ptp4l[3904478.029]: master offset 212 s2 freq -18554 path delay 1109
+ ptp4l[3904478.029]: primary offset 212 s2 freq -18554 path delay 1109
ptp4l[3904478.029]: port 1: UNCALIBRATED to SLAVE on
MASTER_CLOCK_SELECTED
- ptp4l[3904479.029]: master offset 86 s2 freq -18468 path delay 1109
+ ptp4l[3904479.029]: primary offset 86 s2 freq -18468 path delay 1109
- ptp4l[3904480.029]: master offset 23 s2 freq -18505 path delay 1124
+ ptp4l[3904480.029]: primary offset 23 s2 freq -18505 path delay 1124
- ptp4l[3904481.029]: master offset 3 s2 freq -18518 path delay 1132
+ ptp4l[3904481.029]: primary offset 3 s2 freq -18518 path delay 1132
- ptp4l[3904482.029]: master offset -169 s2 freq -18689 path delay 1141
+ ptp4l[3904482.029]: primary offset -169 s2 freq -18689 path delay 1141
2.Synchronize local timer clock on O-RU for sample application::
phc2sys[3904512.268]: CLOCK_REALTIME phc offset -300 s2 freq -38892
delay 1532
-3. Modify configs/default.cfg as shown below to run PTP master on
+3. Modify configs/default.cfg as shown below to run PTP primary on
Fronthaul of O-RU::
diff --git a/configs/default.cfg b/configs/default.cfg
# Run time options
-4.Start PTP master toward O-DU::
+4.Start PTP primary toward O-DU::
./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 –m
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best
- master
+ primary
- ptp4l[3903863.734]: assuming the grand master role
+ ptp4l[3903863.734]: assuming the main reference role
-5.Synchronize local NIC PTP master clock to local NIC PTP slave clock::
+5.Synchronize local NIC PTP primary clock to local NIC PTP secondary clock::
./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
6. On O-DU Install PTP for Linux tools from source code the same way as
on O-RU above but no need to apply the patch for msg.c
-7. Start slave port toward PTP master from O-RU using the same
+7. Start secondary port toward PTP primary from O-RU using the same
default_slave.cfg as on O-RU (see above)::
./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 –m
ptp4l[809092.934]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[809092.949]: port 1: new foreign master 3cfdfe.fffe.bd005d-1
+ ptp4l[809092.949]: port 1: new foreign primary 3cfdfe.fffe.bd005d-1
- ptp4l[809096.949]: selected best master clock 3cfdfe.fffe.bd005d
+ ptp4l[809096.949]: selected best primary clock 3cfdfe.fffe.bd005d
ptp4l[809096.950]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
requests for current port state and comparing it with the expected
value. This verification should be done before initialization.
-*notes. “SLAVE” is the only expected value in this release; only a
-non-master scenario is supported currently.*
+*notes. “SECONDARY” is the only expected value in this release; only a
+non-primary scenario is supported currently.*
+
+*notes1. Inclusive language terms were used except for the PTP traces where the source code has
+not been updated to support the inclusive language terms yet.*
.. |image0| image:: media/image3.png
:width: 2.52364in
The recommended configuration for NICs is::
- ethtool -i enp216s0f0
-
+ ethtool -i enp33s0f0
driver: i40e
-
- version: 2.9.21
-
- firmware-version: 6.80 0x80003d05 1.2007.0
-
+ version: 2.10.19.82
+ firmware-version: 7.20 0x80007949 1.2585.0
expansion-rom-version:
-
- bus-info: 0000:d8:00.0
-
+ bus-info: 0000:21:00.0
supports-statistics: yes
-
supports-test: yes
-
supports-eeprom-access: yes
-
supports-register-dump: yes
-
supports-priv-flags: yes
-
- [root@5gnr-sc12-xran testmac]# ethtool -T enp216s0f0::
-
-
- Time stamping parameters for enp216s0f0:
-
- Capabilities:
-
- hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
-
- software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
-
- hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
-
- software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
-
- software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
-
- hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
-
- PTP Hardware Clock: 2
-
- Hardware Transmit Timestamp Modes:
-
- off (HWTSTAMP_TX_OFF)
-
- on (HWTSTAMP_TX_ON)
-
- Hardware Receive Filter Modes:
-
- none (HWTSTAMP_FILTER_NONE)
-
- ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
-
- ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
-
- ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
-
- ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
-
- ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
-
- ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
-
- ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
-
- ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
-
- ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
-
- ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
-
- ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
-
-PTP Grand Master is required to be available in the network to provide
+ ethtool -T enp33s0f0
+ Time stamping parameters for enp33s0f0:
+ Capabilities:
+ hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
+ software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
+ hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
+ software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
+ software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
+ hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
+ PTP Hardware Clock: 4
+ Hardware Transmit Timestamp Modes:
+ off (HWTSTAMP_TX_OFF)
+ on (HWTSTAMP_TX_ON)
+ Hardware Receive Filter Modes:
+ none (HWTSTAMP_FILTER_NONE)
+ ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
+ ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
+ ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
+ ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
+ ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
+ ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
+ ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
+ ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
+ ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
+ ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
+ ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
+
+
+A PTP Main Reference Clock is required to be available in the network to provide
synchronization of both O-DU and RU to GPS time.
-The software package includes Linux\* CentOS\* operating system and RT
-patch according to *Cloud-Native*-platform *Setup* document (refer to
-Table 2). Only real-time HOST is required.
-
1.Installing Intel® C++ Compiler v19.0.3 is preferred. or you could get
Intel® C++ Compiler through below link with community license,
however the version you could get is always latest version, the
feedback through O-DU Low project WIKI page if you meet an issue. |br|
`https://software.intel.com/en-us/system-studio/choose-download <https://software.intel.com/en-us/system-studio/choose-download%20>`__
-2.Download DPDK 18.08.
-
-3.With FlexRAN BBDev patch as per release 20.02. (Note currently this may require a license from Intel)
+2.Download DPDK 19.11.
-4.Change DPDK files according to below diff information which relevant to O-RAN FH::
+3.Change DPDK files according to below diff information which relevant to O-RAN FH::
diff --git a/drivers/net/i40e/i40e_ethdev.c
b/drivers/net/i40e/i40e_ethdev.c
[root@xran dpdk]# ./usertools/dpdk-setup.sh
- select [16] x86_64-native-linuxapp-icc
+ select [39] x86_64-native-linuxapp-icc
- select [19] Insert VFIO module
+ select [46] Insert VFIO module
- exit [35] Exit Script
+ exit [62] Exit Script
6.Make below file changes in dpdk that assure i40e to get best
latency of packet processing::
cat /proc/cmdline
- BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64
- root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root
- rd.lvm.lv=centos/swap intel_iommu=on iommu=pt usbcore.autosuspend=-1
- selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
- intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off
- idle=poll hugepagesz=1G hugepages=40 hugepagesz=2M hugepages=0
- default_hugepagesz=1G isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39
- kthread_cpus=0,20 irqaffinity=0,20 nohz_full=1-19,21-39
+ BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro
+ crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt
+ usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
+ intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll
+ hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G
+ isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20
+ nohz_full=1-19,21-39
2.Download from Intel Website and install updated version of i40e
-driver if needed. The current recommended version of i40e is x2.9.21.
+driver if needed. The current recommended version of i40e is 2.10.19.82.
+However, any latest version of i40e after x2.9.21 expected to be functional for ORAN FH.
3.Identify PCIe Bus address of the Front Haul NIC::
- lspci \|grep Eth
-
- 19:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
-
- 19:00.1 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
-
- 41:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
-
- 41:00.1 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
-
- d8:00.0 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02) <<< port used for FH
-
- d8:00.1 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02)
+ lspci |grep Eth
+ 19:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 19:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 1d:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 1d:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 67:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722 for 10GBASE-T (rev 09)
+
4.Identify the Ethernet device name::
- ethtool -i enp216s0f0
-
+ ethtool -i enp33s0f0
driver: i40e
-
- version: 2.9.21
-
- firmware-version: 6.80 0x80003d05 1.2007.0
-
+ version: 2.10.19.82
+ firmware-version: 7.20 0x80007949 1.2585.0
expansion-rom-version:
-
- bus-info: 0000:d8:00.0
-
+ bus-info: 0000:21:00.0
supports-statistics: yes
-
supports-test: yes
-
supports-eeprom-access: yes
-
supports-register-dump: yes
-
supports-priv-flags: yes
+ Enable
+
5.Enable two virtual functions (VF) on the device::
- echo 2 > /sys/class/net/enp216s0f0/device/sriov_numvfs
+ echo 2 > /sys/class/net/enp33s0f0/device/sriov_numvfs
More information about VFs supported by Intel NICs can be found at
https://doc.dpdk.org/guides/nics/intel_vf.html.
lspci|grep Eth
- 19:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
+ 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 21:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
+ 21:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
+
+
+6.Configure MAC address and VLAN settings for VFs for XRAN, based on
+requirements for xRAN scenario and assignment of VLAN ID using IP
+tool perform configuration of VF.
- 19:00.1 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
+ Example where O-DU and O-RU simulation run on the same sytem::
+
+ #!/bin/bash
- 41:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
+ echo 2 > /sys/bus/pci/devices/0000\:21\:00.0/sriov_numvfs
+ ip link set enp33s0f0 vf 1 mac 00:11:22:33:44:66 vlan 1
+ ip link set enp33s0f0 vf 0 mac 00:11:22:33:44:66 vlan 2
+ echo 2 > /sys/bus/pci/devices/0000\:21\:00.1/sriov_numvfs
+ ip link set enp33s0f1 vf 1 mac 00:11:22:33:44:55 vlan 1
+ ip link set enp33s0f1 vf 0 mac 00:11:22:33:44:55 vlan 2
- 41:00.1 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
+ where output is next::
- d8:00.0 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02)
+ [root@xran app]# ip link show
- d8:00.1 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02)
+ 1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
- d8:02.0 Ethernet controller: Intel Corporation XL710/X710 Virtual
- Function (rev 02)
+ link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
- d8:02.1 Ethernet controller: Intel Corporation XL710/X710 Virtual
- Function (rev 02)
-
-6.Configure MAC address and VLAN settings for VFs for XRAN, based on
-requirements for xRAN scenario and assignment of VLAN ID using IP
-tool perform configuration of VF as shown below::
-
- [root@xran app]# ip link set enp216s0f0 vf 0 mac 00:11:22:33:44:66 vlan
- 2
+ 2: enp25s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- [root@xran app]# ip link set enp216s0f0 vf 1 mac 00:11:22:33:44:66 vlan
- 1
+ link/ether 64:4c:36:10:1f:30 brd ff:ff:ff:ff:ff:ff
- [root@xran app]# ip link show
+ 3: enp25s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- 1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode
- DEFAULT qlen 1
+ link/ether 64:4c:36:10:1f:31 brd ff:ff:ff:ff:ff:ff
- link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
+ 4: enp29s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
+
+ link/ether 64:4c:36:10:1f:34 brd ff:ff:ff:ff:ff:ff
- 2: enp65s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 5: enp29s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether a4:bf:01:3e:6b:79 brd ff:ff:ff:ff:ff:ff
+ link/ether 64:4c:36:10:1f:35 brd ff:ff:ff:ff:ff:ff
- 3: eno2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP
- mode DEFAULT qlen 1000
+ 6: enp33s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether a4:bf:01:3e:6b:7a brd ff:ff:ff:ff:ff:ff
+ link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff
- 4: enp25s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ vf 0 MAC 00:11:22:33:44:66, vlan 2, spoof checking on, link-state auto, trust off
- link/ether 90:e2:ba:d3:b2:ec brd ff:ff:ff:ff:ff:ff
+ vf 1 MAC 00:11:22:33:44:66, vlan 1, spoof checking on, link-state auto, trust off
- 5: enp129s0f0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq
- state DOWN mode DEFAULT qlen 1000
+ 7: enp33s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 3c:fd:fe:a8:e0:70 brd ff:ff:ff:ff:ff:ff
+ link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff
- 6: enp129s0f1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq
- state DOWN mode DEFAULT qlen 1000
+ vf 0 MAC 00:11:22:33:44:55, vlan 2, spoof checking on, link-state auto, trust off
- link/ether 3c:fd:fe:a8:e0:71 brd ff:ff:ff:ff:ff:ff
+ vf 1 MAC 00:11:22:33:44:55, vlan 1, spoof checking on, link-state auto, trust off
- 7: enp216s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 8: eno1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 3c:fd:fe:9e:93:68 brd ff:ff:ff:ff:ff:ff
+ link/ether a4:bf:01:3e:1f:be brd ff:ff:ff:ff:ff:ff
- vf 0 MAC 00:11:22:33:44:66, vlan 2, spoof checking on, link-state auto,
- trust off
+ 9: eno2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- vf 1 MAC 00:11:22:33:44:66, vlan 1, spoof checking on, link-state auto,
- trust off
+ link/ether a4:bf:01:3e:1f:bf brd ff:ff:ff:ff:ff:ff
- 8: enp25s0f1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq
- state DOWN mode DEFAULT qlen 1000
+ 10: npacf0g0l0: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
- link/ether 90:e2:ba:d3:b2:ed brd ff:ff:ff:ff:ff:ff
+ link/generic
- 9: enp216s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 11: npacf0g0l1: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
- link/ether 3c:fd:fe:9e:93:69 brd ff:ff:ff:ff:ff:ff
+ link/generic
- 12: enp216s2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 12: npacf0g0l2: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
- link/ether 96:fa:4d:04:4d:87 brd ff:ff:ff:ff:ff:ff
+ link/generic
- 13: enp216s2f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq
- state UP mode DEFAULT qlen 1000
+ 13: npacf0g0l3: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
- link/ether a6:67:49:bb:bd:5e brd ff:ff:ff:ff:ff:ff
+ link/generic
After this step FH NIC is configured.
-VF for C-plane is VF1 on PH enp216s0f0, it has ETH mac address
-00:11:22:33:44:66 and VLAN tag 1. PCIe Bus address is VF1 is d8:02.1
+O-DU
+
+VF for C-plane is VF1 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 1. PCIe Bus address is VF1 is 21d8:02.1
+
+VF for U-plane is VF0 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 2. PCIe Bus address is VF1 is 21d8:02.0
+
+O-RU
+
+VF for C-plane is VF1 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 1. PCIe Bus address is VF1 is 21:0a.1
+
+VF for U-plane is VF0 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 2. PCIe Bus address is VF1 is 21:0a.0
-VF for U-plane is VF0 on PH enp216s0f0, it has ETH mac address
-00:11:22:33:44:66 and VLAN tag 2. PCIe Bus address is VF1 is d8:02.0
A.4 Install and Configure Sample Application
--------------------------------------------
export GTEST_ROOT=`pwd`/gtest-1.7.0
- export RTE_SDK=`pwd`/dpdk-18.08
+ export RTE_SDK=`pwd`/dpdk-19.11
export RTE_TARGET=x86_64-native-linuxapp-icc
Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1
used for U-plane and C-plane correspondingly::
- ./build/sample-app ./usecase/mu0_10mhz/config_file_o_du.dat 0000:d8:02.0
- 0000:d8:02.1
+ ./build/sample-app -c ./usecase/mu0_10mhz/config_file_o_du.dat -p 2 0000:21d8:02.0 0000:21d8:02.1
4. Run application using run_o_du.sh (run_o_ru.sh).
Figure 8. ORAN Fronthaul Process
The XRAN library provides support for transporting In-band and
-Quadrature (IQ) samples between the O-DU and O-RU within the RAN
+Quadrature (IQ) samples between the O-DU and O-RU within the xRAN
architecture based on functional split 7.2x. The library defines the
xRAN packet formats to be used to transport radio samples within Front
Haul according to the ORAN Fronthaul specification. It provides
functionality for generating xRAN packets, appending IQ samples in the
-packet payload, and extracting IQ samples from xRAN packets. The Bronze release version
-of the library supports U-plane and C-plane only. It is ready to
-be used in the PTP synchronized |br|
-environment.
+packet payload, and extracting IQ samples from xRAN packets.
-Regarding the clock model and synchronization topology, configurations
+Note: The Bronze release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment.
+
+Note: Regarding the clock model and synchronization topology, configurations
C1 and C3 of the connection between O-DU and O-RU are the only
configurations supported in this release of the xRAN implementation.
-Quality of PTP synchronization with respect to S-plane of ORAN Fronthaul
-requirements as defined for O-RU is out of the scope of this document.
-PTP master and PTP slave configuration are expected to satisfy only the
-O-DU side of |br|
-requirements and provide the “best-effort” PTP master for
+Note: Quality of PTP synchronization with respect to S-plane of ORAN
+Fronthaul requirements as defined for O-RU is out of the scope of this
+document. PTP primary and PTP secondary configuration are expected to satisfy
+only the O-DU side of requirements and provide the “best-effort” PTP primary for
O-RU. This may or may not be sufficient for achieving the end to end
system requirements of S-plane. Specialized dedicated NIC card with
-additional HW functionality might be |br|
-required to achieve PTP master
+additional HW functionality might be required to achieve PTP primary
functionality to satisfy O-RU precision requirements for RAN deployments
scenarios.
---------------------
The ORAN Fronthaul specification defines a list of mandatory
-functionality. Not all features defined as Mandatory for |br|
-O-DU are
+functionality. Not all features defined as Mandatory for O-DU are
currently supported to fully extended. The following tables contain
information on what is available and the level of validation performed
for this release.
-2. Cells with a red background are listed as mandatory in the
+Note. Cells with a red background are listed as mandatory in the
specification but not supported in this implementation of xRAN.
Table 7. ORAN Mandatory and Optional Feature Support
| | 8 spatial | | |
| | streams) | | |
+-----------------+-----------------+-----------+----------------+
-| | Support for | | N |
+| | Support for | | Y |
| | CAT-A RU (> 8 | | |
| | spatial | | |
| | streams) | | |
| | UE Channel Info | | N |
+-----------------+-----------------+-----------+----------------+
| Bandwidth | Programmable | Mandatory | Y |
-| Saving | s | | |
-| | tatic-bit-width | | |
+| Saving | static-bit-width| | |
| | Fixed Point IQ | | |
+-----------------+-----------------+-----------+----------------+
-| | Real-time | | Y |
-| | var | | |
-| | iable-bit-width | | |
+| | Real-time | | Y |
+| | variable-bit | | |
+| | -width | | |
+-----------------+-----------------+-----------+----------------+
| | Compressed IQ | | Y |
+-----------------+-----------------+-----------+----------------+
Table 8. Levels of Validation
+------------+------------+------------+------------+-----+-----+---+
-| Category | Item | Q4 (20.02) | | | | |
+| Category | Item | Q4 (20.04) | | | | |
+============+============+============+============+=====+=====+===+
| | | Status | C | I | T | |
+------------+------------+------------+------------+-----+-----+---+
| | and | | | | | |
| | U-plane | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Max Number | 4 | Y | Y | N | |
+| | Max Number | 16 | Y | Y | N | |
| | of VLAN | | | | | |
| | per | | | | | |
| | physical | | | | | |
| | Total | Supported | Y | N | N | |
| | _msgs_rcvd | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| B\ | RU | Index and | Y | N | N | |
+| B\ | RU | Index and | Y | Y | N | |
| eamforming | b\ | weights | | | | |
| | eamforming | | | | | |
| | type | | | | | |
| | control | | | | | |
| | method | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Number of | No-re | Y | N | N | |
+| | Number of | No-re | Y | Y | N | |
| | beams | strictions | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| IQ | U-plane | Supported | Y | N | N | |
+| IQ | U-plane | Supported | Y | Y | Y | |
| c\ | data | | | | | |
| ompression | c\ | | | | | |
| | ompression | | | | | |
| | method | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | U-plane | BFP: | Y | N | N | |
+| | U-plane | BFP: | Y | Y | Y | |
| | data IQ | 8,9,12,14 | | | | |
| | bitwidth | bits | | | | |
| | (Before / | | | | | |
| | co | | | | | |
| | mpression) | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Static | Supported | Y | Y | N | |
+| | Static | Supported | N | N | N | |
| | con\ | | | | | |
| | figuration | | | | | |
| | of U-plane | | | | | |
| | Section | Supported | Y | Y | Y | |
| | Type 1 | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Section | Supported | Y | Y | N | |
+| | Section | Supported | Y | Y | Y | |
| | Type 3 | | | | | |
+------------+------------+------------+------------+-----+-----+---+
| | Section | Not | N | N | N | |
| | | (section | | | | |
| | | type) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | udCompHdr | Supported | N | N | N |
+| | | udCompHdr | Supported | Y | Y | N |
| | | (user data | | | | |
| | | c\ | | | | |
| | | ompression | | | | |
| | | Extension | | | | |
| | | Commands* | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | extType | Supported | Y | N | N |
+| | | extType | Supported | Y | Y | N |
| | | (extension | | | | |
| | | type) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | ef | Supported | Y | N | N |
+| | | ef | Supported | Y | Y | N |
| | | (extension | | | | |
| | | flag) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | extLen | Supported | Y | N | N |
+| | | extLen | Supported | Y | Y | N |
| | | (extension | | | | |
| | | length) | | | | |
+------------+------------+------------+------------+-----+-----+---+
| | E\ | | | | | |
| | xtensions | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | *ExtType=1:| bfwCompHdr | Supported | Y | N | N |
+| | *ExtType=1:| bfwCompHdr | Supported | Y | Y | N |
| | B\ | (beam\ | | | | |
| | eamforming | forming | | | | |
| | Weights | weight | | | | |
| | Type* | ompression | | | | |
| | | header) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | bf | Supported | Y | N | N |
+| | | bf | Supported | Y | Y | N |
| | | wCompParam | | | | |
| | | (b\ | | | | |
| | | eamforming | | | | |
| | | ompression | | | | |
| | | parameter) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | bfwl | Supported | Y | N | N |
+| | | bfwl | Supported | Y | Y | N |
| | | (b\ | | | | |
| | | eamforming | | | | |
| | | weight | | | | |
| | | in-phase | | | | |
| | | value) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | bfwQ | Supported | Y | N | N |
+| | | bfwQ | Supported | Y | Y | N |
| | | (b\ | | | | |
| | | eamforming | | | | |
| | | weight | | | | |
are supported.
Handling of ecpriRtcid/ecpriPcid Bit field size is configurable and can
-be defined on the initialization stage of the xRAN |br|
-library.
+be defined on the initialization stage of the xRAN library.
.. image:: images/Bit-Allocations-of-ecpriRtcid-ecpriPcid.jpg
:width: 600
-------
The following diagrams show xRAN packet protocols’ headers and data
-arrangement with and without compression |br|
-support.
+arrangement with and without compression support.
XRAN packet meant for traffic with compression enabled has the
Compression Header added after each Application Header. According to
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The Common Radio Application Header is followed by the Application
-Header that is repeated for each Data Section |br|
-within the eCPRI message.
+Header that is repeated for each Data Section within the eCPRI message.
The relevant section of xRAN packet is shown in color.
.. image:: images/Data-Section-Application-Data-Header.jpg
~~~~~~~~~~~~
An xRAN packet data payload contains a number of PRBs. Each PRB is built
-of 12 IQ samples. The supported IQ bit width is 16. udCompParam is not
-included in the data payload as compression currently is not supported.
-The data section is shown in color.
+of 12 IQ samples. Flexible IQ bit width is supported. If compression is enabled udCompParam is included in the data payload. The data section is shown in colour.
.. image:: images/Data-Payload.jpg
:width: 600
C-Plane messages are encapsulated using a two-layered header approach.
The first layer consists of an eCPRI standard header, including
corresponding fields used to indicate the message type, while the second
-layer is an application layer |br|
-including necessary fields for control and
-synchronization. Within the application layer, a “section” defines the |br|
-characteristics of U-plane data to be transferred or received from a
-beam with one pattern id. In general, the transport header, |br|
-application
+layer is an application layer including necessary fields for control and
+synchronization. Within the application layer, a “section” defines the characteristics of U-plane data to be transferred or received from a
+beam with one pattern id. In general, the transport header,application
header, and sections are all intended to be aligned on 4-byte boundaries
-and are transmitted in “network byte |br|
-order” meaning the most significant
+and are transmitted in “network byte order” meaning the most significant
byte of a multi-byte parameter is transmitted first.
Table 9 is a list of sections currently supported.
Section extensions are not supported in this release.
The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h
-and the fields are appropriately re-ordered in |br|
-order to apply the
+and the fields are appropriately re-ordered in order to apply the
conversion of network byte order after setting values.
+The comments in source code of xRAN lib can be used to see more information on
+implementation specifics of handling sections as well as particular fields.
+Additional changes may be needed on C-plane to perform IOT with O-RU depending on the scenario.
Ethernet Header
~~~~~~~~~~~~~~~
- timeOffset
-- frameStrucutre: defined as the structure of
+- frameStructure: defined as the structure of
xran_cp_radioapp_frameStructure
- cpLength
Install ICC
------------
Intel® C++ Compiler v19.0.3 is used for the test application and system integration with L1,
-The Intel® C++ Compiler can be obtained using the follwoing link https://software.intel.com/en-us/system-studio/choose-download with community |br|
+The Intel® C++ Compiler can be obtained using the following link https://software.intel.com/en-us/system-studio/choose-download with community |br|
license::
COPY $icc_license_file $BUILD_DIR/license.lic
performed yet, so please provide feedback through O-DU Low project WIKI page if you face any issues.*
-Download Intel System Studio from Intel website and install ICC ::
+You can follow the installation guide from above website to download Intel System Studio and install. Intel® Math Kernel Library, Intel® Integrated Performance Primitives and Intel® C++ Compiler are mandatory components.
+Here we are using the Linux* Host,Linux* Target and standalone installer as one example, below link might need update based on the website ::
- #wget https://registrationcenter-download.intel.com/akdlm/irc_nas/16242/system_studio_2020_ultimate_edition_offline.tar.gz
+ #wget https://registrationcenter-download.intel.com/akdlm/irc_nas/16789/system_studio_2020_u2_ultimate_edition_offline.tar.gz
#cd /opt && mkdir intel && cp $BUILD_DIR/license.lic intel/license.lic
- #tar -zxvf $BUILD_DIR/system_studio_2020_ultimate_edition_offline.tar.gz
+ #tar -zxvf $BUILD_DIR/system_studio_2020_u2_ultimate_edition_offline.tar.gz
Edit system_studio_2020_ultimate_edition_offline/silent.cfg to accept the EULA file as below example::
#export PATH=/opt/intel/system_studio_2020/bin/:$PATH
-Build DPDK
------------
+Download and Build DPDK
+-----------------------
- download DPDK::
- #wget http://fast.dpdk.org/rel/dpdk-18.08.tar.xz
- #tar -xf dpdk-18.08.tar.xz
+ #wget http://static.dpdk.org/rel/dpdk-19.11.tar.x
+ #tar -xf dpdk-19.11.tar.xz
#export RTE_TARGET=x86_64-native-linuxapp-icc
- #export RTE_SDK=Intallation_DIR/dpdk-18.08
+ #export RTE_SDK=Intallation_DIR/dpdk-19.11
- - patch DPDK for O-RAN FHI lib, this patch is specific for O-RAN FHI to reduce the data transmission latency of Intel NIC. This may not be needed for some NICs, please refer to O-RAN FHI Lib Introduction -> setup configuration -> A.2 prerequisites
+ - patch DPDK for O-RAN FHI lib, this patch is specific for O-RAN FHI to reduce the data transmission latency of Intel NIC. This may not be needed for some NICs, please refer to |br| O-RAN FHI Lib Introduction -> setup configuration -> A.2 prerequisites
- - SW FEC was enabled by default, to enable HW FEC with specific accelerator card, you need get the associated driver and build steps from the accelerator card vendors.
+ - SW FEC was enabled by default, to enable HW FEC with specific accelerator card, you need to get the associated driver and build steps from the accelerator card vendors.
- - enable IGB UIO for NIC card::
-
- CONFIG_RTE_EAL_IGB_UIO=y
- CONFIG_RTE_KNI_KMOD=y
- build DPDK
build DPDK::
#./usertools/dpdk-setup.sh
- select [16] x86_64-native-linuxapp-icc
- select [19] Insert VFIO module
- exit [35] Exit Script
+ select [39] x86_64-native-linuxapp-icc
+ exit [62] Exit Script
- set DPDK path
DPDK path is needed during build and run lib/app::
- #export RTE_SDK="your DPDK path"
+ #export RTE_SDK=Intallation_DIR/dpdk-19.11
+ #export DESTDIR=Installation_DIR/dpdk-19.11
Install google test
#tar -xvf googletest-release-1.7.0.tar.gz
#mv googletest-release-1.7.0 gtest-1.7.0
#export GTEST_DIR=YOUR_DIR/gtest-1.7.0
+ #export GTEST_ROOT= $GTEST_DIR
#cd ${GTEST_DIR}
#g++ -isystem ${GTEST_DIR}/include -I${GTEST_DIR} -pthread -c ${GTEST_DIR}/src/gtest-all.cc
#ar -rv libgtest.a gtest-all.o
Configure FEC card
--------------------
-For the Bronze Release only as SW FEC is available so this step is not needed, for later releases the required information will be added to the document.
+For the Bronze Release only a SW FEC is available so this step is not needed, for later releases the required information will be added to the document.
+
+Customize a setup environment shell script
+------------------------------------------
+Using as an example the provided in the folder phy\\setupenv.sh as the starting point
+customize this script to provide the paths to the tools and libraries that
+are used building and running the code.
+You can add for example the following entries based on your particular installation and the
+following illustration is just an example::
+
+- export DIR_ROOT=/home/
+- #set the L1 binary root DIR
+- export DIR_ROOT_L1_BIN=$DIR_ROOT/FlexRAN
+- #set the phy root DIR
+- export DIR_ROOT_PHY=$DIR_ROOT/phy
+- #set the DPDK root DIR
+- #export DIR_ROOT_DPDK=/home/dpdk-19.11
+- #set the GTEST root DIR
+- #export DIR_ROOT_GTEST=/home/gtest/gtest-1.7.0
+- export DIR_WIRELESS_TEST_5G=$DIR_ROOT_L1_BIN/testcase
+- export DIR_WIRELESS_SDK=$DIR_ROOT_L1_BIN/sdk/build-avx512-icc
+- export DIR_WIRELESS_TABLE_5G=$DIR_ROOT_L1_BIN/l1/bin/nr5g/gnb/l1/table
+- #source /opt/intel/system_studio_2019/bin/iccvars.sh intel64 -platform linux
+- export XRAN_DIR=$DIR_ROOT_PHY/fhi_lib
+- export XRAN_LIB_SO=true
+- export RTE_TARGET=x86_64-native-linuxapp-icc
+- #export RTE_SDK=$DIR_ROOT_DPDK
+- #export DESTDIR=""
+- #export GTEST_ROOT=$DIR_ROOT_GTEST
+- export ORAN_5G_FAPI=true
+- export DIR_WIRELESS_WLS=$DIR_ROOT_PHY/wls_lib
+- export DEBUG_MODE=true
+- export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS:$XRAN_DIR/lib/build
+- export DIR_WIRELESS=$DIR_ROOT_L1_BIN/l1
+- export DIR_WIRELESS_ORAN_5G_FAPI=$DIR_ROOT_PHY/fapi_5g
+- export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_ROOT_L1_BIN/libs/cpa/bin
+
+Then issue::
+
+- source ./setupenv.sh
+
+This sets up the correct environment to build the code
+
+Then build the wls_lib, FHI_Lib, 5G FAPI TM prior to running the code with the steps described in the Run L1 section
+
+
and requires that DPDK
be installed in the system since in the makefile it uses the RTE_SDK environment variable when
building the library. |br|
-The current release was tested using DPDK version 18.08 but it doesn't preclude the
+The current release was tested using DPDK version 19.11 but it doesn't preclude the
use of newer releases. |br|
Also the 5G FAPI TM currently uses the Intel Compiler that is defined as part of the ODULOW documentation.
The ORAN FAPI 5G Translator Module (TM) is a standalone application that communicates with the ODU-High using the 5G FAPI protocol defined
by the Small Cell Forum and communicates with the ODU Low using the Intel L2-L1 API using the Wireless Subsystem Interface
-Library (WLS) to handle the shared memory and buffer management required by the |br|
-Interfaces. In addition the ORAN 5G FAPI TM requires the
+Library (WLS) to handle the shared memory and buffer management required by the Interfaces. In addition the ORAN 5G FAPI TM requires the
Data Plane Design Kit (DPDK) which is integrated with the WLS Library.
Table 1. Terminology
ORAN 5G FAPI TM Release Notes
=============================
-Version oran_release_bronze_v1.0, May 2020
-------------------------------------------
+Version FAPI TM oran_release_bronze_v1.1, Aug 2020
+------------------------------------------------------
+
+* Increased test coverage. All supported DL, UL and FD standard MIMO cases are validated
+* Support for carrier aggregation
+* Support for API ordering
+* Support for handling Intel proprietary PHY shutdown message in radio mode
+* FAPI TM latency measurement
+* Bug fixes
+* Feedback provided to SCF on parameter gaps identified in SCF 5G FAPI specification dated March 2020
+* This version of the 5G FAPI TM incorporates the changes that were provided to the SCF.
+
+
+Version FAPI TM oran_release_bronze_v1.0, May 2020
+------------------------------------------------------
* First release of the 5G FAPI TM to ORAN in support of the Bronze Release
* This version supports 5G only
* PARAM.config and PARAM.resp are not supported
.. See the License for the specific language governing permissions and
.. limitations under the License.
-.. ODULOW documentation master
+.. ODULOW documentation main
-.. _odulow documentation master:
+.. _odulow documentation main:
O-RAN O-DU Low
==============
-**User Guide, May 2020**
+**User Guide, August 2020**
.. toctree::
:maxdepth: 2
overview1.rst
Assumptions_Dependencies.rst
build_prerequisite.rst
+ release-notes.rst
.. _odulow_phy_fhi_library:
-.. fhi library documentation master
+.. fhi library documentation main
FHI Library
===========
overview.rst
Introduction_fh.rst
- release-notes.rst
+ release-notes-fh.rst
* :ref:`search`
=====================================
The O-RAN FHI Lib is built on top of DPDK to perform U-plane and C-plane functions according to the
-ORAN Fronthaul |br|
-Interface specification between O-DU and O-RU.
-S-Plane support requires PTP for Linux version 2.0 or later |br|
-The management plane is outside of the scope of this library implementation.
+ORAN Fronthaul Interface specification between O-DU and O-RU.
+The S-Plane support requires PTP for Linux version 2.0 or later.
+The Management plane is outside of the scope of this library implementation.
Project Resources
:depth: 3
:local:
-The O-DU low project focus on the baseband PHY Reference Design, which uses Xeon® series Processor with Intel |br|
-Architecture. This 5GNR Reference PHY consists of a L1 binary \
-and three kinds of interfaces which are validated on a |br|
-Intel® Xeon® SkyLake / CascadeLake platforms and demonstrates the capabilities of the software running different \
+The O-DU low project focus on the baseband PHY Reference Design, which uses Xeon® series Processor with Intel Architecture. This 5GNR Reference PHY consists of a L1 binary \
+and three kinds of interfaces which are validated on a Intel® Xeon® SkyLake / CascadeLake platforms and demonstrates the capabilities of the software running different \
5GNR L1 features. It implements the relevant functions described in [3GPP TS 38.211, 212, 213, 214 and 215].
The L1 has three \
--- /dev/null
+.. Copyright (c) 2019 Intel
+..
+.. Licensed under the Apache License, Version 2.0 (the "License");
+.. you may not use this file except in compliance with the License.
+.. You may obtain a copy of the License at
+..
+.. http://www.apache.org/licenses/LICENSE-2.0
+..
+.. Unless required by applicable law or agreed to in writing, software
+.. distributed under the License is distributed on an "AS IS" BASIS,
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+.. See the License for the specific language governing permissions and
+.. limitations under the License.
+
+.. |br| raw:: html
+
+ <br />
+
+Front Haul Interface Library Release Notes
+==========================================
+
+Version FH oran_release_bronze_v1.1, Aug 2020
+------------------------------------------------
+
+* Add profile and support for LTE.
+* Add support for the 32x32 massive mimo scenario. Up to 2 cells demo showed with testmac
+* mmWave RRH integration. Address regression from the previous release.
+* Integrate block floating-point compression/decompression.
+* Enhance C-plane for the Category B scenario.
+
+
+Version FH oran_release_bronze_v1.0, May 2020
+------------------------------------------------
+
+* Integration and optimization of block floating point compression and decompression.
+* Category B support
+* Add support for alpha and beta value when calculating SFN based on GPS time.
+* Support End to End integration with commercial UE with xRAN/ORAN RRU for both mmWave and
+ sub-6 scenarios
+
+Version FH oran_release_amber_v1.0, 1 Nov 2019
+-------------------------------------------------
+* Second version released to ORAN in support of Release A
+* Incorporates support for 5G NR sub 6 and mmWave
+* Support for Application fragementation under Transport features was added
+* This release has been designed and implemented to support the following numerologies defined in the 3GPP |br|
+ specification
+ * Numerology 0 with bandwidth 5/10/20 MHz with up to 12 cells
+ * Numerology 1 with bandwidth 100MHz with up to 1 cell
+ * Numerology 3 with bandwidth 100MHz with up to 1 cell
+* The feature set of xRAN protocol should be aligned with Radio Unit (O-RU) implementation
+* Inter-operability testing (IOT) is required to confirm correctness of functionality on both sides
+* The following mandatory features of the ORAN FH interface are not yet supported in this release
+* RU Category Support of CAT-B RU (i.e. precoding in RU)
+* Beamforming Beam Index Based and Real Time BF weights
+* Transport Features QoS over FrontHaul
+
+
+Version FH seedcode_v1.0, 25 Jul 2019
+---------------------------------------
+* This first version supports only mmWave per 5G NR and it is not yet
+* optimized
+* It is a first draft prior to the November 2019 Release A
+* The following mandatory features of the ORAN FH interface are not yet
+* supported in this initial release
+* RU Category Support of CAT-B RU (i.e. precoding in RU)
+* Beamforming Beam Index Based and Real Time BF weights
+* Transport Features QoS over FrontHaul and Application Fragmentation
+
+
+
+
<br />
-Front Haul Interface Library Release Notes
+O-DU Low Project Release Notes
==========================================
-Version ORAN-seedcode_v1.3, May 2020
---------------------------------------
+O-DU Low Bronze Release V 1.1, Aug 2020
+-----------------------------------------
+* Enhanced feature set for O-RAN FrontHaul compliant Radio<-> L1 interface, FAPI compliant L1<->L2 interfaces, and a shared memory and buffer management library for efficient L1<->L2 communication
+* Enhanced the code coverage test through more test cases.
+* Bug fixes according to unit test and integration test with third party.
+* Please refer to version FH oran_release_bronze_v1.1, FAPI TM oran_release_bronze_v1.1 and WLS oran_release_bronze_v1.1 release notes for additional details.
-* Third version released to ORAN in support of Release B
-* Add scripts to run refPHY in Docker* containers, Kubernetes* clusters, Multus*, and Data Plane
- Development Kit-Single-Root Input/Output Visualization (DPDK-SRIOV) plugin.
-* Integration and optimization of block floating point compression and decompression.
-* Category B support
-* Add support for alpha and beta value when calculating SFN based on GPS time.
-* Support End to End integration with commercial UE with xRAN/ORAN RRU for both mmWave and
- sub-6 scenarios
+O-DU Low Bronze Release V 1.0, May 2020
+-----------------------------------------
+O-DU Low Bronze release include:
+* ORAN WG8/WG4 Software Specification compliant DU Low implementation including O-RAN FrontHaul compliant Radio<-> L1 interface, FAPI compliant L1<->L2 interfaces, and a shared memory and buffer management library for efficient L1<->L2 communication
+* Ability to link in a high-performance L1 stack application with advanced 5GNR features including 3GPP TS 38.211, 212, 213, 214 and 215, running on Intel Xeon processor based O-DU hardware, and packaged with a comprehensive functional and performance evaluation framework
+* Please refer version FH oran_release_bronze_v1.0, FAPI TM oran_release_bronze_v1.0 and WLS oran_release_bronze_v1.0 release notes for Detail features
-Version ORAN-seedcode_v1.2, 1 Nov 2019
---------------------------------------
-* Second version released to ORAN in support of Release A
-* Incorporates support for 5G NR sub 6 and mmWave
-* Support for Application fragementation under Transport features was added
-* This release has been designed and implemented to support the following numerologies defined in the 3GPP |br|
- specification
-* Numerology 0 with bandwidth 5/10/20 MHz with up to 12 cells
-* Numerology 1 with bandwidth 100MHz with up to 1 cell
-* Numerology 3 with bandwidth 100MHz with up to 1 cell
-* The feature set of xRAN protocol should be aligned with Radio Unit (O-RU) implementation
-* Inter-operability testing (IOT) is required to confirm correctness of functionality on both sides
-* The following mandatory features of the ORAN FH interface are not yet supported in this release
-* RU Category Support of CAT-B RU (i.e. precoding in RU)
-* Beamforming Beam Index Based and Real Time BF weights
-* Transport Features QoS over FrontHaul
+O-DU Low Amber Release V 1.0, 1 Nov 2019
+------------------------------------------
+O-DU Low Amber release include:
+* ORAN WG4 Software Specification compliant O-FH lib implementation
+* Please refer version FH oran_release_amber_v1.0 release notes for Detail features
-Version ORAN-seedcode_v1.1, 25 Jul 2019
----------------------------------------
-* This first version supports only mmWave per 5G NR and it is not yet
-* optimized
-* It is a first draft prior to the November 2019 Release A
-* The following mandatory features of the ORAN FH interface are not yet
-* supported in this initial release
-* RU Category Support of CAT-B RU (i.e. precoding in RU)
-* Beamforming Beam Index Based and Real Time BF weights
-* Transport Features QoS over FrontHaul and Application Fragmentation
Download L1 and testmac through https://github.com/intel/FlexRAN
+CheckList Before Running the code
+---------------------------------
+Before running the L1 and Testmac code make sure that you have built the wls_lib, FHI_lib and 5G_FAPI_TM using the instructions provided earlier in this
+document and in the order specified in this documentation.
Run L1 with testmac
--------------------
-Three console windows are needed, one for L1 app, one for FAPI TM, one for testmac. They need to run in the following order L1-> FAPI TM-> testmac. |br|
-In each console window, the environment needs to be set using a shell script of example::
+Three console windows are needed, one for L1 app, one for FAPI TM, one for testmac. They need to run in the following order L1-> FAPI TM-> testmac.
+In each console window, the environment needs to be set using a shell script under folder phy/ example::
- #source ./setupenv.sh
+ #source ./setupenv.sh
* Run L1 under folder FlexRAN/l1/bin/nr5g/gnb/l1 in timer mode using::
#l1.sh -e
-**Note** that the markups dpdkBasebandFecMode and dpdkBasebandDevice needs to be adjusted in the relevant phycfg.xml under folder |br|
+**Note** that the markups dpdkBasebandFecMode and dpdkBasebandDevice needs to be adjusted in the relevant phycfg.xml under folder
FlexRAN/l1/bin/nr5g/gnb/l1 before starting L1. |br|
dpdkBasebandFecMode = 0 for LDPC Encoder/Decoder in software. |br|
dpdkBasebandFecMode = 1 for LDPC Encoder/Decoder in FPGA. (Not supported in the Bronze Release for the Open Source Community) |br|
testnum is always a 4 digit number. First digit represents the number of carriers to run.
For example, to run Test Case 5 for Uplink Rx mu=3, 100Mhz for 1 carrier, the command would be:
run 1 3 100 1005
-All the pre-defined test cases for the Bronze Release are defined in the Test Cases section in https://github.com/intel/FlexRAN and also in the Test |br|
+All the pre-defined test cases for the Bronze Release are defined in the Test Cases section in https://github.com/intel/FlexRAN and also in the Test
Cases section of this document.
-If user wants to run more slots (than specified in test config file) or change the mode or change the TTI interval of the test, then the command phystart can be used as follows:
+If the user wants to run more slots (than specified in test config file) or change the mode or change the TTI interval of the test, then the command phystart can be used as follows:
- **phystart mode interval num_tti**
-- **mode** is 0 (Radio) or 1 (Timer)
+- **mode** is 4 (ORAN compatible Radio) or 1 (Timer)
- **interval** is the TTI duration scaled as per Numerology (only used in timer mode).
The wls library uses DPDK as the basis for the shared memory operations and requires that DPDK
be installed in the system since in the makefile it uses the RTE_SDK environment variable when
building the library. |br|
-The current release was tested using DPDK version 18.08 but it doesn't preclude the
+The current release was tested using DPDK version 19.11 but it doesn't preclude the
use of newer releases. |br|
Also the library uses the Intel Compiler that is defined as part of the ODULOW documentation.
WLS Library Release Notes
=========================
-Version oran_release_bronze_v1.0, May 2020
-------------------------------------------
+Version WLS oran_release_bronze_v1.1, Aug 2020
+--------------------------------------------------
+* Second release of this library aligned with FlexRAN 20.04
+* No changes to external interfaces,
+
+Version WLS oran_release_bronze_v1.0, May 2020
+--------------------------------------------------
* First release of the wls library to ORAN in support of the Bronze Release
* This version supports both single and dual instances using a single Open function
Wls Lib Overview
================
-The Wls_lib is a Wireless Service library that supports shared memory and buffer management used by applications |br|
-implementing a gNb or eNb. |br|
-This library uses DPDK, libhugetlbfs and pthreads to provide memcpy less data exchange between an L2 application, |br|
+The Wls_lib is a Wireless Service library that supports shared memory and buffer management used by applications
+implementing a gNb or eNb.
+This library uses DPDK, libhugetlbfs and pthreads to provide memcpy less data exchange between an L2 application,
API Translator Module and a L1 application by sharing the same memory zone from the DPDK perspective.
Project Resources
* **WLS_NumBlocks()** returns number of current available blocks provided by master for a new transfer of data from the slave.
-The **_1()** functions are only needed when using the WLS_Open_Dual().
\ No newline at end of file
+The **_1()** functions are only needed when using the WLS_Open_Dual().
+
+The source code and documentation will be updated in the next release to use inclusive engineering terms.
\ No newline at end of file
functionality is encapsulated. The complete list of all \*.c and \*.h
files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is:
-├──fhi_lib
+├── app
-│ ├── lib
+│ ├── dpdk.sh
-│ │ ├── api
+│ ├── gen_test.m
-│ │ │ ├── xran_compression.h
+│ ├── Makefile
-│ │ │ ├── xran_compression.hpp
+│ ├── src
-│ │ │ ├── xran_cp_api.h
+│ │ ├── common.c
-│ │ │ ├── xran_fh_o_du.h
+│ │ ├── common.h
-│ │ │ ├── xran_mlog_lnx.h
+│ │ ├── config.c
-│ │ │ ├── xran_pkt_cp.h
+│ │ ├── config.h
-│ │ │ ├── xran_pkt.h
+│ │ ├── debug.h
-│ │ │ ├── xran_pkt_up.h
+│ │ ├── sample-app.c
-│ │ │ ├── xran_sync_api.h
+│ │ └── xran_mlog_task_id.h
-│ │ │ ├── xran_timer.h
+│ └── usecase
-│ │ │ ├── xran_transport.h
+│ ├── cat_b
-│ │ │ └── xran_up_api.h
+│ ├── lte_a
-│ │ ├── ethernet
+│ ├── lte_b
-│ │ │ ├── ethdi.c
+│ ├── mu0_10mhz
-│ │ │ ├── ethdi.h
+│ ├── mu0_20mhz
-│ │ │ ├── ethernet.c
+│ ├── mu0_5mhz
-│ │ │ └── ethernet.h
+│ ├── mu1_100mhz
-│ │ ├── Makefile
+│ └── mu3_100mhz
-â\94\82Â Â â\94\82Â Â â\94\94â\94\80â\94\80 src
+â\94\9câ\94\80â\94\80 banner.txt
-â\94\82Â Â â\94\82Â Â â\94\82Â Â â\94\9câ\94\80â\94\80 xran_app_frag.c
+â\94\9câ\94\80â\94\80 build.sh
-â\94\82Â Â â\94\82Â Â â\94\82Â Â â\94\9câ\94\80â\94\80 xran_app_frag.h
+â\94\9câ\94\80â\94\80 lib
-│ │ │ ├── xran_common.c
+│ ├── api
-│ │ │ ├── xran_common.h
+│ │ ├── xran_compression.h
-│ │ │ ├── xran_compression.cpp
+│ │ ├── xran_compression.hpp
-│ │ │ ├── xran_cp_api.c
+│ │ ├── xran_cp_api.h
-│ │ │ ├── xran_frame_struct.c
+│ │ ├── xran_fh_o_du.h
-│ │ │ ├── xran_frame_struct.h
+│ │ ├── xran_mlog_lnx.h
-│ │ │ ├── xran_lib_mlog_tasks_id.h
+│ │ ├── xran_pkt_cp.h
-│ │ │ ├── xran_main.c
+│ │ ├── xran_pkt.h
-│ │ │ ├── xran_printf.h
+│ │ ├── xran_pkt_up.h
-│ │ │ ├── xran_sync_api.c
+│ │ ├── xran_sync_api.h
-│ │ │ ├── xran_timer.c
+│ │ ├── xran_timer.h
-│ │ │ ├── xran_transport.c
+│ │ ├── xran_transport.h
-│ │ │ ├── xran_ul_tables.c
+│ │ └── xran_up_api.h
-│ │ │ └── xran_up_api.c
+│ ├── ethernet
-│ ├── readme.txt
+│ │ ├── ethdi.c
-│ ├── Licenses.txt
+│ │ ├── ethdi.h
-│ ├── build.sh
+│ │ ├── ethernet.c
-│ └── test
+│ │ └── ethernet.h
-│ │ ├── common
+│ ├── Makefile
-│ │ │ ├── common.cpp
+│ └── src
-│ │ │ ├── common.hpp
+│ ├── xran_app_frag.c
-│ │ │ ├── common_typedef_xran.h
+│ ├── xran_app_frag.h
-│ │ ├── xranlib_unit_test_main.cc
+│ ├── xran_bfp_cplane16.cpp
-│ │ └── xran_lib_wrap.hpp
+│ ├── xran_bfp_cplane32.cpp
-│ │ ├── master.py
+│ ├── xran_bfp_cplane64.cpp
-│ │ ├── readme.txt
+│ ├── xran_bfp_cplane8.cpp
-│ │ └── test_xran
+│ ├── xran_bfp_ref.cpp
-│ │ │ ├── chain_tests.cc
+│ ├── xran_bfp_utils.hpp
-│ │ │ ├── compander_functional.cc
+│ ├── xran_common.c
-│ │ │ ├── conf.json
+│ ├── xran_common.h
-│ │ │ ├── c_plane_tests.cc
+│ ├── xran_compression.cpp
-│ │ │ ├── init_sys_functional.cc
+│ ├── xran_cp_api.c
-│ │ │ ├── Makefile
+│ ├── xran_frame_struct.c
-│ │ │ ├── prach_functional.cc
+│ ├── xran_frame_struct.h
-│ │ │ ├── prach_performance.cc
+│ ├── xran_lib_mlog_tasks_id.h
-│ │ │ ├── unittests.cc
+│ ├── xran_main.c
+
+│ ├── xran_printf.h
+
+│ ├── xran_sync_api.c
+
+│ ├── xran_timer.c
+
+│ ├── xran_transport.c
+
+│ ├── xran_ul_tables.c
+
+│ └── xran_up_api.c
+
+├── Licenses.txt
+
+├── readme.md
+
+└── test
+
+ ├── common
+
+ │ ├── common.cpp
+
+ │ ├── common.hpp
+
+ │ ├── common_typedef_xran.h
+
+ │ ├── json.hpp
+
+ │ ├── MIT_License.txt
+
+ │ ├── xranlib_unit_test_main.cc
+
+ │ └── xran_lib_wrap.hpp
+
+ ├── master.py
+
+ ├── readme.txt
+
+ └── test_xran
+
+ ├── chain_tests.cc
+
+ ├── compander_functional.cc
+
+ ├── conf.json
+
+ ├── c_plane_tests.cc
+
+ ├── init_sys_functional.cc
+
+ ├── Makefile
+
+ ├── prach_functional.cc
+
+ ├── prach_performance.cc
+
+ ├── unittests.cc
+
+ └── u_plane_functional.cc
-│ │ │ ├── u_plane_functional.cc
General Introduction
--------------------
This library depends on DPDK primitives to perform Ethernet networking
in userspace, including initialization and control of Ethernet ports.
Ethernet ports are expected to be SRIOV virtual functions (VF) but also
-can be physical functions (PF) as well
+can be physical functions (PF) as well.
This library is expected to be included in the project via
xran_fh_o_du.h, statically compiled and linked with the L1 application
as well as DPDK libraries. The xRAN packet processing-specific
functionality is encapsulated into this library and not exposed to the
-rest of the 5G NR pipeline. An abstract interface similar to the mmWave
-front haul interface is defined in xran_fh_o_du.h to be available for
-usage.
+rest of the 5G NR pipeline.
This way, xRAN specific changes are decoupled from the 5G NR L1
pipeline. As a result, the design and implementation of the 5G L1
required. The current version of the library does not support multiple
sessions without a restart of the full L1 application.
-
+Configuration
~~~~~~~~~~~~~
-The xRAN library configuration is provided in the set of structures,
-such as struct xran_fh_init and struct xran_fh_config. The sample
-application gives an example of a test configuration used for mmWave.
+The xRAN library configuration is provided in the set of structures, such as struct xran_fh_init and struct xran_fh_config.
+The sample application gives an example of a test configuration used for LTE and 5GNR mmWave and Sub 6. Sample application
+folder /app/usecase/ contains set of examples for different Radio Access technology (LTE|5G NR), different category (A|B)
+and list of numerologies (0,1,3) and list of bandwidths (5,10,20,100Mhz).
Some configuration options are not used in the Bronze Release and are reserved
for future use.
- Init DPDK timers and DPDK rings for internal packet processing
-- Instantiate ORAH FH thread doing
+- Instantiate ORAN FH thread doing
-- Timing processing (xran_timing_source_thread())
+ - Timing processing (xran_timing_source_thread())
-- ETH PMD (process_dpdk_io())
+ - ETH PMD (process_dpdk_io())
-- IO XRAN-PHY exchange (ring_processing_func())
+ - IO XRAN-PHY exchange (ring_processing_func())
**xran_open()** performs additional configuration as per run scenario:
~~~~~~~~~~~~~
Exchange of IQ samples, as well as C-plane specific information, is
-performed using a set of buffers allocated by xRAN |br|
-library from DPDK
+performed using a set of buffers allocated by xRAN library from DPDK
memory and shared with the l1 application. Buffers are allocated as a
standard mbuf structure and DPDK pools are used to manage the allocation
and free resources. Shared buffers are allocated at the init stage and
xran_prb_map and similar to the data plane. The same mbuf memory is used
to allocate memory map of PRBs for each TTI.
-/\* Beamforming weights for single stream for each PRBs given number of
-Antenna elements \*/
-
+/\* Beamforming waights for single stream for each PRBs given number of Antenna elements \*/
struct xran_cp_bf_weight{
-int16_t nAntElmTRx; /* num TRX for this allocation \*/
-
-int8_t\* p_ext_section; /* pointer to form extType \*/
-
-int16_t ext_section_sz; /* extType section size \*/
-
-};
-
-struct xran_cp_bf_attribute{
-
-int16_t weight[4];
-
-};
-
-struct xran_cp_bf_precoding{
-
-int16_t weight[4];
-
-};
-
-/\* section descriptor for given number of PRBs used on U-plane packet
-creation \*/
+ int16_t nAntElmTRx; /\*< num TRX for this allocation \*/
+ int8_t* p_ext_start; /\*< pointer to start of buffer for full C-plane packet \*/
+ int8_t* p_ext_section; /\*< pointer to form extType \*/
+ int16_t ext_section_sz; /\*< extType section size \*/
+/\* section descriptor for given number of PRBs used on U-plane packet creation \*/
struct xran_section_desc {
-uint16_t section_id; /* section id used for this element \*/
-
-int16_t iq_buffer_offset; /* Offset in bytes for the content of IQs
-with in main symb buffer \*/
+ uint16_t section_id; /\*< section id used for this element \*/
-int16_t iq_buffer_len; /* Length in bytes for the content of IQs with
-in main symb buffer \*/
-
-uint8_t \*pData; /* optional pointer to data buffer \*/
-
-void \*pCtrl; /* optional poitner to mbuf \*/
+ int16_t iq_buffer_offset; /\*< Offset in bytes for the content of IQs with in main symb buffer \*/
+ int16_t iq_buffer_len; /\*< Length in bytes for the content of IQs with in main symb buffer \*/
+ uint8_t \*pData; /\*< optional pointer to data buffer \*/
+ void \*pCtrl; /\*< optional poitner to mbuf \*/
+
};
-/* PRB element structure \*/
-
struct xran_prb_elm {
-
-int16_t nRBStart; /* start RB of RB allocation \*/
-
-int16_t nRBSize; /* number of RBs used \*/
-
-int16_t nStartSymb; /* start symbol ID \*/
-
-int16_t numSymb; /* number of symbols \*/
-
-int16_t nBeamIndex; /* beam index for given PRB \*/
-
-int16_t bf_weight_update; /* need to update beam weights or not \*/
-
-int16_t compMethod; /* compression index for given PRB \*/
-
-int16_t iqWidth; /* compression bit width for given PRB \*/
-
-int16_t BeamFormingType; /* index based, weights based or
-attribute-based beam forming*/
-
-struct xran_section_desc \* p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT];
-/* section desctiptors to U-plane data given RBs \*/
-
-struct xran_cp_bf_weight bf_weight; /* beam forming information
-relevant for given RBs \*/
-
-union {
-
-struct xran_cp_bf_attribute bf_attribute;
-
-struct xran_cp_bf_precoding bf_precoding;
-
-};
-
-};
-
-/* PRB map structure \*/
+ int16_t nRBStart; /\*< start RB of RB allocation \*/
+ int16_t nRBSize; /\*< number of RBs used \*/
+ int16_t nStartSymb; /\*< start symbol ID \*/
+ int16_t numSymb; /\\*< number of symbols \*/
+ int16_t nBeamIndex; /\*< beam index for given PRB \*/
+ int16_t bf_weight_update; /\* need to update beam weights or not \*/
+ int16_t compMethod; /\*< compression index for given PRB \*/
+ int16_t iqWidth; /\*< compression bit width for given PRB \*/
+ int16_t BeamFormingType; /\*< index based, weights based or attribute based beam forming\*/
+
+ struct xran_section_desc * p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /\*< section desctiptors to U-plane data given RBs \*/
+ struct xran_cp_bf_weight bf_weight; /\*< beam forming information relevant for given RBs \*/
+
+ union {
+ struct xran_cp_bf_attribute bf_attribute;
+ struct xran_cp_bf_precoding bf_precoding;
+
+ };
+
+/\* PRB map structure \*/
struct xran_prb_map {
-
-uint8_t dir; /* DL or UL direction \*/
-
-uint8_t xran_port; /* xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/
-
-uint16_t band_id; /* xran band id \*/
-
-uint16_t cc_id; /* componnent carrier id [0 - (XRAN_MAX_SECTOR_NR-1)]
-\*/
-
-uint16_t ru_port_id; /* RU device antenna portid [0 -
-(XRAN_MAX_ANTENNA_NR-1)*/
-
-uint16_t tti_id; /* xRAN slot id [0 - (max tti-1)] \*/
-
-uint8_t start_sym_id; /* start symbol Id [0-13] \*/
-
-uint32_t nPrbElm; /* total number of PRB elements for given map [0-
-(XRAN_MAX_PRBS-1)] \*/
-
-struct xran_prb_elm prbMap[XRAN_MAX_PRBS];
-
+ uint8_t dir; /\*< DL or UL direction \*/
+ uint8_t xran_port; /\*< xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/
+ uint16_t band_id; /\*< xran band id \*/
+ uint16_t cc_id; /\*< componnent carrier id [0 - (XRAN_MAX_SECTOR_NR-1)] \*/
+ uint16_t ru_port_id; /\*< RU device antenna port id [0 - (XRAN_MAX_ANTENNA_NR-1) \*/
+ uint16_t tti_id; /\*< xRAN slot id [0 - (max tti-1)] \*/
+ uint8_t start_sym_id; /\*< start symbol Id [0-13] \*/
+ uint32_t nPrbElm; /\*< total number of PRB elements for given map [0- (XRAN_MAX_PRBS-1)] \*/
+ struct xran_prb_elm prbMap[XRAN_MAX_PRBS];
+
};
+
For the Bronze release C-plane sections are expected to be provided by L1
-pipeline. If 100% of RBs allocated at all times single element of RB map
+pipeline. If 100% of RBs always allocated single element of RB map
is expected to be allocated across all symbols. Dynamic RB allocation is
performed base on C-plane configuration.
- Compression and beamforming are not used
+Common Header Fields::
+
+- dataDirection = XRAN_DIR_DL
+- payloadVersion = XRAN_PAYLOAD_VER
+- filterIndex = XRAN_FILTERINDEX_STANDARD
+- frameId = [0..99]
+- subframeId = [0..9]
+- slotID = [0..9]
+- startSymbolid = 0
+- numberOfsections = 1
+- sectionType = XRAN_CP_SECTIONTYPE_1
+- udCompHdr.idIqWidth = 0
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
+- reserved = 0
+
+Section Fields::
+
+- sectionId = [0..4095]
+- rb = XRAN_RBIND_EVERY
+- symInc = XRAN_SYMBOLNUMBER_NOTINC
+- startPrbc = 0
+- numPrbc = 66
+- reMask = 0xfff
+- numSymbol = 14
+- ef = 0
+- beamId = 0
+
+
**C-Plane Message – uplink symbol data for uplink slot**
- Single CP message with the single section of section type 1
- Compression and beamforming are not used
+Common Header Fields::
+
+- dataDirection = XRAN_DIR_UL
+- payloadVersion = XRAN_PAYLOAD_VER
+- filterIndex = XRAN_FILTERINDEX_STANDARD
+- frameId = [0..99]
+- subframeId = [0..9]
+- slotID = [0..9]
+- startSymbolid = 3
+- numberOfsections = 1
+- sectionType = XRAN_CP_SECTIONTYPE_1
+- udCompHdr.idIqWidth = 0
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
+- reserved = 0
+
+Section Fields::
+
+- sectionId = [0..4095]
+- rb = XRAN_RBIND_EVERY
+- symInc = XRAN_SYMBOLNUMBER_NOTINC
+- startPrbc = 0
+- numPrbc = 66
+- reMask = 0xfff
+- numSymbol = 11
+- ef = 0
+- beamId = 0
+
+
**C-Plane Message – PRACH**
- Single CP message with the single section of section type 3 including
- Compression and beamforming are not used
+Common Header Fields::
+
+- dataDirection = XRAN_DIR_UL
+- payloadVersion = XRAN_PAYLOAD_VER
+- filterIndex = XRAN_FILTERINDEPRACH_ABC
+- frameId = [0,99]
+- subframeId = [0,3]
+- slotID = 3 or 7
+- startSymbolid = 7
+- numberOfSections = 1
+- sectionType = XRAN_CP_SECTIONTYPE_3
+- timeOffset = 2026
+- frameStructure.FFTSize = XRAN_FFTSIZE_1024
+- frameStructure.u = XRAN_SCS_120KHZ
+- cpLength = 0
+- udCompHdr.idIqWidth = 0
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
+
+Section Fields::
+
+- sectionId = [0..4095]
+- rb = XRAN_RBIND_EVERY
+- symInc = XRAN_SYMBOLNUMBER_NOTINC
+- startPrbc = 0
+- numPrbc = 12
+- reMask = 0xfff
+- numSymbol = 6
+- ef = 0
+- beamId = 0
+- frequencyOffset = -792
+- reserved
+
+
Functions to Store/Retrieve Section Information
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
There are several functions to store/retrieve section information of
C-Plane messages. Since U-plane messages must be generated by the
information in the sections of a C-Plane message, it is required to
-store and retrieve section |br|
-information.
+store and retrieve section information.
**APIs and Data Structure**
'''''''''''''''''''''''''''
maximum number of context is defined by two and it can be adjusted if
needed.
-8. Since the context index is not managed by the library and APIs are
+Note. Since the context index is not managed by the library and APIs are
expecting it from the caller as a parameter, the caller shall
consider a proper method to manage it to avoid corruption. The
current reference implementation uses a slot and subframe index to
builds eCPRI header filling structure fields by taking the IQ sample
size and populating a particular packet length and sequence number.
-Currently, the supported IQ bit width is 16.
+With compression, supported IQ bit widths are 8,9,10,12,14.
Implementation of a U-plane set of functions is defined in xran_up_api.c
and is used to prepare U-plane packet content according to the given
the system timer which in turn is synchronized to PTP (GPS)
Only single-shot timers are used to schedule processing based on
-particular events such as symbol time. The packet |br|
+events such as symbol time. The packet |br|
processing function
calls rte_timer_manage() in the loop, and the resulting execution of
timer function happens right |br|
thread_priority = 89
[WLS_CFG]
-device_name = /dev/wls
+device_name = /dev/wls0
shmem_size = 2126512128
; info
; error
; trace
-; hexdump
[LOGGER]
level = info
+[DPDK]
+; IOVA Mode
+; 0 - PA
+; 1 - VA
+dpdk_iova_mode = 0
+
; URRLC Not Supported
; [URLLC_WORKER]
; core_id = 12
DEFS := $(DEFS) DEBUG_MODE
endif
+ifeq ($(STATISTIC_MODE),true)
+DEFS := $(DEFS) STATISTIC_MODE
+endif
+
DEFS := $(addprefix -D,$(DEFS))
CFLAGS := -g -Wall -Wextra -Wunused -wd9 -Wno-deprecated-declarations -Wimplicit-function-declaration -fasm-blocks -fstack-protector-strong -z,now, -z,relro -z noexecstack -Wformat -Wformat-security -Werror=format-security -fno-strict-overflow -fwrapv $(DEFS) $(INC)
CFLAGS := $(CFLAGS) -Werror
endif
-RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+#RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls
LINUX_ORAN_5G_FAPI_SRC := \
#define FAPI_STOP_REQUEST 0x05
#define FAPI_STOP_INDICATION 0x06
#define FAPI_ERROR_INDICATION 0x07
-// Reserved 0x08 - 0x7f
-#define FAPI_VENDOR_EXT_SHUTDOWN_REQUEST 0x08
-#define FAPI_VENDOR_MESSAGE 0x09
-#ifdef DEBUG_MODE
-#define FAPI_VENDOR_EXT_DL_IQ_SAMPLES 0x0A
-#define FAPI_VENDOR_EXT_UL_IQ_SAMPLES 0x0B
-#endif
-// WLS operation
-#define FAPI_MSG_HEADER_IND 0x2A
-
-// WLS operation with PDSCH Payload
-#define FAPI_MSG_PHY_ZBC_BLOCK_REQ 0x2B
-
-// WLS operation with PUSCH Payload
-#define FAPI_MSG_PHY_ZBC_BLOCK_IND 0x2C
+// Reserved 0x08 - 0x0F and 0x02 - 0x7f
+// 0x01 - 0x1F is used in vendor extension
#define FAPI_DL_TTI_REQUEST 0x80
#define FAPI_UL_TTI_REQUEST 0x81
#define FAPI_SRS_INDICATION 0x88
#define FAPI_RACH_INDICATION 0x89
// Reserved 0x8a -0xff
-#ifdef DEBUG_MODE
-#define FAPI_VENDOR_EXT_START_RESPONSE 0x8A
-#endif
-#define FAPI_VENDOR_EXT_SHUTDOWN_RESPONSE 0x8B
// Tags per 5G FAPI
// Cell Parameters
#define FAPI_MSG_UL_DCI_ERR 0x7
#define FAPI_MSG_TX_ERR 0x8
-// TODO : Work out what the correct maximums should be// Needs Review for 5G
-#if 0
-// Number of UL/DL configurations, I, as defined by 36.212 section 5.3.3.1.4
-// todo : work out what the max is
-#define FAPI_MAX_UL_DL_CONFIGURATIONS 4
-#define FAPI_MAX_NUM_PHYSICAL_ANTENNAS 4
-#define FAPI_MAX_NUM_SCHEDULED_UES 8
-#define FAPI_MAX_NUM_SUBBANDS 8
-#define FAPI_MAX_ANTENNA_PORT_COUNT 2
-#endif
-
// 5G FAPI Definitions
#define FAPI_NUMEROLOGIES 5
#define FAPI_MAX_NUM_UNUSED_ROOT_SEQUENCES 63 // 38.331 page 383
#define FAPI_MAX_NUMBER_OF_GROUPS_PER_TTI 16 // FlexRAN API Table 33
#define FAPI_MAX_NUMBER_UL_PDUS_PER_TTI 328 // (MAX_NUM_PUSCH+MAX_NUM_PUCCH+MAX_NUM_SRS+MAX_NUM_PRACH_DET)
#define FAPI_MAX_NUMBER_DCI_PDUS_PER_TTI 32 // Based on MAX_NUM_PDCCH
-#define FAPI_MAX_NUMBER_OF_TLVS_PER_PDU 2 // one for each codeword
+#define FAPI_MAX_NUMBER_OF_TLVS_PER_PDU 1 // one for each codeword
#define FAPI_MAX_NUMBER_TX_PDUS_PER_TTI 129 // Same as FAPI_MAX_NUMBER_DL_PDUS_PER_TTI
// Based on 38.214 5.1.3.4, the TBS is 1376264 bits and divided by 8 and
// aligned to 64 bytes
#define FAPI_MAX_PDU_LENGTH 172096
+#define FAPI_TX_DATA_PAYLOAD 0x00
+#define FAPI_TX_DATA_PTR_TO_PAYLOAD_32 0x01
+#define FAPI_TX_DATA_OFFSET_TO_PAYLOAD 0x02
+#define FAPI_TX_DATA_PTR_TO_PAYLOAD_64 0x03
#define FAPI_MAX_NUMBER_OF_PDUS_PER_TTI 129 // Same as FAPI_MAX_NUMBER_DL_PDUS_PER_TTI
#define FAPI_MAX_NUMBER_OF_ULSCH_PDUS_PER_SLOT 64 // NUM_PUSCH_CHAN*FAPI_MAX_NUMBER_OF_CODEWORDS_PER_PDU
#define FAPI_MAX_NUM_TLVS_SHUTDOWN 1 // Based on Timer Mode requirement.
#define FAPI_MAX_UCI_BIT_BYTE_LEN 256
-#ifdef DEBUG_MODE
-#define FAPI_MAX_IQ_SAMPLE_FILE_SIZE 576
-#define FAPI_MAX_IQ_SAMPLE_DL_PORTS 8
-#define FAPI_MAX_IQ_SAMPLE_UL_PORTS 2
-#define FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS 4
-#define FAPI_MAX_IQ_SAMPLE_UL_ANTENNA 32
-#define FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE 4096
-#endif
-
-#define FAPI_PRACH_PDU_TYPE 0
-#define FAPI_PUSCH_PDU_TYPE 1
-#define FAPI_PUCCH_PDU_TYPE 2
-#define FAPI_SRS_PDU_TYPE 3
-
-#define FAPI_PDCCH_PDU_TYPE 0
-#define FAPI_PDSCH_PDU_TYPE 1
-#define FAPI_PBCH_PDU_TYPE 2
-#define FAPI_CSIRS_PDU_TYPE 3
+ enum ul_tti_pdu_type_e {
+ FAPI_PRACH_PDU_TYPE = 0,
+ FAPI_PUSCH_PDU_TYPE,
+ FAPI_PUCCH_PDU_TYPE,
+ FAPI_SRS_PDU_TYPE,
+ FAPI_UL_TTI_PDU_TYPE_MAX
+ };
+
+ enum dl_tti_pdu_type_e {
+ FAPI_PDCCH_PDU_TYPE = 0,
+ FAPI_PDSCH_PDU_TYPE,
+ FAPI_CSIRS_PDU_TYPE,
+ FAPI_PBCH_PDU_TYPE,
+ FAPI_DL_TTI_PDU_TYPE_MAX
+ };
//------------------------------------------------------------------------------------------------------------
-// Linked list header prent at the top of all messages
- typedef struct _fapi_api_queue_elem {
- struct _fapi_api_queue_elem *p_next;
- // p_tx_data_elm_list used for TX_DATA.request processing
- struct _fapi_api_queue_elem *p_tx_data_elm_list;
- uint8_t msg_type;
- uint8_t num_message_in_block;
- uint32_t msg_len;
- uint32_t align_offset;
- uint64_t time_stamp;
- } fapi_api_queue_elem_t, *p_fapi_api_queue_elem_t;
-
// Updated per 5G FAPI
typedef struct {
uint8_t num_msg;
// Can be used for Phy Id or Carrier Id 5G FAPI Table 3-2
uint8_t handle;
uint8_t pad[2];
- } fapi_msg_header_t, *p_fapi_msg_header_t;
+ } fapi_msg_header_t,
+ *p_fapi_msg_header_t;
// Updated per 5G FAPI
typedef struct {
uint16_t rsv; // To be 32-bit aligned, if FAPI_NUMEROLOGIES changes to some other value than 5 please ensure 32 bit alignment
} fapi_config_num_tlv_t;
- typedef struct {
- uint16_t hopping_id;
- uint8_t carrier_aggregation_level;
- uint8_t group_hop_flag;
- uint8_t sequence_hop_flag;
- // uint8_t nDMRS_type_A_pos;
- uint8_t pad[3];
- } fapi_config_req_vendor_msg_t;
-
- typedef struct {
- uint16_t sfn;
- uint16_t slot;
- uint32_t mode;
-#ifdef DEBUG_MODE
- uint32_t count;
- uint32_t period;
-#endif
- } fapi_start_req_vendor_msg_t;
-
- typedef struct {
- uint16_t sfn;
- uint16_t slot;
- } fapi_stop_req_vendor_msg_t;
-
- typedef struct {
- fapi_msg_t header;
- fapi_config_req_vendor_msg_t config_req_vendor;
- fapi_start_req_vendor_msg_t start_req_vendor;
- fapi_stop_req_vendor_msg_t stop_req_vendor;
- } fapi_vendor_msg_t;
-
// Updated per 5G FAPI
typedef struct {
fapi_msg_t header; // For PARAM.req message length in fapi_msg_t is zero per 5G FAPI 3.3.1.1
uint8_t aggregationLevel;
fapi_precoding_bmform_t pc_and_bform;
uint8_t beta_pdcch_1_0;
- uint8_t powerControlOfssetSS;
+ uint8_t powerControlOffsetSS;
uint16_t payloadSizeBits;
uint8_t payload[FAPI_DCI_PAYLOAD_BYTE_LEN]; // 5G FAPI Table 3-37
} fapi_dl_dci_t;
uint8_t cceRegMappingType;
uint8_t regBundleSize;
uint8_t interleaverSize;
- uint8_t coreSetSize;
+ uint8_t coreSetType;
uint16_t shiftIndex;
uint8_t precoderGranularity;
- uint8_t coreSetType;
+ uint8_t pad;
uint16_t numDlDci; // 5G FAPI Table 3-36
fapi_dl_dci_t dlDci[FAPI_MAX_NUMBER_DL_DCI];
} fapi_dl_pdcch_pdu_t;
// Updated per 5G FAPI
typedef struct {
- uint16_t pdu_length;
+ uint32_t pdu_length;
uint16_t pdu_index;
- uint32_t num_tlvs;
+ uint16_t num_tlvs;
fapi_uint8_ptr_tlv_t tlvs[FAPI_MAX_NUMBER_OF_TLVS_PER_PDU]; // 5G FAPI Table 3-58 Subset
} fapi_tx_pdu_desc_t;
uint16_t timingAdvance;
uint16_t rssi; // 5G FAPI Table 3-65
uint8_t pad1[2];
- uint8_t uciBits[FAPI_MAX_UCI_BIT_BYTE_LEN];
fapi_sr_f0f1_info_t srInfo; // This is included if indicated by the pduBitmap
fapi_harq_f0f1_info_t harqInfo; // This is included if indicated by the pduBitmap
} fapi_uci_o_pucch_f0f1_t;
fapi_rach_pdu_t rachPdu[FAPI_MAX_NUMBER_RACH_PDUS_PER_SLOT]; // 5G FAPI Table 3-74
} fapi_rach_indication_t;
-//Vendor extension messages
- typedef struct {
- fapi_msg_t header;
- uint16_t sfn;
- uint16_t slot;
- uint32_t test_type;
- } fapi_vendor_ext_shutdown_req_t;
-
- typedef struct {
- fapi_msg_t header;
- uint16_t sfn;
- uint16_t slot;
- uint32_t nStatus;
- } fapi_vendor_ext_shutdown_res_t;
-
-#ifdef DEBUG_MODE
- typedef struct {
- uint32_t carrNum;
- uint32_t numSubframes;
- uint32_t testUeMode;
- uint32_t timerModeFreqDomain;
- uint32_t phaseCompensationEnable;
- uint32_t startFrameNum;
- uint32_t startSlotNum;
- char filename_in_ul_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
- [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_in_ul_urllc[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
- [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_in_prach_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
- [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_in_srs_iq[FAPI_MAX_IQ_SAMPLE_UL_ANTENNA]
- [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_out_dl_iq[FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_out_dl_iq_urllc[FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_out_dl_beam[FAPI_MAX_IQ_SAMPLE_DL_PORTS]
- [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- char filename_out_ul_beam[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
- [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
- uint8_t buffer[FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE];
- } fapi_vendor_ext_iq_samples_info_t;
-
- typedef struct {
- fapi_msg_t header;
- fapi_vendor_ext_iq_samples_info_t iq_samples_info;
- } fapi_vendor_ext_iq_samples_req_t;
-
- typedef struct {
- fapi_msg_t header;
- } fapi_vendor_ext_dl_iq_samples_res_t;
-
- typedef struct {
- fapi_msg_t header;
- } fapi_vendor_ext_ul_iq_samples_res_t;
-
- typedef struct {
- fapi_msg_t header;
- } fapi_vendor_ext_start_response_t;
-#endif
//------------------------------------------------------------------------------
#if defined(__cplusplus)
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+#ifndef _FAPI_VENDOR_EXTENSION_H_
+#define _FAPI_VENDOR_EXTENSION_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define FAPI_VENDOR_MESSAGE 0x10
+#define FAPI_VENDOR_EXT_SHUTDOWN_REQUEST 0x11
+#define FAPI_VENDOR_EXT_SHUTDOWN_RESPONSE 0x12
+
+#ifdef DEBUG_MODE
+#define FAPI_VENDOR_EXT_DL_IQ_SAMPLES 0x13
+#define FAPI_VENDOR_EXT_UL_IQ_SAMPLES 0x14
+#define FAPI_VENDOR_EXT_START_RESPONSE 0x15
+#endif
+
+/* ----- WLS Operation --- */
+#define FAPI_VENDOR_MSG_HEADER_IND 0x1A
+
+// PDSCH Payload
+#define FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ 0x1B
+
+// Linked list header present at the top of all messages
+ typedef struct _fapi_api_queue_elem {
+ struct _fapi_api_queue_elem *p_next;
+ // p_tx_data_elm_list used for TX_DATA.request processing
+ struct _fapi_api_queue_elem *p_tx_data_elm_list;
+ uint8_t msg_type;
+ uint8_t num_message_in_block;
+ uint32_t msg_len;
+ uint32_t align_offset;
+ uint64_t time_stamp;
+ } fapi_api_queue_elem_t,
+ *p_fapi_api_queue_elem_t;
+/* ----------------------- */
+
+#ifdef DEBUG_MODE
+#define FAPI_MAX_IQ_SAMPLE_FILE_SIZE 576
+#define FAPI_MAX_IQ_SAMPLE_DL_PORTS 16
+#define FAPI_MAX_IQ_SAMPLE_UL_PORTS 2
+#define FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS 8
+#define FAPI_MAX_IQ_SAMPLE_UL_ANTENNA 64
+#define FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE 4096
+#endif
+
+ typedef struct {
+ uint16_t hopping_id;
+ uint8_t carrier_aggregation_level;
+ uint8_t group_hop_flag;
+ uint8_t sequence_hop_flag;
+ // uint8_t nDMRS_type_A_pos;
+ uint8_t pad[3];
+ } fapi_config_req_vendor_msg_t;
+
+ typedef struct {
+ uint16_t sfn;
+ uint16_t slot;
+ uint32_t mode;
+#ifdef DEBUG_MODE
+ uint32_t count;
+ uint32_t period;
+#endif
+ } fapi_start_req_vendor_msg_t;
+
+ typedef struct {
+ uint16_t sfn;
+ uint16_t slot;
+ } fapi_stop_req_vendor_msg_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ fapi_config_req_vendor_msg_t config_req_vendor;
+ fapi_start_req_vendor_msg_t start_req_vendor;
+ fapi_stop_req_vendor_msg_t stop_req_vendor;
+ } fapi_vendor_msg_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ uint16_t sfn;
+ uint16_t slot;
+ uint32_t test_type;
+ } fapi_vendor_ext_shutdown_req_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ uint16_t sfn;
+ uint16_t slot;
+ uint32_t nStatus;
+ } fapi_vendor_ext_shutdown_res_t;
+
+#ifdef DEBUG_MODE
+ typedef struct {
+ uint32_t carrNum;
+ uint32_t numSubframes;
+ uint32_t nIsRadioMode;
+ uint32_t timerModeFreqDomain;
+ uint32_t phaseCompensationEnable;
+ uint32_t startFrameNum;
+ uint32_t startSlotNum;
+ uint32_t startSymNum;
+ char filename_in_ul_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
+ [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+ char filename_in_prach_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
+ [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+ char filename_in_srs_iq[FAPI_MAX_IQ_SAMPLE_UL_ANTENNA]
+ [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+ char filename_out_dl_iq[FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+ char filename_out_dl_beam[FAPI_MAX_IQ_SAMPLE_DL_PORTS]
+ [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+ char filename_out_ul_beam[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
+ [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+ uint8_t buffer[FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE];
+ } fapi_vendor_ext_iq_samples_info_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ fapi_vendor_ext_iq_samples_info_t iq_samples_info;
+ } fapi_vendor_ext_iq_samples_req_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ } fapi_vendor_ext_dl_iq_samples_res_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ } fapi_vendor_ext_ul_iq_samples_res_t;
+
+ typedef struct {
+ fapi_msg_t header;
+ } fapi_vendor_ext_start_response_t;
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+#endif // FAPI_VENDOR_EXTENSION_H_
#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_wls.h"
+#include "nr5g_fapi_log.h"
static nr5g_fapi_fapi2mac_queue_t fapi2mac_q[FAPI_MAX_PHY_INSTANCES];
}
queue = nr5g_fapi_fapi2mac_queue(phy_id);
+ if (pthread_mutex_lock((pthread_mutex_t *) & queue->lock)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock fapi2mac aggregate list"
+ "pthread mutex"));
+ return;
+ }
if (queue->p_send_list_head && queue->p_send_list_tail) {
p_fapi_msg_hdr = (p_fapi_msg_header_t) (queue->p_send_list_head + 1);
p_fapi_msg_hdr->num_msg += 1;
} else {
queue->p_send_list_head = queue->p_send_list_tail = p_list_elem;
}
+ if (pthread_mutex_unlock((pthread_mutex_t *) & queue->lock)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("unable to unlock fapi2mac aggregate list"
+ "pthread mutex"));
+ return;
+ }
}
//------------------------------------------------------------------------------
)
{
uint8_t phy_id = 0;
+ p_fapi_msg_header_t p_fapi_msg_hdr = NULL;
p_fapi_api_queue_elem_t p_commit_list_head = NULL;
p_fapi_api_queue_elem_t p_commit_list_tail = NULL;
p_nr5g_fapi_fapi2mac_queue_t queue = NULL;
for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) {
queue = nr5g_fapi_fapi2mac_queue(phy_id);
+ if (pthread_mutex_lock((pthread_mutex_t *) & queue->lock)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock fapi2mac aggregate list"
+ "pthread mutex"));
+ return;
+ }
if (queue->p_send_list_head && queue->p_send_list_tail) {
- if (p_commit_list_head && p_commit_list_tail) {
- p_commit_list_tail->p_next = queue->p_send_list_head;
- p_commit_list_tail = queue->p_send_list_tail;
+ p_fapi_msg_hdr =
+ (p_fapi_msg_header_t) (queue->p_send_list_head + 1);
+ if (p_fapi_msg_hdr->num_msg) {
+ if (p_commit_list_head && p_commit_list_tail) {
+ p_commit_list_tail->p_next = queue->p_send_list_head;
+ p_commit_list_tail = queue->p_send_list_tail;
+ } else {
+ p_commit_list_head = queue->p_send_list_head;
+ p_commit_list_tail = queue->p_send_list_tail;
+ }
} else {
- p_commit_list_head = queue->p_send_list_head;
- p_commit_list_tail = queue->p_send_list_tail;
+ nr5g_fapi_fapi2mac_wls_free_buffer((void *)
+ queue->p_send_list_head);
}
queue->p_send_list_head = queue->p_send_list_tail = NULL;
}
+ if (pthread_mutex_unlock((pthread_mutex_t *) & queue->lock)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("unable to unlock fapi2mac aggregate list"
+ "pthread mutex"));
+ return;
+ }
}
if (p_commit_list_head)
return p_list_elem;
}
+//------------------------------------------------------------------------------
+/** @ingroup group_lte_source_phy_fapi
+ *
+ * @return void
+ *
+ * @description This function initializes the pthead_mutext_lock.
+ */
+void nr5g_fapi_fapi2mac_init_api_list(
+ )
+{
+ uint8_t phy_id = 0;
+ p_nr5g_fapi_fapi2mac_queue_t queue = NULL;
+
+ for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) {
+ queue = nr5g_fapi_fapi2mac_queue(phy_id);
+ pthread_mutex_init((pthread_mutex_t *) & queue->lock, NULL);
+ }
+}
#ifndef NR5G_FAPI_FAPI2MAC_API_H
#define NR5G_FAPI_FAPI2MAC_API_H
-#include "fapi_interface.h"
+#include "fapi_vendor_extension.h"
+#include "nr5g_fapi_std.h"
typedef struct _nr5g_fapi_fapi2mac_queue {
- p_fapi_api_queue_elem_t p_send_list_head; // list head to, send to MAC
- p_fapi_api_queue_elem_t p_send_list_tail; // list tail to, send to MAC
-} nr5g_fapi_fapi2mac_queue_t, *p_nr5g_fapi_fapi2mac_queue_t;
+ volatile pthread_mutex_t lock;
+ volatile p_fapi_api_queue_elem_t p_send_list_head; // list head to, send to MAC
+ volatile p_fapi_api_queue_elem_t p_send_list_tail; // list tail to, send to MAC
+} nr5g_fapi_fapi2mac_queue_t,
+*p_nr5g_fapi_fapi2mac_queue_t;
// Function definitions
// -----------------------------------------------------------------------------
uint8_t phy_id,
p_fapi_api_queue_elem_t p_list_elem);
+void nr5g_fapi_fapi2mac_init_api_list(
+ );
#endif
// phyStats->iaL1ApiStats.errorInd++; //TODO
NR5G_FAPI_LOG(INFO_LOG, ("[NR5G_FAPI][ERROR.indication][%d][%d,%d]",
- p_phy_instance->phy_id,
- p_iapi_resp->sSFN_Slot.nSFN,
- p_iapi_resp->sSFN_Slot.nSlot));
+ p_phy_instance->phy_id,
+ p_iapi_resp->sSFN_Slot.nSFN, p_iapi_resp->sSFN_Slot.nSlot));
return SUCCESS;
}
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
PSHUTDOWNRESPONSEStruct p_iapi_resp);
-#ifdef DEBUG_MODE
uint8_t nr5g_fapi_start_resp(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
PSTARTRESPONSEStruct p_iapi_resp);
+#ifdef DEBUG_MODE
uint8_t nr5g_fapi_dl_iq_samples_response(
p_nr5g_fapi_phy_ctx_t p_phy_ctx,
PADD_REMOVE_BBU_CORES p_iapi_resp);
{
uint8_t phy_id = 0;
- p_fapi_api_queue_elem_t p_list_elem = NULL;
- p_fapi_msg_header_t p_fapi_msg_hdr = NULL;
-
for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) {
if ((FAPI_STATE_CONFIGURED == p_phy_ctx->phy_instance[phy_id].state) ||
(FAPI_STATE_RUNNING == p_phy_ctx->phy_instance[phy_id].state)) {
- p_list_elem =
- nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_MSG_HEADER_IND, 1,
- sizeof(fapi_msg_header_t));
- if (!p_list_elem) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI MSG HDR] Unable to create "
- "list element. Out of memory!!!"));
- return FAILURE;
- }
-
- p_fapi_msg_hdr = (fapi_msg_header_t *) (p_list_elem + 1);
- p_fapi_msg_hdr->num_msg = 0;
- p_fapi_msg_hdr->handle = phy_id;
-
- // Add element to send list
- nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem);
- NR5G_FAPI_LOG(DEBUG_LOG,
- ("[FAPI MSG HDR] FAPI Message Header Added for PHY: %d",
- phy_id));
+ nr5g_fapi_message_header_per_phy(phy_id);
}
}
p_fapi_msg_header_t p_fapi_msg_hdr = NULL;
p_list_elem =
- nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_MSG_HEADER_IND, 1,
+ nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_VENDOR_MSG_HEADER_IND, 1,
sizeof(fapi_msg_header_t));
if (!p_list_elem) {
NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI MSG HDR] Unable to create "
#include "nr5g_fapi_framework.h"
#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
+#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
#include "nr5g_fapi_stats.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
if (p_iapi_resp->nStatus == SUCCESS) {
#ifdef DEBUG_MODE
p_list_elem =
- nr5g_fapi_fapi2mac_create_api_list_elem(
- FAPI_VENDOR_EXT_SHUTDOWN_RESPONSE, 1,
- sizeof(fapi_vendor_ext_shutdown_res_t));
+ nr5g_fapi_fapi2mac_create_api_list_elem
+ (FAPI_VENDOR_EXT_SHUTDOWN_RESPONSE, 1,
+ sizeof(fapi_vendor_ext_shutdown_res_t));
if (!p_list_elem) {
NR5G_FAPI_LOG(ERROR_LOG, ("[SHUTDOWN.response] Unable to create "
"list element. Out of memory!!!"));
fapi_req.slot = 0;
fapi_req.test_type = p_phy_instance->shutdown_test_type;
nr5g_fapi_shutdown_request(p_phy_instance, &fapi_req);
+ nr5g_fapi_fapi2phy_send_api_list();
} else {
NR5G_FAPI_LOG(ERROR_LOG, ("[SHUTDOWN.response] Invalid status "
"from PHY, hence triggering Error Indication"));
PSTARTRESPONSEStruct p_iapi_resp)
{
uint8_t phy_id;
+#ifdef DEBUG_MODE
fapi_vendor_ext_start_response_t *p_fapi_resp;
+#endif
fapi_error_ind_t *p_fapi_error_ind;
p_fapi_api_queue_elem_t p_list_elem;
p_nr5g_fapi_phy_instance_t p_phy_instance = NULL;
#include "nr5g_fapi_framework.h"
#include "gnb_l1_l2_api.h"
#include "nr5g_fapi_fapi2mac_api.h"
+#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
+#include "nr5g_fapi_fapi2phy_p5_proc.h"
+#include "nr5g_fapi_fapi2phy_p5_pvt_proc.h"
/** @ingroup group_source_api_p5_fapi2mac_proc
*
{
uint8_t phy_id;
- fapi_stop_ind_t *p_fapi_resp;
fapi_error_ind_t *p_fapi_error_ind;
p_fapi_api_queue_elem_t p_list_elem;
p_nr5g_fapi_phy_instance_t p_phy_instance = NULL;
p_stats = &p_phy_instance->stats;
p_stats->iapi_stats.iapi_stop_ind++;
- if (0 == p_iapi_resp->nStatus) {
+ if (SUCCESS == p_iapi_resp->nStatus) {
if (FAPI_STATE_RUNNING == p_phy_instance->state) {
p_phy_instance->state = FAPI_STATE_CONFIGURED;
}
+#ifdef DEBUG_MODE
p_list_elem =
nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_STOP_INDICATION, 1,
sizeof(fapi_stop_ind_t));
"list element. Out of memory!!!"));
return FAILURE;
}
-
+ fapi_stop_ind_t *p_fapi_resp;
p_fapi_resp = (fapi_stop_ind_t *) (p_list_elem + 1);
p_fapi_resp->header.msg_id = FAPI_STOP_INDICATION;
p_fapi_resp->header.length = (uint16_t) sizeof(fapi_stop_ind_t);
nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem);
p_stats->fapi_stats.fapi_stop_ind++;
NR5G_FAPI_LOG(INFO_LOG, ("[STOP.indication][%d]", phy_id));
- } else if (1 == p_iapi_resp->nStatus) {
+#else
+ fapi_vendor_ext_shutdown_req_t fapi_req;
+ fapi_req.header.msg_id = FAPI_VENDOR_EXT_SHUTDOWN_REQUEST;
+ fapi_req.header.length = sizeof(fapi_vendor_ext_shutdown_req_t);
+ fapi_req.sfn = 0;
+ fapi_req.slot = 0;
+ fapi_req.test_type = 0;
+ nr5g_fapi_shutdown_request(p_phy_instance, &fapi_req);
+ nr5g_fapi_fapi2phy_send_api_list();
+#endif
+ } else if (FAILURE == p_iapi_resp->nStatus) {
p_list_elem =
nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_ERROR_INDICATION, 1,
sizeof(fapi_error_ind_t));
}
if (NULL == p_iapi_resp) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[UL_IQ_SAMPLES.response] Invalid iapi "
+ NR5G_FAPI_LOG(ERROR_LOG, ("[UL_IQ_SAMPLES.response] Invalid IAPI "
"ULIQ_Samples response message"));
return FAILURE;
}
phy_id = p_iapi_resp->sSFN_Slot.nCarrierIdx;
p_phy_instance = &p_phy_ctx->phy_instance[phy_id];
- if (p_phy_instance->phy_id != phy_id) {
- NR5G_FAPI_LOG(ERROR_LOG, (" [UL_IQ_SAMPLES.response] Invalid "
- "phy instance"));
- return FAILURE;
- }
// Create FAPI message header
if (p_phy_instance->state == FAPI_STATE_IDLE) {
nr5g_fapi_message_header_per_phy(phy_id);
p_stats->fapi_stats.fapi_crc_ind++;
NR5G_FAPI_LOG(DEBUG_LOG, ("[CRC.indication][%d][%d,%d]",
- p_phy_instance->phy_id,
- p_phy_crc_ind->sSFN_Slot.nSFN,
- p_phy_crc_ind->sSFN_Slot.nSlot));
+ p_phy_instance->phy_id,
+ p_phy_crc_ind->sSFN_Slot.nSFN, p_phy_crc_ind->sSFN_Slot.nSlot));
return SUCCESS;
}
return FAILURE;
}
- phy_id = p_iapi_resp->sSFN_Slot.nCarrierIdx;
- p_phy_instance = &p_phy_ctx->phy_instance[phy_id];
- if ((p_phy_instance->phy_id != phy_id)) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[SLOT.indication] Invalid " "phy instance"));
- return FAILURE;
- }
-
- p_stats = &p_phy_instance->stats;
- p_stats->iapi_stats.iapi_slot_ind++;
+ for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) {
+ if (FAPI_STATE_RUNNING == p_phy_ctx->phy_instance[phy_id].state) {
+ p_phy_instance = &p_phy_ctx->phy_instance[phy_id];
+ if ((p_phy_instance->phy_id != phy_id)) {
+ NR5G_FAPI_LOG(ERROR_LOG,
+ ("[SLOT.indication] Invalid " "phy instance"));
+ return FAILURE;
+ }
- p_list_elem =
- nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_SLOT_INDICATION, 1,
- sizeof(fapi_slot_ind_t));
- if (!p_list_elem) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[SLOT.indication] Unable to create "
- "list element. Out of memory!!!"));
- return FAILURE;
- }
+ p_stats = &p_phy_instance->stats;
+ p_stats->iapi_stats.iapi_slot_ind++;
- p_fapi_slot_ind = (fapi_slot_ind_t *) (p_list_elem + 1);
- p_fapi_slot_ind->header.msg_id = FAPI_SLOT_INDICATION;
- p_fapi_slot_ind->header.length = (uint16_t) sizeof(fapi_slot_ind_t);
- p_fapi_slot_ind->sfn = p_iapi_resp->sSFN_Slot.nSFN;
- p_fapi_slot_ind->slot = p_iapi_resp->sSFN_Slot.nSlot;
+ p_list_elem =
+ nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_SLOT_INDICATION, 1,
+ sizeof(fapi_slot_ind_t));
+ if (!p_list_elem) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("[SLOT.indication] Unable to create "
+ "list element. Out of memory!!!"));
+ return FAILURE;
+ }
- /* Add element to send list */
- nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem);
+ p_fapi_slot_ind = (fapi_slot_ind_t *) (p_list_elem + 1);
+ p_fapi_slot_ind->header.msg_id = FAPI_SLOT_INDICATION;
+ p_fapi_slot_ind->header.length = (uint16_t) sizeof(fapi_slot_ind_t);
+ p_fapi_slot_ind->sfn = p_iapi_resp->sSFN_Slot.nSFN;
+ p_fapi_slot_ind->slot = p_iapi_resp->sSFN_Slot.nSlot;
- p_stats->fapi_stats.fapi_slot_ind++;
- NR5G_FAPI_LOG(DEBUG_LOG, ("[SLOT.indication][%d][%d,%d]",
- p_phy_instance->phy_id,
- p_iapi_resp->sSFN_Slot.nSFN,
- p_iapi_resp->sSFN_Slot.nSlot));
+ /* Add element to send list */
+ nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem);
+ p_stats->fapi_stats.fapi_slot_ind++;
+ NR5G_FAPI_LOG(DEBUG_LOG, ("[SLOT.indication][%d][%d,%d]",
+ p_phy_instance->phy_id,
+ p_iapi_resp->sSFN_Slot.nSFN, p_iapi_resp->sSFN_Slot.nSlot));
+ }
+ }
return SUCCESS;
}
p_stats->fapi_stats.fapi_srs_ind++;
NR5G_FAPI_LOG(DEBUG_LOG, ("[SRS.indication][%d][%d,%d]",
p_phy_instance->phy_id,
- p_phy_srs_ind->sSFN_Slot.nSFN,
- p_phy_srs_ind->sSFN_Slot.nSlot));
+ p_phy_srs_ind->sSFN_Slot.nSFN, p_phy_srs_ind->sSFN_Slot.nSlot));
return SUCCESS;
}
p_stats->fapi_stats.fapi_uci_ind++;
NR5G_FAPI_LOG(DEBUG_LOG, ("[UCI.indication][%d][%d,%d]",
p_phy_instance->phy_id,
- p_phy_uci_ind->sSFN_Slot.nSFN,
- p_phy_uci_ind->sSFN_Slot.nSlot));
+ p_phy_uci_ind->sSFN_Slot.nSFN, p_phy_uci_ind->sSFN_Slot.nSlot));
return SUCCESS;
}
if (num_uci_bits > 0) {
NR5G_FAPI_MEMCPY(p_uci_pucch_f2_f3_f4->uciBits,
sizeof(uint8_t) * FAPI_MAX_UCI_BIT_BYTE_LEN,
- p_uci_pdu_data_struct->nUciBits, num_uci_bits);
+ p_uci_pdu_data_struct->nUciBits,
+ sizeof(uint8_t) * FAPI_MAX_UCI_BIT_BYTE_LEN);
}
}
/******************************************************************************
- << 3)*
* Copyright (c) 2019 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
p_ia_config_req->nSSBPrbOffset =
GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length) / (pow(2,
p_ia_config_req->nSubcCommon));
+ p_phy_instance->phy_config.nSSBPrbOffset =
+ p_ia_config_req->nSSBPrbOffset;
break;
case FAPI_SSB_PERIOD_TAG:
p_file_info = (fapi_vendor_ext_iq_samples_info_t *) (p_list_elem + 1);
p_file_info->carrNum = p_fapi_req->iq_samples_info.carrNum;
p_file_info->numSubframes = p_fapi_req->iq_samples_info.numSubframes;
- p_file_info->testUeMode = p_fapi_req->iq_samples_info.testUeMode;
+ p_file_info->nIsRadioMode = p_fapi_req->iq_samples_info.nIsRadioMode;
p_file_info->timerModeFreqDomain =
p_fapi_req->iq_samples_info.timerModeFreqDomain;
p_file_info->phaseCompensationEnable =
p_fapi_req->iq_samples_info.phaseCompensationEnable;
p_file_info->startFrameNum = p_fapi_req->iq_samples_info.startFrameNum;
p_file_info->startSlotNum = p_fapi_req->iq_samples_info.startSlotNum;
+ p_file_info->startSymNum = p_fapi_req->iq_samples_info.startSymNum;
if (FAILURE == NR5G_FAPI_MEMCPY(p_file_info->buffer,
sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE,
p_fapi_req->iq_samples_info.buffer, sizeof(CONFIGREQUESTStruct))) {
"failed!!!"));
}
- if (FAILURE == NR5G_FAPI_STRCPY(p_file_info->filename_out_dl_iq_urllc,
- sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE,
- p_fapi_req->iq_samples_info.filename_out_dl_iq_urllc,
- sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE)) {
- NR5G_FAPI_LOG(ERROR_LOG, ("[DL_IQ_Samples.request] URLLC file name "
- "copy failed!!!"));
- }
-
for (num_ant = 0; num_ant < FAPI_MAX_IQ_SAMPLE_DL_PORTS; num_ant++) {
if (FAILURE ==
NR5G_FAPI_STRCPY(p_file_info->filename_out_dl_beam[num_ant],
return FAILURE;
}
- if (p_fapi_vendor_msg->start_req_vendor.mode > 1) {
+ if (p_fapi_vendor_msg->start_req_vendor.mode > 4) {
NR5G_FAPI_LOG(ERROR_LOG, ("[START.request] PHY Mode %u invalid",
p_fapi_vendor_msg->start_req_vendor.mode));
return FAILURE;
p_file_info = (fapi_vendor_ext_iq_samples_info_t *) (p_list_elem + 1);
p_file_info->carrNum = p_fapi_req->iq_samples_info.carrNum;
p_file_info->numSubframes = p_fapi_req->iq_samples_info.numSubframes;
- p_file_info->testUeMode = p_fapi_req->iq_samples_info.testUeMode;
+ p_file_info->nIsRadioMode = p_fapi_req->iq_samples_info.nIsRadioMode;
p_file_info->timerModeFreqDomain =
p_fapi_req->iq_samples_info.timerModeFreqDomain;
p_file_info->phaseCompensationEnable =
p_fapi_req->iq_samples_info.phaseCompensationEnable;
p_file_info->startFrameNum = p_fapi_req->iq_samples_info.startFrameNum;
p_file_info->startSlotNum = p_fapi_req->iq_samples_info.startSlotNum;
+ p_file_info->startSymNum = p_fapi_req->iq_samples_info.startSymNum;
if (FAILURE == NR5G_FAPI_MEMCPY(p_file_info->buffer,
sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE,
p_fapi_req->iq_samples_info.buffer, sizeof(CONFIGREQUESTStruct))) {
"failed!!!"));
}
- if (FAILURE ==
- NR5G_FAPI_STRCPY(p_file_info->filename_in_ul_urllc[num_ant],
- sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE,
- p_fapi_req->iq_samples_info.filename_in_ul_urllc[num_ant],
- sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE)) {
- NR5G_FAPI_LOG(ERROR_LOG,
- ("[UL_IQ_Samples.request] URLLC file name " "copy failed!!!"));
- }
if (FAILURE ==
NR5G_FAPI_STRCPY(p_file_info->filename_in_prach_iq[num_ant],
sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE,
fapi_dl_pdsch_pdu_t * p_pdsch_pdu,
PDLSCHPDUStruct p_dlsch_pdu);
-uint8_t nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(
+uint16_t nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(
uint8_t beta_pdcch_1_0);
void nr5g_fapi_fill_ssb_pdu(
p_stats->fapi_stats.fapi_dl_tti_pdus++;
p_fapi_dl_tti_req_pdu = &p_fapi_req->pdus[idx];
switch (p_fapi_dl_tti_req_pdu->pduType) {
- case DL_PDU_TYPE_DCI:
+ case FAPI_PDCCH_PDU_TYPE:
nDCI++;
p_dci_pdu = (PDCIPDUStruct) pPduStruct;
NR5G_FAPI_MEMSET(p_dci_pdu, RUP32B(sizeof(DCIPDUStruct)), 0,
pdcch_size);
p_pdcch_pdu = &p_fapi_dl_tti_req_pdu->pdu.pdcch_pdu;
- p_dci_pdu->sPDUHdr.nPDUType = p_fapi_dl_tti_req_pdu->pduType;
+ p_dci_pdu->sPDUHdr.nPDUType = DL_PDU_TYPE_DCI;
p_dci_pdu->sPDUHdr.nPDUSize = pdcch_size;
total_size += pdcch_size;
nr5g_fapi_fill_dci_pdu(p_phy_instance, p_pdcch_pdu, p_dci_pdu);
break;
- case DL_PDU_TYPE_DLSCH:
+ case FAPI_PDSCH_PDU_TYPE:
p_dlsch_pdu = (PDLSCHPDUStruct) pPduStruct;
p_pdsch_pdu = &p_fapi_dl_tti_req_pdu->pdu.pdsch_pdu;
NR5G_FAPI_MEMSET(p_dlsch_pdu, RUP32B(sizeof(DLSCHPDUStruct)), 0,
pdsch_size);
- p_dlsch_pdu->sPDUHdr.nPDUType = p_fapi_dl_tti_req_pdu->pduType;
+ p_dlsch_pdu->sPDUHdr.nPDUType = DL_PDU_TYPE_DLSCH;
p_dlsch_pdu->sPDUHdr.nPDUSize = pdsch_size;
total_size += pdsch_size;
nr5g_fapi_fill_pdsch_pdu(p_phy_instance, p_pdsch_pdu,
p_dlsch_pdu);
break;
- case DL_PDU_TYPE_PBCH:
+ case FAPI_PBCH_PDU_TYPE:
p_bch_pdu = (PBCHPDUStruct) pPduStruct;
p_ssb_pdu = &p_fapi_dl_tti_req_pdu->pdu.ssb_pdu;
NR5G_FAPI_MEMSET(p_bch_pdu, RUP32B(sizeof(BCHPDUStruct)), 0,
pbch_size);
- p_bch_pdu->sPDUHdr.nPDUType = p_fapi_dl_tti_req_pdu->pduType;
+ p_bch_pdu->sPDUHdr.nPDUType = DL_PDU_TYPE_PBCH;
p_bch_pdu->sPDUHdr.nPDUSize = pbch_size;
total_size += pbch_size;
nr5g_fapi_fill_ssb_pdu(p_phy_instance, p_bch_pdu, p_ssb_pdu);
break;
- case DL_PDU_TYPE_CSIRS:
+ case FAPI_CSIRS_PDU_TYPE:
pCSIRSPdu = (PCSIRSPDUStruct) pPduStruct;
p_csi_rs_pdu = &p_fapi_dl_tti_req_pdu->pdu.csi_rs_pdu;
NR5G_FAPI_MEMSET(pCSIRSPdu, RUP32B(sizeof(CSIRSPDUStruct)), 0,
csirs_size);
- pCSIRSPdu->sPDUHdr.nPDUType = p_fapi_dl_tti_req_pdu->pduType;
+ pCSIRSPdu->sPDUHdr.nPDUType = DL_PDU_TYPE_CSIRS;
pCSIRSPdu->sPDUHdr.nPDUSize = csirs_size;
total_size += csirs_size;
nr5g_fapi_fill_csi_rs_pdu(p_phy_instance, pCSIRSPdu,
p_dci_pdu->nTotalBits = p_pdcch_pdu->dlDci[0].payloadSizeBits;
p_dci_pdu->nEpreRatioOfPDCCHToSSB =
- nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(p_pdcch_pdu->dlDci[0].
- beta_pdcch_1_0);
+ nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(p_pdcch_pdu->
+ dlDci[0].beta_pdcch_1_0);
p_dci_pdu->nEpreRatioOfDmrsToSSB =
- p_pdcch_pdu->dlDci[0].powerControlOfssetSS;
+ p_pdcch_pdu->dlDci[0].powerControlOffsetSS;
if (FAILURE == NR5G_FAPI_MEMCPY(p_dci_pdu->nDciBits,
sizeof(uint8_t) * MAX_DCI_BIT_BYTE_LEN,
p_pdcch_pdu->dlDci[0].payload,
NR5G_FAPI_LOG(ERROR_LOG, ("PDCCH: RNTI: %d -- DCI Bits copy error.",
p_pdcch_pdu->dlDci[0].rnti));
}
-
p_stats->iapi_stats.iapi_dl_tti_pdcch_pdus++;
}
p_dlsch_pdu->nRV[1] = p_pdsch_pdu->cwInfo[1].rvIndex;
p_dlsch_pdu->nTBSize[1] = p_pdsch_pdu->cwInfo[1].tbSize;
}
-
- p_dlsch_pdu->nNrOfAntennaPorts = p_phy_instance->phy_config.n_nr_of_rx_ant;
+ //p_dlsch_pdu->nNrOfAntennaPorts = p_phy_instance->phy_config.n_nr_of_rx_ant;
p_dlsch_pdu->nNrOfLayers = p_pdsch_pdu->nrOfLayers;
+ p_dlsch_pdu->nNrOfAntennaPorts = p_pdsch_pdu->nrOfLayers;
p_dlsch_pdu->nTransmissionScheme = p_pdsch_pdu->transmissionScheme;
p_dlsch_pdu->nDMRSConfigType = p_pdsch_pdu->dmrsConfigType;
p_dlsch_pdu->nNIDnSCID = p_pdsch_pdu->dlDmrsScramblingId;
p_dlsch_pdu->nPTRSFreqDensity = p_pdsch_pdu->ptrsFreqDensity;
p_dlsch_pdu->nPTRSReOffset = p_pdsch_pdu->ptrsReOffset;
p_dlsch_pdu->nEpreRatioOfPDSCHToPTRS = p_pdsch_pdu->nEpreRatioOfPdschToPtrs;
+ // Currently no mapping info available.
+ //p_dlsch_pdu->nEpreRatioOfPDSCHToSSB = 0x1170;
// PTRS Information
p_dlsch_pdu->nPTRSPresent = p_pdsch_pdu->pduBitMap & 0x0001;
p_dlsch_pdu->nNrOfPTRSPorts =
__builtin_popcount(p_pdsch_pdu->ptrsPortIndex);
- p_dlsch_pdu->nPTRSPortIndex[0] = p_pdsch_pdu->ptrsPortIndex;
+ for (idx = 0; idx < p_dlsch_pdu->nNrOfPTRSPorts &&
+ idx < MAX_DL_PER_UE_PTRS_PORT_NUM; idx++) {
+ p_dlsch_pdu->nPTRSPortIndex[idx] = idx;
+ }
+
// Don't Cares
p_dlsch_pdu->nNrOfDMRSAssPTRS[0] = 0x1;
p_dlsch_pdu->nNrOfDMRSAssPTRS[1] = 0x1;
p_dlsch_pdu->n1n2 = 0x201;
+
+ for (idx = 0; (idx < MAX_TXRU_NUM && idx < port_index); idx++) {
+ p_dlsch_pdu->nTxRUIdx[idx] = p_dlsch_pdu->nPortIndex[idx];
+ }
+ p_dlsch_pdu->nNrofTxRU = port_index;
p_stats->iapi_stats.iapi_dl_tti_pdsch_pdus++;
}
* |-----------------------------------------|
*
**/
-uint8_t nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(
+uint16_t nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(
uint8_t beta_pdcch_1_0)
{
if (beta_pdcch_1_0 > 0 && beta_pdcch_1_0 <= 2) {
PBCHPDUStruct p_bch_pdu,
fapi_dl_ssb_pdu_t * p_ssb_pdu)
{
+ uint8_t *p_mib = (uint8_t *) & p_bch_pdu->nMIB[0];
+ uint8_t *payload = (uint8_t *) & p_ssb_pdu->bchPayload.bchPayload;
nr5g_fapi_stats_t *p_stats;
+ p_mib[0] = payload[0];
+ p_mib[1] = payload[1];
+ p_mib[2] = payload[2];
p_stats = &p_phy_instance->stats;
p_stats->fapi_stats.fapi_dl_tti_ssb_pdus++;
p_bch_pdu->nSSBSubcOffset = p_ssb_pdu->ssbSubCarrierOffset;
+ p_bch_pdu->nSSBPrbOffset = p_phy_instance->phy_config.nSSBPrbOffset;
p_stats->iapi_stats.iapi_dl_tti_ssb_pdus++;
- // p_ssb_pdu->bchPayload = p_bch_pdu->nMIB
- // p_ssb_pdu->ssbBlockIndex
- // p_ssb_pdu->physCellId
- // p_ssb_pdu->betaPss
- // p_ssb_pdu->bchPayloadFlag
- // p_ssb_pdu->ssbOffsetPointA
- // p_ssb_pdu->preCodingAndBeamforming
}
/** @ingroup group_nr5g_test_config
// pCSIRSPdu->nEpreRatioToSSB = p_csi_rs_pdu->powerControlOffsetSs;
p_stats->iapi_stats.iapi_dl_tti_csi_rs_pdus++;
}
-
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p7_proc.h"
#include "nr5g_fapi_fapi2phy_p7_pvt_proc.h"
+#include "nr5g_fapi_memory.h"
/** @ingroup group_source_api_p7_fapi2phy_proc
*
fapi_tx_data_req_t * p_fapi_req,
PTXRequestStruct p_phy_req)
{
- uint16_t idx;
- uint32_t tlv;
+#define GATHER_SIZE 3
+#define GATHER_PDU_IDX 0
+#define GATHER_CW1 1
+#define GATHER_CW2 2
+ int gather[FAPI_MAX_NUMBER_DL_PDUS_PER_TTI][GATHER_SIZE];
+ int gathered_count = 0;
+ uint8_t *tag;
+ uint32_t length;
+ uint16_t idx, count, found;
fapi_tx_pdu_desc_t *p_fapi_pdu = NULL;
PDLPDUDataStruct p_phy_pdu = NULL;
+ NR5G_FAPI_MEMSET(gather,
+ (sizeof(int) * FAPI_MAX_NUMBER_DL_PDUS_PER_TTI * 3), -1,
+ (sizeof(int) * FAPI_MAX_NUMBER_DL_PDUS_PER_TTI * 3));
+ NR5G_FAPI_MEMSET(p_phy_req, sizeof(TXRequestStruct), 0,
+ sizeof(TXRequestStruct));
p_phy_req->sMsgHdr.nMessageType = MSG_TYPE_PHY_TX_REQ;
p_phy_req->sMsgHdr.nMessageLen = (uint16_t) sizeof(TXRequestStruct);
p_phy_req->sSFN_Slot.nCarrierIdx = p_phy_instance->phy_id;
p_phy_req->sSFN_Slot.nSlot = p_fapi_req->slot;
p_phy_req->nPDU = p_fapi_req->num_pdus;
p_phy_pdu = (PDLPDUDataStruct) (p_phy_req + 1);
+
for (idx = 0; idx < p_fapi_req->num_pdus; idx++) {
+ found = FALSE;
p_fapi_pdu = &p_fapi_req->pdu_desc[idx];
- for (tlv = 0; tlv < p_fapi_pdu->num_tlvs; tlv++) {
+ for (count = 0; count < gathered_count; count++) {
+ if (gather[count][GATHER_PDU_IDX] == p_fapi_pdu->pdu_index) {
+ found = TRUE;
+ break;
+ }
+ }
+
+ if (found) {
+ gather[count][GATHER_CW2] = idx;
+ } else {
+ if (gathered_count < FAPI_MAX_NUMBER_DL_PDUS_PER_TTI) {
+ gather[gathered_count][GATHER_PDU_IDX] = p_fapi_pdu->pdu_index;
+ gather[gathered_count][GATHER_CW1] = idx;
+ gathered_count++;
+ } else {
+ NR5G_FAPI_LOG(ERROR_LOG,
+ ("exceeded Max DL Pdus supported per tti: %d [%d] ",
+ gathered_count, FAPI_MAX_NUMBER_DL_PDUS_PER_TTI));
+ }
+ }
+ }
+
+ for (count = 0; count < gathered_count; count++) {
+ p_phy_pdu->nPduLen1 = 0;
+ p_phy_pdu->nPduLen2 = 0;
+ p_phy_pdu->pPayload1 = NULL;
+ p_phy_pdu->pPayload2 = NULL;
+ if (gather[count][GATHER_CW1] >= 0) {
+ p_fapi_pdu = &p_fapi_req->pdu_desc[gather[count][GATHER_CW1]];
p_phy_pdu->nPduIdx = p_fapi_pdu->pdu_index;
- p_phy_pdu->nPduLen1 = 0;
- p_phy_pdu->nPduLen2 = 0;
- p_phy_pdu->pPayload1 = NULL;
- p_phy_pdu->pPayload2 = NULL;
- if (tlv == 0) {
- p_phy_pdu->nPduLen1 = p_fapi_pdu->tlvs[tlv].tl.length;
- p_phy_pdu->pPayload1 = p_fapi_pdu->tlvs[tlv].value;
+ tag = (uint8_t *) & p_fapi_pdu->tlvs[0].tl.tag;
+ if (*tag == FAPI_TX_DATA_PTR_TO_PAYLOAD_64) {
+ tag++;
+ length =
+ (((uint32_t) *
+ tag) << 16) | (uint32_t) p_fapi_pdu->tlvs[0].tl.length;
+ p_phy_pdu->nPduLen1 = length;
+ p_phy_pdu->pPayload1 = p_fapi_pdu->tlvs[0].value;
+ } else {
+ NR5G_FAPI_LOG(ERROR_LOG,
+ ("Only 64 bit Ptr to Payload in TX_DATA.req is supported"));
+ }
+ }
+ if (gather[count][GATHER_CW2] >= 0) {
+ p_fapi_pdu = &p_fapi_req->pdu_desc[gather[count][GATHER_CW2]];
+ tag = (uint8_t *) & p_fapi_pdu->tlvs[0].tl.tag;
+ if (*tag == FAPI_TX_DATA_PTR_TO_PAYLOAD_64) {
+ tag++;
+ length =
+ (((uint32_t) *
+ tag) << 16) | (uint32_t) p_fapi_pdu->tlvs[0].tl.length;
+ p_phy_pdu->nPduLen2 = length;
+ p_phy_pdu->pPayload2 = p_fapi_pdu->tlvs[0].value;
} else {
- p_phy_pdu->nPduLen2 = p_fapi_pdu->tlvs[tlv].tl.length;
- p_phy_pdu->pPayload2 = p_fapi_pdu->tlvs[tlv].value;
+ NR5G_FAPI_LOG(ERROR_LOG,
+ ("Only 64 bit Ptr to Payload in TX_DATA.req is supported"));
}
}
p_phy_pdu++;
p_ia_dci_pdu->nCpType = p_fapi_dci_pdu->pdcchPduConfig.cyclicPrefix;
p_freq_dom_res = &p_fapi_dci_pdu->pdcchPduConfig.freqDomainResource[0];
p_ia_dci_pdu->nFreqDomain[0] =
- ((uint32_t) (p_freq_dom_res[0])) |
+ ((uint32_t) (p_freq_dom_res[0])) |
(((uint32_t) (p_freq_dom_res[1])) << 8) |
(((uint32_t) (p_freq_dom_res[2])) << 16) |
(((uint32_t) (p_freq_dom_res[3])) << 24);
p_ia_dci_pdu->nFreqDomain[1] =
- ((uint32_t) (p_freq_dom_res[4])) |
+ ((uint32_t) (p_freq_dom_res[4])) |
(((uint32_t) (p_freq_dom_res[5])) << 8);
p_ia_dci_pdu->nStartSymbolIndex =
p_fapi_dci_pdu->pdcchPduConfig.startSymbolIndex;
p_ia_dci_pdu->nTotalBits =
p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].payloadSizeBits;
p_ia_dci_pdu->nEpreRatioOfPDCCHToSSB =
- p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].powerControlOfssetSS;
+ p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].powerControlOffsetSS;
p_ia_dci_pdu->nEpreRatioOfDmrsToSSB =
p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].beta_pdcch_1_0;
p_ia_dci_pdu->nTotalBits =
p_stats->iapi_stats.iapi_ul_dci_pdus++;
return SUCCESS;
}
-
-
-
-
nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem);
p_stats->iapi_stats.iapi_ul_config_req++;
- NR5G_FAPI_LOG(TRACE_LOG, ("[NR5G_FAPI][UL_TTI.request][%d][%d,%d]",
+ NR5G_FAPI_LOG(DEBUG_LOG, ("[UL_TTI.request][%d][%d,%d]",
p_phy_instance->phy_id,
p_ia_ul_config_req->sSFN_Slot.nSFN,
p_ia_ul_config_req->sSFN_Slot.nSlot));
p_ul_data_chan->nSubcSpacing = p_pusch_pdu->subCarrierSpacing;
p_ul_data_chan->nCpType = p_pusch_pdu->cyclicPrefix;
p_ul_data_chan->nMCS = p_pusch_pdu->mcsIndex;
- p_ul_data_chan->nTransPrecode = 0;
+ p_ul_data_chan->nTransPrecode = !(p_pusch_pdu->transformPrecoding);
mcs_table = p_pusch_pdu->mcsTable;
if (mcs_table <= 2) {
p_ul_data_chan->nMcsTable = mcs_table;
nr_of_layers = p_ul_data_chan->nNrOfLayers = p_pusch_pdu->nrOfLayers;
for (i = 0; (i < FAPI_MAX_DMRS_PORTS && port_index < nr_of_layers); i++) {
if (port_index < FAPI_MAX_UL_LAYERS) {
- if ((dmrs_ports >> i) && 0x0001) {
+ if ((dmrs_ports >> i) & 0x0001) {
p_ul_data_chan->nPortIndex[port_index++] = i;
}
} else {
p_pucch_info->handle = p_ul_ctrl_chan->nUEId =
(uint16_t) p_pucch_pdu->handle;
+ p_ul_ctrl_chan->nBWPSize = p_pucch_pdu->bwpSize;
+ p_ul_ctrl_chan->nBWPStart = p_pucch_pdu->bwpStart;
p_ul_ctrl_chan->nSubcSpacing = p_pucch_pdu->subCarrierSpacing;
p_ul_ctrl_chan->nCpType = p_pucch_pdu->cyclicPrefix;
p_pucch_info->pucch_format = p_ul_ctrl_chan->nFormat =
sizeof(ULConfigRequestStruct));
for (i = 0; i < num_fapi_pdus; i++) {
+ p_pdu_head->nPDUSize = 0;
p_stats->fapi_stats.fapi_ul_tti_pdus++;
p_fapi_ul_tti_req_pdu = &p_fapi_req->pdus[i];
p_fapi_ul_tti_req_pdu->pduType));
return FAILURE;
}
- break;
}
p_pdu_head =
(PDUStruct *) ((uint8_t *) p_pdu_head + p_pdu_head->nPDUSize);
printf("init dev name: %s\n", p_cfg->wls.device_name);
char *const file_prefix = basename(p_cfg->wls.device_name);
printf("init basename: %s\n", file_prefix);
- char whitelist[32];
+ char whitelist[32], iova_mode[64];
uint8_t i;
char *argv[] = { p_cfg->prgname, "--proc-type=secondary",
- "--file-prefix", file_prefix, whitelist
+ "--file-prefix", file_prefix, whitelist, iova_mode
};
#if 0
char coremask[32];
/* initialize EAL first */
snprintf(whitelist, 32, "-w %s", "0000:00:06.0");
+
+ if (p_cfg->dpdk.iova_mode == 0)
+ snprintf(iova_mode, 64, "%s", "--iova-mode=pa");
+ else
+ snprintf(iova_mode, 64, "%s", "--iova-mode=va");
+
printf("Calling rte_eal_init: ");
for (i = 0; i < RTE_DIM(argv); i++) {
printf("%s ", argv[i]);
uint8_t nr5g_fapi_framework_init(
p_nr5g_fapi_cfg_t p_cfg)
{
- uint8_t retval = FAILURE;
p_nr5g_fapi_phy_ctx_t p_phy_ctx = nr5g_fapi_get_nr5g_fapi_phy_ctx();
- p_nr5g_fapi_wls_context_t pwls;
pthread_attr_t *p_mac2phy_attr, *p_phy2mac_attr;
struct sched_param param;
NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_INT] WLS init Failed"));
return FAILURE;
}
- // First let's wait for the L1 and L2 to be present
- while (retval) {
- retval = nr5g_fapi_fapi2phy_wls_ready();
- }
- // Now the L2 is up so let's make sure that the L1 was started first
- retval = FAILURE;
- while (retval) {
- retval = nr5g_fapi_fapi2mac_wls_ready();
- }
-
- usleep(1000000);
- // Now that the L2 is up and has completed the Common Memory initialization
- // the FT needs to initialize the FAPI2PHY buffers
- pwls = nr5g_fapi_wls_context();
- if (pwls) {
- if (FAILURE == nr5g_fapi2Phy_wls_init(pwls)) {
- return FAILURE;
- }
- } else {
- return FAILURE;
- }
+ NR5G_FAPI_LOG(INFO_LOG, ("[FAPI_INT] WLS init Successful"));
p_phy_ctx->phy2mac_worker_core_id = p_cfg->phy2mac_worker.core_id;
p_phy_ctx->mac2phy_worker_core_id = p_cfg->mac2phy_worker.core_id;
-
p_phy2mac_attr = &p_cfg->phy2mac_thread_info.thread_attr;
pthread_attr_init(p_phy2mac_attr);
if (!pthread_attr_getschedparam(p_phy2mac_attr, ¶m)) {
#include "nr5g_fapi_fapi2mac_wls.h"
#include "nr5g_fapi_log.h"
+static p_fapi_api_queue_elem_t p_fapi2mac_buffers;
+
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_fapi2mac_group
*
p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context();
WLS_HANDLE h_wls = nr5g_fapi_fapi2mac_wls_instance();
- if (pthread_mutex_lock((pthread_mutex_t *) & p_wls_ctx->
- fapi2mac_lock_alloc)) {
+ if (pthread_mutex_lock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_alloc)) {
NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock alloc pthread mutex"));
return NULL;
}
- pa_block = (uint64_t) WLS_DequeueBlock((void *)h_wls);
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2mac_lock_alloc)) {
+ if (p_fapi2mac_buffers) {
+ p_va_block = (void *)p_fapi2mac_buffers;
+ p_fapi2mac_buffers = p_fapi2mac_buffers->p_next;
+ } else {
+ pa_block = (uint64_t) WLS_DequeueBlock((void *)h_wls);
+ if (!pa_block) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_alloc)) {
+ NR5G_FAPI_LOG(ERROR_LOG,
+ ("unable to unlock alloc pthread mutex"));
+ return NULL;
+ }
+ //NR5G_FAPI_LOG(ERROR_LOG, ("nr5g_fapi_fapi2phy_wls_alloc_buffer alloc error\n"));
+ return NULL;
+ }
+ p_va_block = (void *)nr5g_fapi_wls_pa_to_va(h_wls, pa_block);
+ }
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_alloc)) {
NR5G_FAPI_LOG(ERROR_LOG, ("unable to unlock alloc pthread mutex"));
return NULL;
}
+ return p_va_block;
+}
- if (!pa_block) {
- //NR5G_FAPI_LOG(ERROR_LOG, ("nr5g_fapi_fapi2phy_wls_alloc_buffer alloc error\n"));
- return NULL;
+//------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
+ *
+ * @param void
+ *
+ * @return Pointer to the memory block
+ *
+ * @description
+ * This function allocates a block of memory from the pool
+ *
+**/
+//------------------------------------------------------------------------------
+void nr5g_fapi_fapi2mac_wls_free_buffer(
+ void *buffers)
+{
+ p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context();
+
+ if (pthread_mutex_lock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_alloc)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock alloc pthread mutex"));
+ return;
+ }
+ if (p_fapi2mac_buffers) {
+ ((p_fapi_api_queue_elem_t) buffers)->p_next = p_fapi2mac_buffers;
+ p_fapi2mac_buffers = (p_fapi_api_queue_elem_t) buffers;
+ } else {
+ p_fapi2mac_buffers = (p_fapi_api_queue_elem_t) buffers;
+ p_fapi2mac_buffers->p_next = NULL;
+ }
+
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_alloc)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("unable to unlock alloc pthread mutex"));
+ return;
}
- p_va_block = (void *)nr5g_fapi_wls_pa_to_va(h_wls, pa_block);
- return p_va_block;
}
//------------------------------------------------------------------------------
h_wls = nr5g_fapi_fapi2mac_wls_instance();
data = (uint64_t *) WLS_Get1(h_wls, &ms, &mt, &f);
*msg_size = ms, *msg_type = mt, *flags = f;
- NR5G_FAPI_LOG(TRACE_LOG, ("[NR5G_FAPI][FAPI2MAC WLS][GET] %p size: %d "
+ NR5G_FAPI_LOG(TRACE_LOG, ("[FAPI2MAC WLS][GET] %p size: %d "
"type: %x flags: %x", data, *msg_size, *msg_type, *flags));
return data;
WLS_HANDLE h_mac_wls = nr5g_fapi_fapi2mac_wls_instance();
uint64_t pa = nr5g_fapi_wls_va_to_pa(h_mac_wls, (void *)p_msg);
- NR5G_FAPI_LOG(TRACE_LOG, ("[NR5G_FAPI][FAPI2MAC WLS][PUT] %ld size: %d "
+ NR5G_FAPI_LOG(TRACE_LOG, ("[FAPI2MAC WLS][PUT] %ld size: %d "
"type: %x flags: %x", pa, msg_size, msg_type, flags));
ret = WLS_Put1(h_mac_wls, (uint64_t) pa, msg_size, msg_type, flags);
fapi_msg_t *p_msg_header = NULL;
uint16_t flags = 0;
p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context();
+ uint64_t start_tick = __rdtsc();
p_curr_msg = p_list_elem;
if (p_curr_msg && p_curr_msg->p_next) {
flags = WLS_SG_FIRST;
- if (p_curr_msg->msg_type == FAPI_MSG_HEADER_IND) {
+ if (p_curr_msg->msg_type == FAPI_VENDOR_MSG_HEADER_IND) {
if (SUCCESS != nr5g_fapi_fapi2mac_wls_put(p_curr_msg,
p_curr_msg->msg_len + sizeof(fapi_api_queue_elem_t),
- FAPI_MSG_HEADER_IND, flags)) {
+ FAPI_VENDOR_MSG_HEADER_IND, flags)) {
printf("Error\n");
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2mac_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
p_curr_msg->msg_len + sizeof(fapi_api_queue_elem_t),
p_msg_header->msg_id, flags)) {
printf("Error\n");
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2mac_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
p_curr_msg->msg_len + sizeof(fapi_api_queue_elem_t),
p_msg_header->msg_id, flags)) {
printf("Error\n");
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2mac_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
}
}
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2mac_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2mac_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG, ("unable to unlock send pthread mutex"));
return FAILURE;
}
+ tick_total_wls_send_per_tti_ul += __rdtsc() - start_tick;
+
return ret;
}
p_fapi_api_queue_elem_t p_qelm = NULL;
p_fapi_api_queue_elem_t p_tail_qelm = NULL;
WLS_HANDLE h_wls = nr5g_fapi_fapi2mac_wls_instance();
+ uint64_t start_tick = 0;
num_elms = nr5g_fapi_fapi2mac_wls_wait();
if (!num_elms)
return p_qelm_list;
+ start_tick = __rdtsc();
do {
p_msg = nr5g_fapi_fapi2mac_wls_get(&msg_size, &msg_type, &flags);
if (p_msg) {
}
num_elms--;
} while (num_elms && is_msg_present(flags));
+ tick_total_wls_get_per_tti_dl += __rdtsc() - start_tick;
return p_qelm_list;
}
#define _5G_FAPI_FAPI2MAC_WLS_H
#include "fapi_interface.h"
+#include "fapi_vendor_extension.h"
uint8_t nr5g_fapi_fapi2mac_is_valid_wls_ptr(
void *data);
+
uint8_t nr5g_fapi_fapi2mac_wls_send(
p_fapi_api_queue_elem_t p_list_elem);
+
p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_wls_recv(
);
void *nr5g_fapi_fapi2mac_wls_alloc_buffer(
);
+void nr5g_fapi_fapi2mac_wls_free_buffer(
+ void *buffers);
+
#endif /*_5G_FAPI_FAPI2MAC_WLS_H*/
#include "nr5g_fapi_std.h"
#include "nr5g_fapi_common_types.h"
+#include "nr5g_fapi_internal.h"
#include "nr5g_fapi_wls.h"
#include "nr5g_fapi_fapi2phy_wls.h"
#include "nr5g_fapi_log.h"
+static uint32_t g_to_free_send_list_cnt[TO_FREE_SIZE] = { 0 };
+static uint64_t g_to_free_send_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} };
+static uint32_t g_to_free_recv_list_cnt[TO_FREE_SIZE] = { 0 };
+static uint64_t g_to_free_recv_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} };
+
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
*
h_wls = nr5g_fapi_fapi2phy_wls_instance();
data = (uint64_t *) WLS_Get(h_wls, &ms, &mt, &f);
*msg_size = ms, *msg_type = mt, *flags = f;
- NR5G_FAPI_LOG(TRACE_LOG, ("[NR5G_FAPI][FAPI2PHY WLS][GET] %p size: %d "
+ NR5G_FAPI_LOG(TRACE_LOG, ("[FAPI2PHY WLS][GET] %p size: %d "
"type: %x flags: %x", data, *msg_size, *msg_type, *flags));
return data;
int ret = SUCCESS;
WLS_HANDLE h_phy_wls = nr5g_fapi_fapi2phy_wls_instance();
uint64_t pa = nr5g_fapi_wls_va_to_pa(h_phy_wls, (void *)p_msg);
- NR5G_FAPI_LOG(TRACE_LOG, ("[NR5G_FAPI][FAPI2PHY WLS][PUT] %ld size: %d "
+ NR5G_FAPI_LOG(TRACE_LOG, ("[FAPI2PHY WLS][PUT] %ld size: %d "
"type: %x flags: %x", pa, msg_size, msg_type, flags));
ret = WLS_Put(h_phy_wls, pa, msg_size, msg_type, flags);
return ret;
}
-//----------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
- *
- * @param void
- *
- * @return 0 if SUCCESS
- *
- * @description
- * This function is called at WLS init and waits in an infinite for L1 to respond back with some information
- * needed by the L2
- *
-**/
-//----------------------------------------------------------------------------------
-inline uint8_t nr5g_fapi_fapi2phy_wls_ready(
- )
-{
- int ret = SUCCESS;
- //NR5G_FAPI_LOG(TRACE_LOG, ("Waiting for L1 to respond in WLS Ready"));
- ret = WLS_Ready(nr5g_fapi_fapi2phy_wls_instance());
- return ret;
-}
-
//----------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
*
PMAC2PHY_QUEUE_EL p_qelm_list = NULL;
PMAC2PHY_QUEUE_EL p_qelm = NULL;
PMAC2PHY_QUEUE_EL p_tail_qelm = NULL;
+ uint64_t start_tick = 0;
num_elms = nr5g_fapi_fapi2phy_wls_wait();
if (!num_elms)
return p_qelm_list;
+ start_tick = __rdtsc();
+
do {
p_msg = nr5g_fapi_fapi2phy_wls_get(&msg_size, &msg_type, &flags);
if (p_msg) {
wls_fapi_add_blocks_to_ul();
}
+ tick_total_wls_get_per_tti_ul += __rdtsc() - start_tick;
return p_qelm_list;
}
if (SUCCESS != nr5g_fapi_fapi2phy_wls_put((uint64_t) p_curr_msg,
p_curr_msg->nMessageLen + sizeof(MAC2PHY_QUEUE_EL),
p_msg_header->nMessageType, flags)) {
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2phy_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2phy_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
p_curr_msg->nMessageLen + sizeof(MAC2PHY_QUEUE_EL),
p_msg_header->nMessageType, flags) != SUCCESS) {
printf("Error\n");
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2phy_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2phy_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
} /* p_curr_msg->Next */
flags = WLS_SG_NEXT;
}
- } else { // one block
+ } else { // one block
count++;
if (nr5g_fapi_fapi2phy_is_sdu_zbc_block(p_curr_msg, &n_zbc_blocks)) {
printf("Error ZBC block cannot be only one in the list\n");
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2phy_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2phy_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
p_curr_msg->nMessageLen + sizeof(MAC2PHY_QUEUE_EL),
p_curr_msg->nMessageType, flags)) {
printf("Error\n");
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2phy_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2phy_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG,
("unable to unlock send pthread mutex"));
}
wls_fapi_free_send_free_list(g_free_send_idx);
}
- if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->
- fapi2phy_lock_send)) {
+ if (pthread_mutex_unlock((pthread_mutex_t *) &
+ p_wls_ctx->fapi2phy_lock_send)) {
NR5G_FAPI_LOG(ERROR_LOG, ("unable to unlock send pthread mutex"));
return FAILURE;
}
return ret;
}
+
+//------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_lib_group
+ *
+ * @param[in] pListElem Pointer to List element header
+ * @param[in] idx Subframe Number
+ *
+ * @return Number of blocks freed
+ *
+ * @description This function Frees all the blocks in a List Element Linked
+ * List coming from L1 by storing them into an array to be
+ * freed at a later point in time.
+**/
+//------------------------------------------------------------------------------
+uint8_t get_stats_location(
+ uint8_t msg_type)
+{
+ uint8_t loc;
+ switch (msg_type) {
+ case MSG_TYPE_PHY_CONFIG_REQ:
+ loc = MEM_STAT_CONFIG_REQ;
+ break;
+ case MSG_TYPE_PHY_START_REQ:
+ loc = MEM_STAT_START_REQ;
+ break;
+ case MSG_TYPE_PHY_STOP_REQ:
+ loc = MEM_STAT_STOP_REQ;
+ break;
+ case MSG_TYPE_PHY_SHUTDOWN_REQ:
+ loc = MEM_STAT_SHUTDOWN_REQ;
+ break;
+ case MSG_TYPE_PHY_DL_CONFIG_REQ:
+ loc = MEM_STAT_DL_CONFIG_REQ;
+ break;
+ case MSG_TYPE_PHY_UL_CONFIG_REQ:
+ loc = MEM_STAT_UL_CONFIG_REQ;
+ break;
+ case MSG_TYPE_PHY_UL_DCI_REQ:
+ loc = MEM_STAT_UL_DCI_REQ;
+ break;
+ case MSG_TYPE_PHY_TX_REQ:
+ loc = MEM_STAT_TX_REQ;
+ break;
+ case MSG_TYPE_PHY_DL_IQ_SAMPLES:
+ loc = MEM_STAT_DL_IQ_SAMPLES;
+ break;
+ case MSG_TYPE_PHY_UL_IQ_SAMPLES:
+ loc = MEM_STAT_UL_IQ_SAMPLES;
+ break;
+ default:
+ loc = MEM_STAT_DEFAULT;
+ }
+
+ return loc;
+}
+
+//------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_lib_group
+ *
+ * @param[in] pListElem Pointer to List element header
+ * @param[in] idx Subframe Number
+ *
+ * @return Number of blocks freed
+ *
+ * @description This function Frees all the blocks in a List Element Linked
+ * List coming from L1 by storing them into an array to be
+ * freed at a later point in time.
+**/
+//------------------------------------------------------------------------------
+void wls_fapi_add_recv_apis_to_free(
+ PMAC2PHY_QUEUE_EL pListElem,
+ uint32_t idx)
+{
+ PMAC2PHY_QUEUE_EL pNextMsg = NULL;
+ L1L2MessageHdr *p_msg_header = NULL;
+ PRXULSCHIndicationStruct p_phy_rx_ulsch_ind = NULL;
+ int count, i;
+ uint8_t *ptr = NULL;
+
+ WLS_HANDLE h_wls;
+ p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context();
+ h_wls = p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST];
+
+ count = g_to_free_recv_list_cnt[idx];
+ pNextMsg = pListElem;
+ while (pNextMsg) {
+ if (count >= TOTAL_FREE_BLOCKS) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("%s: Reached max capacity of free list.\n"
+ "\t\t\t\tlist index: %d list count: %d max list count: %d",
+ __func__, idx, count, TOTAL_FREE_BLOCKS));
+ return;
+ }
+
+ g_to_free_recv_list[idx][count++] = (uint64_t) pNextMsg;
+ p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
+ if (p_msg_header->nMessageType == MSG_TYPE_PHY_RX_ULSCH_IND) {
+ p_phy_rx_ulsch_ind = (PRXULSCHIndicationStruct) p_msg_header;
+ for (i = 0; i < p_phy_rx_ulsch_ind->nUlsch; i++) {
+ ptr = p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i].pPayload;
+ ptr = (uint8_t *) nr5g_fapi_wls_pa_to_va(h_wls, (uint64_t) ptr);
+
+ if (ptr) {
+ g_to_free_recv_list[idx][count++] = (uint64_t) ptr;
+ }
+ }
+ }
+ pNextMsg = pNextMsg->pNext;
+ }
+
+ g_to_free_recv_list[idx][count] = 0L;
+ g_to_free_recv_list_cnt[idx] = count;
+
+ NR5G_FAPI_LOG(DEBUG_LOG, ("To Free %d\n", count));
+}
+
+//------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_lib_group
+ *
+ * @param[in] idx subframe Number
+ *
+ * @return Number of blocks freed
+ *
+ * @description This function frees all blocks that have been added to the
+ * free array
+**/
+//------------------------------------------------------------------------------
+void wls_fapi_free_recv_free_list(
+ uint32_t idx)
+{
+ PMAC2PHY_QUEUE_EL pNextMsg = NULL;
+ int count = 0;
+
+ if (idx >= TO_FREE_SIZE) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx));
+ return;
+ }
+
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_recv_list[idx][count];
+ while (pNextMsg) {
+ wls_fapi_free_buffer(pNextMsg, MIN_UL_BUF_LOCATIONS);
+ g_to_free_recv_list[idx][count++] = 0L;
+ if (g_to_free_recv_list[idx][count])
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_recv_list[idx][count];
+ else
+ pNextMsg = 0L;
+ }
+
+ NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count));
+ g_to_free_recv_list_cnt[idx] = 0;
+
+ return;
+}
+
+//------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_lib_group
+ *
+ * @param[in] pListElem Pointer to List element header
+ * @param[in] idx Subframe Number
+ *
+ * @return Number of blocks freed
+ *
+ * @description This function Frees all the blocks in a List Element Linked
+ * List coming from L1 by storing them into an array to be
+ * freed at a later point in time.
+**/
+//------------------------------------------------------------------------------
+void wls_fapi_add_send_apis_to_free(
+ PMAC2PHY_QUEUE_EL pListElem,
+ uint32_t idx)
+{
+ PMAC2PHY_QUEUE_EL pNextMsg = NULL;
+ L1L2MessageHdr *p_msg_header = NULL;
+ PRXULSCHIndicationStruct p_phy_rx_ulsch_ind = NULL;
+ int count, i;
+ uint8_t *ptr = NULL;
+
+ count = g_to_free_send_list_cnt[idx];
+ pNextMsg = pListElem;
+ while (pNextMsg) {
+ if (count >= TOTAL_FREE_BLOCKS) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("%s: Reached max capacity of free list.\n"
+ "\t\t\t\tlist index: %d list count: %d max list count: %d",
+ __func__, idx, count, TOTAL_FREE_BLOCKS));
+ return;
+ }
+
+ g_to_free_send_list[idx][count++] = (uint64_t) pNextMsg;
+ p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
+ if (p_msg_header->nMessageType == MSG_TYPE_PHY_RX_ULSCH_IND) {
+ p_phy_rx_ulsch_ind = (PRXULSCHIndicationStruct) p_msg_header;
+ for (i = 0; i < p_phy_rx_ulsch_ind->nUlsch; i++) {
+ ptr = p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i].pPayload;
+ if (ptr) {
+ g_to_free_send_list[idx][count++] = (uint64_t) ptr;
+ }
+ }
+ }
+ pNextMsg = pNextMsg->pNext;
+ }
+
+ g_to_free_send_list[idx][count] = 0L;
+ g_to_free_send_list_cnt[idx] = count;
+
+ NR5G_FAPI_LOG(DEBUG_LOG, ("To Free %d\n", count));
+}
+
+//------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_lib_group
+ *
+ * @param[in] idx subframe Number
+ *
+ * @return Number of blocks freed
+ *
+ * @description This function frees all blocks that have been added to the
+ * free array
+**/
+//------------------------------------------------------------------------------
+void wls_fapi_free_send_free_list(
+ uint32_t idx)
+{
+ PMAC2PHY_QUEUE_EL pNextMsg = NULL;
+ L1L2MessageHdr *p_msg_header = NULL;
+ int count = 0, loc = 0;
+
+ if (idx >= TO_FREE_SIZE) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx));
+ return;
+ }
+
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[idx][count];
+ while (pNextMsg) {
+ p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
+ loc = get_stats_location(p_msg_header->nMessageType);
+ wls_fapi_free_buffer(pNextMsg, loc);
+ g_to_free_send_list[idx][count++] = 0L;
+ if (g_to_free_send_list[idx][count])
+ pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[idx][count];
+ else
+ pNextMsg = 0L;
+ }
+
+ NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count));
+ g_to_free_send_list_cnt[idx] = 0;
+
+ return;
+}
void *data);
PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_wls_recv(
);
-
-inline uint8_t nr5g_fapi_fapi2phy_wls_ready(
- );
inline uint8_t nr5g_fapi_fapi2phy_wls_wait(
);
+void wls_fapi_add_send_apis_to_free(
+ PMAC2PHY_QUEUE_EL pListElem,
+ uint32_t idx);
+void wls_fapi_free_send_free_list(
+ uint32_t idx);
+void wls_fapi_add_recv_apis_to_free(
+ PMAC2PHY_QUEUE_EL pListElem,
+ uint32_t idx);
+void wls_fapi_free_recv_free_list(
+ uint32_t idx);
#endif /*_NR5G_FAPI2PHY_WLS_H_*/
nr5g_fapi_wls_context_t g_wls_ctx;
-static uint32_t g_to_free_send_list_cnt[TO_FREE_SIZE] = { 0 };
-static uint64_t g_to_free_send_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} };
-static uint32_t g_to_free_recv_list_cnt[TO_FREE_SIZE] = { 0 };
-static uint64_t g_to_free_recv_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} };
-
static uint8_t alloc_track[ALLOC_TRACK_SIZE];
//------------------------------------------------------------------------------
return &g_wls_ctx;
}
+//----------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
+ *
+ * @param void
+ *
+ * @return 0 if SUCCESS
+ *
+ * @description
+ * This function is called at WLS init and waits in an infinite for L1 to respond back with some information
+ * needed by the L2
+ *
+**/
+//----------------------------------------------------------------------------------
+inline uint8_t nr5g_fapi_fapi2phy_wls_ready(
+ )
+{
+ int retval = 0;
+ p_nr5g_fapi_wls_context_t p_wls = nr5g_fapi_wls_context();
+
+ retval = WLS_Ready(p_wls->h_wls[NR5G_FAPI2PHY_WLS_INST]);
+
+ return retval;
+}
+
+//----------------------------------------------------------------------------------
+/** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group
+ *
+ * @param void
+ *
+ * @return 0 if SUCCESS
+ *
+ * @description
+ * This function is called at WLS init and waits in an infinite for L1 to respond back with some information
+ * needed by the L2
+ *
+**/
+//----------------------------------------------------------------------------------
+inline uint8_t nr5g_fapi_fapi2mac_wls_ready(
+ )
+{
+ int retval = 0;
+ p_nr5g_fapi_wls_context_t p_wls = nr5g_fapi_wls_context();
+
+ retval = WLS_Ready1(p_wls->h_wls[NR5G_FAPI2MAC_WLS_INST]);
+
+ return retval;
+}
+
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_wls_lib_group
*
p_nr5g_fapi_cfg_t cfg)
{
p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context();
- const char *dev_name = "wls";
+ const char *dev_name = "wls0";
if (p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST] &&
p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST]) {
p_wls_ctx->shmem_size = cfg->wls.shmem_size;
p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST] =
- WLS_Open_Dual(dev_name /*"wls"cfg->wls.device_name */ ,
- WLS_SLAVE_CLIENT,
+ WLS_Open_Dual(dev_name, WLS_SLAVE_CLIENT,
cfg->wls.shmem_size, &p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]);
if ((NULL == p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]) &&
(NULL == p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST])) {
- // NR5G_FAPI_LOG(ERROR_LOG,("[NR5G_FAPI_ WLS] WLS instance connected."));
+ NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI_ WLS] WLS Open Dual Failed."));
return FAILURE;
}
// Issue WLS_Alloc() for FAPI2MAC
printf("Unable to alloc WLS Memory\n");
return FAILURE;
}
+ // Now the L2 is up so let's make sure that the L1 was started first
+ usleep(1000000);
+ // First let's wait for the L1 and L2 to be present
+ while (nr5g_fapi_fapi2phy_wls_ready()) ;
+ NR5G_FAPI_LOG(INFO_LOG, ("L1 is up..."));
+ // Now the L2 is up so let's make sure that the L1 was started first
+ while (nr5g_fapi_fapi2mac_wls_ready()) ;
+ NR5G_FAPI_LOG(INFO_LOG, ("L2 is up..."));
+
+ // Now that the L2 is up and has completed the Common Memory initialization
+ usleep(1000000);
+ if (FAILURE == nr5g_fapi_wls_memory_init()) {
+ return FAILURE;
+ }
pthread_mutex_init((pthread_mutex_t *)
- &p_wls_ctx->fapi2phy_lock_send, NULL);
+ & p_wls_ctx->fapi2phy_lock_send, NULL);
pthread_mutex_init((pthread_mutex_t *)
- &p_wls_ctx->fapi2phy_lock_alloc, NULL);
+ & p_wls_ctx->fapi2phy_lock_alloc, NULL);
pthread_mutex_init((pthread_mutex_t *)
- &p_wls_ctx->fapi2mac_lock_send, NULL);
+ & p_wls_ctx->fapi2mac_lock_send, NULL);
pthread_mutex_init((pthread_mutex_t *)
- &p_wls_ctx->fapi2mac_lock_alloc, NULL);
+ & p_wls_ctx->fapi2mac_lock_alloc, NULL);
return SUCCESS;
}
*
**/
//-------------------------------------------------------------------------------------------
-int wls_fapi_create_partition(
+uint8_t wls_fapi_create_partition(
p_nr5g_fapi_wls_context_t pWls)
{
#define WLS_HUGE_DEF_PAGE_SIZEA 0x40000000LL
* between FAPI and PHY.
**/
//------------------------------------------------------------------------------
-uint8_t nr5g_fapi2Phy_wls_init(
- p_nr5g_fapi_wls_context_t pwls)
+uint8_t nr5g_fapi_wls_memory_init(
+ )
{
int nBlocks = 0;
- uint8_t retval = SUCCESS;
+ p_nr5g_fapi_wls_context_t p_wls = nr5g_fapi_wls_context();
- retval = wls_fapi_create_partition(pwls);
- if ((nBlocks = wls_fapi_add_blocks_to_ul()) == 0) {
+ if (FAILURE == wls_fapi_create_partition(p_wls))
return FAILURE;
- }
-
- return retval;
-}
-
-uint8_t get_stats_location(
- uint8_t msg_type)
-{
- uint8_t loc;
- switch (msg_type) {
- case MSG_TYPE_PHY_CONFIG_REQ:
- loc = MEM_STAT_CONFIG_REQ;
- break;
- case MSG_TYPE_PHY_START_REQ:
- loc = MEM_STAT_START_REQ;
- break;
- case MSG_TYPE_PHY_STOP_REQ:
- loc = MEM_STAT_STOP_REQ;
- break;
- case MSG_TYPE_PHY_SHUTDOWN_REQ:
- loc = MEM_STAT_SHUTDOWN_REQ;
- break;
- case MSG_TYPE_PHY_DL_CONFIG_REQ:
- loc = MEM_STAT_DL_CONFIG_REQ;
- break;
- case MSG_TYPE_PHY_UL_CONFIG_REQ:
- loc = MEM_STAT_UL_CONFIG_REQ;
- break;
- case MSG_TYPE_PHY_UL_DCI_REQ:
- loc = MEM_STAT_UL_DCI_REQ;
- break;
- case MSG_TYPE_PHY_TX_REQ:
- loc = MEM_STAT_TX_REQ;
- break;
- case MSG_TYPE_PHY_DL_IQ_SAMPLES:
- loc = MEM_STAT_DL_IQ_SAMPLES;
- break;
- case MSG_TYPE_PHY_UL_IQ_SAMPLES:
- loc = MEM_STAT_UL_IQ_SAMPLES;
- break;
- default:
- loc = MEM_STAT_DEFAULT;
- }
-
- return loc;
-}
-//------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_lib_group
- *
- * @param[in] pListElem Pointer to List element header
- * @param[in] idx Subframe Number
- *
- * @return Number of blocks freed
- *
- * @description This function Frees all the blocks in a List Element Linked
- * List coming from L1 by storing them into an array to be
- * freed at a later point in time.
-**/
-//------------------------------------------------------------------------------
-void wls_fapi_add_recv_apis_to_free(
- PMAC2PHY_QUEUE_EL pListElem,
- uint32_t idx)
-{
- PMAC2PHY_QUEUE_EL pNextMsg = NULL;
- L1L2MessageHdr *p_msg_header = NULL;
- PRXULSCHIndicationStruct p_phy_rx_ulsch_ind = NULL;
- int count, i;
- uint8_t *ptr = NULL;
-
- WLS_HANDLE h_wls;
- p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context();
- h_wls = p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST];
-
- count = g_to_free_recv_list_cnt[idx];
- pNextMsg = pListElem;
- while (pNextMsg) {
- if (count >= TOTAL_FREE_BLOCKS) {
- NR5G_FAPI_LOG(ERROR_LOG, ("%s: Reached max capacity of free list.\n"
- "\t\t\t\tlist index: %d list count: %d max list count: %d",
- __func__, idx, count, TOTAL_FREE_BLOCKS));
- return;
- }
-
- g_to_free_recv_list[idx][count++] = (uint64_t) pNextMsg;
- p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
- if (p_msg_header->nMessageType == MSG_TYPE_PHY_RX_ULSCH_IND) {
- p_phy_rx_ulsch_ind = (PRXULSCHIndicationStruct) p_msg_header;
- for (i = 0; i < p_phy_rx_ulsch_ind->nUlsch; i++) {
- ptr = p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i].pPayload;
- ptr = (uint8_t *) nr5g_fapi_wls_pa_to_va(h_wls, (uint64_t) ptr);
-
- if (ptr) {
- g_to_free_recv_list[idx][count++] = (uint64_t) ptr;
- }
- }
- }
- pNextMsg = pNextMsg->pNext;
- }
-
- g_to_free_recv_list[idx][count] = 0L;
- g_to_free_recv_list_cnt[idx] = count;
-
- NR5G_FAPI_LOG(DEBUG_LOG, ("To Free %d\n", count));
-}
-
-//------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_lib_group
- *
- * @param[in] idx subframe Number
- *
- * @return Number of blocks freed
- *
- * @description This function frees all blocks that have been added to the
- * free array
-**/
-//------------------------------------------------------------------------------
-void wls_fapi_free_recv_free_list(
- uint32_t idx)
-{
- PMAC2PHY_QUEUE_EL pNextMsg = NULL;
- int count = 0;
-
- if (idx >= TO_FREE_SIZE) {
- NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx));
- return;
- }
-
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_recv_list[idx][count];
- while (pNextMsg) {
- wls_fapi_free_buffer(pNextMsg, MIN_UL_BUF_LOCATIONS);
- g_to_free_recv_list[idx][count++] = 0L;
- if (g_to_free_recv_list[idx][count])
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_recv_list[idx][count];
- else
- pNextMsg = 0L;
- }
-
- NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count));
- g_to_free_recv_list_cnt[idx] = 0;
-
- return;
-}
-
-//------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_lib_group
- *
- * @param[in] pListElem Pointer to List element header
- * @param[in] idx Subframe Number
- *
- * @return Number of blocks freed
- *
- * @description This function Frees all the blocks in a List Element Linked
- * List coming from L1 by storing them into an array to be
- * freed at a later point in time.
-**/
-//------------------------------------------------------------------------------
-void wls_fapi_add_send_apis_to_free(
- PMAC2PHY_QUEUE_EL pListElem,
- uint32_t idx)
-{
- PMAC2PHY_QUEUE_EL pNextMsg = NULL;
- L1L2MessageHdr *p_msg_header = NULL;
- PRXULSCHIndicationStruct p_phy_rx_ulsch_ind = NULL;
- int count, i;
- uint8_t *ptr = NULL;
-
- count = g_to_free_send_list_cnt[idx];
- pNextMsg = pListElem;
- while (pNextMsg) {
- if (count >= TOTAL_FREE_BLOCKS) {
- NR5G_FAPI_LOG(ERROR_LOG, ("%s: Reached max capacity of free list.\n"
- "\t\t\t\tlist index: %d list count: %d max list count: %d",
- __func__, idx, count, TOTAL_FREE_BLOCKS));
- return;
- }
-
- g_to_free_send_list[idx][count++] = (uint64_t) pNextMsg;
- p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
- if (p_msg_header->nMessageType == MSG_TYPE_PHY_RX_ULSCH_IND) {
- p_phy_rx_ulsch_ind = (PRXULSCHIndicationStruct) p_msg_header;
- for (i = 0; i < p_phy_rx_ulsch_ind->nUlsch; i++) {
- ptr = p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i].pPayload;
- if (ptr) {
- g_to_free_send_list[idx][count++] = (uint64_t) ptr;
- }
- }
- }
- pNextMsg = pNextMsg->pNext;
- }
-
- g_to_free_send_list[idx][count] = 0L;
- g_to_free_send_list_cnt[idx] = count;
-
- NR5G_FAPI_LOG(DEBUG_LOG, ("To Free %d\n", count));
-}
-
-//------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_lib_group
- *
- * @param[in] idx subframe Number
- *
- * @return Number of blocks freed
- *
- * @description This function frees all blocks that have been added to the
- * free array
-**/
-//------------------------------------------------------------------------------
-void wls_fapi_free_send_free_list(
- uint32_t idx)
-{
- PMAC2PHY_QUEUE_EL pNextMsg = NULL;
- L1L2MessageHdr *p_msg_header = NULL;
- int count = 0, loc = 0;
-
- if (idx >= TO_FREE_SIZE) {
- NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx));
- return;
- }
-
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[idx][count];
- while (pNextMsg) {
- p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1);
- loc = get_stats_location(p_msg_header->nMessageType);
- wls_fapi_free_buffer(pNextMsg, loc);
- g_to_free_send_list[idx][count++] = 0L;
- if (g_to_free_send_list[idx][count])
- pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list[idx][count];
- else
- pNextMsg = 0L;
- }
-
- NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count));
- g_to_free_send_list_cnt[idx] = 0;
-
- return;
-}
-
-//------------------------------------------------------------------------------
-/** @ingroup nr5g_fapi_source_framework_wls_lib_group
- *
- * @param[in] idx subframe Number
- *
- * @return Number of blocks freed
- *
- * @description This function frees all blocks that have been added to the
- * free array
-**/
-//------------------------------------------------------------------------------
-void wls_fapi_free_list_all(
- void)
-{
- uint32_t idx;
-
- for (idx = 0; idx < TO_FREE_SIZE; idx++) {
- wls_fapi_free_send_free_list(idx);
- wls_fapi_free_recv_free_list(idx);
+ if ((nBlocks = wls_fapi_add_blocks_to_ul()) == 0) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("Unable to allocate blocks to PHY"));
+ return FAILURE;
}
- nr5g_fapi_wls_print_stats();
+ return SUCCESS;
}
void *pEndOfStorage;
uint32_t nBlockSize;
uint32_t nBlockCount;
-} WLS_FAPI_MEM_STRUCT, *PWLS_FAPI_MEM_STRUCT;
+} WLS_FAPI_MEM_STRUCT,
+*PWLS_FAPI_MEM_STRUCT;
// WLS context structure
typedef struct _nr5g_fapi_wls_context {
volatile pthread_mutex_t fapi2phy_lock_alloc;
volatile pthread_mutex_t fapi2mac_lock_send;
volatile pthread_mutex_t fapi2mac_lock_alloc;
-} nr5g_fapi_wls_context_t, *p_nr5g_fapi_wls_context_t;
+} nr5g_fapi_wls_context_t,
+*p_nr5g_fapi_wls_context_t;
extern nr5g_fapi_wls_context_t g_wls_ctx;
inline p_nr5g_fapi_wls_context_t nr5g_fapi_wls_context(
);
+inline uint8_t nr5g_fapi_fapi2phy_wls_ready(
+ );
+inline uint8_t nr5g_fapi_fapi2mac_wls_ready(
+ );
uint8_t nr5g_fapi_wls_init(
);
-uint8_t nr5g_fapi2Phy_wls_init(
- p_nr5g_fapi_wls_context_t p_wls);
-
+uint8_t nr5g_fapi_wls_memory_init(
+ );
uint8_t nr5g_fapi_wls_destroy(
WLS_HANDLE h_wls);
void *wls_fapi_alloc_buffer(
void nr5g_fapi_wls_show_data(
void *ptr,
uint32_t size);
-int32_t wls_fapi_sdu_zbc_block_add_to_free(
- void *pMsgHeaderHead,
- int count,
- uint64_t * pToFreeList);
void wls_fapi_free_list_all(
void);
void nr5g_fapi_wls_print_stats(
void);
-void wls_fapi_add_send_apis_to_free(
- PMAC2PHY_QUEUE_EL pListElem,
- uint32_t idx);
-void wls_fapi_free_send_free_list(
- uint32_t idx);
-void wls_fapi_add_recv_apis_to_free(
- PMAC2PHY_QUEUE_EL pListElem,
- uint32_t idx);
-void wls_fapi_free_recv_free_list(
- uint32_t idx);
#endif /*_NR5G_FAPI_WLS_H_*/
#include "nr5g_fapi_fapi2phy_api.h"
#include "nr5g_fapi_fapi2phy_p5_proc.h"
#include "nr5g_fapi_fapi2phy_p7_proc.h"
+#include "nr5g_fapi_log.h"
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_workers_mac2phy_group
p_nr5g_fapi_phy_instance_t p_phy_instance = NULL;
uint8_t num_apis = 0;
uint8_t phy_id = 0;
+ uint64_t start_tick = __rdtsc();
NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] %s:", __func__));
p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config;
if (p_msg_list->p_next) {
p_prev_elm = p_msg_list;
while (p_msg_list) {
- if (FAPI_MSG_HEADER_IND == p_msg_list->msg_type) {
+ if (FAPI_VENDOR_MSG_HEADER_IND == p_msg_list->msg_type) {
p_prev_elm->p_next = NULL;
break;
}
if (p_per_carr_api_list) {
p_fapi_msg = (fapi_msg_t *) (p_per_carr_api_list + 1);
+#ifdef DEBUG_MODE
if ((p_fapi_msg->msg_id != FAPI_VENDOR_EXT_UL_IQ_SAMPLES)) {
+#endif
p_phy_instance = &p_phy_ctx->phy_instance[phy_id];
if (FAPI_STATE_IDLE == p_phy_instance->state) {
if (p_fapi_msg->msg_id != FAPI_CONFIG_REQUEST) {
}
p_phy_instance->phy_id = phy_id;
}
+#ifdef DEBUG_MODE
}
+#endif
nr5g_fapi_mac2phy_api_processing_handler(p_phy_instance,
p_per_carr_api_list);
p_per_carr_api_list = NULL;
}
}
+ tick_total_parse_per_tti_dl += __rdtsc() - start_tick;
+ start_tick = __rdtsc();
+
// Send to PHY
NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Send to PHY.."));
nr5g_fapi_fapi2phy_send_api_list();
+ tick_total_wls_send_per_tti_dl += __rdtsc() - start_tick;
}
//------------------------------------------------------------------------------
msg_type = p_curr_elm->msg_type;
if (msg_type == FAPI_TX_DATA_REQUEST) {
p_tx_data_elm = p_curr_elm;
- } else if (msg_type == FAPI_MSG_PHY_ZBC_BLOCK_REQ) {
+ } else if (msg_type == FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ) {
if (p_tx_data_pdu_list) {
p_tx_data_pdu_list_tail->p_next = p_curr_elm;
p_tx_data_pdu_list_tail = p_tx_data_pdu_list_tail->p_next;
p_tx_data_elm->p_tx_data_elm_list = p_tx_data_pdu_list;
p_tx_data_elm->p_next = NULL;
}
+
+ if (FAILURE == nr5g_fapi_check_api_ordering(p_phy_instance, p_msg_list)) {
+ NR5G_FAPI_LOG(ERROR_LOG, ("API Ordering is wrong."));
+ return;
+ }
// Walk through the API list
while (p_msg_list) {
p_fapi_msg = (fapi_msg_t *) (p_msg_list + 1);
#endif
case FAPI_VENDOR_EXT_SHUTDOWN_REQUEST:
- nr5g_fapi_shutdown_request(p_phy_instance,
- (fapi_vendor_ext_shutdown_req_t *) p_fapi_msg);
+ {
+ nr5g_fapi_shutdown_request(p_phy_instance,
+ (fapi_vendor_ext_shutdown_req_t *) p_fapi_msg);
+ nr5g_fapi_statistic_info_print();
+ if (g_statistic_start_flag == 1)
+ g_statistic_start_flag = 0;
+ }
break;
/* P5 Message Processing */
case FAPI_CONFIG_REQUEST:
- nr5g_fapi_config_request(p_phy_instance, (fapi_config_req_t *)
- p_fapi_msg, p_vendor_msg);
+ {
+ nr5g_fapi_config_request(p_phy_instance,
+ (fapi_config_req_t *)
+ p_fapi_msg, p_vendor_msg);
+ nr5g_fapi_statistic_info_init();
+ }
+
break;
case FAPI_START_REQUEST:
break;
case FAPI_STOP_REQUEST:
- nr5g_fapi_stop_request(p_phy_instance, (fapi_stop_req_t *)
- p_fapi_msg, p_vendor_msg);
- break;
+ {
+ nr5g_fapi_stop_request(p_phy_instance, (fapi_stop_req_t *)
+ p_fapi_msg, p_vendor_msg);
+ nr5g_fapi_statistic_info_print();
+ if (g_statistic_start_flag == 1)
+ g_statistic_start_flag = 0;
+ }
+ break;
/* P7 Message Processing */
case FAPI_DL_TTI_REQUEST:
- nr5g_fapi_dl_tti_request(p_phy_instance, (fapi_dl_tti_req_t *)
- p_fapi_msg, p_vendor_msg);
+ {
+ nr5g_fapi_dl_tti_request(p_phy_instance,
+ (fapi_dl_tti_req_t *)
+ p_fapi_msg, p_vendor_msg);
+ if (g_statistic_start_flag == 0)
+ g_statistic_start_flag = 1;
+ }
break;
case FAPI_UL_TTI_REQUEST:
p_msg_list = p_msg_list->p_next;
}
}
+
+uint8_t nr5g_fapi_check_api_ordering(
+ p_nr5g_fapi_phy_instance_t p_phy_instance,
+ p_fapi_api_queue_elem_t p_msg_list)
+{
+ uint16_t msg_id, api_order_check = FAPI_CONFIG_REQUEST;
+ p_fapi_api_queue_elem_t p_msg = p_msg_list;
+ fapi_msg_t *p_fapi_msg = NULL;
+
+ if (p_phy_instance && p_phy_instance->state == FAPI_STATE_RUNNING) {
+ p_fapi_msg = (fapi_msg_t *) (p_msg + 1);
+ msg_id = p_fapi_msg->msg_id;
+ // check if first msg is CONFIG.req
+ if (msg_id == FAPI_CONFIG_REQUEST) {
+ p_msg = p_msg->p_next;
+ }
+ api_order_check = FAPI_DL_TTI_REQUEST;
+ // Continue checking remaining APIs
+ while (p_msg) {
+ p_fapi_msg = (fapi_msg_t *) (p_msg + 1);
+ msg_id = p_fapi_msg->msg_id;
+ if ((msg_id == FAPI_DL_TTI_REQUEST) && (msg_id == api_order_check)) {
+ api_order_check = FAPI_UL_TTI_REQUEST;
+ } else if ((msg_id == FAPI_UL_TTI_REQUEST) &&
+ (msg_id == api_order_check)) {
+ api_order_check = FAPI_UL_DCI_REQUEST;
+ } else {
+ break;
+ }
+ p_msg = p_msg->p_next;
+ }
+ if (api_order_check != FAPI_UL_DCI_REQUEST) {
+ return FAILURE;
+ }
+ }
+
+ return SUCCESS;
+}
#include "nr5g_fapi_framework.h"
#include "fapi_interface.h"
+#include "fapi_vendor_extension.h"
void nr5g_fapi_mac2phy_api_recv_handler(
void *config,
p_nr5g_fapi_phy_instance_t p_phy_instance,
p_fapi_api_queue_elem_t p_msg_list);
+uint8_t nr5g_fapi_check_api_ordering(
+ p_nr5g_fapi_phy_instance_t p_phy_instance,
+ p_fapi_api_queue_elem_t p_msg_list);
#endif
#include "nr5g_fapi_fapi2mac_api.h"
#include "nr5g_fapi_fapi2mac_p5_proc.h"
#include "nr5g_fapi_fapi2mac_p7_proc.h"
-
+#include "nr5g_fapi_log.h"
//------------------------------------------------------------------------------
/** @ingroup nr5g_fapi_source_framework_workers_phy2mac_group
*
CPU_SET(p_phy_ctx->phy2mac_worker_core_id, &cpuset);
pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset);
+ nr5g_fapi_fapi2mac_init_api_list();
+
usleep(1000);
while (!p_phy_ctx->process_exit) {
p_msg_list = nr5g_fapi_fapi2phy_wls_recv();
{
PMAC2PHY_QUEUE_EL p_curr_msg;
PL1L2MessageHdr p_msg_header = NULL;
+ uint64_t start_tick = __rdtsc();
NR5G_FAPI_LOG(TRACE_LOG, ("[PHY2MAC] %s:", __func__));
{
nr5g_fapi_slot_indication((p_nr5g_fapi_phy_ctx_t) config,
(PSlotIndicationStruct) p_msg_header);
+ nr5g_fapi_statistic_info_set_all();
}
break;
}
p_curr_msg = p_curr_msg->pNext;
}
+ tick_total_parse_per_tti_ul += __rdtsc() - start_tick;
+
}
#define NR5G_FAPI_DEVICE_NAME_LEN 512
+enum {
+ DPDK_IOVA_PA_MODE = 0,
+ DPDK_IOVA_VA_MODE,
+ DPDK_IOVA_MAX_MODE
+};
+
typedef struct _nr5g_fapi_thread_info {
pthread_t thread_id; /* ID returned by pthread_create() */
pthread_attr_t thread_attr;
uint64_t shmem_size;
} nr5g_fapi_config_wls_cfg_t;
+typedef struct nr5g_fapi_config_dpdk_cfg_t {
+ uint8_t iova_mode; /*0 - PA mode, 1 - VA mode */
+} nr5g_fapi_config_dpdk_cft_t;
+
typedef struct _nr5g_fapi_config_log_cfg {
nr5g_fapi_log_types_t level;
} nr5g_fapi_config_log_cfg_t;
nr5g_fapi_config_log_cfg_t logger;
nr5g_fapi_thread_info_t mac2phy_thread_info;
nr5g_fapi_thread_info_t phy2mac_thread_info;
-} nr5g_fapi_cfg_t, *p_nr5g_fapi_cfg_t;
+ nr5g_fapi_config_dpdk_cft_t dpdk;
+} nr5g_fapi_cfg_t,
+*p_nr5g_fapi_cfg_t;
p_nr5g_fapi_cfg_t nr5g_fapi_config_loader(
char *prgname,
typedef struct _nr5g_fapi_phy_config {
uint8_t n_nr_of_rx_ant;
uint16_t phy_cell_id;
-} nr5g_fapi_phy_config_t, *pnr5g_fapi_phy_config_t;
+ uint8_t nSSBPrbOffset;
+} nr5g_fapi_phy_config_t,
+*pnr5g_fapi_phy_config_t;
typedef struct _nr5g_fapi_rach_info {
uint16_t phy_cell_id;
// parameters from config request
nr5g_fapi_stats_t stats;
nr5g_fapi_ul_slot_info_t ul_slot_info[MAX_UL_SLOT_INFO_COUNT];
-} nr5g_fapi_phy_instance_t, *p_nr5g_fapi_phy_instance_t;
+} nr5g_fapi_phy_instance_t,
+*p_nr5g_fapi_phy_instance_t;
// Phy Context
typedef struct _nr5g_fapi_phy_context {
uint8_t phy2mac_worker_core_id;
pthread_t phy2mac_tid;
pthread_t mac2phy_tid;
- uint64_t process_exit;
+ volatile uint64_t process_exit;
nr5g_fapi_phy_instance_t phy_instance[FAPI_MAX_PHY_INSTANCES];
-} nr5g_fapi_phy_ctx_t, *p_nr5g_fapi_phy_ctx_t;
+} nr5g_fapi_phy_ctx_t,
+*p_nr5g_fapi_phy_ctx_t;
// Function Declarations
inline p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx(
/******************************************************************************
-*
* Copyright (c) 2019 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
#include "fapi_interface.h"
#include "nr5g_fapi_common_types.h"
-#define RELEASE_15 0x0001
-
#define MAX_UL_SLOT_INFO_COUNT 10 //Maximum no of Slots for which UL_TTI.request info has to
#define FAPI_MAX_NUM_PUSCH_PDU 255 //as per Table 3-44
#define FAPI_MAX_NUM_PUCCH_PDU 255 //as per Table 3-44
#define FAPI_MAX_NUM_SRS_PDU 255 //as per Table 3-73
#define FAPI_MAX_NUM_RACH_PDU 255 //as per Table 3-74
+#define FAPI_MAX_PHY_INSTANCES 12
-// Updated per 5G FAPI
-typedef enum {
- FAPI_UL_TTI_REQ_PRACH_PDU_TYPE = 0,
- FAPI_UL_TTI_REQ_PUSCH_PDU_TYPE,
- FAPI_UL_TTI_REQ_PUCCH_PDU_TYPE,
- FAPI_UL_TTI_REQ_SRS_PDU_TYPE
-} fapiULTtiReqPduType_e;
+// CONFIGURATION INFORMATION CARRIER CONFIGURATION BANDWIDTH
+#define FAPI_BANDWIDTH_5_MHZ 5
+#define FAPI_BANDWIDTH_10_MHZ 10
+#define FAPI_BANDWIDTH_15_MHZ 15
+#define FAPI_BANDWIDTH_20_MHZ 20
+#define FAPI_BANDWIDTH_25_MHZ 25
+#define FAPI_BANDWIDTH_30_MHZ 30
+#define FAPI_BANDWIDTH_40_MHZ 40
+#define FAPI_BANDWIDTH_50_MHZ 50
+#define FAPI_BANDWIDTH_60_MHZ 60
+#define FAPI_BANDWIDTH_70_MHZ 70
+#define FAPI_BANDWIDTH_80_MHZ 80
+#define FAPI_BANDWIDTH_90_MHZ 90
+#define FAPI_BANDWIDTH_100_MHZ 100
+#define FAPI_BANDWIDTH_200_MHZ 200
+#define FAPI_BANDWIDTH_400_MHZ 400
-// Updated per 5G FAPI
-typedef enum {
- FAPI_UCI_IND_ON_PUSCH_PDU_TYPE = 0,
- FAPI_UCI_IND_ON_PUCCH_FMT_0_1_PDU_TYPE,
- FAPI_UCI_IND_ON_PUCCH_FMT_2_3_4_PDU_TYPE
-} fapiUciIndPdu_Type_e;
+#define FAPI_SUBCARRIER_SPACING_15 0
+#define FAPI_SUBCARRIER_SPACING_30 1
+#define FAPI_SUBCARRIER_SPACING_60 2
+#define FAPI_SUBCARRIER_SPACING_120 3
-// CRC
-enum {
- FAPI_CRC_CORRECT = 0,
- FAPI_CRC_ERROR = 1
-};
+#define FAPI_FFT_SIZE_512 512
+#define FAPI_FFT_SIZE_1024 1024
+#define FAPI_FFT_SIZE_2048 2048
+#define FAPI_FFT_SIZE_4096 4096
-// Release/Features support
-typedef enum {
- FAPI_NOT_SUPPORTED = 0,
- FAPI_SUPPORTED,
-} fapiSupport_t;
+#define FAPI_MAX_DL_LAYERS MAX_NUM_DL_LAYERS
+#define FAPI_MAX_UL_LAYERS 4
+// FAPI Supports MAX 12; Mapping to Intel Phys capabilities
+#define FAPI_MAX_DMRS_PORTS MAX_DL_PER_UE_DMRS_PORT_NUM
+// FAPI Supports MAX 12; Mapping to Intel Phys capabilities
+#define FAPI_MAX_PTRS_PORTS MAX_DL_PER_UE_PTRS_PORT_NUM
// FAPI States
/**
FAPI_STATE_RUNNING
} fapi_states_t;
-// Information of optional and mandatory status for a TLV
typedef enum {
- FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,
- FAPI_IDLE_STATE_ONLY_MANDATORY,
- FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,
- FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,
- FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,
- FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL
-} fapiTlvStatus_t;
+ FAPI_PUCCH_FORMAT_TYPE_0 = 0,
+ FAPI_PUCCH_FORMAT_TYPE_1,
+ FAPI_PUCCH_FORMAT_TYPE_2,
+ FAPI_PUCCH_FORMAT_TYPE_3,
+ FAPI_PUCCH_FORMAT_TYPE_4,
+} nr5g_fapi_uci_format_t;
-// PARAMETERS INFORMATION
-#define FAPI_NORMAL_CYCLIC_PREFIX_MASK 0x01
-#define FAPI_EXTENDED_CYCLIC_PREFIX_MASK 0x02
+typedef struct {
+ uint8_t group_id;
+ uint16_t initial_cyclic_shift;
+ uint8_t nr_of_symbols;
+ uint8_t start_symbol_index;
+ uint8_t time_domain_occ_idx;
+} nr5g_fapi_pucch_resources_t;
-// In 5G FAPI FrameDuplexType as part of Cell Configuration
-typedef enum _fapi_duplex_ {
- FAPI_TDD = 0,
- FAPI_FDD
-} fapi_duplex_e;
-// Subcarrier spacing information
-#define FAPI_15KHZ_MASK 0x01
-#define FAPI_30KHZ_MASK 0x02
-#define FAPI_60KHZ_MASK 0x04
-#define FAPI_120KHZ_MASK 0x08
+typedef enum {
+ MEM_STAT_CONFIG_REQ = 0,
+ MEM_STAT_START_REQ,
+ MEM_STAT_STOP_REQ,
+ MEM_STAT_SHUTDOWN_REQ,
+ MEM_STAT_DL_CONFIG_REQ,
+ MEM_STAT_UL_CONFIG_REQ,
+ MEM_STAT_UL_DCI_REQ,
+ MEM_STAT_TX_REQ,
+ MEM_STAT_DL_IQ_SAMPLES,
+ MEM_STAT_UL_IQ_SAMPLES,
+ MEM_STAT_DEFAULT,
+} _mem_stats_for_dl;
-// Bandwitdth information
-#define FAPI_5MHZ_BW_MASK 0x0001
-#define FAPI_10MHZ_BW_MASK 0x0002
-#define FAPI_15MHZ_BW_MASK 0x0004
-#define FAPI_20MHZ_BW_MASK 0x0010
-#define FAPI_40MHZ_BW_MASK 0x0020
-#define FAPI_50MHZ_BW_MASK 0x0040
-#define FAPI_60MHZ_BW_MASK 0x0080
-#define FAPI_70MHZ_BW_MASK 0x0100
-#define FAPI_80MHZ_BW_MASK 0x0200
-#define FAPI_90MHZ_BW_MASK 0x0400
-#define FAPI_100MHZ_BW_MASK 0x0800
-#define FAPI_200MHZ_BW_MASK 0x1000
-#define FAPI_400MHZ_BW_MASK 0x2000
+//Unused definitions
+#define RELEASE_15 0x0001
+
+#define FAPI_NORMAL_CYCLIC_PREFIX_MASK 0x01
+#define FAPI_EXTENDED_CYCLIC_PREFIX_MASK 0x02
// PDCCH Information
#define FAPI_CCE_MAPPING_INTERLEAVED_MASK 0x01
#define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK 0xff
#define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH 2
-#define FAPI_MAX_PHY_INSTANCES 12
+// Subcarrier spacing information
+#define FAPI_15KHZ_MASK 0x01
+#define FAPI_30KHZ_MASK 0x02
+#define FAPI_60KHZ_MASK 0x04
+#define FAPI_120KHZ_MASK 0x08
-typedef enum modulationOrder {
- FAPI_QPSK = 0,
- FAPI_16QAM,
- FAPI_64QAM,
- FAPI_256QAM
-} fapiModOrder_t;
+// Bandwitdth information
+#define FAPI_5MHZ_BW_MASK 0x0001
+#define FAPI_10MHZ_BW_MASK 0x0002
+#define FAPI_15MHZ_BW_MASK 0x0004
+#define FAPI_20MHZ_BW_MASK 0x0010
+#define FAPI_40MHZ_BW_MASK 0x0020
+#define FAPI_50MHZ_BW_MASK 0x0040
+#define FAPI_60MHZ_BW_MASK 0x0080
+#define FAPI_70MHZ_BW_MASK 0x0100
+#define FAPI_80MHZ_BW_MASK 0x0200
+#define FAPI_90MHZ_BW_MASK 0x0400
+#define FAPI_100MHZ_BW_MASK 0x0800
+#define FAPI_200MHZ_BW_MASK 0x1000
+#define FAPI_400MHZ_BW_MASK 0x2000
#define FAPI_MAX_MUMIMO_USERS_MASK 0xff
//Upper Limit for PDSCHS TBs per Slot
#define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK 0xff
-typedef enum aggregationFactor {
- FAPI_PUSCH_AGG_FACTOR_1 = 0,
- FAPI_PUSCH_AGG_FACTOR_2,
- FAPI_PUSCH_AGG_FACTOR_4,
- FAPI_PUSCH_AGG_FACTOR_8
-} fapiPuschAggFactor_t;
-
// PRACH Parameters
#define FAPI_PRACH_LF_FORMAT_0_MASK 0x01
#define FAPI_PRACH_LF_FORMAT_1_MASK 0x02
#define FAPI_PRACH_SF_FORMAT_C0_MASK 0x80
#define FAPI_PRACH_SF_FORMAT_C2_MASK 0x100
-typedef enum prachMaxOccasionsPerSlot {
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_1 = 0,
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_2,
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_4,
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_8
-} fapi_prachMaxFdOccasionsPerSlot_t;
-
// Measurement Parameters
#define FAPI_RSSI_REPORT_IN_DBM_MASK 0x01
#define FAPI_RSSI_REPORT_IN_DBFS_MASK 0x02
-// CONFIGURATION INFORMATION CARRIER CONFIGURATION BANDWIDTH
-#define FAPI_BANDWIDTH_5_MHZ 5
-#define FAPI_BANDWIDTH_10_MHZ 10
-#define FAPI_BANDWIDTH_15_MHZ 15
-#define FAPI_BANDWIDTH_20_MHZ 20
-#define FAPI_BANDWIDTH_25_MHZ 25
-#define FAPI_BANDWIDTH_30_MHZ 30
-#define FAPI_BANDWIDTH_40_MHZ 40
-#define FAPI_BANDWIDTH_50_MHZ 50
-#define FAPI_BANDWIDTH_60_MHZ 60
-#define FAPI_BANDWIDTH_70_MHZ 70
-#define FAPI_BANDWIDTH_80_MHZ 80
-#define FAPI_BANDWIDTH_90_MHZ 90
-#define FAPI_BANDWIDTH_100_MHZ 100
-#define FAPI_BANDWIDTH_200_MHZ 200
-#define FAPI_BANDWIDTH_400_MHZ 400
-
-#define FAPI_SUBCARRIER_SPACING_15 0
-#define FAPI_SUBCARRIER_SPACING_30 1
-#define FAPI_SUBCARRIER_SPACING_60 2
-#define FAPI_SUBCARRIER_SPACING_120 3
-
-#define FAPI_FFT_SIZE_512 512
-#define FAPI_FFT_SIZE_1024 1024
-#define FAPI_FFT_SIZE_2048 2048
-#define FAPI_FFT_SIZE_4096 4096
// Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1
// Lower Bound KHz
#define FAPI_MIN_FREQUENCY_PT_A 450000
#define FAPI_PRACHZEROCORRCONF_MASK 0x0f
// Number of Unused Root Sequences Mask
#define FAPI_UNUSEDROOTSEQUENCES_MASK 0x0f
-// SSBPERRACH
-typedef enum {
- FAPI_SSB_PER_RACH_1_OVER_8 = 0,
- FAPI_SSB_PER_RACH_1_OVER_4,
- FAPI_SSB_PER_RACH_1_OVER_2,
- FAPI_SSB_PER_RACH_1,
- FAPI_SSB_PER_RACH_2,
- FAPI_SSB_PER_RACH_4,
- FAPI_SSB_PER_RACH_8,
- FAPI_SSB_PER_RACH_16
-} fapiSsbPerRach_t;
-
-typedef enum {
- FAPI_PUCCH_FORMAT_TYPE_0 = 0,
- FAPI_PUCCH_FORMAT_TYPE_1,
- FAPI_PUCCH_FORMAT_TYPE_2,
- FAPI_PUCCH_FORMAT_TYPE_3,
- FAPI_PUCCH_FORMAT_TYPE_4,
-} nr5g_fapi_uci_format_t;
-
-typedef struct {
- uint8_t group_id;
- uint16_t initial_cyclic_shift;
- uint8_t nr_of_symbols;
- uint8_t start_symbol_index;
- uint8_t time_domain_occ_idx;
-} nr5g_fapi_pucch_resources_t;
-// SSB Table
+// SSB
+#define FAPI_SSB_SUB6_THRESHOLD 6000000
// Ssb Offset Point A max
#define FAPI_SSB_OFFSET_POINTA_MAX 2199
// betaPSS i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1
#define FAPI_RSSI_REPORTED_IN_DBFS 2
// Error Indication
#define FAPI_SFN_MASK 0x03ff
-// Status and Error Codes for either .response or ERROR.indication
-// Updated per 5g FAPI Table 3-31
-typedef enum {
- MSG_OK = 0,
- MSG_INVALID_STATE,
- MSG_INVALID_CONFIG,
- SFN_OUT_OF_SYNC,
- MSG_SLOT_ERR,
- MSG_BCH_MISSING,
- MSG_INVALID_SFN,
- MSG_UL_DCI_ERR,
- MSG_TX_ERR
-} fapiStatusAndErrorCodes_e;
-
- // Digital Beam Table (DBT) PDU
- // Number of Digital Beam Mask
- // Number of TX RUS Mask
- // Beam Index Mask
- // Digital Beam Index weights Real and Imaginary Mask
-
- // Precoding Matrix (PM) PDU
- // Precoding Matrix ID Mask
- // Number of Layers Mask
- // Number of Antenna Ports at the precoder output Mask
- // Precoder Weights Real and Imaginary Mask
-#define FAPI_U16_MASK 0xffff
-
// Slot Indication
-
#define FAPI_SLOT_MAX_VALUE 159
- // DL_TTI.request
- // nPDUS mask
- // nGroup mask
+#define FAPI_U16_MASK 0xffff
#define FAPI_U8_MASK 0xff
-
-typedef enum {
- FAPI_DL_TTI_REQ_PDCCH_PDU_TYPE = 0,
- FAPI_DL_TTI_REQ_PDSCH_PDU_TYPE,
- FAPI_DL_TTI_REQ_CSI_RS_PDU_TYPE,
- FAPI_DL_TTI_REQ_SSB_PDU_TYPE
-} fapiDlTtiReqPduType_e;
-
-// nUe
// Define Maximum number of Ues per Group
#define FAPI_MAX_NUMBER_OF_UES_PER_GROUP 12
#define FAPI_MCS_TABLE_QAM_64_LOW_SE 2
#define FAPI_REDUNDANCY_INDEX_MASK 0x03
-#define FAPI_MAX_DL_LAYERS 8
-#define FAPI_MAX_UL_LAYERS 4
-//#define FAPI_MAX_DMRS_PORTS 12
-#define FAPI_MAX_DMRS_PORTS MAX_DL_PER_UE_DMRS_PORT_NUM
-#define FAPI_MAX_PTRS_PORTS 12
-
-#define FAPI_TRANSMISSION_SCHEME_1 1
#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A 0
#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC 1
#define FAPI_PTRS_FREQ_DENSITY_4 1
#define FAPI_PTRS_RE_OFFSET_MASK 0x03
#define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK 0x03
+
// PDSCH Power Control Offset
#define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB 0
#define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB 1
#define FAPI_CSI_PARTX_CRC_NOT_PRESENT 2
#define FAPI_CSI_PARTX_PAYLOAD_MAX 214
+// CRC
+enum {
+ FAPI_CRC_CORRECT = 0,
+ FAPI_CRC_ERROR = 1
+};
+
+// Release/Features support
typedef enum {
- MEM_STAT_CONFIG_REQ = 0,
- MEM_STAT_START_REQ,
- MEM_STAT_STOP_REQ,
- MEM_STAT_SHUTDOWN_REQ,
- MEM_STAT_DL_CONFIG_REQ,
- MEM_STAT_UL_CONFIG_REQ,
- MEM_STAT_UL_DCI_REQ,
- MEM_STAT_TX_REQ,
- MEM_STAT_DL_IQ_SAMPLES,
- MEM_STAT_UL_IQ_SAMPLES,
- MEM_STAT_DEFAULT,
-} _mem_stats_for_dl;
+ FAPI_NOT_SUPPORTED = 0,
+ FAPI_SUPPORTED,
+} fapiSupport_t;
+
+// Information of optional and mandatory status for a TLV
+typedef enum {
+ FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,
+ FAPI_IDLE_STATE_ONLY_MANDATORY,
+ FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,
+ FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,
+ FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,
+ FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL
+} fapiTlvStatus_t;
+
+typedef enum modulationOrder {
+ FAPI_QPSK = 0,
+ FAPI_16QAM,
+ FAPI_64QAM,
+ FAPI_256QAM
+} fapiModOrder_t;
+
+// SSBPERRACH
+typedef enum {
+ FAPI_SSB_PER_RACH_1_OVER_8 = 0,
+ FAPI_SSB_PER_RACH_1_OVER_4,
+ FAPI_SSB_PER_RACH_1_OVER_2,
+ FAPI_SSB_PER_RACH_1,
+ FAPI_SSB_PER_RACH_2,
+ FAPI_SSB_PER_RACH_4,
+ FAPI_SSB_PER_RACH_8,
+ FAPI_SSB_PER_RACH_16
+} fapiSsbPerRach_t;
#endif //_NR5G_FAPI_INTELNAL_H_
#define NR5G_FAPI_STATS_FNAME "FapiStats.txt"
typedef enum _nr5g_fapi_log_types_t {
- INFO_LOG = 0,
+ NONE_LOG = 0,
+ INFO_LOG, // default
DEBUG_LOG,
ERROR_LOG,
TRACE_LOG,
- HEXDUMP_LOG,
- NONE_LOG // default
} nr5g_fapi_log_types_t;
extern nr5g_fapi_log_types_t nr5g_fapi_log_level_g;
// NR5G_FAPI__LOG utility Macro for logging.
#define NR5G_FAPI_LOG(TYPE, MSG) do { \
if(TYPE == ERROR_LOG) { \
- printf("[NR5G_FAPI][%s]", get_logger_type_str(TYPE)); \
+ printf("[%s]", get_logger_type_str(TYPE)); \
printf MSG ;\
printf("\n");\
} \
else \
{ \
- if(nr5g_fapi_log_level_g == NONE_LOG) { \
- } \
- else if(TYPE <= nr5g_fapi_log_level_g) { \
- printf("[NR5G_FAPI][%s]", get_logger_type_str(TYPE)); \
- printf MSG ;\
- printf("\n");\
- } \
- else if(TYPE <= nr5g_fapi_log_level_g && TYPE == DEBUG_LOG) { \
- printf("[NR5G_FAPI][%s]", get_logger_type_str(TYPE)); \
+ if((nr5g_fapi_log_level_g > NONE_LOG) && (TYPE <= nr5g_fapi_log_level_g)) { \
+ printf("[%s]", get_logger_type_str(TYPE)); \
printf MSG ;\
printf("\n");\
} \
- else if(TYPE == nr5g_fapi_log_level_g && TYPE == TRACE_LOG) { \
- printf("[NR5G_FAPI][%s]", get_logger_type_str(TYPE)); \
- printf MSG ;\
- printf("\n");\
- } \
- else {}\
} \
} while(0)
+typedef struct _nr5g_fapi_performance_statistic {
+ uint64_t min_cycle;
+ uint64_t max_cycle;
+ uint64_t avg_cycle;
+ uint32_t count;
+} nr5g_fapi_performance_statistic_t;
+
+extern nr5g_fapi_log_types_t nr5g_fapi_log_level_g;
+extern nr5g_fapi_performance_statistic_t fapi_statis_info_wls_get_dl;
+extern nr5g_fapi_performance_statistic_t fapi_statis_info_parse_dl;
+extern nr5g_fapi_performance_statistic_t fapi_statis_info_wls_send_dl;
+extern nr5g_fapi_performance_statistic_t fapi_statis_info_wls_get_ul;
+extern nr5g_fapi_performance_statistic_t fapi_statis_info_parse_ul;
+extern nr5g_fapi_performance_statistic_t fapi_statis_info_wls_send_ul;
+extern uint64_t tick_total_wls_get_per_tti_dl;
+extern uint64_t tick_total_parse_per_tti_dl;
+extern uint64_t tick_total_wls_send_per_tti_dl;
+extern uint64_t tick_total_wls_get_per_tti_ul;
+extern uint64_t tick_total_parse_per_tti_ul;
+extern uint64_t tick_total_wls_send_per_tti_ul;
+extern uint16_t g_statistic_start_flag;
+
+uint16_t nr5g_fapi_statistic_info_set(
+ nr5g_fapi_performance_statistic_t * fapi_statis_info,
+ uint64_t * tick_val_in,
+ uint16_t start_flag);
+
+uint16_t nr5g_fapi_statistic_info_init(
+ );
+
+uint16_t nr5g_fapi_statistic_info_print(
+ );
+uint16_t nr5g_fapi_statistic_info_set_all(
+ );
+
#endif // NR5G_FAPI_LOG_H_
static void nr5g_fapi_cmd_exit(
p_nr5g_fapi_phy_ctx_t p_phy_ctx)
{
- p_phy_ctx->process_exit = 0;
+ p_phy_ctx->process_exit = 1;
printf("Exitting App...\n");
exit(0);
}
pclose(fp);
return NULL;
}
+ pclose(fp);
num_cpus = atoi(max_core);
entry = rte_cfgfile_get_entry(cfg_file, "MAC2PHY_WORKER", "core_id");
if (entry) {
}
entry =
- rte_cfgfile_get_entry(cfg_file, "MAC2PHY_WORKER", "thread_sched_policy");
+ rte_cfgfile_get_entry(cfg_file, "MAC2PHY_WORKER",
+ "thread_sched_policy");
if (entry) {
cfg->mac2phy_worker.thread_sched_policy = (uint8_t) atoi(entry);
if (cfg->mac2phy_worker.thread_sched_policy != SCHED_FIFO &&
}
entry =
- rte_cfgfile_get_entry(cfg_file, "PHY2MAC_WORKER", "thread_sched_policy");
+ rte_cfgfile_get_entry(cfg_file, "PHY2MAC_WORKER",
+ "thread_sched_policy");
if (entry) {
cfg->phy2mac_worker.thread_sched_policy = (uint8_t) atoi(entry);
if (cfg->phy2mac_worker.thread_sched_policy != SCHED_FIFO &&
cfg->logger.level = ERROR_LOG;
else if (!strcmp(entry, "trace"))
cfg->logger.level = TRACE_LOG;
- else if (!strcmp(entry, "hexdump"))
- cfg->logger.level = HEXDUMP_LOG;
else
cfg->logger.level = NONE_LOG;
}
- pclose(fp);
+ entry = rte_cfgfile_get_entry(cfg_file, "DPDK", "dpdk_iova_mode");
+ if (entry) {
+ cfg->dpdk.iova_mode = (uint8_t) atoi(entry);
+ if (cfg->dpdk.iova_mode >= DPDK_IOVA_MAX_MODE) {
+ printf("The mode is out of range: %d", cfg->dpdk.iova_mode);
+ exit(-1);
+ }
+ }
return cfg;
}
**/
#include "nr5g_fapi_std.h"
#include "nr5g_fapi_log.h"
+#include "nr5g_fapi_memory.h"
nr5g_fapi_log_types_t nr5g_fapi_log_level_g;
+nr5g_fapi_performance_statistic_t fapi_statis_info_wls_get_dl;
+nr5g_fapi_performance_statistic_t fapi_statis_info_parse_dl;
+nr5g_fapi_performance_statistic_t fapi_statis_info_wls_send_dl;
+nr5g_fapi_performance_statistic_t fapi_statis_info_wls_get_ul;
+nr5g_fapi_performance_statistic_t fapi_statis_info_parse_ul;
+nr5g_fapi_performance_statistic_t fapi_statis_info_wls_send_ul;
+uint64_t tick_total_wls_get_per_tti_dl = 0;
+uint64_t tick_total_parse_per_tti_dl = 0;
+uint64_t tick_total_wls_send_per_tti_dl = 0;
+uint64_t tick_total_wls_get_per_tti_ul = 0;
+uint64_t tick_total_parse_per_tti_ul = 0;
+uint64_t tick_total_wls_send_per_tti_ul = 0;
+uint16_t g_statistic_start_flag = 0;
//------------------------------------------------------------------------------
/** @ingroup group_lte_source_phy_api
case TRACE_LOG:
return ("TRACE_LOG");
- case HEXDUMP_LOG:
- return ("HEXDUMP_LOG");
-
default:
printf("Log Error Type\n");
return ("");
{
return nr5g_fapi_log_level_g;
}
+#ifdef STATISTIC_MODE
+uint16_t nr5g_fapi_statistic_info_set(
+ nr5g_fapi_performance_statistic_t * fapi_statis_info,
+ uint64_t * tick_val_in,
+ uint16_t start_flag)
+{
+
+ uint64_t tick_val = *tick_val_in;
+ uint64_t cnt = fapi_statis_info->count;
+
+ if (start_flag) {
+ if (cnt) {
+ if (tick_val < fapi_statis_info->min_cycle) {
+ fapi_statis_info->min_cycle = tick_val;
+ } else if (tick_val > fapi_statis_info->max_cycle) {
+ fapi_statis_info->max_cycle = tick_val;
+ }
+
+ fapi_statis_info->avg_cycle += tick_val;
+ fapi_statis_info->count++;
+
+ } else {
+ fapi_statis_info->avg_cycle = tick_val;
+ fapi_statis_info->min_cycle = tick_val;
+ fapi_statis_info->max_cycle = tick_val;
+ fapi_statis_info->count++;
+ }
+ }
+ *tick_val_in = 0;
+ return 0;
+}
+
+uint16_t nr5g_fapi_statistic_info_set_all(
+ )
+{
+
+ nr5g_fapi_statistic_info_set(&fapi_statis_info_wls_get_dl,
+ &tick_total_wls_get_per_tti_dl, g_statistic_start_flag);
+ nr5g_fapi_statistic_info_set(&fapi_statis_info_parse_dl,
+ &tick_total_parse_per_tti_dl, g_statistic_start_flag);
+ nr5g_fapi_statistic_info_set(&fapi_statis_info_wls_send_dl,
+ &tick_total_wls_send_per_tti_dl, g_statistic_start_flag);
+ nr5g_fapi_statistic_info_set(&fapi_statis_info_wls_get_ul,
+ &tick_total_wls_get_per_tti_ul, g_statistic_start_flag);
+ nr5g_fapi_statistic_info_set(&fapi_statis_info_parse_ul,
+ &tick_total_parse_per_tti_ul, g_statistic_start_flag);
+ nr5g_fapi_statistic_info_set(&fapi_statis_info_wls_send_ul,
+ &tick_total_wls_send_per_tti_ul, g_statistic_start_flag);
+
+ return 0;
+}
+
+uint16_t nr5g_fapi_statistic_info_init(
+ )
+{
+
+ NR5G_FAPI_MEMSET(&fapi_statis_info_wls_get_dl,
+ sizeof(nr5g_fapi_performance_statistic_t), 0,
+ sizeof(nr5g_fapi_performance_statistic_t));
+ NR5G_FAPI_MEMSET(&fapi_statis_info_parse_dl,
+ sizeof(nr5g_fapi_performance_statistic_t), 0,
+ sizeof(nr5g_fapi_performance_statistic_t));
+ NR5G_FAPI_MEMSET(&fapi_statis_info_wls_send_dl,
+ sizeof(nr5g_fapi_performance_statistic_t), 0,
+ sizeof(nr5g_fapi_performance_statistic_t));
+ NR5G_FAPI_MEMSET(&fapi_statis_info_wls_get_ul,
+ sizeof(nr5g_fapi_performance_statistic_t), 0,
+ sizeof(nr5g_fapi_performance_statistic_t));
+ NR5G_FAPI_MEMSET(&fapi_statis_info_parse_ul,
+ sizeof(nr5g_fapi_performance_statistic_t), 0,
+ sizeof(nr5g_fapi_performance_statistic_t));
+ NR5G_FAPI_MEMSET(&fapi_statis_info_wls_send_ul,
+ sizeof(nr5g_fapi_performance_statistic_t), 0,
+ sizeof(nr5g_fapi_performance_statistic_t));
+ return 0;
+
+}
+
+uint16_t nr5g_fapi_statistic_info_print(
+ )
+{
+
+ printf("\n");
+ printf
+ ("dl wls get Kcycle (count, min, max, avg) : %d %9.2f %9.2f %9.2f \n",
+ fapi_statis_info_wls_get_dl.count,
+ fapi_statis_info_wls_get_dl.min_cycle / 1000.,
+ fapi_statis_info_wls_get_dl.max_cycle / 1000.,
+ fapi_statis_info_wls_get_dl.avg_cycle /
+ fapi_statis_info_wls_get_dl.count / 1000.);
+ printf
+ ("dl FAPI parse Kcycle (count, min, max, avg): %d %9.2f %9.2f %9.2f \n",
+ fapi_statis_info_parse_dl.count,
+ fapi_statis_info_parse_dl.min_cycle / 1000.,
+ fapi_statis_info_parse_dl.max_cycle / 1000.,
+ fapi_statis_info_parse_dl.avg_cycle / fapi_statis_info_parse_dl.count /
+ 1000.);
+ printf
+ ("dl wls send Kcycle(count, min, max, avg) : %d %9.2f %9.2f %9.2f \n",
+ fapi_statis_info_wls_send_dl.count,
+ fapi_statis_info_wls_send_dl.min_cycle / 1000.,
+ fapi_statis_info_wls_send_dl.max_cycle / 1000.,
+ fapi_statis_info_wls_send_dl.avg_cycle /
+ fapi_statis_info_wls_send_dl.count / 1000.);
+
+ printf
+ ("ul wls get Kcycle(count, min, max, avg) : %d %9.2f %9.2f %9.2f \n",
+ fapi_statis_info_wls_get_ul.count,
+ fapi_statis_info_wls_get_ul.min_cycle / 1000.,
+ fapi_statis_info_wls_get_ul.max_cycle / 1000.,
+ fapi_statis_info_wls_get_ul.avg_cycle /
+ fapi_statis_info_wls_get_ul.count / 1000.);
+ printf
+ ("ul FAPI parse Kcycle(count, min, max, avg) : %d %9.2f %9.2f %9.2f \n",
+ fapi_statis_info_parse_ul.count,
+ fapi_statis_info_parse_ul.min_cycle / 1000.,
+ fapi_statis_info_parse_ul.max_cycle / 1000.,
+ fapi_statis_info_parse_ul.avg_cycle / fapi_statis_info_parse_ul.count /
+ 1000.);
+ printf
+ ("ul wls send Kcycle(count, min, max, avg) : %d %9.2f %9.2f %9.2f \n",
+ fapi_statis_info_wls_send_ul.count,
+ fapi_statis_info_wls_send_ul.min_cycle / 1000.,
+ fapi_statis_info_wls_send_ul.max_cycle / 1000.,
+ fapi_statis_info_wls_send_ul.avg_cycle /
+ fapi_statis_info_wls_send_ul.count / 1000.);
+ return 0;
+
+}
+#else
+uint16_t nr5g_fapi_statistic_info_set(
+ nr5g_fapi_performance_statistic_t * fapi_statis_info,
+ uint64_t * tick_val_in,
+ uint16_t start_flag)
+{
+
+ fapi_statis_info->avg_cycle = 0;
+ *tick_val_in = 0;
+ if(start_flag) *tick_val_in = 0;
+ return 0;
+}
+
+uint16_t nr5g_fapi_statistic_info_set_all(
+ )
+{
+
+
+ return 0;
+}
+
+uint16_t nr5g_fapi_statistic_info_init(
+ )
+{
+
+
+ return 0;
+
+}
+
+uint16_t nr5g_fapi_statistic_info_print(
+ )
+{
+
+ return 0;
+
+}
+#endif
FILE *fp = NULL;
enum { FILE_MODE = 0666 };
nr5g_fapi_stats_t *p_stats;
- char *fname = NULL, stats_fname[NR5G_FAPI_STATS_FNAME_LEN];
+ char *fname = NULL;
#ifdef DEBUG_MODE
+ char stats_fname[NR5G_FAPI_STATS_FNAME_LEN];
uint32_t test_num;
uint32_t test_type;
char test_type_str[][8] = { {"DL"}, {"UL"}, {"FD"} };
}
close(fd);
}
-
--- /dev/null
+###############################################################################
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+################################################################################
+#
+# Usage: source inden_options
+#
+
+find . -name '*.[ch]' | xargs indent -nbad -bap -nbc -nbbo -hnl -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli4 -d0 -di1 -nfc1 -i4 -nip -l80 -nlp -npcs -nprs -npsl -sai -saf -saw -ncs -nsc -sob -nfca -cp33 -ss -ts4 -il1 -nut -bfda
+
+#indent source/api/fapi2mac/nr5g_fapi_fapi2mac_api.c -nbad -bap -nbc -nbbo -hnl -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli4 -d0 -di1 -nfc1 -i4 -nip -l80 -nlp -npcs -nprs -npsl -sai -saf -saw -ncs -nsc -sob -nfca -cp33 -ss -ts4 -il1 -nut -bfda
+
+
+
+#indent nr5g_fapi.c -bad -bap -bli0 -br -ce -ci4 -i4 -nbbo -ncdb -bfda -nhnl -nlp -nsc -nip -npcs -nut -kr
-Wall \
-Wimplicit-function-declaration \
-g -O3 -wd1786
-CC_FLAGS += -fstack-protector-strong -z,now, -z,relro -z noexecstack -Wformat -Wformat-security -Werror=format-security -fno-strict-overflow -fwrapv
CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -no-prec-div \
-no-prec-div -fp-model fast=2\
XRAN_LIB_DIR=$(XRAN_DIR)/lib/build
LD_FLAGS += -L$(XRAN_LIB_DIR) -lxran
-RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,-lrte_flow_classify -Wl,--whole-archive -Wl,-lrte_pipeline -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_table -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_port -Wl,--no-whole-archive -Wl,-lrte_pdump -Wl,-lrte_distributor -Wl,-lrte_ip_frag -Wl,-lrte_meter -Wl,-lrte_lpm -Wl,--whole-archive -Wl,-lrte_acl -Wl,--no-whole-archive -Wl,-lrte_jobstats -Wl,-lrte_metrics -Wl,-lrte_bitratestats -Wl,-lrte_latencystats -Wl,-lrte_power -Wl,-lrte_efd -Wl,-lrte_bpf -Wl,--whole-archive -Wl,-lrte_cfgfile -Wl,-lrte_gro -Wl,-lrte_gso -Wl,-lrte_hash -Wl,-lrte_member -Wl,-lrte_vhost -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_net -Wl,-lrte_ethdev -Wl,-lrte_bbdev -Wl,-lrte_cryptodev -Wl,-lrte_security -Wl,-lrte_compressdev -Wl,-lrte_eventdev -Wl,-lrte_rawdev -Wl,-lrte_timer -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_pci -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_reorder -Wl,-lrte_sched -Wl,-lrte_kni -Wl,-lrte_common_octeontx -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_bus_dpaa -Wl,-lrte_bus_fslmc -Wl,-lrte_mempool_bucket -Wl,-lrte_mempool_stack -Wl,-lrte_mempool_dpaa -Wl,-lrte_mempool_dpaa2 -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_ark -Wl,-lrte_pmd_avf -Wl,-lrte_pmd_avp -Wl,-lrte_pmd_axgbe -Wl,-lrte_pmd_bnxt -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_dpaa -Wl,-lrte_pmd_dpaa2 -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ena -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_failsafe -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_kni -Wl,-lrte_pmd_lio -Wl,-lrte_pmd_nfp -Wl,-lrte_pmd_null -Wl,-lrte_pmd_qede -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_softnic -Wl,-lrte_pmd_tap -Wl,-lrte_pmd_thunderx_nicvf -Wl,-lrte_pmd_vdev_netvsc -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_vhost -Wl,-lrte_pmd_ifc -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_bus_vmbus -Wl,-lrte_pmd_netvsc -Wl,-lrte_pmd_bbdev_null -Wl,-lrte_pmd_null_crypto -Wl,-lrte_pmd_crypto_scheduler -Wl,-lrte_pmd_dpaa2_sec -Wl,-lrte_pmd_dpaa_sec -Wl,-lrte_pmd_virtio_crypto -Wl,-lrte_pmd_octeontx_zip -Wl,-lrte_pmd_qat -Wl,-lrte_pmd_skeleton_event -Wl,-lrte_pmd_sw_event -Wl,-lrte_pmd_octeontx_ssovf -Wl,-lrte_pmd_dpaa_event -Wl,-lrte_pmd_dpaa2_event -Wl,-lrte_mempool_octeontx -Wl,-lrte_pmd_octeontx -Wl,-lrte_pmd_opdl_event -Wl,-lrte_pmd_skeleton_rawdev -Wl,-lrte_pmd_dpaa2_cmdif -Wl,-lrte_pmd_dpaa2_qdma -Wl,-lrte_bus_ifpga -Wl,-lrte_pmd_ifpga_rawdev -Wl,--no-whole-archive -Wl,-lrt -Wl,-lm -Wl,-lnuma -Wl,-ldl -Wl,
+RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,-lrte_flow_classify -Wl,--whole-archive -Wl,-lrte_pipeline -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_table -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_port -Wl,--no-whole-archive -Wl,-lrte_pdump -Wl,-lrte_distributor -Wl,-lrte_ip_frag -Wl,-lrte_meter -Wl,-lrte_lpm -Wl,--whole-archive -Wl,-lrte_acl -Wl,--no-whole-archive -Wl,-lrte_jobstats -Wl,-lrte_metrics -Wl,-lrte_bitratestats -Wl,-lrte_latencystats -Wl,-lrte_power -Wl,-lrte_efd -Wl,-lrte_bpf -Wl,--whole-archive -Wl,-lrte_cfgfile -Wl,-lrte_gro -Wl,-lrte_gso -Wl,-lrte_hash -Wl,-lrte_member -Wl,-lrte_vhost -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_net -Wl,-lrte_ethdev -Wl,-lrte_bbdev -Wl,-lrte_cryptodev -Wl,-lrte_security -Wl,-lrte_compressdev -Wl,-lrte_eventdev -Wl,-lrte_rawdev -Wl,-lrte_timer -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_pci -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_reorder -Wl,-lrte_sched -Wl,-lrte_kni -Wl,-lrte_common_octeontx -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_bus_dpaa -Wl,-lrte_common_dpaax -Wl,-lrte_stack -Wl,-lrte_bus_fslmc -Wl,-lrte_mempool_bucket -Wl,-lrte_mempool_stack -Wl,-lrte_mempool_dpaa -Wl,-lrte_mempool_dpaa2 -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_ark -Wl,-lrte_pmd_iavf -Wl,-lrte_pmd_avp -Wl,-lrte_pmd_axgbe -Wl,-lrte_pmd_bnxt -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_dpaa -Wl,-lrte_pmd_dpaa2 -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ena -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_failsafe -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_kni -Wl,-lrte_pmd_lio -Wl,-lrte_pmd_nfp -Wl,-lrte_pmd_null -Wl,-lrte_pmd_qede -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_softnic -Wl,-lrte_pmd_tap -Wl,-lrte_pmd_thunderx_nicvf -Wl,-lrte_pmd_vdev_netvsc -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_vhost -Wl,-lrte_pmd_ifc -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_bus_vmbus -Wl,-lrte_pmd_netvsc -Wl,-lrte_pmd_bbdev_null -Wl,-lrte_pmd_null_crypto -Wl,-lrte_pmd_crypto_scheduler -Wl,-lrte_pmd_dpaa2_sec -Wl,-lrte_pmd_dpaa_sec -Wl,-lrte_pmd_virtio_crypto -Wl,-lrte_pmd_octeontx_zip -Wl,-lrte_pmd_qat -Wl,-lrte_pmd_skeleton_event -Wl,-lrte_pmd_sw_event -Wl,-lrte_pmd_octeontx_ssovf -Wl,-lrte_pmd_dpaa_event -Wl,-lrte_pmd_dpaa2_event -Wl,-lrte_mempool_octeontx -Wl,-lrte_pmd_octeontx -Wl,-lrte_pmd_opdl_event -Wl,-lrte_rawdev_skeleton -Wl,-lrte_rawdev_dpaa2_cmdif -Wl,-lrte_rawdev_dpaa2_qdma -Wl,-lrte_bus_ifpga -Wl,--no-whole-archive -Wl,-lrt -Wl,-lm -Wl,-lnuma -Wl,-ldl -Wl,
LD_FLAGS += $(RTE_LIBS)
ifeq ($(MLOG),1)
#*
#*******************************************************************************/
+if [ -z "$RTE_SDK" ]
+then
+ echo "## ERROR: Please make sure environment variable RTE_SDK is set to valid DPDK path."
+ echo " To fix, please do: export RTE_SDK=path_to_dpdk_folder before running this script"
+ exit 1
+fi
-export RTE_SDK=/home/turner/dpdk
-export RTE_TARGET=x86_64-native-linuxapp-icc
+if [ -z "$RTE_TARGET" ]
+then
+ echo "## ERROR: Please make sure environment variable RTE_TARGET is set to valid DPDK path."
+ exit 1
+fi
#
# Unloads igb_uio.ko.
#
remove_vfio_module()
{
- echo "Unloading any existing VFIO module"
- /sbin/lsmod | grep -s vfio > /dev/null
- if [ $? -eq 0 ] ; then
- sudo /sbin/rmmod vfio-pci
- sudo /sbin/rmmod vfio_iommu_type1
- sudo /sbin/rmmod vfio
- fi
+ echo "Unloading any existing VFIO module"
+ /sbin/lsmod | grep -s vfio > /dev/null
+ if [ $? -eq 0 ] ; then
+ sudo /sbin/rmmod vfio-pci
+ sudo /sbin/rmmod vfio_iommu_type1
+ sudo /sbin/rmmod vfio
+ fi
}
#
#
load_vfio_module()
{
- remove_vfio_module
-
- VFIO_PATH="kernel/drivers/vfio/pci/vfio-pci.ko"
-
- echo "Loading VFIO module"
- /sbin/lsmod | grep -s vfio_pci > /dev/null
- if [ $? -ne 0 ] ; then
- if [ -f /lib/modules/$(uname -r)/$VFIO_PATH ] ; then
- sudo /sbin/modprobe vfio-pci
- fi
- fi
-
- # make sure regular users can read /dev/vfio
- echo "chmod /dev/vfio"
- sudo chmod a+x /dev/vfio
- if [ $? -ne 0 ] ; then
- echo "FAIL"
- quit
- fi
- echo "OK"
-
- # check if /dev/vfio/vfio exists - that way we
- # know we either loaded the module, or it was
- # compiled into the kernel
- if [ ! -e /dev/vfio/vfio ] ; then
- echo "## ERROR: VFIO not found!"
- fi
+ remove_vfio_module
+
+
+ echo "Loading VFIO module"
+ /sbin/lsmod | grep -s vfio_pci > /dev/null
+ if [ $? -ne 0 ] ; then
+ sudo /sbin/modprobe -v vfio-pci
+ fi
+
+ # make sure regular users can read /dev/vfio
+ echo "chmod /dev/vfio"
+ sudo chmod a+x /dev/vfio
+ if [ $? -ne 0 ] ; then
+ echo "FAIL"
+ quit
+ fi
+ echo "OK"
+
+ # check if /dev/vfio/vfio exists - that way we
+ # know we either loaded the module, or it was
+ # compiled into the kernel
+ if [ ! -e /dev/vfio/vfio ] ; then
+ echo "## ERROR: VFIO not found!"
+ fi
}
$RTE_SDK/usertools/dpdk-devbind.py --status
if [ ${VM_DETECT} == 'HOST' ]; then
#HOST
- $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:22:02.0
- $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:22:02.1
- $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:22:0a.0
- $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:22:0a.1
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.0
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.1
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.0
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.1
else
#VM
$RTE_SDK/usertools/dpdk-devbind.py --bind=igb_uio 0000:00:04.0
close all;
clear all;
+ % 5MHz 10MHz 15MHz 20 MHz
+nLteNumRbsPerSymF1 = ...
+[
+ % 5MHz 10MHz 15MHz 20 MHz
+ [25, 50, 75, 100] % Numerology 0 (15KHz)
+];
+
% 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
nNumRbsPerSymF1 = ...
[
];
% total number of tests
-tests_total = 6
+tests_total = 12
+tech_all = ... % 0 - NR 1- LTE
+ [
+ 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1
+ ]
+
sub6_all = ...
[
- true, true, true, true, false, true,
+ true, true, true, true, false, true, true, true, true, true, true, true
]
mu_all = ...
[
- 0, 0, 0, 1, 3, 1
+ 0, 0, 0, 1, 3, 1, 0, 0, 0, 0, 0, 0
]
bw_all = ...
[
- 5, 10, 20, 100, 100, 100
+ 5, 10, 20, 100, 100, 100, 20, 10, 5, 20, 10, 5
]
ant_num_all = ...
[
- 4, 4, 4, 4, 4, 8
+ 4, 4, 4, 4, 4, 8, 4, 4, 4, 8, 8, 8
]
bfw_gen_all = ...
[
- false, false, false, false, false, true
+ false, false, false, false, false, true, false, false, false, true, true, true,
]
trx_all = ...
[
- 32, 32, 32, 32, 32, 32
+ 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32
]
path_to_usecase_all = ...
[
"./usecase/mu1_100mhz/";
"./usecase/mu3_100mhz/";
"./usecase/cat_b/mu1_100mhz/";
+ "./usecase/lte_a/mu0_20mhz/";
+ "./usecase/lte_a/mu0_10mhz/";
+ "./usecase/lte_a/mu0_5mhz/";
+ "./usecase/lte_b/mu0_20mhz/";
+ "./usecase/lte_b/mu0_10mhz/";
+ "./usecase/lte_b/mu0_5mhz/";
]
path_to_usecase_all = cellstr(path_to_usecase_all)
nSlots_all = ...
[
- 40,40,40,40,40,10
+ 40,40,40,40,40,10,40,40,40,10,10,10
]
%select mu and bw to generate test files
for test_num =(1:1:tests_total)
test_num
+ isLte=tech_all(test_num) %false
sub6=sub6_all(test_num) %false
mu=mu_all(test_num) % 0,1, or 3
bw=bw_all(test_num) %5,10,20,100 MHz
nSlots=nSlots_all(test_num) % any 40 and 160
- if sub6
- disp('Sub6')
+ if isLte
+ disp('LTE')
if mu < 3
nNumerology = mu+1;
switch (bw)
case {5}
- numRBs = nNumRbsPerSymF1(nNumerology,0+1);
+ numRBs = nLteNumRbsPerSymF1(nNumerology,0+1);
case {10}
- numRBs = nNumRbsPerSymF1(nNumerology,1+1);
+ numRBs = nLteNumRbsPerSymF1(nNumerology,1+1);
case {15}
- numRBs = nNumRbsPerSymF1(nNumerology,2+1);
+ numRBs = nLteNumRbsPerSymF1(nNumerology,2+1);
case {20}
- numRBs = nNumRbsPerSymF1(nNumerology,3+1);
- case {25}
- numRBs = nNumRbsPerSymF1(nNumerology,4+1);
- case {30}
- numRBs = nNumRbsPerSymF1(nNumerology,5+1);
- case {40}
- numRBs = nNumRbsPerSymF1(nNumerology,6+1);
- case {50}
- numRBs = nNumRbsPerSymF1(nNumerology,7+1);
- case {60}
- numRBs = nNumRbsPerSymF1(nNumerology,8+1);
- case {70}
- numRBs = nNumRbsPerSymF1(nNumerology,9+1);
- case {80}
- numRBs = nNumRbsPerSymF1(nNumerology,10+1);
- case {90}
- numRBs = nNumRbsPerSymF1(nNumerology,11+1);
- case {100}
- numRBs = nNumRbsPerSymF1(nNumerology,12+1);
- otherwise
- disp('Unknown BW && mu')
+ numRBs = nLteNumRbsPerSymF1(nNumerology,3+1);
end
end
else
- disp('mmWave')
- if (mu >=2) && (mu <= 3)
- nNumerology = mu;
- switch (bw)
- case {50}
- numRBs = nNumRbsPerSymF2(nNumerology-1,0+1);
- case {100}
- numRBs = nNumRbsPerSymF2(nNumerology-1,1+1);
- case {200}
- numRBs = nNumRbsPerSymF2(nNumerology-1,2+1);
- case {400}
- numRBs = nNumRbsPerSymF2(nNumerology-1,3+1);
- otherwise
- disp('Unknown BW && mu')
+ if sub6
+ disp('Sub6')
+ if mu < 3
+ nNumerology = mu+1;
+ switch (bw)
+ case {5}
+ numRBs = nNumRbsPerSymF1(nNumerology,0+1);
+ case {10}
+ numRBs = nNumRbsPerSymF1(nNumerology,1+1);
+ case {15}
+ numRBs = nNumRbsPerSymF1(nNumerology,2+1);
+ case {20}
+ numRBs = nNumRbsPerSymF1(nNumerology,3+1);
+ case {25}
+ numRBs = nNumRbsPerSymF1(nNumerology,4+1);
+ case {30}
+ numRBs = nNumRbsPerSymF1(nNumerology,5+1);
+ case {40}
+ numRBs = nNumRbsPerSymF1(nNumerology,6+1);
+ case {50}
+ numRBs = nNumRbsPerSymF1(nNumerology,7+1);
+ case {60}
+ numRBs = nNumRbsPerSymF1(nNumerology,8+1);
+ case {70}
+ numRBs = nNumRbsPerSymF1(nNumerology,9+1);
+ case {80}
+ numRBs = nNumRbsPerSymF1(nNumerology,10+1);
+ case {90}
+ numRBs = nNumRbsPerSymF1(nNumerology,11+1);
+ case {100}
+ numRBs = nNumRbsPerSymF1(nNumerology,12+1);
+ otherwise
+ disp('Unknown BW && mu')
+ end
+ end
+ else
+ disp('mmWave')
+ if (mu >=2) && (mu <= 3)
+ nNumerology = mu;
+ switch (bw)
+ case {50}
+ numRBs = nNumRbsPerSymF2(nNumerology-1,0+1);
+ case {100}
+ numRBs = nNumRbsPerSymF2(nNumerology-1,1+1);
+ case {200}
+ numRBs = nNumRbsPerSymF2(nNumerology-1,2+1);
+ case {400}
+ numRBs = nNumRbsPerSymF2(nNumerology-1,3+1);
+ otherwise
+ disp('Unknown BW && mu')
+ end
end
end
end
-
if numRBs ==0
disp('Incorrect Numerology and BW combination.')
return
+++ /dev/null
-#! /bin/bash
-
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-ulimit -c unlimited
-echo 1 > /proc/sys/kernel/core_uses_pid
-
-
-#40G
-#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1
-
-#25G
-../build/sample-app ../usecase/mu0_20mhz/12/config_file_o_du_0.dat 0000:86:02.0 0000:86:02.1
-
-
+++ /dev/null
-#! /bin/bash
-
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-ulimit -c unlimited
-echo 1 > /proc/sys/kernel/core_uses_pid
-
-
-#40G
-#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1
-
-#25G
-../build/sample-app ../usecase/mu0_20mhz/12/config_file_o_ru_0.dat 0000:af:0a.0 0000:af:0a.1
-
-
+++ /dev/null
-#! /bin/bash
-
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-ulimit -c unlimited
-echo 1 > /proc/sys/kernel/core_uses_pid
-
-
-#40G
-#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1
-
-#25G
-../build/sample-app ../usecase/mu0_20mhz/12/config_file_o_du_1.dat 0000:86:02.2 0000:86:02.3
-
+++ /dev/null
-#! /bin/bash
-
-#******************************************************************************
-#
-# Copyright (c) 2019 Intel.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-#******************************************************************************/
-
-ulimit -c unlimited
-echo 1 > /proc/sys/kernel/core_uses_pid
-
-
-#40G
-#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1
-
-#25G
-../build/sample-app ../usecase/mu0_20mhz/12/config_file_o_ru_1.dat 0000:af:0a.2 0000:af:0a.3
-
#40G
-./build/sample-app ./usecase/mu1_100mhz/config_file_o_du.dat 0000:18:02.0 0000:18:02.1
+#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1
#25G
-#./build/sample-app ./usecase/cat_b/mu1_100mhz/config_file_o_du.dat 0000:21:02.0 0000:21:02.1
-#./build/sample-app ./usecase/mu1_100mhz/config_file_o_du.dat 0000:86:02.0 0000:86:02.1
+./build/sample-app -c ./usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat -p 2 0000:21:02.0 0000:21:02.1
+#./build/sample-app ./usecase/mu1_100mhz/config_file_o_du.dat 0000:18:02.0 0000:18:02.1
#
#******************************************************************************/
-
ulimit -c unlimited
echo 1 > /proc/sys/kernel/core_uses_pid
+
#40G
-./build/sample-app ./usecase/mu1_100mhz/config_file_o_ru.dat 0000:18:02.0 0000:18:02.1
+#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1
#25G
-#./build/sample-app ./usecase/mu0_5mhz/config_file_o_ru.dat 0000:22:0a.0 0000:22:0a.1
+
+./build/sample-app -c ./usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat -p 2 0000:21:0a.0 0000:21:0a.1
#./build/sample-app ./usecase/mu1_100mhz/config_file_o_ru.dat 0000:18:0a.0 0000:18:0a.1
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
+// F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
+uint16_t nLteNumRbsPerSymF1[1][4] =
+{
+ // 5MHz 10MHz 15MHz 20 MHz
+ {25, 50, 75, 100}, // Numerology 0 (15KHz)
+};
+
// F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
uint16_t nNumRbsPerSymF1[3][13] =
{
*
**/
//-------------------------------------------------------------------------------------------
-uint16_t app_xran_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
+uint16_t app_xran_get_num_rbs(uint8_t ranTech, uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
{
uint32_t error = 1;
uint16_t numRBs = 0;
- if (nAbsFrePointA <= 6000000)
- {
+ if (ranTech == XRAN_RAN_LTE) {
+ switch(nBandwidth)
+ {
+ case PHY_BW_5_0_MHZ:
+ numRBs = nLteNumRbsPerSymF1[nNumerology][0];
+ error = 0;
+ break;
+ case PHY_BW_10_0_MHZ:
+ numRBs = nLteNumRbsPerSymF1[nNumerology][1];
+ error = 0;
+ break;
+ case PHY_BW_15_0_MHZ:
+ numRBs = nLteNumRbsPerSymF1[nNumerology][2];
+ error = 0;
+ break;
+ case PHY_BW_20_0_MHZ:
+ numRBs = nLteNumRbsPerSymF1[nNumerology][3];
+ error = 0;
+ break;
+ default:
+ error = 1;
+ break;
+ }
+ } else if (nAbsFrePointA <= 6000000) {
// F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
if (nNumerology < 3)
{
if (error)
{
- printf("ERROR: %s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA);
+ printf("ERROR: %s: RAN[%s] nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, (ranTech ? "LTE" : "5G NR"), nNumerology, nBandwidth, nAbsFrePointA);
}
else
{
- printf("%s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA, numRBs);
+ printf("%s: RAN [%s] nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, (ranTech ? "LTE" : "5G NR"), nNumerology, nBandwidth, nAbsFrePointA, numRBs);
}
return numRBs;
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include <rte_common.h>
#include <rte_mbuf.h>
-#define VERSIONX "#DIRTY#"
+#define VERSIONX "oran_bronze_release_v1.1"
#define APP_O_DU 0
#define APP_O_RU 1
void sys_save_buf_to_file(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
int sys_load_file_to_buff(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num);
uint32_t app_xran_get_scs(uint8_t nMu);
-uint16_t app_xran_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA);
+uint16_t app_xran_get_num_rbs(uint8_t ranTech, uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA);
uint32_t app_xran_cal_nrarfcn(uint32_t nCenterFreq);
int32_t app_xran_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType,
uint32_t nTddPeriod, struct xran_slot_config *psSlotConfig);
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include "debug.h"
#include <rte_ethdev.h>
-#include <inttypes.h>
#define MAX_LINE_SIZE 512
/* Configuration file maximum supported line length */
#define KEY_APP_MODE "appMode"
#define KEY_XRAN_MODE "xranMode"
+#define KEY_XRAN_TECH "xranRanTech"
#define KEY_MU_NUMBER "mu"
#define KEY_NDLABSFREPOINTA "nDLAbsFrePointA"
#define KEY_NULABSFREPOINTA "nULAbsFrePointA"
#define KEY_NDLFFTSIZE "nDLFftSize"
#define KEY_NULFFTSIZE "nULFftSize"
+#define KEY_DU_PORT_ID_BITWIDTH "DU_Port_ID_bitwidth"
+#define KEY_BANDSECTOR_ID_BITWIDTH "BandSector_ID_bitwidth"
+#define KEY_CC_ID_BITWIDTH "CC_ID_bitwidth"
+#define KEY_RU_PORT_ID_BITWIDTH "RU_Port_ID_bitwidth"
+
#define KEY_NFRAMEDUPLEXTYPE "nFrameDuplexType"
#define KEY_NTDDPERIOD "nTddPeriod"
#define KEY_MTU_SIZE "MTUSize"
#define KEY_IO_CORE "ioCore"
-#define KEY_SYSTEM_CORE "systemCore"
-#define KEY_PKT_PROC_CORE "pktProcCore"
-#define KEY_PKT_AUX_CORE "pktAuxCore"
-#define KEY_TIMING_CORE "timingCore"
+#define KEY_IO_WORKER "ioWorker"
+#define KEY_IO_SLEEP "ioSleep"
+#define KEY_SYSTEM_CORE "systemCore"
+#define KEY_IOVA_MODE "iovaMode"
#define KEY_INSTANCE_ID "instanceId"
-#define KEY_LLS_CU_MAC "llsCUMac"
+#define KEY_DU_MAC "duMac"
#define KEY_RU_MAC "ruMac"
#define KEY_FILE_NUMSLOTS "numSlots"
#define KEY_IQ_SWAP "iqswap"
#define KEY_HTONS_SWAP "nebyteorderswap"
#define KEY_COMPRESSION "compression"
+#define KEY_COMP_TYPE "compType"
+
#define KEY_BFW_NUM "totalBFWeights"
#define KEY_NPRBELEM_UL "nPrbElemUl"
#define KEY_PRBELEM_UL "PrbElemUl"
+
/**
* Set runtime configuration parameters to their defaults.
*
static int fillConfigStruct(RuntimeConfig *config, const char *key, const char *value)
{
int32_t parse_res = 0;
+ static unsigned int section_idx_dl = 0, section_idx_ul;
if (strcmp(key, KEY_APP_MODE) == 0){
config->appMode = atoi(value);
+ } else if (strcmp(key, KEY_XRAN_TECH) == 0) {
+ config->xranTech = atoi(value);
} else if (strcmp(key, KEY_XRAN_MODE) == 0) {
config->xranCat = atoi(value);
} else if (strcmp(key, KEY_CC_PER_PORT_NUM) == 0) {
} else if (strcmp(key, KEY_NFRAMEDUPLEXTYPE) == 0) {
config->nFrameDuplexType = atoi(value);
printf("nFrameDuplexType: %d\n",config->nFrameDuplexType);
+ } else if (strcmp(key, KEY_DU_PORT_ID_BITWIDTH) == 0) {
+ config->DU_Port_ID_bitwidth = atoi(value);
+ printf("DU_Port_ID_bitwidth: %d\n",config->DU_Port_ID_bitwidth);
+ } else if (strcmp(key, KEY_BANDSECTOR_ID_BITWIDTH) == 0) {
+ config->BandSector_ID_bitwidth = atoi(value);
+ printf("BandSector_ID_bitwidth: %d\n",config->BandSector_ID_bitwidth);
+ } else if (strcmp(key, KEY_CC_ID_BITWIDTH) == 0) {
+ config->CC_ID_bitwidth = atoi(value);
+ printf("CC_ID_bitwidth: %d\n",config->CC_ID_bitwidth);
+ } else if (strcmp(key, KEY_RU_PORT_ID_BITWIDTH) == 0) {
+ config->RU_Port_ID_bitwidth = atoi(value);
+ printf("RU_Port_ID_bitwidth: %d\n",config->RU_Port_ID_bitwidth);
} else if (strcmp(key, KEY_NTDDPERIOD) == 0) {
config->nTddPeriod = atoi(value);
printf("nTddPeriod: %d\n",config->nTddPeriod);
printf("slot_num %d exceeds TddPeriod\n",slot_num);
}
else{
- sscanf(value, "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x",
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[0],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[1],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[2],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[3],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[4],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[5],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[6],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[7],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[8],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[9],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[10],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[11],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[12],
- (uint32_t*)&config->sSlotConfig[slot_num].nSymbolType[13]);
+ sscanf(value, "%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx,%02hhx",
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[0],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[1],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[2],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[3],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[4],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[5],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[6],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[7],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[8],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[9],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[10],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[11],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[12],
+ (uint8_t *)&config->sSlotConfig[slot_num].nSymbolType[13]);
printf("sSlotConfig%d: ",slot_num);
for (i = 0; i< 14; i++){
printf("%d ",config->sSlotConfig[slot_num].nSymbolType[i]);
config->nebyteorderswap = atoi(value);
} else if (strcmp(key, KEY_COMPRESSION) == 0) {
config->compression = atoi(value);
+ } else if (strcmp(key, KEY_COMP_TYPE) == 0) {
+ config->CompHdrType = atoi(value);
} else if (strcmp(key, KEY_MTU_SIZE) == 0) {
config->mtu = atoi(value);
printf("mtu %d\n", config->mtu);
+ } else if (strcmp(key, KEY_IO_SLEEP) == 0) {
+ config->io_sleep = atoi(value);
+ printf("io_sleep %d \n", config->io_sleep);
} else if (strcmp(key, KEY_IO_CORE) == 0) {
config->io_core = atoi(value);
- printf("io_core %d\n", config->io_core);
+ printf("io_core %d [core id]\n", config->io_core);
+ } else if (strcmp(key, KEY_IO_WORKER) == 0) {
+ config->io_worker = strtoll(value, NULL, 0);
+ printf("io_worker 0x%lx [mask]\n", config->io_worker);
} else if (strcmp(key, KEY_SYSTEM_CORE) == 0) {
config->system_core = atoi(value);
- printf("system_core -c %" PRIx64 "\n", config->system_core);
- } else if (strcmp(key, KEY_PKT_PROC_CORE) == 0) {
- config->pkt_proc_core = atoi(value);
- printf("pkt_proc_core -c %" PRIx64 "\n", config->pkt_proc_core);
- } else if (strcmp(key, KEY_PKT_AUX_CORE) == 0) {
- config->pkt_aux_core = atoi(value);
- printf("pkt_aux_core -c %" PRIx64 "\n", config->pkt_aux_core);
- } else if (strcmp(key, KEY_TIMING_CORE) == 0) {
- config->timing_core = atoi(value);
- printf("timing_core -c %" PRIx64 "\n", config->timing_core);
- }else if (strcmp(key, KEY_INSTANCE_ID) == 0) {
+ printf("system core %d [core id]\n", config->system_core);
+ } else if (strcmp(key, KEY_IOVA_MODE) == 0) {
+ config->iova_mode = atoi(value);
+ printf("iova_mode %d\n", config->iova_mode);
+ } else if (strcmp(key, KEY_INSTANCE_ID) == 0) {
config->instance_id = atoi(value);
printf("instance_id %d\n", config->instance_id);
- }else if (strcmp(key, KEY_LLS_CU_MAC) == 0) {
- sscanf(value, "%02x:%02x:%02x:%02x:%02x:%02x", (uint32_t*)&config->o_du_addr.addr_bytes[0],
- (uint32_t*)&config->o_du_addr.addr_bytes[1],
- (uint32_t*)&config->o_du_addr.addr_bytes[2],
- (uint32_t*)&config->o_du_addr.addr_bytes[3],
- (uint32_t*)&config->o_du_addr.addr_bytes[4],
- (uint32_t*)&config->o_du_addr.addr_bytes[5]);
-
- printf("lls-CU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
- config->o_du_addr.addr_bytes[0],
- config->o_du_addr.addr_bytes[1],
- config->o_du_addr.addr_bytes[2],
- config->o_du_addr.addr_bytes[3],
- config->o_du_addr.addr_bytes[4],
- config->o_du_addr.addr_bytes[5]);
-
- } else if (strcmp(key, KEY_RU_MAC) == 0) {
- sscanf(value, "%02x:%02x:%02x:%02x:%02x:%02x", (uint32_t*)&config->o_ru_addr.addr_bytes[0],
- (uint32_t*)&config->o_ru_addr.addr_bytes[1],
- (uint32_t*)&config->o_ru_addr.addr_bytes[2],
- (uint32_t*)&config->o_ru_addr.addr_bytes[3],
- (uint32_t*)&config->o_ru_addr.addr_bytes[4],
- (uint32_t*)&config->o_ru_addr.addr_bytes[5]);
-
- printf("RU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
- config->o_ru_addr.addr_bytes[0],
- config->o_ru_addr.addr_bytes[1],
- config->o_ru_addr.addr_bytes[2],
- config->o_ru_addr.addr_bytes[3],
- config->o_ru_addr.addr_bytes[4],
- config->o_ru_addr.addr_bytes[5]);
+ } else if (strncmp(key, KEY_DU_MAC, strlen(KEY_DU_MAC)) == 0) {
+ unsigned int vf_num = 0;
+ sscanf(key,"duMac%02u",&vf_num);
+ if (vf_num >= XRAN_VF_MAX) {
+ printf("duMac%d exceeds max antenna supported\n",vf_num);
+ } else {
+ printf("duMac%d: %s\n",vf_num, value);
+ sscanf(value, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", (uint8_t*)&config->o_du_addr[vf_num].addr_bytes[0],
+ (uint8_t*)&config->o_du_addr[vf_num].addr_bytes[1],
+ (uint8_t*)&config->o_du_addr[vf_num].addr_bytes[2],
+ (uint8_t*)&config->o_du_addr[vf_num].addr_bytes[3],
+ (uint8_t*)&config->o_du_addr[vf_num].addr_bytes[4],
+ (uint8_t*)&config->o_du_addr[vf_num].addr_bytes[5]);
+
+ printf("[vf %d]O-DU MAC address: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx\n",
+ vf_num,
+ config->o_du_addr[vf_num].addr_bytes[0],
+ config->o_du_addr[vf_num].addr_bytes[1],
+ config->o_du_addr[vf_num].addr_bytes[2],
+ config->o_du_addr[vf_num].addr_bytes[3],
+ config->o_du_addr[vf_num].addr_bytes[4],
+ config->o_du_addr[vf_num].addr_bytes[5]);
+ }
+ } else if (strncmp(key, KEY_RU_MAC, strlen(KEY_RU_MAC)) == 0) {
+ unsigned int vf_num = 0;
+ sscanf(key,"ruMac%02u",&vf_num);
+ if (vf_num >= XRAN_VF_MAX) {
+ printf("ruMac%d exceeds max antenna supported\n",vf_num);
+ } else {
+ printf("ruMac%d: %s\n",vf_num, value);
+
+ sscanf(value, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", (uint8_t*)&config->o_ru_addr[vf_num].addr_bytes[0],
+ (uint8_t*)&config->o_ru_addr[vf_num].addr_bytes[1],
+ (uint8_t*)&config->o_ru_addr[vf_num].addr_bytes[2],
+ (uint8_t*)&config->o_ru_addr[vf_num].addr_bytes[3],
+ (uint8_t*)&config->o_ru_addr[vf_num].addr_bytes[4],
+ (uint8_t*)&config->o_ru_addr[vf_num].addr_bytes[5]);
+
+ printf("[vf %d]RU MAC address: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx\n",
+ vf_num,
+ config->o_ru_addr[vf_num].addr_bytes[0],
+ config->o_ru_addr[vf_num].addr_bytes[1],
+ config->o_ru_addr[vf_num].addr_bytes[2],
+ config->o_ru_addr[vf_num].addr_bytes[3],
+ config->o_ru_addr[vf_num].addr_bytes[4],
+ config->o_ru_addr[vf_num].addr_bytes[5]);
+ }
} else if (strcmp(key, KEY_FILE_NUMSLOTS) == 0) {
config->numSlots = atoi(value);
printf("numSlots: %d\n",config->numSlots);
}
printf("nPrbElemUl: %d\n",config->PrbMapUl.nPrbElm);
} else if (strncmp(key, KEY_PRBELEM_UL, strlen(KEY_PRBELEM_UL)) == 0) {
- unsigned int section_idx = 0;
- sscanf(key,"PrbElemUl%u",§ion_idx);
- if (section_idx >= config->PrbMapUl.nPrbElm){
- printf("section_idx %d exceeds nPrbElem\n",section_idx);
+ sscanf(key,"PrbElemUl%u",§ion_idx_ul);
+ if (section_idx_ul >= config->PrbMapUl.nPrbElm){
+ printf("section_idx %d exceeds nPrbElemUl\n",section_idx_ul);
}
else{
- struct xran_prb_elm *pPrbElem = &config->PrbMapUl.prbMap[section_idx];
+ struct xran_prb_elm *pPrbElem = &config->PrbMapUl.prbMap[section_idx_ul];
sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd",
(int16_t*)&pPrbElem->nRBStart,
(int16_t*)&pPrbElem->nRBSize,
(int16_t*)&pPrbElem->compMethod,
(int16_t*)&pPrbElem->iqWidth,
(int16_t*)&pPrbElem->BeamFormingType);
- printf("nPrbElemUl%d: ",section_idx);
+ printf("nPrbElemUl%d: ",section_idx_ul);
printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n",
pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType);
}
}
printf("nPrbElemDl: %d\n",config->PrbMapDl.nPrbElm);
} else if (strncmp(key, KEY_PRBELEM_DL, strlen(KEY_PRBELEM_DL)) == 0) {
- unsigned int section_idx = 0;
- sscanf(key,"PrbElemDl%u",§ion_idx);
- if (section_idx >= config->PrbMapDl.nPrbElm){
- printf("section_idx %d exceeds nPrbElem\n",section_idx);
+ sscanf(key,"PrbElemDl%u",§ion_idx_dl);
+ if (section_idx_dl >= config->PrbMapDl.nPrbElm){
+ printf("section_idx %d exceeds nPrbElemDl\n",section_idx_dl);
}
else{
- struct xran_prb_elm *pPrbElem = &config->PrbMapDl.prbMap[section_idx];
+ struct xran_prb_elm *pPrbElem = &config->PrbMapDl.prbMap[section_idx_dl];
sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd",
(int16_t*)&pPrbElem->nRBStart,
(int16_t*)&pPrbElem->nRBSize,
(int16_t*)&pPrbElem->compMethod,
(int16_t*)&pPrbElem->iqWidth,
(int16_t*)&pPrbElem->BeamFormingType);
- printf("nPrbElemDl%d: ",section_idx);
+ printf("nPrbElemDl%d: ",section_idx_dl);
printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n",
pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType);
}
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
typedef struct _RuntimeConfig
{
uint8_t appMode; /**< Application mode: lls-CU or RU */
- uint8_t xranCat; /**< xran mode: Categoty A | Category B */
+ uint8_t xranTech; /**< Radio Access Technology (NR or LTE) */
+ uint8_t xranCat; /**< xran mode: NR Categoty A, NR Category B, LTE Cat A, LTE Cat B */
uint8_t numCC; /**< Number of CC per ports supported by RU */
uint8_t numAxc; /**< Number of Antenna Carriers per CC */
uint8_t numUlAxc; /**< Number of Antenna Carriers per CC for UL (Cat B) */
uint32_t ttiPeriod; /**< TTI period */
uint32_t testVect; /**< Test Signal to send */
- struct ether_addr o_du_addr; /**< lls-CU Ethernet Mac Address */
- struct ether_addr o_ru_addr; /**< RU Ethernet Mac Address */
- struct ether_addr tmp_addr; /**< Temp Ethernet Mac Address */
-
- uint32_t instance_id; /**< Instance ID of application */
- uint32_t io_core; /**< Core used for IO */
- uint64_t system_core; /* <system core ID> */
- uint64_t pkt_proc_core;
- uint64_t pkt_aux_core;
- uint64_t timing_core;
-
+ struct rte_ether_addr o_du_addr[XRAN_VF_MAX]; /**< O-DU Ethernet Mac Address */
+ struct rte_ether_addr o_ru_addr[XRAN_VF_MAX]; /**< O-RU Ethernet Mac Address */
+ struct rte_ether_addr tmp_addr; /**< Temp Ethernet Mac Address */
+
+ uint32_t instance_id; /**< Instance ID of application */
+ uint32_t io_core; /**< Core used for IO */
+ uint64_t io_worker; /**< Mask for worker cores */
+ int32_t io_sleep; /**< enable sleep on PMD cores */
+ uint32_t system_core; /* house keeping core */
+ int iova_mode; /**< DPDK IOVA Mode */
+
uint32_t mtu; /**< maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) */
int numSlots; /**< number of slots in IQ vector */
uint8_t prachOffset; /**< Sets the PRACH position in frequency / subcarrier position, n_PRBoffset^RA and is expressed as a physical resource block number.
Set by SIB2, prach-FreqOffset in E-UTRA. */
- uint8_t prachConfigIndex; /**< TS36.211 - Table 5.7.1-2 : PRACH Configuration Index */
- uint8_t iqswap; /**< do swap of IQ before send to ETH */
+ uint8_t prachConfigIndex;/**< TS36.211 - Table 5.7.1-2 : PRACH Configuration Index */
+ uint8_t iqswap; /**< do swap of IQ before send to ETH */
uint8_t nebyteorderswap; /**< do swap of byte order from host byte order to network byte order. ETH */
uint8_t compression; /**< enable use case with compression */
+ uint8_t CompHdrType; /**< dynamic or static compression header */
uint16_t totalBfWeights; /**< The total number of beamforming weights on RU */
struct xran_slot_config sSlotConfig[XRAN_MAX_TDD_PERIODICITY];
struct xran_prb_map PrbMapDl;
struct xran_prb_map PrbMapUl;
+
+ int32_t DU_Port_ID_bitwidth;
+ int32_t BandSector_ID_bitwidth;
+ int32_t CC_ID_bitwidth;
+ int32_t RU_Port_ID_bitwidth;
+
} RuntimeConfig;
/**
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
#include <pthread.h>
#include <sys/stat.h>
#include <unistd.h>
+#include <getopt.h> // for getopt
+
#include "common.h"
#include "config.h"
static struct xran_fh_init xranInit;
void * xranHandle = NULL;
+struct sample_app_params {
+ int num_vfs;
+ char *cfg_file;
+};
+
+
struct xran_fh_config xranConf;
struct xran_fh_config *pXranConf = NULL;
static BbuXranIoIfStruct gsXranIoIf;
static XranLibConfigStruct *gpXranLibConfig = NULL;
-extern long rx_counter;
-extern long tx_counter;
-extern long tx_bytes_counter;
-extern long rx_bytes_counter;
-extern long tx_bytes_per_sec;
-extern long rx_bytes_per_sec;
long old_rx_counter = 0;
long old_tx_counter = 0;
-
#define CPU_HZ tick_per_usec //us
/* Application User space functions */
uint32_t *u32dptr;
uint16_t *u16dptr;
uint8_t *u8dptr;
+ uint32_t xran_max_antenna_nr = RTE_MAX(startupConfiguration.numAxc, startupConfiguration.numUlAxc);
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(startupConfiguration.antElmTRx, xran_max_antenna_nr);
SWXRANInterfaceTypeEnum eInterfaceType;
eInterfaceType = XRANFTHTX_OUT;
printf("nSectorIndex[%d] = %d\n",i, nSectorIndex[i]);
status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
+ XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init , status %d\n", status);
}
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
{
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < xran_max_antenna_nr; z++){
psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0;
psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
if(ptr){
u32dptr = (uint32_t*)(ptr);
- uint8_t *ptr_temp = (uint8_t *)ptr;
memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen);
// ptr_temp[0] = j; // TTI
// ptr_temp[1] = i; // Sec
/* C-plane DL */
eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
+ XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init , status %d\n", status);
}
eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
+ XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init , status %d\n", status);
}
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
{
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < xran_max_antenna_nr; z++){
psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status);
}
pPrbElem->p_sec_desc[k] = sd_ptr;
+ memset(sd_ptr,0,sizeof(struct xran_section_desc));
}
}
}
for(i = 0; i<nSectorNum; i++)
{
eInterfaceType = XRANFTHRX_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
+ status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
if(XRAN_STATUS_SUCCESS != status)
{
printf("Failed at xran_bm_init, status %d\n", status);
for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
{
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < xran_max_antenna_nr; z++){
psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0;
psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
/* C-plane */
eInterfaceType = XRANFTHTX_SEC_DESC_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
+ XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init , status %d\n", status);
}
eInterfaceType = XRANFTHRX_PRB_MAP_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
+ XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < xran_max_antenna_nr; z++){
psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status);
}
pPrbElem->p_sec_desc[k] = sd_ptr;
+ memset(sd_ptr,0,sizeof(struct xran_section_desc));
}
}
}
for(i = 0; i<nSectorNum; i++)
{
eInterfaceType = XRANFTHRACH_IN;
- status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
+ status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
{
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < xran_max_antenna_nr; z++){
psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
- psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR; // ant number.
+ psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr; // ant number.
psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHPrachRxBuffers[j][i][z][0];
for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
{
}
/* add SRS rx buffer */
- for(i = 0; i<nSectorNum; i++)
+ for(i = 0; i<nSectorNum && xran_max_ant_array_elm_nr; i++)
{
eInterfaceType = XRANSRS_IN;
status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN*XRAN_MAX_ANT_ARRAY_ELM_NR*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
+ XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
if(XRAN_STATUS_SUCCESS != status) {
rte_panic("Failed at xran_bm_init, status %d\n", status);
}
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
{
- for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
+ for(z = 0; z < xran_max_ant_array_elm_nr; z++){
psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0;
psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
- psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANT_ARRAY_ELM_NR; /* ant number */
+ psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_ant_array_elm_nr; /* ant number */
psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHSrsRxBuffers[j][i][z][0];
for(k = 0; k < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; k++)
{
}
}
-
for(i=0; i<nSectorNum; i++)
{
for(j=0; j<XRAN_N_FE_BUF_LEN; j++)
{
for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ pFthTxBuffer[i][z][j] = NULL;
+ pFthTxPrbMapBuffer[i][z][j] = NULL;
+ pFthRxBuffer[i][z][j] = NULL;
+ pFthRxPrbMapBuffer[i][z][j] = NULL;
+ pFthRxRachBuffer[i][z][j] = NULL;
+ }
+ for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
+ pFthRxSrsBuffer[i][z][j] = NULL;
+ }
+ }
+ }
+
+ for(i=0; i<nSectorNum; i++)
+ {
+ for(j=0; j<XRAN_N_FE_BUF_LEN; j++)
+ {
+ for(z = 0; z < xran_max_antenna_nr; z++){
pFthTxBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
pFthTxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxRachBuffer[i][z][j] = &(psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
}
- for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
+ for(z = 0; z < xran_max_ant_array_elm_nr && xran_max_ant_array_elm_nr; z++){
pFthRxSrsBuffer[i][z][j] = &(psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList);
}
}
}
/* add SRS callback here */
- for (i = 0; i<nSectorNum; i++) {
+ for (i = 0; i<nSectorNum && xran_max_ant_array_elm_nr; i++) {
xran_5g_srs_req(psBbuIo->nInstanceHandle[0][i], pFthRxSrsBuffer[i],
xran_fh_rx_srs_callback,&pFthRxSrsBuffer[i][0]);
}
uint16_t *u16dptr;
uint8_t *u8dptr;
+ uint32_t xran_max_antenna_nr = RTE_MAX(startupConfiguration.numAxc, startupConfiguration.numUlAxc);
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(startupConfiguration.antElmTRx, xran_max_antenna_nr);
+
char *pos = NULL;
struct xran_prb_map *pRbMap = NULL;
for(cc_id = 0; cc_id <nSectorNum; cc_id++)
{
for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) {
- for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++){
for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
- flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
+ if(startupConfiguration.appMode == APP_O_DU)
+ flowId = startupConfiguration.numAxc * cc_id + ant_id;
+ else
+ flowId = startupConfiguration.numUlAxc * cc_id + ant_id;
+
if(p_tx_play_buffer[flowId]){
/* c-plane DL */
pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
int16_t ext_len = 9600;
int16_t ext_sec_total = 0;
int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
- int idRb = 0;
- int16_t *ptr = NULL;
- int i;
+ int8_t * ext_buf_start = ext_buf;
if (ext_buf){
ext_buf += (RTE_PKTMBUF_HEADROOM +
sizeof (struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_common_header) +
sizeof(struct xran_cp_radioapp_section1));
ext_len -= (RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_common_header) +
sizeof(struct xran_cp_radioapp_section1));
+
ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
ext_len,
(int16_t *) (dl_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4),
pXranConf->nAntElmTRx,
p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
if(ext_sec_total > 0){
+ p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start;
p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
}else {
bfp_com_rsp.data_out = (int8_t*)dst;
bfp_com_rsp.len = 0;
- if(xranlib_compress_avx512(&bfp_com_req, &bfp_com_rsp) < 0){
- printf ("compression failed [%d]\n",
- p_prbMapElm->compMethod);
- exit(-1);
- } else {
- payload_len = bfp_com_rsp.len;
- }
+ xranlib_compress_avx512(&bfp_com_req, &bfp_com_rsp);
+ payload_len = bfp_com_rsp.len;
+
}else {
printf ("p_prbMapElm->compMethod == %d is not supported\n",
p_prbMapElm->compMethod);
int16_t ext_len = 9600;
int16_t ext_sec_total = 0;
int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
+ int8_t * ext_buf_start = ext_buf;
int idRb = 0;
int16_t *ptr = NULL;
int i;
if (ext_buf){
+
ext_buf += (RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header) +
sizeof(struct xran_cp_radioapp_section1));
ext_len -= (RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header) +
sizeof(struct xran_cp_radioapp_section1));
+
ptr = (int16_t*)(ul_bfw_pos +(p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4);
ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
ext_len,
pXranConf->nAntElmTRx,
p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
if(ext_sec_total > 0){
+ p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start;
p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
}else {
/* prach TX for RU only */
if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
- for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++){
for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
- flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
+ flowId = startupConfiguration.numAxc*cc_id + ant_id;
if(p_tx_prach_play_buffer[flowId]){
pos = ((char*)p_tx_prach_play_buffer[flowId]);
/* SRS TX for RU only */
if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
- for(ant_id = 0; ant_id < XRAN_MAX_ANT_ARRAY_ELM_NR; ant_id++){
+ for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++){
for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) {
- flowId = XRAN_MAX_ANT_ARRAY_ELM_NR*cc_id + ant_id;
+ flowId = startupConfiguration.antElmTRx*cc_id + ant_id;
if(p_tx_srs_play_buffer[flowId]){
pos = ((char*)p_tx_srs_play_buffer[flowId]) + tx_srs_play_buffer_position[flowId];
uint16_t *u16dptr;
uint8_t *u8dptr;
+ uint32_t xran_max_antenna_nr = RTE_MAX(startupConfiguration.numAxc, startupConfiguration.numUlAxc);
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(startupConfiguration.antElmTRx, xran_max_antenna_nr);
+
char *pos = NULL;
for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
for(cc_id = 0; cc_id <nSectorNum; cc_id++)
{
for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti++) {
- for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++){
int32_t idxElm = 0;
struct xran_prb_map *pRbMap = NULL;
struct xran_prb_elm *pRbElm = NULL;
pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
if(pRbMap == NULL)
exit(-1);
- flowId = XRAN_MAX_ANTENNA_NR * cc_id + ant_id;
+
+ if(startupConfiguration.appMode == APP_O_RU)
+ flowId = startupConfiguration.numAxc * cc_id + ant_id;
+ else
+ flowId = startupConfiguration.numUlAxc * cc_id + ant_id;
+
for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
pRbElm = &pRbMap->prbMap[0];
if(pRbMap->nPrbElm == 1){
ptr = psBbuIo->sFrontHaulRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
if(ptr){
u32dptr = (uint32_t*)(ptr);
- char* my_ptr =(char *)ptr;
rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L);
}else {
printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id);
bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
bfp_decom_rsp.len = 0;
- if(xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp) < 0){
- printf ("compression failed [%d]\n",
- pRbElm->compMethod);
- exit(-1);
- } else {
- payload_len = bfp_decom_rsp.len;
- }
+ xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp);
+ payload_len = bfp_decom_rsp.len;
+
} else {
rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4);
}
/* prach RX for O-DU only */
if(startupConfiguration.appMode == APP_O_DU) {
- flowId = XRAN_MAX_ANTENNA_NR * cc_id + ant_id;
+ flowId = startupConfiguration.numAxc * cc_id + ant_id;
for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++){
if(p_prach_log_buffer[flowId]){
/* (0-79 slots) 10ms of IQs */
}
/* SRS RX for O-DU only */
- if(startupConfiguration.appMode == APP_O_DU) {
- for(ant_id = 0; ant_id < XRAN_MAX_ANT_ARRAY_ELM_NR; ant_id++){
- flowId = XRAN_MAX_ANT_ARRAY_ELM_NR*cc_id + ant_id;
+ if(startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs) {
+ for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++){
+ flowId = startupConfiguration.antElmTRx*cc_id + ant_id;
for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++){
if(p_srs_log_buffer[flowId]){
pos = ((char*)p_srs_log_buffer[flowId]) + srs_log_buffer_position[flowId];
char *compilation_time = __TIME__;
uint32_t nLen;
- uint32_t i;
snprintf(sysversion, 99, "Version: %s", VERSIONX);
nLen = strlen(sysversion);
printf("build-time: %s\n", compilation_time);
}
+static void app_Help(void)
+{
+ char help_content[] = \
+ "sample application\n\n"\
+ "Usage: sample-app config_file_o_du.dat -p 2 0000:21:02.0 0000:21:02.1 0000:21:0a.0 0000:21:0a.1\n\n"\
+ "supports the following parameters:\n\n"\
+ "-p | --num_eth_pfs <number of ETH ports to connect to O-RU|O-DU> 1 - default sanity test\n"
+ "-c | --cfgfile <name of cfg file>\n"\
+ "-h | --help print usage\n";
+
+ printf("%s", help_content);
+}
+
+/**
+ *******************************************************************************
+ *
+ * @fn app_parse_args
+ * @brief is used to parse incoming app args
+ *
+ * @param[i] argc - app arg count
+ * @param[i] argv - array of args
+ * @param[o] params - app startup params filled basing on args parse
+ * @return number of parsed args
+ *
+ * @description
+ * The routine is parse input args and convert them into app startup params
+ *
+ * @references
+ * MS-111070-SP
+ *
+ * @ingroup icc_service_unit_test
+ *
+ ******************************************************************************/
+static int app_parse_args(int argc, char ** argv, struct sample_app_params* params)
+{
+ int c;
+ int *pInt;
+ int cnt = 0;
+
+ struct option long_options[] = {
+ {"cfgfile", required_argument, 0, 'c'},
+ {"num_eth_pfs", required_argument, 0, 'p'},
+ {"help", no_argument, 0, 'h'},
+ {0, 0, 0, 0}
+ };
+
+ memset(params, 0, sizeof (*params));
+
+ while (1) {
+ //int this_option_optind = optind ? optind : 1;
+ int option_index = 0;
+
+ c = getopt_long(argc, argv, "c:p:h", long_options, &option_index);
+
+ if (c == -1)
+ break;
+
+ cnt += 1;
+ pInt = NULL;
+
+ switch (c) {
+ case 'p': // test Case selection
+ pInt = ¶ms->num_vfs;
+ break;
+ case 'c':
+ params->cfg_file = optarg;
+ break;
+ case 'h':
+ app_Help();
+ exit(0);
+ }
+
+ if (pInt && optarg) {
+ // get int arg
+ if (optarg[0] == '0' && (optarg[1] == 'x' || optarg[1] == 'X')) {
+ sscanf(optarg, "%x", (unsigned *) pInt);
+ } else {
+ *pInt = atoi(optarg);
+ }
+ }
+ }
+ return cnt;
+}
+
+int32_t app_init_set_eAxCId_conf(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg)
+{
+ int32_t shift;
+ uint16_t mask;
+
+ if(p_s_cfg->DU_Port_ID_bitwidth && p_s_cfg->BandSector_ID_bitwidth && p_s_cfg->CC_ID_bitwidth
+ && p_s_cfg->RU_Port_ID_bitwidth &&
+ (p_s_cfg->DU_Port_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth + p_s_cfg->CC_ID_bitwidth
+ + p_s_cfg->RU_Port_ID_bitwidth) == 16 /* eAxC ID subfields are 16 bits */
+ ){ /* bit mask provided */
+
+ mask = 0;
+ p_eAxC_cfg->bit_ruPortId = 0;
+ for (shift = 0; shift < p_s_cfg->RU_Port_ID_bitwidth; shift++){
+ mask |= 1 << shift;
+ }
+ p_eAxC_cfg->mask_ruPortId = mask;
+
+ p_eAxC_cfg->bit_ccId = p_s_cfg->RU_Port_ID_bitwidth;
+ mask = 0;
+ for (shift = p_s_cfg->RU_Port_ID_bitwidth; shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; shift++){
+ mask |= 1 << shift;
+ }
+ p_eAxC_cfg->mask_ccId = mask;
+
+
+ p_eAxC_cfg->bit_bandSectorId = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth;
+ mask = 0;
+ for (shift = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; shift++){
+ mask |= 1 << shift;
+ }
+ p_eAxC_cfg->mask_bandSectorId = mask;
+
+ p_eAxC_cfg->bit_cuPortId = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth;
+ mask = 0;
+ for (shift = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth;
+ shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth + p_s_cfg->DU_Port_ID_bitwidth; shift++){
+ mask |= 1 << shift;
+ }
+ p_eAxC_cfg->mask_cuPortId = mask;
+
+
+ } else { /* bit mask config is not provided */
+ switch (p_s_cfg->xranCat){
+ case XRAN_CATEGORY_A: {
+ p_eAxC_cfg->mask_cuPortId = 0xf000;
+ p_eAxC_cfg->mask_bandSectorId = 0x0f00;
+ p_eAxC_cfg->mask_ccId = 0x00f0;
+ p_eAxC_cfg->mask_ruPortId = 0x000f;
+ p_eAxC_cfg->bit_cuPortId = 12;
+ p_eAxC_cfg->bit_bandSectorId = 8;
+ p_eAxC_cfg->bit_ccId = 4;
+ p_eAxC_cfg->bit_ruPortId = 0;
+ break;
+ }
+ case XRAN_CATEGORY_B: {
+ p_eAxC_cfg->mask_cuPortId = 0xf000;
+ p_eAxC_cfg->mask_bandSectorId = 0x0c00;
+ p_eAxC_cfg->mask_ccId = 0x0300;
+ p_eAxC_cfg->mask_ruPortId = 0x00ff; /* more than [0-127] eAxC */
+ p_eAxC_cfg->bit_cuPortId = 12;
+ p_eAxC_cfg->bit_bandSectorId = 10;
+ p_eAxC_cfg->bit_ccId = 8;
+ p_eAxC_cfg->bit_ruPortId = 0;
+ break;
+ }
+ default:
+ rte_panic("Incorrect Category\n");
+ }
+ }
+
+ if(p_s_cfg->xranCat == XRAN_CATEGORY_A)
+ p_s_cfg->numUlAxc = p_s_cfg->numAxc;
+
+ printf("bit_cuPortId %2d mask 0x%04x\n",p_eAxC_cfg->bit_cuPortId, p_eAxC_cfg->mask_cuPortId);
+ printf("bit_bandSectorId %2d mask 0x%04x\n",p_eAxC_cfg->bit_bandSectorId, p_eAxC_cfg->mask_bandSectorId);
+ printf("bit_ccId %2d mask 0x%04x\n",p_eAxC_cfg->bit_ccId, p_eAxC_cfg->mask_ccId);
+ printf("ruPortId %2d mask 0x%04x\n",p_eAxC_cfg->bit_ruPortId, p_eAxC_cfg->mask_ruPortId);
+
+ return 0;
+}
+
int main(int argc, char *argv[])
{
int i;
int32_t xret = 0;
struct stat st = {0};
uint32_t filenameLength = strlen(argv[1]);
- char *pCheckName1 = NULL, *pCheckName2 = NULL;
enum xran_if_state xran_curr_if_state = XRAN_INIT;
+ struct sample_app_params arg_params;
+
- uint64_t nMask = (uint64_t)1;
- uint16_t nCoreUsage[4*64+1];
- uint16_t nCoreId[4*64];
- float nTotal = 0.0;
uint64_t nTotalTime;
uint64_t nUsedTime;
uint32_t nCoreUsed;
float nUsedPercent;
+ app_parse_args(argc, argv, &arg_params);
+
+ if( (arg_params.num_vfs % 2) != 0 || arg_params.num_vfs >= XRAN_VF_MAX){
+ printf("warning: arg_params.num_vfs is not correct\n");
+ exit(-1);
+ }
+
+ if (argc == 3 + arg_params.num_vfs){
+ printf("Need at least two argument - the PCI address of the network port");
+ exit(-1);
+ }
- if (argc == 3)
- errx(2, "Need two argument - the PCI address of the network port");
if (filenameLength >= 256)
{
printf("Config file name input is too long, exiting!\n");
version_print();
//add for Klocworks
- len = strlen(argv[1]) + 1;
+ printf("arg_params.cfg_file (%s)\n", arg_params.cfg_file);
+ len = strlen(arg_params.cfg_file) + 1;
if (len > (sizeof(filename) - 10))
len = (sizeof(filename) - 10);
- strncpy(filename, argv[1], (sizeof(filename) - 10));
+ strncpy(filename, arg_params.cfg_file, (sizeof(filename) - 10));
filename[len] = '\0';
if (xran_is_synchronized() != 0)
nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/
nFpgaToSW_PRACH_RxBufferLen = 8192;
nSW_ToFpga_FTH_TxBufferLen = 13168 + /* 273*12*4 + 64* + ETH AND ORAN HDRs */
- XRAN_MAX_SECTIONS_PER_SYM* (RTE_PKTMBUF_HEADROOM + sizeof(struct ether_hdr) +
+ XRAN_MAX_SECTIONS_PER_SYM* (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) +
sizeof(struct xran_ecpri_hdr) +
sizeof(struct radio_app_common_hdr) +
sizeof(struct data_section_hdr));
nFpgaToSW_FTH_RxBufferLen = 3328;
nFpgaToSW_PRACH_RxBufferLen = 8192;
nSW_ToFpga_FTH_TxBufferLen = 3328 +
- XRAN_MAX_SECTIONS_PER_SYM * (RTE_PKTMBUF_HEADROOM + sizeof(struct ether_hdr) +
+ XRAN_MAX_SECTIONS_PER_SYM * (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) +
sizeof(struct xran_ecpri_hdr) +
sizeof(struct radio_app_common_hdr) +
sizeof(struct data_section_hdr));
xranInit.io_cfg.id = 0;/* O-DU */
xranInit.io_cfg.core = startupConfiguration.io_core;
xranInit.io_cfg.system_core = startupConfiguration.system_core;
- xranInit.io_cfg.pkt_proc_core = startupConfiguration.pkt_proc_core;
- xranInit.io_cfg.pkt_aux_core = startupConfiguration.pkt_aux_core; /* do not start*/
- xranInit.io_cfg.timing_core = startupConfiguration.timing_core;
+ xranInit.io_cfg.pkt_proc_core = startupConfiguration.io_worker; /* do not start */
+ xranInit.io_cfg.pkt_aux_core = 0; /* do not start*/
+ xranInit.io_cfg.timing_core = startupConfiguration.io_core;
+ xranInit.io_cfg.dpdkIoVaMode = startupConfiguration.iova_mode;
} else {
printf("set O-RU\n");
xranInit.io_cfg.id = 1; /* O-RU*/
xranInit.io_cfg.core = startupConfiguration.io_core;
xranInit.io_cfg.system_core = startupConfiguration.system_core;
- xranInit.io_cfg.pkt_proc_core = startupConfiguration.pkt_proc_core;
- xranInit.io_cfg.pkt_aux_core = startupConfiguration.pkt_aux_core; /* do not start*/
- xranInit.io_cfg.timing_core = startupConfiguration.timing_core;
+ xranInit.io_cfg.pkt_proc_core = startupConfiguration.io_worker; /* do not start */
+ xranInit.io_cfg.pkt_aux_core = 0; /* do not start */
+ xranInit.io_cfg.timing_core = startupConfiguration.io_core;
+ xranInit.io_cfg.dpdkIoVaMode = startupConfiguration.iova_mode;
}
- cpu_set_t cpuset;
- pthread_t thread;
-
- thread = pthread_self();
- CPU_ZERO(&cpuset);
- CPU_SET(xranInit.io_cfg.system_core,&cpuset);
- pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset);
-/* if (s != 0)
- handle_error_en(s, "pthread_setaffinity_np");
-*/
-
+ xranInit.io_cfg.io_sleep = startupConfiguration.io_sleep;
xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
- if(startupConfiguration.xranCat == XRAN_CATEGORY_A){
- xranInit.eAxCId_conf.mask_cuPortId = 0xf000;
- xranInit.eAxCId_conf.mask_bandSectorId = 0x0f00;
- xranInit.eAxCId_conf.mask_ccId = 0x00f0;
- xranInit.eAxCId_conf.mask_ruPortId = 0x000f;
- xranInit.eAxCId_conf.bit_cuPortId = 12;
- xranInit.eAxCId_conf.bit_bandSectorId = 8;
- xranInit.eAxCId_conf.bit_ccId = 4;
- xranInit.eAxCId_conf.bit_ruPortId = 0;
- } else {
- xranInit.eAxCId_conf.mask_cuPortId = 0xf000;
- xranInit.eAxCId_conf.mask_bandSectorId = 0x0c00;
- xranInit.eAxCId_conf.mask_ccId = 0x0300;
- xranInit.eAxCId_conf.mask_ruPortId = 0x00ff; /* more than [0-127] eAxC */
- xranInit.eAxCId_conf.bit_cuPortId = 12;
- xranInit.eAxCId_conf.bit_bandSectorId = 10;
- xranInit.eAxCId_conf.bit_ccId = 8;
- xranInit.eAxCId_conf.bit_ruPortId = 0;
- }
+ app_init_set_eAxCId_conf(&xranInit.eAxCId_conf, &startupConfiguration);
- xranInit.io_cfg.dpdk_dev[XRAN_UP_VF] = argv[2];
- xranInit.io_cfg.dpdk_dev[XRAN_CP_VF] = argv[3];
- xranInit.mtu = startupConfiguration.mtu;
+ printf("arg_params.num_vfs %d\n", arg_params.num_vfs);
+ for(i = 0; i < arg_params.num_vfs/2; i++){
+ xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i] = argv[5+2*i];
+ printf("VF[%d] %s\n",XRAN_UP_VF+2*i, xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i]);
+ xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i+1] = argv[5+2*i+1];
+ printf("VF[%d] %s\n",XRAN_UP_VF+2*i+1, xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i+1]);
+ }
- xranInit.p_o_du_addr = (int8_t *)&startupConfiguration.o_du_addr;
- xranInit.p_o_ru_addr = (int8_t *)&startupConfiguration.o_ru_addr;
+ xranInit.io_cfg.num_vfs = arg_params.num_vfs;
+ xranInit.mtu = startupConfiguration.mtu;
+ xranInit.p_o_du_addr = (int8_t *)startupConfiguration.o_du_addr;
+ xranInit.p_o_ru_addr = (int8_t *)startupConfiguration.o_ru_addr;
- snprintf(prefix_name, sizeof(prefix_name), "wls_%d",startupConfiguration.instance_id);
+ sprintf(prefix_name, "wls_%d",startupConfiguration.instance_id);
xranInit.filePrefix = prefix_name;
xranInit.totalBfWeights = startupConfiguration.totalBfWeights;
printf("IQ files size is %d slots\n", startupConfiguration.numSlots);
iq_playback_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
- app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
+ app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
*4L);
iq_playback_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
- app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
+ app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
*4L);
/* 10 * [14*32*273*2*2] = 4892160 bytes */
iq_bfw_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * startupConfiguration.antElmTRx *
- app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
+ app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
*4L);
/* 10 * [14*32*273*2*2] = 4892160 bytes */
iq_bfw_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT *
- app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
+ app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
*4L);
/* 10 * [1*273*2*2] = 349440 bytes */
iq_srs_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
- app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
+ app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
*4L);
for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
- snprintf(filename, sizeof(filename), "./logs/%s-play_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-play_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"DL IFFT IN IQ Samples in human readable format",
(uint8_t*) p_tx_play_buffer[i],
tx_play_buffer_size[i],
1);
- snprintf(filename, sizeof(filename),"./logs/%s-play_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-play_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"DL IFFT IN IQ Samples in binary format",
(uint8_t*) p_tx_play_buffer[i],
if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
- snprintf(filename, sizeof(filename),"./logs/%s-dl_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-dl_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"DL Beamformig weights IQ Samples in human readable format",
(uint8_t*) p_tx_dl_bfw_buffer[i],
tx_dl_bfw_buffer_size[i],
1);
- snprintf(filename, sizeof(filename),"./logs/%s-dl_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-dl_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"DL Beamformig weightsIQ Samples in binary format",
(uint8_t*) p_tx_dl_bfw_buffer[i],
sizeof(short));
- snprintf(filename, sizeof(filename), "./logs/%s-ul_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-ul_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"UL Beamformig weights IQ Samples in human readable format",
(uint8_t*) p_tx_ul_bfw_buffer[i],
tx_ul_bfw_buffer_size[i],
1);
- snprintf(filename, sizeof(filename),"./logs/%s-ul_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-ul_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"UL Beamformig weightsIQ Samples in binary format",
(uint8_t*) p_tx_ul_bfw_buffer[i],
}
if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
- snprintf(filename, sizeof(filename), "./logs/%s-play_prach_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-play_prach_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"PRACH IQ Samples in human readable format",
(uint8_t*) p_tx_prach_play_buffer[i],
tx_prach_play_buffer_size[i],
1);
- snprintf(filename, sizeof(filename), "./logs/%s-play_prach_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-play_prach_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"PRACH IQ Samples in binary format",
(uint8_t*) p_tx_prach_play_buffer[i],
i++) {
- snprintf(filename, sizeof(filename), "./logs/%s-play_srs_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-play_srs_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"SRS IQ Samples in human readable format",
(uint8_t*) p_tx_srs_play_buffer[i],
tx_srs_play_buffer_size[i],
1);
- snprintf(filename,sizeof(filename), "./logs/%s-play_srs_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-play_srs_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"SRS IQ Samples in binary format",
(uint8_t*) p_tx_srs_play_buffer[i],
memset(&xranConf, 0, sizeof(struct xran_fh_config));
pXranConf = &xranConf;
- pXranConf->nDLRBs = app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA);
- pXranConf->nULRBs = app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA);
+ pXranConf->nDLRBs = app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA);
+ pXranConf->nULRBs = app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA);
if(startupConfiguration.DynamicSectionEna == 0){
struct xran_prb_map* pRbMap;
pRbMap->prbMap[0].nBeamIndex = 0;
pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
pRbMap->prbMap[0].iqWidth = 16;
+ } else {
+ struct xran_prb_map* pRbMap;
+ pRbMap = &startupConfiguration.PrbMapDl;
+
+ pRbMap->dir = XRAN_DIR_DL;
+ pRbMap->xran_port = 0;
+ pRbMap->band_id = 0;
+ pRbMap->cc_id = 0;
+ pRbMap->ru_port_id = 0;
+ pRbMap->tti_id = 0;
+ pRbMap->start_sym_id = 0;
+
+ pRbMap = &startupConfiguration.PrbMapUl;
+ pRbMap->dir = XRAN_DIR_UL;
+ pRbMap->xran_port = 0;
+ pRbMap->band_id = 0;
+ pRbMap->cc_id = 0;
+ pRbMap->ru_port_id = 0;
+ pRbMap->tti_id = 0;
+ pRbMap->start_sym_id = 0;
}
timer_set_tsc_freq_from_clock();
pXranConf->prach_conf.nPrachConfIdx = startupConfiguration.prachConfigIndex;
pXranConf->prach_conf.nPrachFreqOffset = -792;
- pXranConf->srs_conf.symbMask = startupConfiguration.srsSymMask;
+ pXranConf->srs_conf.symbMask = startupConfiguration.srsSymMask;
pXranConf->srs_conf.eAxC_offset = 2 * startupConfiguration.numAxc; /* PUSCH, PRACH, SRS */
+ pXranConf->ru_conf.xranTech = startupConfiguration.xranTech;
+ pXranConf->ru_conf.xranCompHdrType = startupConfiguration.CompHdrType;
pXranConf->ru_conf.xranCat = startupConfiguration.xranCat;
pXranConf->ru_conf.iqWidth = startupConfiguration.PrbMapDl.prbMap[0].iqWidth;
exit(-1);
}
- snprintf(filename, sizeof(filename),"mlog-%s", startupConfiguration.appMode == 0 ? "o-du" : "o-ru");
+ sprintf(filename, "mlog-%s", startupConfiguration.appMode == 0 ? "o-du" : "o-ru");
/* MLogOpen(0, 32, 0, 0xFFFFFFFF, filename);*/
uint64_t nActiveCoreMask[MAX_BBU_POOL_CORE_MASK] = {0};
- nActiveCoreMask[0] = 1 << xranInit.io_cfg.timing_core;
- uint32_t numCarriers = startupConfiguration.numCC;
+ nActiveCoreMask[0] = (1 << xranInit.io_cfg.timing_core | xranInit.io_cfg.pkt_proc_core);
- MLogAddTestCase(nActiveCoreMask, numCarriers);
+ MLogAddTestCase(nActiveCoreMask, startupConfiguration.numCC);
fcntl(0, F_SETFL, fcntl(0, F_GETFL) | O_NONBLOCK);
xran_get_time_stats(&nTotalTime, &nUsedTime, &nCoreUsed, 1);
nUsedPercent = ((float)nUsedTime * 100.0) / (float)nTotalTime;
- printf("[%s][rx %ld pps %ld kbps %ld][tx %ld pps %ld kbps %ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld] IO Util: %5.2f %%\n",
+ printf("[%s][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld] IO Util: %5.2f %%\n",
((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"),
- rx_counter,
- rx_counter-old_rx_counter,
- rx_bytes_per_sec*8/1000L,
- tx_counter,
- tx_counter-old_tx_counter,
- tx_bytes_per_sec*8/1000L,
+ x_counters.rx_counter,
+ x_counters.rx_counter-old_rx_counter,
+ x_counters.rx_bytes_per_sec*8/1000L,
+ x_counters.tx_counter,
+ x_counters.tx_counter-old_tx_counter,
+ x_counters.tx_bytes_per_sec*8/1000L,
x_counters.Rx_on_time,
x_counters.Rx_early,
x_counters.Rx_late,
x_counters.Total_msgs_rcvd,
nUsedPercent);
- if(rx_counter > old_rx_counter)
- old_rx_counter = rx_counter;
- if(tx_counter > old_tx_counter)
- old_tx_counter = tx_counter;
+ if(x_counters.rx_counter > old_rx_counter)
+ old_rx_counter = x_counters.rx_counter;
+ if(x_counters.tx_counter > old_tx_counter)
+ old_tx_counter = x_counters.tx_counter;
- if(rx_counter > 0 && tx_counter > 0)
+ if(x_counters.rx_counter > 0 && x_counters.tx_counter > 0)
MLogSetMask(0xFFFFFFFF);
} else {
printf("error xran_get_common_counters\n");
for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
- snprintf(filename, sizeof(filename), "./logs/%s-rx_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-rx_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"UL FFT OUT IQ Samples in human readable format",
(uint8_t*) p_rx_log_buffer[i],
rx_log_buffer_size[i],
1);
- snprintf(filename, sizeof(filename), "./logs/%s-rx_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-rx_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"UL FFT OUT IQ Samples in binary format",
(uint8_t*) p_rx_log_buffer[i],
for(i = 0;
i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
i++) {
- snprintf(filename, sizeof(filename), "./logs/%s-srs_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-srs_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"SRS UL FFT OUT IQ Samples in human readable format",
(uint8_t*) p_srs_log_buffer[i],
srs_log_buffer_size[i],
1);
- snprintf(filename, sizeof(filename), "./logs/%s-srs_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-srs_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"SRS UL FFT OUT IQ Samples in binary format",
(uint8_t*) p_srs_log_buffer[i],
for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
- snprintf(filename, sizeof(filename), "./logs/%s-prach_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-prach_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file_txt(filename,
"PRACH FFT OUT IQ Samples in human readable format",
(uint8_t*) p_prach_log_buffer[i],
prach_log_buffer_size[i],
1);
- snprintf(filename, sizeof(filename), "./logs/%s-prach_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
+ sprintf(filename, "./logs/%s-prach_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
sys_save_buf_to_file(filename,
"PRACH FFT OUT IQ Samples in binary format",
(uint8_t*) p_prach_log_buffer[i],
/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask 0-no workers
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask 0-no workers
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,90,0,14,1,1,1,9,1
+PrbElemDl0=0,64,0,14,0,1,1,9,1
+PrbElemDl1=64,26,0,14,1,1,1,9,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,90,0,14,1,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15 # core id
+ioWorker=0x800000000 # mask 0-no workers
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,90,0,14,1,1,1,9,1
+PrbElemDl0=0,64,0,14,0,1,1,9,1
+PrbElemDl1=64,26,0,14,1,1,1,9,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,90,0,14,1,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=1 # (1) compression enabled (0) compression disabled
+compression=0 # (1) compression enabled (0) compression disabled
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,90,0,14,1,1,1,9,1
+PrbElemDl0=0,64,0,14,0,1,1,9,1
+PrbElemDl1=64,26,0,14,1,1,1,9,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,90,0,14,1,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15 # core id
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
##Section Settings
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
-nPrbElemDl=1
+nPrbElemDl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,90,0,14,1,1,1,9,1
+PrbElemDl0=0,64,0,14,0,1,1,9,1
+PrbElemDl1=64,26,0,14,1,1,1,9,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,90,0,14,1,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
PrbElemDl0=0,90,0,14,0,1,1,9,1
PrbElemDl1=90,90,0,14,1,1,1,9,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,90,0,14,0,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
PrbElemDl0=0,90,0,14,0,1,1,9,1
PrbElemDl1=90,90,0,14,1,1,1,9,1
-nPrbElemUl=1
+nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemUl0=0,90,0,14,0,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
nPrbElemUl=3
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
+PrbElemUl0=0,30,0,14,0,1,1,9,1
+PrbElemUl1=30,30,0,14,1,1,1,9,1
+PrbElemUl2=60,30,0,14,2,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
nPrbElemUl=3
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
# weight base beams
-PrbElemDl0=0,30,0,14,0,1,1,9,1
-PrbElemDl1=30,30,0,14,1,1,1,9,1
-PrbElemDl2=60,30,0,14,2,1,1,9,1
+PrbElemUl0=0,30,0,14,0,1,1,9,1
+PrbElemUl1=30,30,0,14,1,1,1,9,1
+PrbElemUl2=60,30,0,14,2,1,1,9,1
###########################################################
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,1,1,1,9,1
+PrbElemDl1=48,48,0,14,2,1,1,9,1
+PrbElemDl2=96,48,0,14,3,1,1,9,1
+PrbElemDl3=144,48,0,14,4,1,1,9,1
+PrbElemDl4=144,36,0,14,5,1,1,9,1
+PrbElemDl5=180,36,0,14,6,1,1,9,1
+PrbElemDl6=216,36,0,14,7,1,1,9,1
+PrbElemDl7=252,21,0,14,8,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,1,1,1,9,1
+PrbElemUl1=48,48,0,14,2,1,1,9,1
+PrbElemUl2=72,36,0,14,3,1,1,9,1
+PrbElemUl3=108,36,0,14,4,1,1,9,1
+PrbElemUl4=144,36,0,14,5,1,1,9,1
+PrbElemUl5=180,36,0,14,6,1,1,9,1
+PrbElemUl6=216,36,0,14,7,1,1,9,1
+PrbElemUl7=252,21,0,14,8,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+ioWorker=0x800000000
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,1,1,1,9,1
+PrbElemDl1=48,48,0,14,2,1,1,9,1
+PrbElemDl2=96,48,0,14,3,1,1,9,1
+PrbElemDl3=144,48,0,14,4,1,1,9,1
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,1,1,1,9,1
+PrbElemUl1=48,48,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#TDD DDDFU 1 64T64R 100 16 8 100% 180 100%
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=0 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#TDD DDDFU 1 64T64R 100 16 8 100% 180 100%
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,48,0,14,3,1,1,9,1
+PrbElemDl4=192,48,0,14,4,1,1,9,1
+PrbElemDl5=240,33,0,14,5,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,48,0,14,3,1,1,9,1
+PrbElemUl4=192,48,0,14,4,1,1,9,1
+PrbElemUl5=240,33,0,14,5,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=0 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak
+#4%
+#TDD DDFU 1 64T64R 100 8 8 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#Peak
+#4%
+#TDD DDFU 1 64T64R 100 8 8 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#NC
+#12%
+#TDD DDDFU 1 64T64R 100 16 4 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#NC
+#12%
+#TDD DDDFU 1 64T64R 100 16 4 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#MC
+#20%
+#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#MC
+#20%
+#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#66% 180 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#MEC
+#28%
+#TDD DDDFU 1 64T64R 100 4 2 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#MEC
+#28%
+#TDD DDDFU 1 64T64R 100 4 2 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#EC
+#36%
+#TDD DDDFU 1 64T64R 100 2 1 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5 # core id
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=6
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+#EC
+#36%
+#TDD DDDFU 1 64T64R 100 2 1 65% 178 65% 178
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,0,1,1,9,1
+PrbElemDl1=48,48,0,14,1,1,1,9,1
+PrbElemDl2=96,48,0,14,2,1,1,9,1
+PrbElemDl3=144,34,0,14,3,1,1,9,1
+
+nPrbElemUl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,0,1,1,9,1
+PrbElemUl1=48,48,0,14,1,1,1,9,1
+PrbElemUl2=96,48,0,14,2,1,1,9,1
+PrbElemUl3=144,34,0,14,3,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=64 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=10 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/lte_a/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/lte_a/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/lte_a/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/lte_a/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/lte_a/mu0_10mhz/ant_4.bin #CC1
+antC5=./usecase/lte_a/mu0_10mhz/ant_5.bin #CC1
+antC6=./usecase/lte_a/mu0_10mhz/ant_6.bin #CC1
+antC7=./usecase/lte_a/mu0_10mhz/ant_7.bin #CC1
+antC8=./usecase/lte_a/mu0_10mhz/ant_8.bin #CC2
+antC9=./usecase/lte_a/mu0_10mhz/ant_9.bin #CC2
+antC10=./usecase/lte_a/mu0_10mhz/ant_10.bin #CC2
+antC11=./usecase/lte_a/mu0_10mhz/ant_11.bin #CC2
+antC12=./usecase/lte_a/mu0_10mhz/ant_12.bin #CC3
+antC13=./usecase/lte_a/mu0_10mhz/ant_13.bin #CC3
+antC14=./usecase/lte_a/mu0_10mhz/ant_14.bin #CC3
+antC15=./usecase/lte_a/mu0_10mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/lte_a/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/lte_a/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/lte_a/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/lte_a/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/lte_a/mu0_10mhz/ant_4.bin #CC1
+antC5=./usecase/lte_a/mu0_10mhz/ant_5.bin #CC1
+antC6=./usecase/lte_a/mu0_10mhz/ant_6.bin #CC1
+antC7=./usecase/lte_a/mu0_10mhz/ant_7.bin #CC1
+antC8=./usecase/lte_a/mu0_10mhz/ant_8.bin #CC2
+antC9=./usecase/lte_a/mu0_10mhz/ant_9.bin #CC2
+antC10=./usecase/lte_a/mu0_10mhz/ant_10.bin #CC2
+antC11=./usecase/lte_a/mu0_10mhz/ant_11.bin #CC2
+antC12=./usecase/lte_a/mu0_10mhz/ant_12.bin #CC3
+antC13=./usecase/lte_a/mu0_10mhz/ant_13.bin #CC3
+antC14=./usecase/lte_a/mu0_10mhz/ant_14.bin #CC3
+antC15=./usecase/lte_a/mu0_10mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_10mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_10mhz/ant_3.bin
+
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/lte_a/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/lte_a/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/lte_a/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/lte_a/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/lte_a/mu0_20mhz/ant_4.bin #CC1
+antC5=./usecase/lte_a/mu0_20mhz/ant_5.bin #CC1
+antC6=./usecase/lte_a/mu0_20mhz/ant_6.bin #CC1
+antC7=./usecase/lte_a/mu0_20mhz/ant_7.bin #CC1
+antC8=./usecase/lte_a/mu0_20mhz/ant_8.bin #CC2
+antC9=./usecase/lte_a/mu0_20mhz/ant_9.bin #CC2
+antC10=./usecase/lte_a/mu0_20mhz/ant_10.bin #CC2
+antC11=./usecase/lte_a/mu0_20mhz/ant_11.bin #CC2
+antC12=./usecase/lte_a/mu0_20mhz/ant_12.bin #CC3
+antC13=./usecase/lte_a/mu0_20mhz/ant_13.bin #CC3
+antC14=./usecase/lte_a/mu0_20mhz/ant_14.bin #CC3
+antC15=./usecase/lte_a/mu0_20mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/lte_a/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/lte_a/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/lte_a/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/lte_a/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/lte_a/mu0_20mhz/ant_4.bin #CC1
+antC5=./usecase/lte_a/mu0_20mhz/ant_5.bin #CC1
+antC6=./usecase/lte_a/mu0_20mhz/ant_6.bin #CC1
+antC7=./usecase/lte_a/mu0_20mhz/ant_7.bin #CC1
+antC8=./usecase/lte_a/mu0_20mhz/ant_8.bin #CC2
+antC9=./usecase/lte_a/mu0_20mhz/ant_9.bin #CC2
+antC10=./usecase/lte_a/mu0_20mhz/ant_10.bin #CC2
+antC11=./usecase/lte_a/mu0_20mhz/ant_11.bin #CC2
+antC12=./usecase/lte_a/mu0_20mhz/ant_12.bin #CC3
+antC13=./usecase/lte_a/mu0_20mhz/ant_13.bin #CC3
+antC14=./usecase/lte_a/mu0_20mhz/ant_14.bin #CC3
+antC15=./usecase/lte_a/mu0_20mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/lte_a/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/lte_a/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/lte_a/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/lte_a/mu0_5mhz/ant_3.bin #CC0
+antC4=./usecase/lte_a/mu0_5mhz/ant_4.bin #CC1
+antC5=./usecase/lte_a/mu0_5mhz/ant_5.bin #CC1
+antC6=./usecase/lte_a/mu0_5mhz/ant_6.bin #CC1
+antC7=./usecase/lte_a/mu0_5mhz/ant_7.bin #CC1
+antC8=./usecase/lte_a/mu0_5mhz/ant_8.bin #CC2
+antC9=./usecase/lte_a/mu0_5mhz/ant_9.bin #CC2
+antC10=./usecase/lte_a/mu0_5mhz/ant_10.bin #CC2
+antC11=./usecase/lte_a/mu0_5mhz/ant_11.bin #CC2
+antC12=./usecase/lte_a/mu0_5mhz/ant_12.bin #CC3
+antC13=./usecase/lte_a/mu0_5mhz/ant_13.bin #CC3
+antC14=./usecase/lte_a/mu0_5mhz/ant_14.bin #CC3
+antC15=./usecase/lte_a/mu0_5mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/lte_a/mu0_5mhz/ant_0.bin #CC0
+antC1=./usecase/lte_a/mu0_5mhz/ant_1.bin #CC0
+antC2=./usecase/lte_a/mu0_5mhz/ant_2.bin #CC0
+antC3=./usecase/lte_a/mu0_5mhz/ant_3.bin #CC0
+antC4=./usecase/lte_a/mu0_5mhz/ant_4.bin #CC1
+antC5=./usecase/lte_a/mu0_5mhz/ant_5.bin #CC1
+antC6=./usecase/lte_a/mu0_5mhz/ant_6.bin #CC1
+antC7=./usecase/lte_a/mu0_5mhz/ant_7.bin #CC1
+antC8=./usecase/lte_a/mu0_5mhz/ant_8.bin #CC2
+antC9=./usecase/lte_a/mu0_5mhz/ant_9.bin #CC2
+antC10=./usecase/lte_a/mu0_5mhz/ant_10.bin #CC2
+antC11=./usecase/lte_a/mu0_5mhz/ant_11.bin #CC2
+antC12=./usecase/lte_a/mu0_5mhz/ant_12.bin #CC3
+antC13=./usecase/lte_a/mu0_5mhz/ant_13.bin #CC3
+antC14=./usecase/lte_a/mu0_5mhz/ant_14.bin #CC3
+antC15=./usecase/lte_a/mu0_5mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+antPrachC0=./usecase/lte_a/mu0_5mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_5mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_5mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_5mhz/ant_3.bin
+
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioWorker=0x2000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1
+antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1
+antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1
+antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1
+antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2
+antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2
+antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2
+antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2
+antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3
+antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3
+antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3
+antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,25,0,14,1,1,1,9,1
+PrbElemDl1=25,25,0,14,2,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,25,0,14,1,1,1,9,1
+PrbElemUl1=25,25,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioWorker=0x40000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1
+antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1
+antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1
+antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1
+antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2
+antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2
+antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2
+antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2
+antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3
+antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3
+antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3
+antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+
+antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_10mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_10mhz/ant_3.bin
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,25,0,14,1,1,1,9,1
+PrbElemDl1=25,25,0,14,2,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,25,0,14,1,1,1,9,1
+PrbElemUl1=25,25,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioWorker=0x2000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/lte_b/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/lte_b/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/lte_b/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/lte_b/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/lte_b/mu0_20mhz/ant_4.bin #CC1
+antC5=./usecase/lte_b/mu0_20mhz/ant_5.bin #CC1
+antC6=./usecase/lte_b/mu0_20mhz/ant_6.bin #CC1
+antC7=./usecase/lte_b/mu0_20mhz/ant_7.bin #CC1
+antC8=./usecase/lte_b/mu0_20mhz/ant_8.bin #CC2
+antC9=./usecase/lte_b/mu0_20mhz/ant_9.bin #CC2
+antC10=./usecase/lte_b/mu0_20mhz/ant_10.bin #CC2
+antC11=./usecase/lte_b/mu0_20mhz/ant_11.bin #CC2
+antC12=./usecase/lte_b/mu0_20mhz/ant_12.bin #CC3
+antC13=./usecase/lte_b/mu0_20mhz/ant_13.bin #CC3
+antC14=./usecase/lte_b/mu0_20mhz/ant_14.bin #CC3
+antC15=./usecase/lte_b/mu0_20mhz/ant_15.bin #CC3
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,50,0,14,1,1,1,9,1
+PrbElemDl1=50,50,0,14,2,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,50,0,14,1,1,1,9,1
+PrbElemUl1=50,50,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=2048
+nULFftSize=2048
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioWorker=0x40000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/lte_b/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/lte_b/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/lte_b/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/lte_b/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/lte_b/mu0_20mhz/ant_4.bin #CC1
+antC5=./usecase/lte_b/mu0_20mhz/ant_5.bin #CC1
+antC6=./usecase/lte_b/mu0_20mhz/ant_6.bin #CC1
+antC7=./usecase/lte_b/mu0_20mhz/ant_7.bin #CC1
+antC8=./usecase/lte_b/mu0_20mhz/ant_8.bin #CC2
+antC9=./usecase/lte_b/mu0_20mhz/ant_9.bin #CC2
+antC10=./usecase/lte_b/mu0_20mhz/ant_10.bin #CC2
+antC11=./usecase/lte_b/mu0_20mhz/ant_11.bin #CC2
+antC12=./usecase/lte_b/mu0_20mhz/ant_12.bin #CC3
+antC13=./usecase/lte_b/mu0_20mhz/ant_13.bin #CC3
+antC14=./usecase/lte_b/mu0_20mhz/ant_14.bin #CC3
+antC15=./usecase/lte_b/mu0_20mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+
+antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,50,0,14,1,1,1,9,1
+PrbElemDl1=50,50,0,14,2,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,50,0,14,1,1,1,9,1
+PrbElemUl1=50,50,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU (0) | RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+ioWorker=0x2000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1
+antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1
+antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1
+antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1
+antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2
+antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2
+antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2
+antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2
+antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3
+antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3
+antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3
+antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
+#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)]
+DlBfwUe0=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe1=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe2=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe3=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe4=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe5=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe6=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe7=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe8=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe9=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe10=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe11=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe12=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe13=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe14=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+DlBfwUe15=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)]
+UlBfwUe0=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe1=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe2=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe3=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe4=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe5=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe6=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe7=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe8=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe9=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe10=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe11=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe12=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe13=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe14=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
+UlBfwUe15=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
+
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+#rachOffset=43 # RB offset for prach detection (see RIU spec)
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,15,0,14,1,1,1,9,1
+PrbElemDl1=15,10,0,14,2,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,15,0,14,1,1,1,9,1
+PrbElemUl1=15,10,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranRanTech=1 # 5G NR (0) | LTE (1)
+xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B
+antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R
+
+#UEs
+muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources
+DlLayersPerUe=1 #number of RX anntennas on DL UE side
+UlLayersPerUe=1 #number of TX anntennas on UL UE side
+##Numerology
+mu=0 #15Khz Sub Carrier Spacing
+ttiPeriod=1000 # in us TTI period (15Khz default 1000us)
+nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=512
+nULFftSize=512
+
+nFrameDuplexType=0 # 0 - FDD 1 - TDD
+nTddPeriod=0 #TDD priod e.g. DDDS 4
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+ioWorker=0x40000000 # mask [0- no workers]
+ioSleep=1
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1
+antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1
+antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1
+antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1
+antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2
+antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2
+antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2
+antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2
+antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3
+antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3
+antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3
+antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3
+
+## RACH TODO: update for PRACH
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+
+antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin
+antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin
+antPrachC2=./usecase/lte_a/mu0_10mhz/ant_2.bin
+antPrachC3=./usecase/lte_a/mu0_10mhz/ant_3.bin
+#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+prachConfigIndex=189
+
+srsEanble=0 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,15,0,14,1,1,1,9,1
+PrbElemDl1=15,10,0,14,2,1,1,9,1
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,15,0,14,1,1,1,9,1
+PrbElemUl1=15,10,0,14,2,1,1,9,1
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+#CID settings
+DU_Port_ID_bitwidth=2
+BandSector_ID_bitwidth=3
+CC_ID_bitwidth=3
+RU_Port_ID_bitwidth=8
+
+# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF
+# O-RAN.WG4.IOT.0-v02.00
+# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF
+
+#U-plane
+##Transmission Window
+T1a_max_up=437
+T1a_min_up=366
+
+#Reception Window U-plane
+T2a_max_up=437
+T2a_min_up=206
+
+Tadv_cp_dl=125
+
+#Transmission Window
+Ta3_max=232 #in us
+Ta3_min=70 #in us
+
+#Reception Window
+Ta4_max=392
+Ta4_min=70
+
+##Transmission Window Fast C-plane UL
+T1a_max_cp_ul=356
+T1a_min_cp_ul=285
+
+#Reception Window C-plane UL
+T2a_max_cp_ul=356 #in us
+T2a_min_cp_ul=125 #in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B
+T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B
+
+#O-RU Reception Window C-plane DL
+T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B
+T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B
+###########################################################
+
# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
appMode=0 # lls-CU(0) | RU(1)
xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=0 #15Khz Sub Carrier Spacing
nFrameDuplexType=0 # 0 - FDD 1 - TDD
nTddPeriod=0 #TDD priod e.g. DDDS 4
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
+ioCore=5
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
-antC0=./usecase/mu0_10mhz/12/ant_0.bin #CC0
-antC1=./usecase/mu0_10mhz/12/ant_1.bin #CC0
-antC2=./usecase/mu0_10mhz/12/ant_2.bin #CC0
-antC3=./usecase/mu0_10mhz/12/ant_3.bin #CC0
-antC4=./usecase/mu0_10mhz/12/ant_4.bin #CC1
-antC5=./usecase/mu0_10mhz/12/ant_5.bin #CC1
-antC6=./usecase/mu0_10mhz/12/ant_6.bin #CC1
-antC7=./usecase/mu0_10mhz/12/ant_7.bin #CC1
-antC8=./usecase/mu0_10mhz/12/ant_8.bin #CC2
-antC9=./usecase/mu0_10mhz/12/ant_9.bin #CC2
-antC10=./usecase/mu0_10mhz/12/ant_10.bin #CC2
-antC11=./usecase/mu0_10mhz/12/ant_11.bin #CC2
-antC12=./usecase/mu0_10mhz/12/ant_12.bin #CC3
-antC13=./usecase/mu0_10mhz/12/ant_13.bin #CC3
-antC14=./usecase/mu0_10mhz/12/ant_14.bin #CC3
-antC15=./usecase/mu0_10mhz/12/ant_15.bin #CC3
-antC16=./usecase/mu0_10mhz/12/ant_0.bin #CC4
-antC17=./usecase/mu0_10mhz/12/ant_1.bin #CC4
-antC18=./usecase/mu0_10mhz/12/ant_2.bin #CC4
-antC19=./usecase/mu0_10mhz/12/ant_3.bin #CC4
-antC20=./usecase/mu0_10mhz/12/ant_4.bin #CC5
-antC21=./usecase/mu0_10mhz/12/ant_5.bin #CC5
-antC22=./usecase/mu0_10mhz/12/ant_6.bin #CC5
-antC23=./usecase/mu0_10mhz/12/ant_7.bin #CC5
-antC24=./usecase/mu0_10mhz/12/ant_8.bin #CC6
-antC25=./usecase/mu0_10mhz/12/ant_9.bin #CC6
-antC26=./usecase/mu0_10mhz/12/ant_10.bin #CC6
-antC27=./usecase/mu0_10mhz/12/ant_11.bin #CC6
-antC28=./usecase/mu0_10mhz/12/ant_12.bin #CC7
-antC29=./usecase/mu0_10mhz/12/ant_13.bin #CC7
-antC30=./usecase/mu0_10mhz/12/ant_14.bin #CC7
-antC31=./usecase/mu0_10mhz/12/ant_15.bin #CC7
-antC32=./usecase/mu0_10mhz/12/ant_0.bin #CC8
-antC33=./usecase/mu0_10mhz/12/ant_1.bin #CC8
-antC34=./usecase/mu0_10mhz/12/ant_2.bin #CC8
-antC35=./usecase/mu0_10mhz/12/ant_3.bin #CC8
-antC36=./usecase/mu0_10mhz/12/ant_4.bin #CC9
-antC37=./usecase/mu0_10mhz/12/ant_5.bin #CC9
-antC38=./usecase/mu0_10mhz/12/ant_6.bin #CC9
-antC39=./usecase/mu0_10mhz/12/ant_7.bin #CC9
-antC40=./usecase/mu0_10mhz/12/ant_8.bin #CC10
-antC41=./usecase/mu0_10mhz/12/ant_9.bin #CC10
-antC42=./usecase/mu0_10mhz/12/ant_10.bin #CC10
-antC43=./usecase/mu0_10mhz/12/ant_11.bin #CC10
-antC44=./usecase/mu0_10mhz/12/ant_12.bin #CC11
-antC45=./usecase/mu0_10mhz/12/ant_13.bin #CC11
-antC46=./usecase/mu0_10mhz/12/ant_14.bin #CC11
-antC47=./usecase/mu0_10mhz/12/ant_15.bin #CC11
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+antC0=./usecase/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/mu0_10mhz/ant_0.bin #CC1
+antC5=./usecase/mu0_10mhz/ant_1.bin #CC1
+antC6=./usecase/mu0_10mhz/ant_2.bin #CC1
+antC7=./usecase/mu0_10mhz/ant_3.bin #CC1
+antC8=./usecase/mu0_10mhz/ant_0.bin #CC2
+antC9=./usecase/mu0_10mhz/ant_1.bin #CC2
+antC10=./usecase/mu0_10mhz/ant_2.bin #CC2
+antC11=./usecase/mu0_10mhz/ant_3.bin #CC2
+antC12=./usecase/mu0_10mhz/ant_0.bin #CC3
+antC13=./usecase/mu0_10mhz/ant_1.bin #CC3
+antC14=./usecase/mu0_10mhz/ant_2.bin #CC3
+antC15=./usecase/mu0_10mhz/ant_3.bin #CC3
+antC16=./usecase/mu0_10mhz/ant_0.bin #CC4
+antC17=./usecase/mu0_10mhz/ant_1.bin #CC4
+antC18=./usecase/mu0_10mhz/ant_2.bin #CC4
+antC19=./usecase/mu0_10mhz/ant_3.bin #CC4
+antC20=./usecase/mu0_10mhz/ant_0.bin #CC5
+antC21=./usecase/mu0_10mhz/ant_1.bin #CC5
+antC22=./usecase/mu0_10mhz/ant_2.bin #CC5
+antC23=./usecase/mu0_10mhz/ant_3.bin #CC5
+antC24=./usecase/mu0_10mhz/ant_0.bin #CC6
+antC25=./usecase/mu0_10mhz/ant_1.bin #CC6
+antC26=./usecase/mu0_10mhz/ant_2.bin #CC6
+antC27=./usecase/mu0_10mhz/ant_3.bin #CC6
+antC28=./usecase/mu0_10mhz/ant_0.bin #CC7
+antC29=./usecase/mu0_10mhz/ant_1.bin #CC7
+antC30=./usecase/mu0_10mhz/ant_2.bin #CC7
+antC31=./usecase/mu0_10mhz/ant_3.bin #CC7
+antC32=./usecase/mu0_10mhz/ant_0.bin #CC8
+antC33=./usecase/mu0_10mhz/ant_1.bin #CC8
+antC34=./usecase/mu0_10mhz/ant_2.bin #CC8
+antC35=./usecase/mu0_10mhz/ant_3.bin #CC8
+antC36=./usecase/mu0_10mhz/ant_0.bin #CC9
+antC37=./usecase/mu0_10mhz/ant_1.bin #CC9
+antC38=./usecase/mu0_10mhz/ant_2.bin #CC9
+antC39=./usecase/mu0_10mhz/ant_3.bin #CC9
+antC40=./usecase/mu0_10mhz/ant_0.bin #CC10
+antC41=./usecase/mu0_10mhz/ant_1.bin #CC10
+antC42=./usecase/mu0_10mhz/ant_2.bin #CC10
+antC43=./usecase/mu0_10mhz/ant_3.bin #CC10
+antC44=./usecase/mu0_10mhz/ant_0.bin #CC11
+antC45=./usecase/mu0_10mhz/ant_1.bin #CC11
+antC46=./usecase/mu0_10mhz/ant_2.bin #CC11
+antC47=./usecase/mu0_10mhz/ant_3.bin #CC11
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
## control of IQ byte order
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
#C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=400 #in us
-T2a_max_cp_dl=1120 #in us
+T2a_min_cp_dl=400 #in us
+T2a_max_cp_dl=1120 #in us
#Reception Window C-plane UL
-T2a_min_cp_ul=400 #in us
-T2a_max_cp_ul=1120 #in us
+T2a_min_cp_ul=400 #in us
+T2a_max_cp_ul=1120 #in us
#Reception Window U-plane
T2a_min_up=200 # in us
# This is simple configuration file. Use '#' sign for comments
-appMode=1 # lls-CU(0) | RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4)
+ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=0 #15Khz Sub Carrier Spacing
nFrameDuplexType=0 # 0 - FDD 1 - TDD
nTddPeriod=0 #TDD priod e.g. DDDS 4
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70 #lls-CU PF for tcpdump
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+ioCore=10
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
-antC0=./usecase/mu0_10mhz/12/ant_0.bin #CC0
-antC1=./usecase/mu0_10mhz/12/ant_1.bin #CC0
-antC2=./usecase/mu0_10mhz/12/ant_2.bin #CC0
-antC3=./usecase/mu0_10mhz/12/ant_3.bin #CC0
-antC4=./usecase/mu0_10mhz/12/ant_4.bin #CC1
-antC5=./usecase/mu0_10mhz/12/ant_5.bin #CC1
-antC6=./usecase/mu0_10mhz/12/ant_6.bin #CC1
-antC7=./usecase/mu0_10mhz/12/ant_7.bin #CC1
-antC8=./usecase/mu0_10mhz/12/ant_8.bin #CC2
-antC9=./usecase/mu0_10mhz/12/ant_9.bin #CC2
-antC10=./usecase/mu0_10mhz/12/ant_10.bin #CC2
-antC11=./usecase/mu0_10mhz/12/ant_11.bin #CC2
-antC12=./usecase/mu0_10mhz/12/ant_12.bin #CC3
-antC13=./usecase/mu0_10mhz/12/ant_13.bin #CC3
-antC14=./usecase/mu0_10mhz/12/ant_14.bin #CC3
-antC15=./usecase/mu0_10mhz/12/ant_15.bin #CC3
-antC16=./usecase/mu0_10mhz/12/ant_0.bin #CC4
-antC17=./usecase/mu0_10mhz/12/ant_1.bin #CC4
-antC18=./usecase/mu0_10mhz/12/ant_2.bin #CC4
-antC19=./usecase/mu0_10mhz/12/ant_3.bin #CC4
-antC20=./usecase/mu0_10mhz/12/ant_4.bin #CC5
-antC21=./usecase/mu0_10mhz/12/ant_5.bin #CC5
-antC22=./usecase/mu0_10mhz/12/ant_6.bin #CC5
-antC23=./usecase/mu0_10mhz/12/ant_7.bin #CC5
-antC24=./usecase/mu0_10mhz/12/ant_8.bin #CC6
-antC25=./usecase/mu0_10mhz/12/ant_9.bin #CC6
-antC26=./usecase/mu0_10mhz/12/ant_10.bin #CC6
-antC27=./usecase/mu0_10mhz/12/ant_11.bin #CC6
-antC28=./usecase/mu0_10mhz/12/ant_12.bin #CC7
-antC29=./usecase/mu0_10mhz/12/ant_13.bin #CC7
-antC30=./usecase/mu0_10mhz/12/ant_14.bin #CC7
-antC31=./usecase/mu0_10mhz/12/ant_15.bin #CC7
-antC32=./usecase/mu0_10mhz/12/ant_0.bin #CC8
-antC33=./usecase/mu0_10mhz/12/ant_1.bin #CC8
-antC34=./usecase/mu0_10mhz/12/ant_2.bin #CC8
-antC35=./usecase/mu0_10mhz/12/ant_3.bin #CC8
-antC36=./usecase/mu0_10mhz/12/ant_4.bin #CC9
-antC37=./usecase/mu0_10mhz/12/ant_5.bin #CC9
-antC38=./usecase/mu0_10mhz/12/ant_6.bin #CC9
-antC39=./usecase/mu0_10mhz/12/ant_7.bin #CC9
-antC40=./usecase/mu0_10mhz/12/ant_8.bin #CC10
-antC41=./usecase/mu0_10mhz/12/ant_9.bin #CC10
-antC42=./usecase/mu0_10mhz/12/ant_10.bin #CC10
-antC43=./usecase/mu0_10mhz/12/ant_11.bin #CC10
-antC44=./usecase/mu0_10mhz/12/ant_12.bin #CC11
-antC45=./usecase/mu0_10mhz/12/ant_13.bin #CC11
-antC46=./usecase/mu0_10mhz/12/ant_14.bin #CC11
-antC47=./usecase/mu0_10mhz/12/ant_15.bin #CC11
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+antC0=./usecase/mu0_10mhz/ant_0.bin #CC0
+antC1=./usecase/mu0_10mhz/ant_1.bin #CC0
+antC2=./usecase/mu0_10mhz/ant_2.bin #CC0
+antC3=./usecase/mu0_10mhz/ant_3.bin #CC0
+antC4=./usecase/mu0_10mhz/ant_0.bin #CC1
+antC5=./usecase/mu0_10mhz/ant_1.bin #CC1
+antC6=./usecase/mu0_10mhz/ant_2.bin #CC1
+antC7=./usecase/mu0_10mhz/ant_3.bin #CC1
+antC8=./usecase/mu0_10mhz/ant_0.bin #CC2
+antC9=./usecase/mu0_10mhz/ant_1.bin #CC2
+antC10=./usecase/mu0_10mhz/ant_2.bin #CC2
+antC11=./usecase/mu0_10mhz/ant_3.bin #CC2
+antC12=./usecase/mu0_10mhz/ant_0.bin #CC3
+antC13=./usecase/mu0_10mhz/ant_1.bin #CC3
+antC14=./usecase/mu0_10mhz/ant_2.bin #CC3
+antC15=./usecase/mu0_10mhz/ant_3.bin #CC3
+antC16=./usecase/mu0_10mhz/ant_0.bin #CC4
+antC17=./usecase/mu0_10mhz/ant_1.bin #CC4
+antC18=./usecase/mu0_10mhz/ant_2.bin #CC4
+antC19=./usecase/mu0_10mhz/ant_3.bin #CC4
+antC20=./usecase/mu0_10mhz/ant_0.bin #CC5
+antC21=./usecase/mu0_10mhz/ant_1.bin #CC5
+antC22=./usecase/mu0_10mhz/ant_2.bin #CC5
+antC23=./usecase/mu0_10mhz/ant_3.bin #CC5
+antC24=./usecase/mu0_10mhz/ant_0.bin #CC6
+antC25=./usecase/mu0_10mhz/ant_1.bin #CC6
+antC26=./usecase/mu0_10mhz/ant_2.bin #CC6
+antC27=./usecase/mu0_10mhz/ant_3.bin #CC6
+antC28=./usecase/mu0_10mhz/ant_0.bin #CC7
+antC29=./usecase/mu0_10mhz/ant_1.bin #CC7
+antC30=./usecase/mu0_10mhz/ant_2.bin #CC7
+antC31=./usecase/mu0_10mhz/ant_3.bin #CC7
+antC32=./usecase/mu0_10mhz/ant_0.bin #CC8
+antC33=./usecase/mu0_10mhz/ant_1.bin #CC8
+antC34=./usecase/mu0_10mhz/ant_2.bin #CC8
+antC35=./usecase/mu0_10mhz/ant_3.bin #CC8
+antC36=./usecase/mu0_10mhz/ant_0.bin #CC9
+antC37=./usecase/mu0_10mhz/ant_1.bin #CC9
+antC38=./usecase/mu0_10mhz/ant_2.bin #CC9
+antC39=./usecase/mu0_10mhz/ant_3.bin #CC9
+antC40=./usecase/mu0_10mhz/ant_0.bin #CC10
+antC41=./usecase/mu0_10mhz/ant_1.bin #CC10
+antC42=./usecase/mu0_10mhz/ant_2.bin #CC10
+antC43=./usecase/mu0_10mhz/ant_3.bin #CC10
+antC44=./usecase/mu0_10mhz/ant_0.bin #CC11
+antC45=./usecase/mu0_10mhz/ant_1.bin #CC11
+antC46=./usecase/mu0_10mhz/ant_2.bin #CC11
+antC47=./usecase/mu0_10mhz/ant_3.bin #CC11
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
-antPrachC0=./usecase/mu0_10mhz/12/ant_0.bin
-antPrachC1=./usecase/mu0_10mhz/12/ant_1.bin
-antPrachC2=./usecase/mu0_10mhz/12/ant_2.bin
-antPrachC3=./usecase/mu0_10mhz/12/ant_3.bin
-antPrachC4=./usecase/mu0_10mhz/12/ant_4.bin
-antPrachC5=./usecase/mu0_10mhz/12/ant_5.bin
-antPrachC6=./usecase/mu0_10mhz/12/ant_6.bin
-antPrachC7=./usecase/mu0_10mhz/12/ant_7.bin
-antPrachC8=./usecase/mu0_10mhz/12/ant_8.bin
-antPrachC9=./usecase/mu0_10mhz/12/ant_9.bin
-antPrachC10=./usecase/mu0_10mhz/12/ant_10.bin
-antPrachC11=./usecase/mu0_10mhz/12/ant_11.bin
-antPrachC12=./usecase/mu0_10mhz/12/ant_12.bin
-antPrachC13=./usecase/mu0_10mhz/12/ant_13.bin
-antPrachC14=./usecase/mu0_10mhz/12/ant_14.bin
-antPrachC15=./usecase/mu0_10mhz/12/ant_15.bin
-antPrachC16=./usecase/mu0_10mhz/12/ant_0.bin
-antPrachC17=./usecase/mu0_10mhz/12/ant_1.bin
-antPrachC18=./usecase/mu0_10mhz/12/ant_2.bin
-antPrachC19=./usecase/mu0_10mhz/12/ant_3.bin
-antPrachC20=./usecase/mu0_10mhz/12/ant_4.bin
-antPrachC21=./usecase/mu0_10mhz/12/ant_5.bin
-antPrachC22=./usecase/mu0_10mhz/12/ant_6.bin
-antPrachC23=./usecase/mu0_10mhz/12/ant_7.bin
-antPrachC24=./usecase/mu0_10mhz/12/ant_8.bin
-antPrachC25=./usecase/mu0_10mhz/12/ant_9.bin
-antPrachC26=./usecase/mu0_10mhz/12/ant_10.bin
-antPrachC27=./usecase/mu0_10mhz/12/ant_11.bin
-antPrachC28=./usecase/mu0_10mhz/12/ant_12.bin
-antPrachC29=./usecase/mu0_10mhz/12/ant_13.bin
-antPrachC30=./usecase/mu0_10mhz/12/ant_14.bin
-antPrachC31=./usecase/mu0_10mhz/12/ant_15.bin
-antPrachC32=./usecase/mu0_10mhz/12/ant_0.bin
-antPrachC33=./usecase/mu0_10mhz/12/ant_1.bin
-antPrachC34=./usecase/mu0_10mhz/12/ant_2.bin
-antPrachC35=./usecase/mu0_10mhz/12/ant_3.bin
-antPrachC36=./usecase/mu0_10mhz/12/ant_4.bin
-antPrachC37=./usecase/mu0_10mhz/12/ant_5.bin
-antPrachC38=./usecase/mu0_10mhz/12/ant_6.bin
-antPrachC39=./usecase/mu0_10mhz/12/ant_7.bin
-antPrachC40=./usecase/mu0_10mhz/12/ant_8.bin
-antPrachC41=./usecase/mu0_10mhz/12/ant_9.bin
-antPrachC42=./usecase/mu0_10mhz/12/ant_10.bin
-antPrachC43=./usecase/mu0_10mhz/12/ant_11.bin
-antPrachC44=./usecase/mu0_10mhz/12/ant_12.bin
-antPrachC45=./usecase/mu0_10mhz/12/ant_13.bin
-antPrachC46=./usecase/mu0_10mhz/12/ant_14.bin
-antPrachC47=./usecase/mu0_10mhz/12/ant_15.bin
+antPrachC0=./usecase/mu0_10mhz/ant_0.bin
+antPrachC1=./usecase/mu0_10mhz/ant_1.bin
+antPrachC2=./usecase/mu0_10mhz/ant_2.bin
+antPrachC3=./usecase/mu0_10mhz/ant_3.bin
+antPrachC4=./usecase/mu0_10mhz/ant_0.bin
+antPrachC5=./usecase/mu0_10mhz/ant_1.bin
+antPrachC6=./usecase/mu0_10mhz/ant_2.bin
+antPrachC7=./usecase/mu0_10mhz/ant_3.bin
+antPrachC8=./usecase/mu0_10mhz/ant_0.bin
+antPrachC9=./usecase/mu0_10mhz/ant_1.bin
+antPrachC10=./usecase/mu0_10mhz/ant_2.bin
+antPrachC11=./usecase/mu0_10mhz/ant_3.bin
+antPrachC12=./usecase/mu0_10mhz/ant_0.bin
+antPrachC13=./usecase/mu0_10mhz/ant_1.bin
+antPrachC14=./usecase/mu0_10mhz/ant_2.bin
+antPrachC15=./usecase/mu0_10mhz/ant_3.bin
+antPrachC16=./usecase/mu0_10mhz/ant_0.bin
+antPrachC17=./usecase/mu0_10mhz/ant_1.bin
+antPrachC18=./usecase/mu0_10mhz/ant_2.bin
+antPrachC19=./usecase/mu0_10mhz/ant_3.bin
+antPrachC20=./usecase/mu0_10mhz/ant_0.bin
+antPrachC21=./usecase/mu0_10mhz/ant_1.bin
+antPrachC22=./usecase/mu0_10mhz/ant_2.bin
+antPrachC23=./usecase/mu0_10mhz/ant_3.bin
+antPrachC24=./usecase/mu0_10mhz/ant_0.bin
+antPrachC25=./usecase/mu0_10mhz/ant_1.bin
+antPrachC26=./usecase/mu0_10mhz/ant_2.bin
+antPrachC27=./usecase/mu0_10mhz/ant_3.bin
+antPrachC28=./usecase/mu0_10mhz/ant_0.bin
+antPrachC29=./usecase/mu0_10mhz/ant_1.bin
+antPrachC30=./usecase/mu0_10mhz/ant_2.bin
+antPrachC31=./usecase/mu0_10mhz/ant_3.bin
+antPrachC32=./usecase/mu0_10mhz/ant_0.bin
+antPrachC33=./usecase/mu0_10mhz/ant_1.bin
+antPrachC34=./usecase/mu0_10mhz/ant_2.bin
+antPrachC35=./usecase/mu0_10mhz/ant_3.bin
+antPrachC36=./usecase/mu0_10mhz/ant_0.bin
+antPrachC37=./usecase/mu0_10mhz/ant_1.bin
+antPrachC38=./usecase/mu0_10mhz/ant_2.bin
+antPrachC39=./usecase/mu0_10mhz/ant_3.bin
+antPrachC40=./usecase/mu0_10mhz/ant_0.bin
+antPrachC41=./usecase/mu0_10mhz/ant_1.bin
+antPrachC42=./usecase/mu0_10mhz/ant_2.bin
+antPrachC43=./usecase/mu0_10mhz/ant_3.bin
+antPrachC44=./usecase/mu0_10mhz/ant_0.bin
+antPrachC45=./usecase/mu0_10mhz/ant_1.bin
+antPrachC46=./usecase/mu0_10mhz/ant_2.bin
+antPrachC47=./usecase/mu0_10mhz/ant_3.bin
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 #in us TODO: update per RU implementation
#C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=400 #in us
-T2a_max_cp_dl=1120 #in us
+T2a_min_cp_dl=400 #in us
+T2a_max_cp_dl=1120 #in us
#Reception Window C-plane UL
-T2a_min_cp_ul=400 #in us
-T2a_max_cp_ul=1120 #in us
+T2a_min_cp_ul=400 #in us
+T2a_max_cp_ul=1120 #in us
#Reception Window U-plane
T2a_min_up=200 # in us
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
Gps_Beta=0
ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
-CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
-#######################################################################
+#******************************************************************************
#
-# <COPYRIGHT_TAG>
+# Copyright (c) 2019 Intel.
#
-#######################################################################
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
appMode=0 # lls-CU(0) | RU(1)
xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4)
+ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=0 #15Khz Sub Carrier Spacing
nFrameDuplexType=0 # 0 - FDD 1 - TDD
nTddPeriod=0 #TDD priod e.g. DDDS 4
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
-
-numSlots=20 #number of slots per IQ files
-#fd 10Mhz 2
-#antC0=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC0=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC1=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC2=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC3=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC4=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC5=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC6=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC7=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC8=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC9=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC10=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC11=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC12=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC13=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC14=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC15=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC16=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC17=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC18=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC19=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC20=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC21=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC22=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC23=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC24=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC25=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC26=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC27=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC28=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC29=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC30=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC31=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC32=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC33=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC34=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC35=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC36=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC37=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC38=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC39=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC40=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC41=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC42=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC43=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC44=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC45=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC46=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC47=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-
-#antC0=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/ant_1.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/ant_2.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/ant_3.bin #CC0
-
-#antC0=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-
-#antC4=./usecase/mu0_20mhz/12/ant_4.bin #CC1
-#antC5=./usecase/mu0_20mhz/12/ant_5.bin #CC1
-#antC6=./usecase/mu0_20mhz/12/ant_6.bin #CC1
-#antC7=./usecase/mu0_20mhz/12/ant_7.bin #CC1
-#antC8=./usecase/mu0_20mhz/12/ant_8.bin #CC2
-#antC9=./usecase/mu0_20mhz/12/ant_9.bin #CC2
-#antC10=./usecase/mu0_20mhz/12/ant_10.bin #CC2
-#antC11=./usecase/mu0_20mhz/12/ant_11.bin #CC2
-#antC12=./usecase/mu0_20mhz/12/ant_12.bin #CC3
-#antC13=./usecase/mu0_20mhz/12/ant_13.bin #CC3
-#antC14=./usecase/mu0_20mhz/12/ant_14.bin #CC3
-#antC15=./usecase/mu0_20mhz/12/ant_15.bin #CC3
-#antC16=./usecase/mu0_20mhz/12/ant_0.bin #CC4
-#antC17=./usecase/mu0_20mhz/12/ant_1.bin #CC4
-#antC18=./usecase/mu0_20mhz/12/ant_2.bin #CC4
-#antC19=./usecase/mu0_20mhz/12/ant_3.bin #CC4
-#antC20=./usecase/mu0_20mhz/12/ant_4.bin #CC5
-#antC21=./usecase/mu0_20mhz/12/ant_5.bin #CC5
-#antC22=./usecase/mu0_20mhz/12/ant_6.bin #CC5
-#antC23=./usecase/mu0_20mhz/12/ant_7.bin #CC5
-#antC24=./usecase/mu0_20mhz/12/ant_8.bin #CC6
-#antC25=./usecase/mu0_20mhz/12/ant_9.bin #CC6
-#antC26=./usecase/mu0_20mhz/12/ant_10.bin #CC6
-#antC27=./usecase/mu0_20mhz/12/ant_11.bin #CC6
-#antC28=./usecase/mu0_20mhz/12/ant_12.bin #CC7
-#antC29=./usecase/mu0_20mhz/12/ant_13.bin #CC7
-#antC30=./usecase/mu0_20mhz/12/ant_14.bin #CC7
-#antC31=./usecase/mu0_20mhz/12/ant_15.bin #CC7
-#antC32=./usecase/mu0_20mhz/12/ant_0.bin #CC8
-#antC33=./usecase/mu0_20mhz/12/ant_1.bin #CC8
-#antC34=./usecase/mu0_20mhz/12/ant_2.bin #CC8
-#antC35=./usecase/mu0_20mhz/12/ant_3.bin #CC8
-#antC36=./usecase/mu0_20mhz/12/ant_4.bin #CC9
-#antC37=./usecase/mu0_20mhz/12/ant_5.bin #CC9
-#antC38=./usecase/mu0_20mhz/12/ant_6.bin #CC9
-#antC39=./usecase/mu0_20mhz/12/ant_7.bin #CC9
-#antC40=./usecase/mu0_20mhz/12/ant_8.bin #CC10
-#antC41=./usecase/mu0_20mhz/12/ant_9.bin #CC10
-#antC42=./usecase/mu0_20mhz/12/ant_10.bin #CC10
-#antC43=./usecase/mu0_20mhz/12/ant_11.bin #CC10
-#antC44=./usecase/mu0_20mhz/12/ant_12.bin #CC11
-#antC45=./usecase/mu0_20mhz/12/ant_13.bin #CC11
-#antC46=./usecase/mu0_20mhz/12/ant_14.bin #CC11
-#antC47=./usecase/mu0_20mhz/12/ant_15.bin #CC11
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+
+antC0=./usecase/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/mu0_20mhz/ant_0.bin #CC1
+antC5=./usecase/mu0_20mhz/ant_1.bin #CC1
+antC6=./usecase/mu0_20mhz/ant_2.bin #CC1
+antC7=./usecase/mu0_20mhz/ant_3.bin #CC1
+antC8=./usecase/mu0_20mhz/ant_0.bin #CC2
+antC9=./usecase/mu0_20mhz/ant_1.bin #CC2
+antC10=./usecase/mu0_20mhz/ant_2.bin #CC2
+antC11=./usecase/mu0_20mhz/ant_3.bin #CC2
+antC12=./usecase/mu0_20mhz/ant_0.bin #CC3
+antC13=./usecase/mu0_20mhz/ant_1.bin #CC3
+antC14=./usecase/mu0_20mhz/ant_2.bin #CC3
+antC15=./usecase/mu0_20mhz/ant_3.bin #CC3
+antC16=./usecase/mu0_20mhz/ant_0.bin #CC4
+antC17=./usecase/mu0_20mhz/ant_1.bin #CC4
+antC18=./usecase/mu0_20mhz/ant_2.bin #CC4
+antC19=./usecase/mu0_20mhz/ant_3.bin #CC4
+antC20=./usecase/mu0_20mhz/ant_0.bin #CC5
+antC21=./usecase/mu0_20mhz/ant_1.bin #CC5
+antC22=./usecase/mu0_20mhz/ant_2.bin #CC5
+antC23=./usecase/mu0_20mhz/ant_3.bin #CC5
+antC24=./usecase/mu0_20mhz/ant_0.bin #CC6
+antC25=./usecase/mu0_20mhz/ant_1.bin #CC6
+antC26=./usecase/mu0_20mhz/ant_2.bin #CC6
+antC27=./usecase/mu0_20mhz/ant_3.bin #CC6
+antC28=./usecase/mu0_20mhz/ant_0.bin #CC7
+antC29=./usecase/mu0_20mhz/ant_1.bin #CC7
+antC30=./usecase/mu0_20mhz/ant_2.bin #CC7
+antC31=./usecase/mu0_20mhz/ant_3.bin #CC7
+antC32=./usecase/mu0_20mhz/ant_0.bin #CC8
+antC33=./usecase/mu0_20mhz/ant_1.bin #CC8
+antC34=./usecase/mu0_20mhz/ant_2.bin #CC8
+antC35=./usecase/mu0_20mhz/ant_3.bin #CC8
+antC36=./usecase/mu0_20mhz/ant_0.bin #CC9
+antC37=./usecase/mu0_20mhz/ant_1.bin #CC9
+antC38=./usecase/mu0_20mhz/ant_2.bin #CC9
+antC39=./usecase/mu0_20mhz/ant_3.bin #CC9
+antC40=./usecase/mu0_20mhz/ant_0.bin #CC10
+antC41=./usecase/mu0_20mhz/ant_1.bin #CC10
+antC42=./usecase/mu0_20mhz/ant_2.bin #CC10
+antC43=./usecase/mu0_20mhz/ant_3.bin #CC10
+antC44=./usecase/mu0_20mhz/ant_0.bin #CC11
+antC45=./usecase/mu0_20mhz/ant_1.bin #CC11
+antC46=./usecase/mu0_20mhz/ant_2.bin #CC11
+antC47=./usecase/mu0_20mhz/ant_3.bin #CC11
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,75,0,14,0,1,0,16,1
+nPrbElemUl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,75,0,14,0,1,0,16,1
+###########################################################
+
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
##Debug
-debugStop=0 #stop app on 1pps boundary (gps_second % 30)
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
Tadv_cp_dl=25 #in us TODO: update per RU implementation
#C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=400 #in us
-T2a_max_cp_dl=1120 #in us
+T2a_min_cp_dl=400 #in us
+T2a_max_cp_dl=1120 #in us
#Reception Window C-plane UL
-T2a_min_cp_ul=400 #in us
-T2a_max_cp_ul=1120 #in us
+T2a_min_cp_ul=400 #in us
+T2a_max_cp_ul=1120 #in us
#Reception Window U-plane
T2a_min_up=200 # in us
ioCore=5
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
#fd 10Mhz 2
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=45
-
-llsCUMac=00:11:22:33:44:77 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:44 #RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
+ioCore=15
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
#fd 10Mhz 2
-#######################################################################
+#******************************************************************************
#
-# <COPYRIGHT_TAG>
+# Copyright (c) 2019 Intel.
#
-#######################################################################
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
-appMode=1 # lls-CU(0) | RU(1)
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4)
+ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=0 #15Khz Sub Carrier Spacing
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70 #lls-CU PF for tcpdump
-ruMac=00:11:22:33:44:55 #RU VF for RU app
-
-numSlots=20 #number of slots per IQ files
-#fd 10Mhz 2
-#antC0=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC0=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC1=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC2=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC3=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC4=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC5=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC6=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC7=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC8=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC9=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC10=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC11=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC12=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC13=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC14=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC15=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC16=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC17=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC18=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC19=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC20=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC21=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC22=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC23=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC24=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC25=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC26=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC27=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC28=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC29=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC30=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC31=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC32=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC33=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC34=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC35=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC36=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC37=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC38=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC39=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC40=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC41=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC42=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC43=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC44=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC45=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC46=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC47=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-
-#antC0=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/ant_1.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/ant_2.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/ant_3.bin #CC0
-
-#antC0=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-
-#antC4=./usecase/mu0_20mhz/12/ant_4.bin #CC1
-#antC5=./usecase/mu0_20mhz/12/ant_5.bin #CC1
-#antC6=./usecase/mu0_20mhz/12/ant_6.bin #CC1
-#antC7=./usecase/mu0_20mhz/12/ant_7.bin #CC1
-#antC8=./usecase/mu0_20mhz/12/ant_8.bin #CC2
-#antC9=./usecase/mu0_20mhz/12/ant_9.bin #CC2
-#antC10=./usecase/mu0_20mhz/12/ant_10.bin #CC2
-#antC11=./usecase/mu0_20mhz/12/ant_11.bin #CC2
-#antC12=./usecase/mu0_20mhz/12/ant_12.bin #CC3
-#antC13=./usecase/mu0_20mhz/12/ant_13.bin #CC3
-#antC14=./usecase/mu0_20mhz/12/ant_14.bin #CC3
-#antC15=./usecase/mu0_20mhz/12/ant_15.bin #CC3
-#antC16=./usecase/mu0_20mhz/12/ant_0.bin #CC4
-#antC17=./usecase/mu0_20mhz/12/ant_1.bin #CC4
-#antC18=./usecase/mu0_20mhz/12/ant_2.bin #CC4
-#antC19=./usecase/mu0_20mhz/12/ant_3.bin #CC4
-#antC20=./usecase/mu0_20mhz/12/ant_4.bin #CC5
-#antC21=./usecase/mu0_20mhz/12/ant_5.bin #CC5
-#antC22=./usecase/mu0_20mhz/12/ant_6.bin #CC5
-#antC23=./usecase/mu0_20mhz/12/ant_7.bin #CC5
-#antC24=./usecase/mu0_20mhz/12/ant_8.bin #CC6
-#antC25=./usecase/mu0_20mhz/12/ant_9.bin #CC6
-#antC26=./usecase/mu0_20mhz/12/ant_10.bin #CC6
-#antC27=./usecase/mu0_20mhz/12/ant_11.bin #CC6
-#antC28=./usecase/mu0_20mhz/12/ant_12.bin #CC7
-#antC29=./usecase/mu0_20mhz/12/ant_13.bin #CC7
-#antC30=./usecase/mu0_20mhz/12/ant_14.bin #CC7
-#antC31=./usecase/mu0_20mhz/12/ant_15.bin #CC7
-#antC32=./usecase/mu0_20mhz/12/ant_0.bin #CC8
-#antC33=./usecase/mu0_20mhz/12/ant_1.bin #CC8
-#antC34=./usecase/mu0_20mhz/12/ant_2.bin #CC8
-#antC35=./usecase/mu0_20mhz/12/ant_3.bin #CC8
-#antC36=./usecase/mu0_20mhz/12/ant_4.bin #CC9
-#antC37=./usecase/mu0_20mhz/12/ant_5.bin #CC9
-#antC38=./usecase/mu0_20mhz/12/ant_6.bin #CC9
-#antC39=./usecase/mu0_20mhz/12/ant_7.bin #CC9
-#antC40=./usecase/mu0_20mhz/12/ant_8.bin #CC10
-#antC41=./usecase/mu0_20mhz/12/ant_9.bin #CC10
-#antC42=./usecase/mu0_20mhz/12/ant_10.bin #CC10
-#antC43=./usecase/mu0_20mhz/12/ant_11.bin #CC10
-#antC44=./usecase/mu0_20mhz/12/ant_12.bin #CC11
-#antC45=./usecase/mu0_20mhz/12/ant_13.bin #CC11
-#antC46=./usecase/mu0_20mhz/12/ant_14.bin #CC11
-#antC47=./usecase/mu0_20mhz/12/ant_15.bin #CC11
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+ioCore=15
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+
+antC0=./usecase/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/mu0_20mhz/ant_0.bin #CC1
+antC5=./usecase/mu0_20mhz/ant_1.bin #CC1
+antC6=./usecase/mu0_20mhz/ant_2.bin #CC1
+antC7=./usecase/mu0_20mhz/ant_3.bin #CC1
+antC8=./usecase/mu0_20mhz/ant_0.bin #CC2
+antC9=./usecase/mu0_20mhz/ant_1.bin #CC2
+antC10=./usecase/mu0_20mhz/ant_2.bin #CC2
+antC11=./usecase/mu0_20mhz/ant_3.bin #CC2
+antC12=./usecase/mu0_20mhz/ant_0.bin #CC3
+antC13=./usecase/mu0_20mhz/ant_1.bin #CC3
+antC14=./usecase/mu0_20mhz/ant_2.bin #CC3
+antC15=./usecase/mu0_20mhz/ant_3.bin #CC3
+antC16=./usecase/mu0_20mhz/ant_0.bin #CC4
+antC17=./usecase/mu0_20mhz/ant_1.bin #CC4
+antC18=./usecase/mu0_20mhz/ant_2.bin #CC4
+antC19=./usecase/mu0_20mhz/ant_3.bin #CC4
+antC20=./usecase/mu0_20mhz/ant_0.bin #CC5
+antC21=./usecase/mu0_20mhz/ant_1.bin #CC5
+antC22=./usecase/mu0_20mhz/ant_2.bin #CC5
+antC23=./usecase/mu0_20mhz/ant_3.bin #CC5
+antC24=./usecase/mu0_20mhz/ant_0.bin #CC6
+antC25=./usecase/mu0_20mhz/ant_1.bin #CC6
+antC26=./usecase/mu0_20mhz/ant_2.bin #CC6
+antC27=./usecase/mu0_20mhz/ant_3.bin #CC6
+antC28=./usecase/mu0_20mhz/ant_0.bin #CC7
+antC29=./usecase/mu0_20mhz/ant_1.bin #CC7
+antC30=./usecase/mu0_20mhz/ant_2.bin #CC7
+antC31=./usecase/mu0_20mhz/ant_3.bin #CC7
+antC32=./usecase/mu0_20mhz/ant_0.bin #CC8
+antC33=./usecase/mu0_20mhz/ant_1.bin #CC8
+antC34=./usecase/mu0_20mhz/ant_2.bin #CC8
+antC35=./usecase/mu0_20mhz/ant_3.bin #CC8
+antC36=./usecase/mu0_20mhz/ant_0.bin #CC9
+antC37=./usecase/mu0_20mhz/ant_1.bin #CC9
+antC38=./usecase/mu0_20mhz/ant_2.bin #CC9
+antC39=./usecase/mu0_20mhz/ant_3.bin #CC9
+antC40=./usecase/mu0_20mhz/ant_0.bin #CC10
+antC41=./usecase/mu0_20mhz/ant_1.bin #CC10
+antC42=./usecase/mu0_20mhz/ant_2.bin #CC10
+antC43=./usecase/mu0_20mhz/ant_3.bin #CC10
+antC44=./usecase/mu0_20mhz/ant_0.bin #CC11
+antC45=./usecase/mu0_20mhz/ant_1.bin #CC11
+antC46=./usecase/mu0_20mhz/ant_2.bin #CC11
+antC47=./usecase/mu0_20mhz/ant_3.bin #CC11
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
-antPrachC0=./usecase/mu0_20mhz/12/ant_0.bin
-antPrachC1=./usecase/mu0_20mhz/12/ant_1.bin
-antPrachC2=./usecase/mu0_20mhz/12/ant_2.bin
-antPrachC3=./usecase/mu0_20mhz/12/ant_3.bin
-antPrachC4=./usecase/mu0_20mhz/12/ant_4.bin
-antPrachC5=./usecase/mu0_20mhz/12/ant_5.bin
-antPrachC6=./usecase/mu0_20mhz/12/ant_6.bin
-antPrachC7=./usecase/mu0_20mhz/12/ant_7.bin
-antPrachC8=./usecase/mu0_20mhz/12/ant_8.bin
-antPrachC9=./usecase/mu0_20mhz/12/ant_9.bin
-antPrachC10=./usecase/mu0_20mhz/12/ant_10.bin
-antPrachC11=./usecase/mu0_20mhz/12/ant_11.bin
-antPrachC12=./usecase/mu0_20mhz/12/ant_12.bin
-antPrachC13=./usecase/mu0_20mhz/12/ant_13.bin
-antPrachC14=./usecase/mu0_20mhz/12/ant_14.bin
-antPrachC15=./usecase/mu0_20mhz/12/ant_15.bin
-antPrachC16=./usecase/mu0_20mhz/12/ant_0.bin
-antPrachC17=./usecase/mu0_20mhz/12/ant_1.bin
-antPrachC18=./usecase/mu0_20mhz/12/ant_2.bin
-antPrachC19=./usecase/mu0_20mhz/12/ant_3.bin
-antPrachC20=./usecase/mu0_20mhz/12/ant_4.bin
-antPrachC21=./usecase/mu0_20mhz/12/ant_5.bin
-antPrachC22=./usecase/mu0_20mhz/12/ant_6.bin
-antPrachC23=./usecase/mu0_20mhz/12/ant_7.bin
-antPrachC24=./usecase/mu0_20mhz/12/ant_8.bin
-antPrachC25=./usecase/mu0_20mhz/12/ant_9.bin
-antPrachC26=./usecase/mu0_20mhz/12/ant_10.bin
-antPrachC27=./usecase/mu0_20mhz/12/ant_11.bin
-antPrachC28=./usecase/mu0_20mhz/12/ant_12.bin
-antPrachC29=./usecase/mu0_20mhz/12/ant_13.bin
-antPrachC30=./usecase/mu0_20mhz/12/ant_14.bin
-antPrachC31=./usecase/mu0_20mhz/12/ant_15.bin
-antPrachC32=./usecase/mu0_20mhz/12/ant_0.bin
-antPrachC33=./usecase/mu0_20mhz/12/ant_1.bin
-antPrachC34=./usecase/mu0_20mhz/12/ant_2.bin
-antPrachC35=./usecase/mu0_20mhz/12/ant_3.bin
-antPrachC36=./usecase/mu0_20mhz/12/ant_4.bin
-antPrachC37=./usecase/mu0_20mhz/12/ant_5.bin
-antPrachC38=./usecase/mu0_20mhz/12/ant_6.bin
-antPrachC39=./usecase/mu0_20mhz/12/ant_7.bin
-antPrachC40=./usecase/mu0_20mhz/12/ant_8.bin
-antPrachC41=./usecase/mu0_20mhz/12/ant_9.bin
-antPrachC42=./usecase/mu0_20mhz/12/ant_10.bin
-antPrachC43=./usecase/mu0_20mhz/12/ant_11.bin
-antPrachC44=./usecase/mu0_20mhz/12/ant_12.bin
-antPrachC45=./usecase/mu0_20mhz/12/ant_13.bin
-antPrachC46=./usecase/mu0_20mhz/12/ant_14.bin
-antPrachC47=./usecase/mu0_20mhz/12/ant_15.bin
+antPrachC0=./usecase/mu0_20mhz/ant_0.bin
+antPrachC1=./usecase/mu0_20mhz/ant_1.bin
+antPrachC2=./usecase/mu0_20mhz/ant_2.bin
+antPrachC3=./usecase/mu0_20mhz/ant_3.bin
+antPrachC4=./usecase/mu0_20mhz/ant_0.bin
+antPrachC5=./usecase/mu0_20mhz/ant_1.bin
+antPrachC6=./usecase/mu0_20mhz/ant_2.bin
+antPrachC7=./usecase/mu0_20mhz/ant_3.bin
+antPrachC8=./usecase/mu0_20mhz/ant_0.bin
+antPrachC9=./usecase/mu0_20mhz/ant_1.bin
+antPrachC10=./usecase/mu0_20mhz/ant_2.bin
+antPrachC11=./usecase/mu0_20mhz/ant_3.bin
+antPrachC12=./usecase/mu0_20mhz/ant_0.bin
+antPrachC13=./usecase/mu0_20mhz/ant_1.bin
+antPrachC14=./usecase/mu0_20mhz/ant_2.bin
+antPrachC15=./usecase/mu0_20mhz/ant_3.bin
+antPrachC16=./usecase/mu0_20mhz/ant_0.bin
+antPrachC17=./usecase/mu0_20mhz/ant_1.bin
+antPrachC18=./usecase/mu0_20mhz/ant_2.bin
+antPrachC19=./usecase/mu0_20mhz/ant_3.bin
+antPrachC20=./usecase/mu0_20mhz/ant_0.bin
+antPrachC21=./usecase/mu0_20mhz/ant_1.bin
+antPrachC22=./usecase/mu0_20mhz/ant_2.bin
+antPrachC23=./usecase/mu0_20mhz/ant_3.bin
+antPrachC24=./usecase/mu0_20mhz/ant_0.bin
+antPrachC25=./usecase/mu0_20mhz/ant_1.bin
+antPrachC26=./usecase/mu0_20mhz/ant_2.bin
+antPrachC27=./usecase/mu0_20mhz/ant_3.bin
+antPrachC28=./usecase/mu0_20mhz/ant_0.bin
+antPrachC29=./usecase/mu0_20mhz/ant_1.bin
+antPrachC30=./usecase/mu0_20mhz/ant_2.bin
+antPrachC31=./usecase/mu0_20mhz/ant_3.bin
+antPrachC32=./usecase/mu0_20mhz/ant_0.bin
+antPrachC33=./usecase/mu0_20mhz/ant_1.bin
+antPrachC34=./usecase/mu0_20mhz/ant_2.bin
+antPrachC35=./usecase/mu0_20mhz/ant_3.bin
+antPrachC36=./usecase/mu0_20mhz/ant_0.bin
+antPrachC37=./usecase/mu0_20mhz/ant_1.bin
+antPrachC38=./usecase/mu0_20mhz/ant_2.bin
+antPrachC39=./usecase/mu0_20mhz/ant_3.bin
+antPrachC40=./usecase/mu0_20mhz/ant_0.bin
+antPrachC41=./usecase/mu0_20mhz/ant_1.bin
+antPrachC42=./usecase/mu0_20mhz/ant_2.bin
+antPrachC43=./usecase/mu0_20mhz/ant_3.bin
+antPrachC44=./usecase/mu0_20mhz/ant_0.bin
+antPrachC45=./usecase/mu0_20mhz/ant_1.bin
+antPrachC46=./usecase/mu0_20mhz/ant_2.bin
+antPrachC47=./usecase/mu0_20mhz/ant_3.bin
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,75,0,14,0,1,0,16,1
+nPrbElemUl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,75,0,14,0,1,0,16,1
+###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
##Debug
-debugStop=0 #stop app on 1pps boundary (gps_second % 30)
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
Tadv_cp_dl=25 #in us TODO: update per RU implementation
#C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=400 #in us
-T2a_max_cp_dl=1120 #in us
+T2a_min_cp_dl=400 #in us
+T2a_max_cp_dl=1120 #in us
#Reception Window C-plane UL
-T2a_min_cp_ul=400 #in us
-T2a_max_cp_ul=1120 #in us
+T2a_min_cp_ul=400 #in us
+T2a_max_cp_ul=1120 #in us
#Reception Window U-plane
T2a_min_up=200 # in us
ioCore=3
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70 #lls-CU PF for tcpdump
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
#fd 10Mhz 2
ioCore=10
-llsCUMac=00:11:22:33:44:77 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70 #lls-CU PF for tcpdump
-ruMac=00:11:22:33:44:44 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=20 #number of slots per IQ files
#fd 10Mhz 2
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu0_20mhz/ant_0.bin #CC0
antC1=./usecase/mu0_20mhz/ant_1.bin #CC0
Gps_Beta=0
ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu0_20mhz/ant_0.bin #CC0
antC1=./usecase/mu0_20mhz/ant_1.bin #CC0
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
Gps_Beta=0
ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu0_5mhz/ant_0.bin #CC0
antC1=./usecase/mu0_5mhz/ant_1.bin #CC0
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu1_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu1_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu1_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu1_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu1_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu1_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu1_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu1_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+PrbElemDl2=72,36,0,14,3,1,0,16,1
+PrbElemDl3=108,36,0,14,4,1,0,16,1
+PrbElemDl4=144,36,0,14,5,1,0,16,1
+PrbElemDl5=180,36,0,14,6,1,0,16,1
+PrbElemDl6=216,36,0,14,7,1,0,16,1
+PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+PrbElemUl2=72,36,0,14,3,1,0,16,1
+PrbElemUl3=108,36,0,14,4,1,0,16,1
+PrbElemUl4=144,36,0,14,5,1,0,16,1
+PrbElemUl5=180,36,0,14,6,1,0,16,1
+PrbElemUl6=216,36,0,14,7,1,0,16,1
+PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu1_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu1_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu1_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu1_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu1_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu1_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu1_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/mu1_100mhz/ant_8.bin #CC2
+antPrachC9=./usecase/mu1_100mhz/ant_9.bin #CC2
+antPrachC10=./usecase/mu1_100mhz/ant_10.bin #CC2
+antPrachC11=./usecase/mu1_100mhz/ant_11.bin #CC2
+antPrachC12=./usecase/mu1_100mhz/ant_12.bin #CC3
+antPrachC13=./usecase/mu1_100mhz/ant_13.bin #CC3
+antPrachC14=./usecase/mu1_100mhz/ant_14.bin #CC3
+antPrachC15=./usecase/mu1_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,0,0,0,16,0
+PrbElemDl1=137,136,0,14,0,0,0,16,0
+PrbElemDl2=72,36,0,14,3,1,0,16,1
+PrbElemDl3=108,36,0,14,4,1,0,16,1
+PrbElemDl4=144,36,0,14,5,1,0,16,1
+PrbElemDl5=180,36,0,14,6,1,0,16,1
+PrbElemDl6=216,36,0,14,7,1,0,16,1
+PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,0,0,0,16,0
+PrbElemUl1=137,136,0,14,0,0,0,16,0
+PrbElemUl2=72,36,0,14,3,1,0,16,1
+PrbElemUl3=108,36,0,14,4,1,0,16,1
+PrbElemUl4=144,36,0,14,5,1,0,16,1
+PrbElemUl5=180,36,0,14,6,1,0,16,1
+PrbElemUl6=216,36,0,14,7,1,0,16,1
+PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # O-DU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu1_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu1_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu1_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu1_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu1_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu1_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu1_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu1_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,1,1,0,16,0
+PrbElemDl1=137,136,0,14,2,1,0,16,0
+PrbElemDl2=72,36,0,14,3,1,0,16,1
+PrbElemDl3=108,36,0,14,4,1,0,16,1
+PrbElemDl4=144,36,0,14,5,1,0,16,1
+PrbElemDl5=180,36,0,14,6,1,0,16,1
+PrbElemDl6=216,36,0,14,7,1,0,16,1
+PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,1,1,0,16,0
+PrbElemUl1=137,136,0,14,2,1,0,16,0
+PrbElemUl2=72,36,0,14,3,1,0,16,1
+PrbElemUl3=108,36,0,14,4,1,0,16,1
+PrbElemUl4=144,36,0,14,5,1,0,16,1
+PrbElemUl5=180,36,0,14,6,1,0,16,1
+PrbElemUl6=216,36,0,14,7,1,0,16,1
+PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=1 #30Khz Sub Carrier Spacing
+
+ttiPeriod=500 # in us TTI period (30Khz default 500us)
+
+nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=4096
+nULFftSize=4096
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu1_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu1_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu1_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu1_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu1_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu1_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu1_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu1_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/mu1_100mhz/ant_8.bin #CC2
+antPrachC9=./usecase/mu1_100mhz/ant_9.bin #CC2
+antPrachC10=./usecase/mu1_100mhz/ant_10.bin #CC2
+antPrachC11=./usecase/mu1_100mhz/ant_11.bin #CC2
+antPrachC12=./usecase/mu1_100mhz/ant_12.bin #CC3
+antPrachC13=./usecase/mu1_100mhz/ant_13.bin #CC3
+antPrachC14=./usecase/mu1_100mhz/ant_14.bin #CC3
+antPrachC15=./usecase/mu1_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,137,0,14,1,1,0,16,0
+PrbElemDl1=137,136,0,14,2,1,0,16,0
+PrbElemDl2=72,36,0,14,3,1,0,16,1
+PrbElemDl3=108,36,0,14,4,1,0,16,1
+PrbElemDl4=144,36,0,14,5,1,0,16,1
+PrbElemDl5=180,36,0,14,6,1,0,16,1
+PrbElemDl6=216,36,0,14,7,1,0,16,1
+PrbElemDl7=252,21,0,14,8,1,0,16,1
+
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,137,0,14,1,1,0,16,0
+PrbElemUl1=137,136,0,14,2,1,0,16,0
+PrbElemUl2=72,36,0,14,3,1,0,16,1
+PrbElemUl3=108,36,0,14,4,1,0,16,1
+PrbElemUl4=144,36,0,14,5,1,0,16,1
+PrbElemUl5=180,36,0,14,6,1,0,16,1
+PrbElemUl6=216,36,0,14,7,1,0,16,1
+PrbElemUl7=252,21,0,14,8,1,0,16,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+Tadv_cp_dl=125 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=419 # 285.42us
+T2a_max_cp_dl=470 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=125 # 285.42us
+T2a_max_cp_ul=336 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=134 # 71.35in us
+T2a_max_up=345 # 428.12us
+
+#Transmission Window
+Ta3_min=50 # in us
+Ta3_max=171 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=419
+T1a_max_cp_dl=470
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=336
+
+#U-plane
+##Transmission Window
+T1a_min_up=294 #71 + 25 us
+T1a_max_up=345 #71 + 25 us
+
+#Reception Window
+Ta4_min=50 # in us
+Ta4_max=331 # in us
+###########################################################
+
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 # RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70
-ruMac=00:11:22:33:44:55 # RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 # RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
#C-plane
#Transmission Window Fast C-plane DL
T1a_min_cp_dl=285
-T1a_max_cp_dl=429
+T1a_max_cp_dl=392
##Transmission Window Fast C-plane UL
T1a_min_cp_ul=285
Gps_Beta=0
ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70
-ruMac=00:11:22:33:44:55 # RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
numSlots=40 #number of slots per IQ files
antC0=./usecase/mu1_100mhz/ant_0.bin #CC0
# C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
T2a_min_cp_dl=285 # 285.42us
-T2a_max_cp_dl=429 # 428.12us
+T2a_max_cp_dl=392 # 428.12us
#Reception Window C-plane UL
T2a_min_cp_ul=285 # 285.42us
#C-plane
#Transmission Window Fast C-plane DL
T1a_min_cp_dl=285
-T1a_max_cp_dl=429
+T1a_max_cp_dl=392
##Transmission Window Fast C-plane UL
T1a_min_cp_ul=285
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # lls-CU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+#######################################################################
+#Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,33,0,14,1,1,1,12,1
+PrbElemDl1=33,33,0,14,2,1,1,12,1
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,33,0,14,1,1,1,12,1
+PrbElemUl1=33,33,0,14,2,1,1,12,1
+#######################################################################
+
+##Numerology
+mu=3 #mmWave 120Khz Sub Carrier Spacing
+ttiPeriod=125 # in us TTI period (mmWave default 125us)
+nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+# not used
+#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+maxFrameId=99 # set for compatibility with O-RU
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu3_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu3_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu3_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu3_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu3_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu3_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu3_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu3_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu3_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu3_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu3_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu3_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu3_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu3_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu3_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu3_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=81
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 #in us TODO: update per RU implementation
+ #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+
+#Reception Window C-plane DL
+T2a_min_cp_dl=50 #in us
+T2a_max_cp_dl=140 #in us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=50 #in us
+T2a_max_cp_ul=140 #in us
+
+#Reception Window U-plane
+T2a_min_up=25 #in us
+T2a_max_up=140 #in us
+
+#Transmission Window
+Ta3_min=20 #in us
+Ta3_max=32 #in us
+
+###########################################################
+##lls-CU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=70
+T1a_max_cp_dl=100
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=60
+T1a_max_cp_ul=70
+
+#U-plane
+##Transmission Window
+T1a_min_up=35
+T1a_max_up=50
+
+#Reception Window
+Ta4_min=0
+Ta4_max=45
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+#######################################################################
+#Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,33,0,14,1,1,1,12,1
+PrbElemDl1=33,33,0,14,2,1,1,12,1
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,33,0,14,1,1,1,12,1
+PrbElemUl1=33,33,0,14,2,1,1,12,1
+#######################################################################
+
+##Numerology
+mu=3 #mmWave 120Khz Sub Carrier Spacing
+ttiPeriod=125 # in us TTI period (mmWave default 125us)
+nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+ #not used
+#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+maxFrameId=99 # set for compatibility with O-RU
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu3_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu3_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu3_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu3_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu3_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu3_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu3_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu3_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu3_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu3_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu3_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu3_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu3_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu3_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu3_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu3_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/mu3_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/mu3_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/mu3_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/mu3_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/mu3_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/mu3_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/mu3_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/mu3_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/mu3_100mhz/ant_8.bin #CC2
+antPrachC9=./usecase/mu3_100mhz/ant_9.bin #CC2
+antPrachC10=./usecase/mu3_100mhz/ant_10.bin #CC2
+antPrachC11=./usecase/mu3_100mhz/ant_11.bin #CC2
+antPrachC12=./usecase/mu3_100mhz/ant_12.bin #CC3
+antPrachC13=./usecase/mu3_100mhz/ant_13.bin #CC3
+antPrachC14=./usecase/mu3_100mhz/ant_14.bin #CC3
+antPrachC15=./usecase/mu3_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=81
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 #in us TODO: update per RU implementation
+ #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+
+#Reception Window C-plane DL
+T2a_min_cp_dl=50 #in us
+T2a_max_cp_dl=140 #in us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=50 #in us
+T2a_max_cp_ul=140 #in us
+
+#Reception Window U-plane
+T2a_min_up=25 #in us
+T2a_max_up=140 #in us
+
+#Transmission Window
+Ta3_min=20 #in us
+Ta3_max=32 #in us
+
+###########################################################
+##lls-CU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=70
+T1a_max_cp_dl=100
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=60
+T1a_max_cp_ul=70
+
+#U-plane
+##Transmission Window
+T1a_min_up=35
+T1a_max_up=50
+
+#Reception Window
+Ta4_min=0
+Ta4_max=45
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
+appMode=0 # lls-CU(0) | RU(1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=3 #mmWave 120Khz Sub Carrier Spacing
+ttiPeriod=125 # in us TTI period (mmWave default 125us)
+nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#not used
+#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=5
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+maxFrameId=99 # set for compatibility with O-RU
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu3_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu3_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu3_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu3_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu3_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu3_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu3_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu3_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu3_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu3_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu3_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu3_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu3_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu3_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu3_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu3_100mhz/ant_15.bin #CC3
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=81
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=63 #in us TODO: update per RU implementation
+ #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+
+#Reception Window C-plane DL
+T2a_min_cp_dl=116 #in us
+T2a_max_cp_dl=327 #in us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=63 #in us
+T2a_max_cp_ul=274 #in us
+
+#Reception Window U-plane
+T2a_min_up=53 #in us
+T2a_max_up=264 #in us
+
+#Transmission Window
+Ta3_min=20 #in us
+Ta3_max=90 #in us
+
+###########################################################
+##lls-CU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=276
+T1a_max_cp_dl=327
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=223
+T1a_max_cp_ul=274
+
+#U-plane
+##Transmission Window
+T1a_min_up=213
+T1a_max_up=264
+
+#Reception Window
+Ta4_min=20
+Ta4_max=250
+###########################################################
+
--- /dev/null
+#******************************************************************************
+#
+# Copyright (c) 2019 Intel.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
+
+# This is simple configuration file. Use '#' sign for comments
+instanceId=1 # 0,1,2,... in case more than 1 application started on the same system
+appMode=1 # O-DU(0) | O-RU(1)
+xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
+ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
+
+##Numerology
+mu=3 #mmWave 120Khz Sub Carrier Spacing
+ttiPeriod=125 # in us TTI period (mmWave default 125us)
+nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
+nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400
+nDLFftSize=1024
+nULFftSize=1024
+
+nFrameDuplexType=1 # 0 - FDD 1 - TDD
+nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4
+sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD
+sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#not used
+#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD
+
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+ #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
+Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
+Gps_Beta=0
+
+ioCore=10
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+maxFrameId=99 # set for compatibility with O-RU
+
+numSlots=40 #number of slots per IQ files
+antC0=./usecase/mu3_100mhz/ant_0.bin #CC0
+antC1=./usecase/mu3_100mhz/ant_1.bin #CC0
+antC2=./usecase/mu3_100mhz/ant_2.bin #CC0
+antC3=./usecase/mu3_100mhz/ant_3.bin #CC0
+antC4=./usecase/mu3_100mhz/ant_4.bin #CC1
+antC5=./usecase/mu3_100mhz/ant_5.bin #CC1
+antC6=./usecase/mu3_100mhz/ant_6.bin #CC1
+antC7=./usecase/mu3_100mhz/ant_7.bin #CC1
+antC8=./usecase/mu3_100mhz/ant_8.bin #CC2
+antC9=./usecase/mu3_100mhz/ant_9.bin #CC2
+antC10=./usecase/mu3_100mhz/ant_10.bin #CC2
+antC11=./usecase/mu3_100mhz/ant_11.bin #CC2
+antC12=./usecase/mu3_100mhz/ant_12.bin #CC3
+antC13=./usecase/mu3_100mhz/ant_13.bin #CC3
+antC14=./usecase/mu3_100mhz/ant_14.bin #CC3
+antC15=./usecase/mu3_100mhz/ant_15.bin #CC3
+
+antPrachC0=./usecase/mu3_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/mu3_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/mu3_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/mu3_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/mu3_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/mu3_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/mu3_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/mu3_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/mu3_100mhz/ant_8.bin #CC2
+antPrachC9=./usecase/mu3_100mhz/ant_9.bin #CC2
+antPrachC10=./usecase/mu3_100mhz/ant_10.bin #CC2
+antPrachC11=./usecase/mu3_100mhz/ant_11.bin #CC2
+antPrachC12=./usecase/mu3_100mhz/ant_12.bin #CC3
+antPrachC13=./usecase/mu3_100mhz/ant_13.bin #CC3
+antPrachC14=./usecase/mu3_100mhz/ant_14.bin #CC3
+antPrachC15=./usecase/mu3_100mhz/ant_15.bin #CC3
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=81
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
+u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
+
+##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=63 #in us TODO: update per RU implementation
+ #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+
+#Reception Window C-plane DL
+T2a_min_cp_dl=116 #in us
+T2a_max_cp_dl=327 #in us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=63 #in us
+T2a_max_cp_ul=274 #in us
+
+#Reception Window U-plane
+T2a_min_up=53 #in us
+T2a_max_up=264 #in us
+
+#Transmission Window
+Ta3_min=20 #in us
+Ta3_max=90 #in us
+
+###########################################################
+##lls-CU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=276
+T1a_max_cp_dl=327
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=223
+T1a_max_cp_ul=274
+
+#U-plane
+##Transmission Window
+T1a_min_up=213
+T1a_max_up=264
+
+#Reception Window
+Ta4_min=20
+Ta4_max=250
+###########################################################
+
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 # RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
maxFrameId=99 # set for compatibility with O-RU
Gps_Beta=0
ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-#llsCUMac=3c:fd:fe:a8:e0:70
-ruMac=00:11:22:33:44:55 # RU VF for RU app
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
maxFrameId=99 # set for compatibility with O-RU
xclean)
COMMAND_LINE+=$key
COMMAND_LINE+=" "
- ;;
+ ;;
+ clean)
+ COMMAND_LINE+=$key
+ COMMAND_LINE+=" "
+ ;;
*)
echo $key is unknown command # unknown option
;;
else
echo 'Building xRAN Test Application ('$GTEST_ROOT')'
cd $XRAN_FH_TEST_DIR
- make clean;
- make
+ make $COMMAND_LINE;
fi
PROJECT_TYPE := lib
PROJECT_DIR := $(XRAN_DIR)/lib
BUILDDIR := ./build
+
+ifeq ($(XRAN_LIB_SO),)
PROJECT_BINARY := $(BUILDDIR)/$(PROJECT_NAME).a
+else
+PROJECT_BINARY := $(BUILDDIR)/$(PROJECT_NAME).so
+endif
ifeq ($(RTE_SDK),)
$(error "Please define RTE_SDK environment variable")
endif
-RTE_TARGET ?= x86_64-native-linuxapp-gcc
+RTE_TARGET ?= x86_64-native-linux-icc
RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include
API_DIR := $(PROJECT_DIR)/api
$(SRC_DIR)/xran_app_frag.c \
$(SRC_DIR)/xran_main.c
-CPP_SRC = $(SRC_DIR)/xran_compression.cpp
+CPP_SRC = $(SRC_DIR)/xran_compression.cpp \
+ $(SRC_DIR)/xran_bfp_ref.cpp \
+ $(SRC_DIR)/xran_bfp_cplane8.cpp \
+ $(SRC_DIR)/xran_bfp_cplane16.cpp \
+ $(SRC_DIR)/xran_bfp_cplane32.cpp \
+ $(SRC_DIR)/xran_bfp_cplane64.cpp
CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \
-fdata-sections \
-ffunction-sections \
-g \
+ -fPIC \
-Wall \
-Wimplicit-function-declaration \
-g -O3 -wd1786
-CC_FLAGS += -fstack-protector-strong -z,now, -z,relro \
- -z noexecstack -Wformat -Wformat-security -Werror=format-security \
- -fno-strict-overflow -fwrapv
-
CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -no-prec-div \
- -no-prec-div -fp-model fast=2\
+ -no-prec-div -fp-model fast=2 -fPIC \
-no-prec-sqrt -falign-functions=16 -fast-transcendentals \
-Werror -Wno-unused-variable -std=c++11 -mcmodel=large
debug : all
release : all
-
$(PROJECT_BINARY) : $(DIRLIST) echo_start_build $(GENERATE_DEPS) $(PRE_BUILD) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS)
@echo [AR] $(subst $(BUILDDIR)/,,$@)
+ifeq ($(XRAN_LIB_SO),)
@$(AR) $(AR_FLAGS) $@ $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS)
+else
+ @$(CC) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS) -shared -fPIC -o $@
+endif
struct xranlib_compress_request {
int16_t *data_in; /*!< Pointer to data to compress. */
int16_t numRBs; /*!< numRBs */
+ int16_t numDataElements; /*!< number of elements in block process [UP: 24 i.e 12RE*2; CP: 16,32,64,128. i.e AntElm*2] */
int16_t compMethod; /*!< Compression method */
int16_t iqWidth; /*!< Bit size */
int32_t len; /*!< Length of input buffer in bytes */
struct xranlib_decompress_request {
int8_t *data_in; /*!< Pointer to data to decompress. */
int16_t numRBs; /*!< numRBs */
+ int16_t numDataElements; /*!< number of elements in block process [UP: 24 i.e 12RE*2; CP: 16,32,64,128. i.e AntElm*2] */
int16_t compMethod; /*!< Compression method */
int16_t iqWidth; /*!< Bit size */
\param [out] response Structure containing the output data and data length.
\return 0 for success, -1 for error
*/
-int
+int32_t
xranlib_compress(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response);
-
-int xranlib_compress_sse(const struct xranlib_compress_request *request,
+int32_t
+xranlib_compress_sse(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response);
-int xranlib_compress_avx2(const struct xranlib_compress_request *request,
+int32_t
+xranlib_compress_avx2(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response);
-int xranlib_compress_avx512(const struct xranlib_compress_request *request,
+int32_t
+xranlib_compress_avx512(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response);
-int xranlib_compress_avx512_bfw(const struct xranlib_compress_request *request,
+int32_t
+xranlib_compress_avx512_bfw(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response);
//! @}
\param [out] response Structure containing the output data and data length.
\return 0 for success, -1 for error.
**/
-int
+int32_t
xranlib_decompress(const struct xranlib_decompress_request *request,
struct xranlib_decompress_response *response);
-int xranlib_decompress_sse(const struct xranlib_decompress_request *request,
+int32_t
+xranlib_decompress_sse(const struct xranlib_decompress_request *request,
struct xranlib_decompress_response *response);
-int xranlib_decompress_avx2(const struct xranlib_decompress_request *request,
+int32_t
+xranlib_decompress_avx2(const struct xranlib_decompress_request *request,
struct xranlib_decompress_response *response);
-int xranlib_decompress_avx512(const struct xranlib_decompress_request *request,
+int32_t
+xranlib_decompress_avx512(const struct xranlib_decompress_request *request,
struct xranlib_decompress_response *response);
+int32_t
+xranlib_decompress_avx512_bfw(const struct xranlib_decompress_request *request,
+ struct xranlib_decompress_response *response);
+
//! @}
#ifdef __cplusplus
#pragma once
#include <stdint.h>
+#include <immintrin.h>
// This configuration file sets global constants and macros which are
// of general use throughout the project.
// can be assumed to be aligned to a cache line. This allows the
// compiler to generate improved code by using aligned reads and
// writes.
-#define ASSUME_CACHE_ALIGNED(data) __assume_aligned(data, k_cacheByteAlignment);
+#define ASSUME_CACHE_ALIGNED(data)
+// __assume_aligned(data, k_cacheByteAlignment);
/// Intel compiler frequently complains about templates not being declared in an external
/// header. Templates are used throughout this project's source files to define local type-specific
{
/// Compute 32 RB at a time
static constexpr int k_numBitsIQ = 16;
- static constexpr int k_numRB = 16;
- static constexpr int k_numRE = 12;
- static constexpr int k_numREReal = k_numRE * 2;
- static constexpr int k_numSampsExpanded = k_numRB * k_numREReal;
- static constexpr int k_numSampsCompressed = (k_numSampsExpanded * 2) + k_numRB;
+ static constexpr int k_numBitsIQPair = 2 * k_numBitsIQ;
+ static constexpr int k_maxNumBlocks = 16;
+ static constexpr int k_maxNumElements = 128;
+ static constexpr int k_numSampsExpanded = k_maxNumBlocks * k_maxNumElements;
+ static constexpr int k_numSampsCompressed = (k_numSampsExpanded * 2) + k_maxNumBlocks;
struct CompressedData
{
CACHE_ALIGNED uint8_t *dataCompressed;
/// Size of mantissa including sign bit
int iqWidth;
+
+ /// Number of BFP blocks in message
+ int numBlocks;
+
+ /// Number of data elements per compression block (only required for reference function)
+ int numDataElements;
};
struct ExpandedData
/// Size of mantissa including sign bit
int iqWidth;
+
+ /// Number of BFP blocks in message
+ int numBlocks;
+
+ /// Number of data elements per compression block (only required for reference function)
+ int numDataElements;
};
- void BlockFloatCompress_Basic(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_8b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_9b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_10b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_12b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
-
- void BlockFloatExpand_Basic(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_8b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_9b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_10b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_12b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
-}
+ /// Reference compression and expansion functions
+ void BFPCompressRef(const ExpandedData& dataIn, CompressedData* dataOut);
+ void BFPExpandRef(const CompressedData& dataIn, ExpandedData* dataOut);
-namespace BlockFloatCompanderBFW
-{
- /// Compute 32 RB at a time
- static constexpr int k_numBitsIQ = 16;
- static constexpr int k_numRB = 1;
- static constexpr int k_numRE = 32;
- static constexpr int k_numREReal = k_numRE * 2;
- static constexpr int k_numSampsExpanded = k_numRB * k_numREReal;
- static constexpr int k_numSampsCompressed = (k_numSampsExpanded * 2) + k_numRB;
+ /// User-Plane specific compression and expansion functions
+ void BFPCompressUserPlaneAvx512(const ExpandedData& dataIn, CompressedData* dataOut);
+ void BFPExpandUserPlaneAvx512(const CompressedData& dataIn, ExpandedData* dataOut);
- struct CompressedData
- {
- /// Compressed data
- CACHE_ALIGNED uint8_t dataCompressedDataOut[k_numSampsCompressed];
- CACHE_ALIGNED uint8_t *dataCompressed;
- /// Size of mantissa including sign bit
- int iqWidth;
- };
+ /// Control-Plane specific compression and expansion functions for 8 antennas
+ void BFPCompressCtrlPlane8Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+ void BFPExpandCtrlPlane8Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
- struct ExpandedData
- {
- /// Expanded data or input data to compressor
- CACHE_ALIGNED int16_t dataExpandedIn[k_numSampsExpanded];
- CACHE_ALIGNED int16_t *dataExpanded;
+ /// Control-Plane specific compression and expansion functions for 16 antennas
+ void BFPCompressCtrlPlane16Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+ void BFPExpandCtrlPlane16Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
- /// Size of mantissa including sign bit
- int iqWidth;
- };
+ /// Control-Plane specific compression and expansion functions for 32 antennas
+ void BFPCompressCtrlPlane32Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+ void BFPExpandCtrlPlane32Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatCompress_Basic(const ExpandedData& dataIn, CompressedData* dataOut);
-/* void BlockFloatCompress_8b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_9b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_10b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut);
- void BlockFloatCompress_12b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut); */
-
- void BlockFloatExpand_Basic(const CompressedData& dataIn, ExpandedData* dataOut);
-/* void BlockFloatExpand_8b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_9b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_10b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);
- void BlockFloatExpand_12b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut);*/
+ /// Control-Plane specific compression and expansion functions for 64 antennas
+ void BFPCompressCtrlPlane64Avx512(const ExpandedData& dataIn, CompressedData* dataOut);
+ void BFPExpandCtrlPlane64Avx512(const CompressedData& dataIn, ExpandedData* dataOut);
}
#define XRAN_LBTMODE_PARTIAL34 2
#define XRAN_LBTMODE_FULLSTOP 3
+
#define XRAN_EF_F_LAST 0
#define XRAN_EF_F_ANOTHER_ONE 1
-
-
/** Control Plane section extension commands, defined in 5.4.6 Table 5.13 */
enum xran_cp_sectionextcmd {
XRAN_CP_SECTIONEXTCMD_0 = 0, /**< Reserved, for future use */
XRAN_BFABITWIDTH_8BIT = 7, /**< the filed is 8-bit bitwidth */
};
+/** Layer ID for DL transmission in TM1-TM4 5.4.7.3.2 */
+#define XRAN_LAYERID_0 0 /**< Layer 0 */
+#define XRAN_LAYERID_1 1 /**< Layer 1 */
+#define XRAN_LAYERID_2 2 /**< Layer 2 */
+#define XRAN_LAYERID_3 3 /**< Layer 3 */
+#define XRAN_LAYERID_TXD 0xf /**< TxD */
+
+/** LTE Transmission Scheme for section extension type 3 5.4.7.3.3 */
+#define XRAN_TXS_SMUXCDD 0 /**< Spatial Multiplexing (CDD) */
+#define XRAN_TXS_SMUXNOCDD 1 /**< Spatial Multiplexing (no CDD) */
+#define XRAN_TXS_TXDIV 2 /**< Transmit diversity */
+
+
/**
* This structure contains the information to generate the section body of C-Plane message */
struct xran_section_info {
uint8_t bfZeSI;
};
-struct xran_sectionext3_info { /* NOT SUPPORTED */
+struct xran_sectionext3_info {
uint8_t codebookIdx;
uint8_t layerId;
uint8_t numLayers;
uint16_t crsReMask;
uint8_t crsShift;
uint8_t crsSymNum;
+ uint16_t numAntPort; /* number of antenna port - 2 or 4 */
uint16_t beamIdAP1;
uint16_t beamIdAP2;
uint16_t beamIdAP3;
uint16_t cpLength; /* X X 16bits */
};
+/** The structure for the generation of section extension */
+struct xran_section_ext_gen_info {
+ uint16_t type; /**< the type of section extension */
+ uint16_t len; /**< length of extension data */
+ void *data; /**< pointer to extension data */
+ };
+
/**
* This structure to hold the information to generate the sections of C-Plane message */
struct xran_section_gen_info {
uint32_t exDataSize; /**< The number of Extensions or type 6/7 data */
/** the array to store section extension */
- struct {
- uint16_t type; /**< the type of section extension */
- uint16_t len; /**< length of extension data */
- void *data; /**< pointer to extension data */
- } exData[XRAN_MAX_NUM_EXTENSIONS];
+ struct xran_section_ext_gen_info exData[XRAN_MAX_NUM_EXTENSIONS];
+
struct xran_sectionext1_info m_ext1[XRAN_MAX_NUM_EXTENSIONS];
struct xran_sectionext2_info m_ext2[XRAN_MAX_NUM_EXTENSIONS];
struct xran_sectionext3_info m_ext3[XRAN_MAX_NUM_EXTENSIONS];
uint16_t xran_get_cplength(int cpLength);
int32_t xran_get_freqoffset(int freqOffset, int scs);
-int xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf,
+int32_t xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf,
struct xran_cp_gen_params *params,
uint8_t CC_ID, uint8_t Ant_ID,
uint8_t seq_id);
-int xran_parse_cp_pkt(struct rte_mbuf *mbuf,
+int32_t xran_parse_cp_pkt(struct rte_mbuf *mbuf,
struct xran_cp_gen_params *result,
struct xran_recv_packet_info *pkt_info);
-int xran_cp_init_sectiondb(void *pHandle);
-int xran_cp_free_sectiondb(void *pHandle);
-int xran_cp_add_section_info(void *pHandle,
+int32_t xran_cp_init_sectiondb(void *pHandle);
+int32_t xran_cp_free_sectiondb(void *pHandle);
+int32_t xran_cp_add_section_info(void *pHandle,
uint8_t dir, uint8_t cc_id, uint8_t ruport_id,
uint8_t ctx_id, struct xran_section_info *info);
-int xran_cp_add_multisection_info(void *pHandle,
+int32_t xran_cp_add_multisection_info(void *pHandle,
uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id,
struct xran_cp_gen_params *gen_info);
struct xran_section_info *xran_cp_find_section_info(void *pHandle,
struct xran_section_info *xran_cp_iterate_section_info(void *pHandle,
uint8_t dir, uint8_t cc_id, uint8_t ruport_id,
uint8_t ctx_id, uint32_t *next);
+
int xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id);
int xran_cp_reset_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id);
int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination buffer */
uint16_t bfwNumber, /**< number of bf weights in this set of sections */
uint8_t bfwiqWidth, /**< bit size of IQs */
uint8_t bfwCompMeth); /**< compression method */
+struct rte_mbuf *xran_attach_cp_ext_buf(int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len,
+ struct rte_mbuf_ext_shared_info * p_share_data);
+
#ifdef __cplusplus
}
#endif
#define XRAN_PORTS_NUM (1) /**< number of XRAN ports (aka O-RU devices) supported */
#define XRAN_N_FE_BUF_LEN (40) /**< Number of TTIs (slots) */
-#define XRAN_MAX_SECTOR_NR (12) /**< Max sectors per XRAN port */
-#define XRAN_MAX_ANTENNA_NR (16) /**< Max number of extended Antenna-Carriers:
+#define XRAN_MAX_SECTOR_NR (12) /**< Max sectors per XRAN port */
+#define XRAN_MAX_ANTENNA_NR (16) /**< Max number of extended Antenna-Carriers:
a data flow for a single antenna (or spatial stream) for a single carrier in a single sector */
/* see 10.2 Hierarchy of Radiation Structure in O-RU (assume TX and RX pannel are the same dimensions)*/
/** Callback functions to poll BBdev encoder */
typedef int16_t (*phy_encoder_poll_fn)(void);
-/** Callback functions to poll BBdev secoder */
+/** Callback functions to poll BBdev decoder */
typedef int16_t (*phy_decoder_poll_fn)(void);
/** XRAN port enum */
{
XRAN_UP_VF = 0, /**< port type for U-plane */
XRAN_CP_VF, /**< port type for C-plane */
+ XRAN_UP_VF1, /**< port type for U-plane */
+ XRAN_CP_VF1, /**< port type for C-plane */
+ XRAN_UP_VF2, /**< port type for U-plane */
+ XRAN_CP_VF2, /**< port type for C-plane */
+ XRAN_UP_VF3, /**< port type for U-plane */
+ XRAN_CP_VF3, /**< port type for C-plane */
+ XRAN_UP_VF4, /**< port type for U-plane */
+ XRAN_CP_VF4, /**< port type for C-plane */
+ XRAN_UP_VF5, /**< port type for U-plane */
+ XRAN_CP_VF5, /**< port type for C-plane */
+ XRAN_UP_VF6, /**< port type for U-plane */
+ XRAN_CP_VF6, /**< port type for C-plane */
+ XRAN_UP_VF7, /**< port type for U-plane */
+ XRAN_CP_VF7, /**< port type for C-plane */
XRAN_VF_MAX
};
+/** XRAN Radio Access technology enum */
+enum xran_ran_tech
+{
+ XRAN_RAN_5GNR = 0, /**< 5G NR */
+ XRAN_RAN_LTE = 1, /**< LTE */
+ XRAN_RAN_MAX
+};
+
+/** XRAN user data compression header handling types */
+enum xran_comp_hdr_type
+{
+ XRAN_COMP_HDR_TYPE_DYNAMIC = 0, /**< dynamic data format where U-plane udCompHdr controls compression parameters */
+ XRAN_COMP_HDR_TYPE_STATIC = 1, /**< static data format where M-plane defines compression parameters */
+ XRAN_COMP_HDR_TYPE_MAX
+};
+
/** XRAN category enum */
enum xran_category
{
- XRAN_CATEGORY_A = 0,
- XRAN_CATEGORY_B = 1,
+ XRAN_CATEGORY_A = 0, /**< 5G NR Category A */
+ XRAN_CATEGORY_B = 1, /**< 5G NR Category B */
XRAN_CATEGORY_MAX
};
/** DPDK IO configuration for XRAN layer */
struct xran_io_cfg {
uint8_t id; /**< should be (0) for O-DU or (1) O-RU (debug) */
+ uint8_t num_vfs; /**< number of VFs for C-plane and U-plane (should be even) */
char *dpdk_dev[XRAN_VF_MAX]; /**< VFs devices */
- char *bbdev_dev[1]; /**< BBDev dev name */
- int32_t bbdev_mode; /**< DPDK for BBDev */
- int32_t core; /**< reservd */
- int32_t system_core; /**< reservd */
- int32_t pkt_proc_core; /**< reservd */
- int32_t pkt_aux_core; /**< reservd */
- int32_t timing_core; /**< core used by xRAN */
- int32_t port[XRAN_VF_MAX]; /**< VFs ports */
+ char *bbdev_dev[1]; /**< BBDev dev name */
+ int32_t bbdev_mode; /**< DPDK for BBDev */
+ uint32_t dpdkIoVaMode; /**< IOVA Mode */
+ uint32_t dpdkMemorySize; /**< DPDK max memory allocation */
+ int32_t core; /**< reservd */
+ int32_t system_core; /**< reservd */
+ uint64_t pkt_proc_core; /**< worker mask */
+ int32_t pkt_aux_core; /**< reservd */
+ int32_t timing_core; /**< core used by xRAN */
+ int32_t port[XRAN_VF_MAX]; /**< VFs ports */
+ int32_t io_sleep; /**< enable sleep on PMD cores */
};
/** XRAN spec section 3.1.3.1.6 ecpriRtcid / ecpriPcid define */
/** Beamforming waights for single stream for each PRBs given number of Antenna elements */
struct xran_cp_bf_weight{
int16_t nAntElmTRx; /**< num TRX for this allocation */
+ int8_t* p_ext_start; /**< pointer to start of buffer for full C-plane packet */
int8_t* p_ext_section; /**< pointer to form extType */
int16_t ext_section_sz; /**< extType section size */
};
XRAN_Q_I_ORDER /**< Q , I */
};
-/** XRAN front haul IQ compression settings */
+/** XRAN front haul O-RU settings */
struct xran_ru_config {
- enum xran_category xranCat; /**< mode: Catergory A or Category B */
-
- uint8_t iqWidth; /**< IQ bit width */
- uint8_t compMeth; /**< Compression method */
- uint8_t fftSize; /**< FFT Size */
+ enum xran_ran_tech xranTech; /**< 5GNR or LTE */
+ enum xran_category xranCat; /**< mode: Catergory A or Category B */
+ enum xran_comp_hdr_type xranCompHdrType; /**< dynamic or static udCompHdr handling*/
+ uint8_t iqWidth; /**< IQ bit width */
+ uint8_t compMeth; /**< Compression method */
+ uint8_t fftSize; /**< FFT Size */
enum xran_input_byte_order byteOrder; /**< Order of bytes in int16_t in buffer. Big or little endian */
enum xran_input_i_q_order iqOrder; /**< order of IQs in the buffer */
- uint16_t xran_max_frame; /**< max frame number supported */
+ uint16_t xran_max_frame; /**< max frame number supported */
};
/**
phy_encoder_poll_fn bbdev_enc; /**< call back to poll BBDev encoder */
phy_decoder_poll_fn bbdev_dec; /**< call back to poll BBDev decoder */
+ uint16_t tx_cp_eAxC2Vf[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< mapping of C-Plane (ecpriRtcid) or U-Plane (ecpriPcid) to VF */
+ uint16_t tx_up_eAxC2Vf[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< mapping of C-Plane (ecpriRtcid) or U-Plane (ecpriPcid) to VF */
+
+ uint16_t rx_cp_eAxC2Vf[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< mapping of C-Plane (ecpriRtcid) or U-Plane (ecpriPcid) to VF */
+ uint16_t rx_up_eAxC2Vf[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< mapping of C-Plane (ecpriRtcid) or U-Plane (ecpriPcid) to VF */
+
uint32_t log_level; /**< configuration of log level */
};
uint64_t Rx_corrupt; /**< Corrupt/Incorrect header packet */
uint64_t Rx_pkt_dupl; /**< Duplicated packet */
uint64_t Total_msgs_rcvd; /**< Total messages received (on all links) */
+
+ /* debug statistis */
+ uint64_t rx_counter;
+ uint64_t tx_counter;
+ uint64_t tx_bytes_counter;
+ uint64_t rx_bytes_counter;
+ uint64_t tx_bytes_per_sec;
+ uint64_t rx_bytes_per_sec;
+
+ uint64_t rx_pusch_packets[XRAN_MAX_ANTENNA_NR];
+ uint64_t rx_prach_packets[XRAN_MAX_ANTENNA_NR];
+ uint64_t rx_srs_packets;
};
/**
* buffer size
*
* @return
- * ptr - to memory buffer or NULL
+ * buf_len - size of memory allocation
*/
void* xran_malloc(size_t buf_len);
+/**
+ * @ingroup xran
+ *
+ * Function frees memory of given size from heap
+ *
+ * @param buf_len
+ * addr - pointer to buffer
+ *
+ * @return
+ * void
+ */
+void xran_free(void *addr);
/**
* @ingroup xran
*/
uint8_t* xran_add_hdr_offset(uint8_t *dst, int16_t compMethod);
+/**
+ * @ingroup xran
+ *
+ * Function calculates offset for ptr according to ORAN C-plane headers requared
+ *
+ * @param dst
+ * pointer to be addjusted
+ *
+ * @return
+ * ptr - pointer to payload given header requared
+ */
+uint8_t *xran_add_cp_hdr_offset(uint8_t *dst);
+
#ifdef __cplusplus
}
#endif
*****************************************************************************/
struct compression_hdr
{
- uint8_t ud_iq_width:4; /**< Bit width of each I and each Q
- 16 for udIqWidth=0, otherwise equals udIqWidth e.g. udIqWidth = 0000b means I and Q are each 16 bits wide;
- e.g. udIQWidth = 0001b means I and Q are each 1 bit wide;
- e.g. udIqWidth = 1111b means I and Q are each 15 bits wide
- */
uint8_t ud_comp_meth:4;
/**< udCompMeth| compression method |udIqWidth meaning
---------------+-----------------------------+--------------------------------------------
0100b | modulation compression |bitwidth of each compressed I and Q value
0100b - 1111b | reserved for future methods |depends on the specific compression method
*/
+ uint8_t ud_iq_width:4; /**< Bit width of each I and each Q
+ 16 for udIqWidth=0, otherwise equals udIqWidth e.g. udIqWidth = 0000b means I and Q are each 16 bits wide;
+ e.g. udIQWidth = 0001b means I and Q are each 1 bit wide;
+ e.g. udIqWidth = 1111b means I and Q are each 15 bits wide
+ */
} __rte_packed;
/**
*****************************************************************************/
struct xran_pkt_comm_hdr
{
- struct ether_hdr eth_hdr; /**< Ethernet Header */
+ struct rte_ether_hdr eth_hdr; /**< Ethernet Header */
struct xran_ecpri_hdr ecpri_hdr; /**< eCPRI Transport Header */
} __rte_packed;
* DL Precoding Extension Type(ExtType 3) for first data layer.
* Defined in 5.4.7.3 Table 5-22.
* Only be used for LTE TM2-4 and not for other LTE TMs nor NR.
- * The structure is reordered for byte order conversion. Not supported.
+ * The structure is reordered for byte order conversion.
*/
struct xran_cp_radioapp_section_ext3_first {
- /* 16 bytes, need to convert byte order for two parts
- * - 8 / 8 bytes
- */
- uint32_t reserved1:8;
- uint32_t crsSymNum:4; /**< 5.4.7.3.6 CRS symbol number indication */
- uint32_t reserved0:3;
- uint32_t crsShift:1; /**< 5.4.7.3.7 CRS shift used for DL transmission */
- uint32_t crsReMask:12; /**< 5.4.7.3.5 CRS resource element mask */
- uint32_t txScheme:4; /**< 5.4.7.3.3 transmission scheme */
- uint32_t numLayers:4; /**< 5.4.7.3.4 number of layers used for DL transmission */
- uint32_t layerId:4; /**< 5.4.7.3.2 Layer ID for DL transmission */
- uint32_t codebookIndex:8; /**< 5.4.7.3.1 precoder codebook used for transmission */
- uint32_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */
- uint32_t extType:7; /**< 5.4.6.1 extension type */
- uint32_t ef:1; /**< 5.4.6.2 extension flag */
-
- uint16_t beamIdAP3; /**< 5.4.7.3.10 beam id to be used for antenna port 3 */
- uint16_t beamIdAP2; /**< 5.4.7.3.9 beam id to be used for antenna port 2 */
- uint16_t beamIdAP1; /**< 5.4.7.3.8 beam id to be used for antenna port 1 */
- uint16_t reserved2;
+ /* 16 bytes, need to convert byte order for two parts - 8/8 bytes */
+ uint64_t reserved1:8;
+ uint64_t crsSymNum:4; /**< 5.4.7.3.6 CRS symbol number indication */
+ uint64_t reserved0:3;
+ uint64_t crsShift:1; /**< 5.4.7.3.7 CRS shift used for DL transmission */
+ uint64_t crsReMask:12; /**< 5.4.7.3.5 CRS resource element mask */
+ uint64_t txScheme:4; /**< 5.4.7.3.3 transmission scheme */
+ uint64_t numLayers:4; /**< 5.4.7.3.4 number of layers used for DL transmission */
+ uint64_t layerId:4; /**< 5.4.7.3.2 Layer ID for DL transmission */
+ uint64_t codebookIndex:8; /**< 5.4.7.3.1 precoder codebook used for transmission */
+ uint64_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */
+ uint64_t extType:7; /**< 5.4.6.1 extension type */
+ uint64_t ef:1; /**< 5.4.6.2 extension flag */
+
+ uint64_t beamIdAP1:16; /**< 5.4.7.3.8 beam id to be used for antenna port 1 */
+ uint64_t beamIdAP2:16; /**< 5.4.7.3.9 beam id to be used for antenna port 2 */
+ uint64_t beamIdAP3:16; /**< 5.4.7.3.10 beam id to be used for antenna port 3 */
+ uint64_t reserved2:16;
} __attribute__((__packed__));
/**
* DL Precoding Extension Type(ExtType 3) for non-first data layer.
* Defined in 5.4.7.3 Table 5-23.
* Only be used for LTE TM2-4 and not for other LTE TMs nor NR.
- * The structure is reordered for byte order conversion. Not supported.
+ * The structure is reordered for byte order conversion.
*/
struct xran_cp_radioapp_section_ext3_non_first {
/* 4 bytes, need to convert byte order at once */
uint32_t ef:1; /**< 5.4.6.2 extension flag */
} __attribute__((__packed__));
-#if 0
/**
* @ingroup xran_cp_pkt
*
* @description
* Modulation Compression Additional Parameter Extension Type(ExtType 5) for one scaler value.
- * Defined in 5.4.7.5 Table 5-26
- * Only applies to section type 1 3, and 5.
- * The structure is reordered for byte order conversion.
- */
-struct xran_cp_radioapp_section_ext5_1 {
- /* 8 bytes, need to convert byte order at once */
- uint32_t reserved:20;
- uint32_t mcScaleOffset:15; /**< 5.4.7.5.3 scaling value for modulation compression */
- uint32_t csf:1; /**< 5.4.7.5.2 constellation shift flag */
- uint32_t mcScaleReMask:12; /**< 5.4.7.5.1 modulation compression power scale RE mask */
-
- uint32_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */
- uint32_t extType:7; /**< 5.4.6.1 extension type */
- uint32_t ef:1; /**< 5.4.6.2 extension flag */
- } __attribute__((__packed__));
-
-/**
- * @ingroup xran_cp_pkt
- *
- * @description
- * Modulation Compression Additional Parameter Extension Type(ExtType 5) for two scaler values.
- * Defined in 5.4.7.5 Table 5-27
+ * Defined in 5.4.7.5 Table 5-26 and Table 5-27.
* Only applies to section type 1 3, and 5.
* The structure is reordered for byte order conversion.
*/
-struct xran_cp_radioapp_section_ext5_2 {
- /* 12 bytes, need to convert byte order for two parts respectively
- * - 2 and 8 bytes, reserved1 would be OK if it is zero
- */
- uint16_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */
- uint16_t extType:7; /**< 5.4.6.1 extension type */
- uint16_t ef:1; /**< 5.4.6.2 extension flag */
-
- uint32_t reserved0:8;
- uint32_t mcScaleOffset2:15; /**< 5.4.7.5.3 scaling value for modulation compression */
- uint32_t csf2:1; /**< 5.4.7.5.2 constellation shift flag */
- uint32_t mcScaleReMask2:12; /**< 5.4.7.5.1 modulation compression power scale RE mask */
- uint32_t mcScaleOffset1:15; /**< 5.4.7.5.3 scaling value for modulation compression */
- uint32_t csf1:1; /**< 5.4.7.5.2 constellation shift flag */
- uint32_t mcScaleReMask1:12; /**< 5.4.7.5.1 modulation compression power scale RE mask */
-
- uint16_t reserved1;
- } __attribute__((__packed__));
-#endif
-
struct xran_cp_radioapp_section_ext5 {
uint32_t reserved0:8;
uint32_t mcScaleOffset2:15; /**< 5.4.7.5.3 scaling value for modulation compression */
uint32_t mcScaleReMask1:12; /**< 5.4.7.5.1 modulation compression power scale RE mask */
} __attribute__((__packed__));
+
/**********************************************************
* Scheduling and Beam-forming Commands 5.4.2
**********************************************************/
* @ingroup xran_cp_pkt
*
* @description
- * Section definition for type 5: Channel Information (Table 5-6)
+ * Section definition for type 6: Channel Information (Table 5-6)
* Not supported in this release
*/
struct xran_cp_radioapp_section6 {
uint32_t sect_id:12; /**< 5.4.5.1 section identifier */
};
}fields;
+#ifdef FCN_ADAPT
+ uint8_t udCompHdr;
+ uint8_t reserved;
+#endif
} __rte_packed;
*****************************************************************************/
struct eth_xran_up_pkt_hdr
{
- struct ether_hdr eth_hdr;
+ struct rte_ether_hdr eth_hdr;
struct xran_up_pkt_hdr xran_hdr;
}__rte_packed;
return rte_pktmbuf_alloc(_eth_mbuf_pool);
}
-int xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype)
+int32_t xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id)
{
struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
int res = 0;
- mb->port = ctx->io_cfg.port[ETHDI_UP_VF];
- xran_add_eth_hdr_vlan(&ctx->entities[ID_RU], ethertype, mb, ctx->up_vtag);
+ mb->port = ctx->io_cfg.port[vf_id];
+ xran_add_eth_hdr_vlan(&ctx->entities[vf_id][ID_O_RU], ethertype, mb);
- res = xran_enqueue_mbuf(mb, ctx->tx_ring[ETHDI_UP_VF]);
+ res = xran_enqueue_mbuf(mb, ctx->tx_ring[vf_id]);
return res;
}
-int xran_ethdi_mbuf_send_cp(struct rte_mbuf *mb, uint16_t ethertype)
+int32_t xran_ethdi_mbuf_send_cp(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id)
{
struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
int res = 0;
- mb->port = ctx->io_cfg.port[ETHDI_CP_VF];
- xran_add_eth_hdr_vlan(&ctx->entities[ID_RU], ethertype, mb, ctx->cp_vtag);
+ mb->port = ctx->io_cfg.port[vf_id];
+ xran_add_eth_hdr_vlan(&ctx->entities[vf_id][ID_O_RU], ethertype, mb);
- res = xran_enqueue_mbuf(mb, ctx->tx_ring[ETHDI_CP_VF]);
+ res = xran_enqueue_mbuf(mb, ctx->tx_ring[vf_id]);
return res;
}
-#if 0
-void xran_ethdi_stop_tx()
-{
- struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
- rte_timer_stop_sync(&ctx->timer_tx);
-}
-#endif
struct {
uint16_t ethertype;
-int xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback)
+int32_t xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback)
{
int i;
{
struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
-#ifdef VLAN_SUPPORT
- if (rte_vlan_strip(pkt) == 0) {
- if (pkt->vlan_tci == ctx->cp_vtag) {
- dlog("VLAN tci matches %d", pkt->vlan_tci);
- } else {
- wlog("packet with wrong VLAN tag %d, dropping",
- pkt->vlan_tci);
- return 0;
- }
- } else
- dlog("Packet not vlan tagged");
-#endif
-
- const struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(pkt, void *);
+ const struct rte_ether_hdr *eth_hdr = rte_pktmbuf_mtod(pkt, void *);
#if defined(DPDKIO_DEBUG) && DPDKIO_DEBUG > 1
nlog("*** processing RX'ed packet of size %d ***",
return xran_handle_ether(rte_be_to_cpu_16(eth_hdr->ether_type), pkt, rx_time);
}
-#if 0
-//-------------------------------------------------------------------------------------------
-/** @ingroup xran
- *
- * @param[in] port - DPDK ETH port id
- *
- * @return void
- *
- * @description
- * Prints statistics of usage of DPDK port
- *
-**/
-//-------------------------------------------------------------------------------------------
-void xran_ethdi_ports_stats(void)
-{
- struct rte_eth_stats stats;
- struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
- int32_t i = 0;
-
- for(i = 0; i < ETHDI_VF_MAX; i++){
- /* Get stats (extended stats includes common stats) */
- rte_eth_stats_get(ctx->io_cfg.port[i], &stats);
- printf("DPDK stats:\n");
- printf("** Port %hhu **\n", ctx->io_cfg.port[i]);
- printf("ierrors:\t%lu\n", stats.ierrors);
- printf("oerrors:\t%lu\n", stats.oerrors);
- printf("ipackets:\t%lu\n", stats.ipackets);
- printf("opackets:\t%lu\n", stats.opackets);
- printf("imissed:\t%lu\n", stats.imissed);
- printf("rx_nombuf:\t%lu\n", stats.rx_nombuf);
- }
- return ;
-}
-#endif
/* Check the link status of all ports in up to 9s, and print them finally */
static void check_port_link_status(uint8_t portid)
{
uint8_t count, all_ports_up, print_flag = 0;
struct rte_eth_link link;
- printf("\nChecking link status");
+ printf("\nChecking link status portid [%d] ", portid);
fflush(stdout);
for (count = 0; count <= MAX_CHECK_TIME; count++) {
all_ports_up = 1;
}
-int xran_ethdi_init_dpdk_io(char *name, const struct xran_io_loop_cfg *io_cfg,
- int *lcore_id, struct ether_addr *p_lls_cu_addr, struct ether_addr *p_ru_addr,
- uint16_t cp_vlan, uint16_t up_vlan)
+int32_t
+xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg,
+ int *lcore_id, struct rte_ether_addr *p_o_du_addr,
+ struct rte_ether_addr *p_ru_addr)
{
- uint16_t port[2] = {0xffff, 0xffff};
+ uint16_t port[XRAN_VF_MAX];
struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
- int i;
+ int i,ivf;
char core_mask[64];
- long c_mask=0;
- char bbdev_wdev[32] = "";
- char bbdev_vdev[32] = "";
-
- char *argv[] = { name, /*"-c 0xFFFFF00000FFFFF"*/core_mask, "-n2", "--socket-mem=8192", "--proc-type=auto",
+ uint64_t c_mask = 0;
+ uint64_t nWorkerCore = 1;
+ uint32_t coreNum = sysconf(_SC_NPROCESSORS_CONF);
+ char bbdev_wdev[32] = "";
+ char bbdev_vdev[32] = "";
+ char iova_mode[32] = "--iova-mode=pa";
+ char socket_mem[32] = "--socket-mem=8192";
+ char socket_limit[32] = "--socket-limit=8192";
+ char ring_name[32] = "";
+
+ char *argv[] = { name, core_mask, "-n2", iova_mode, socket_mem, socket_limit, "--proc-type=auto",
"--file-prefix", name, "-w", "0000:00:00.0", bbdev_wdev, bbdev_vdev};
if (io_cfg == NULL)
if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_ON){
// hw-accelerated bbdev
printf("hw-accelerated bbdev %s\n", io_cfg->bbdev_dev[0]);
- snprintf(bbdev_wdev, sizeof(bbdev_wdev), "-w %s", io_cfg->bbdev_dev[0]);
+ snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-w %s", io_cfg->bbdev_dev[0]);
} else if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_OFF){
// hw-accelerated bbdev disable
if(io_cfg->bbdev_dev[0]){
printf("hw-accelerated bbdev disable %s\n", io_cfg->bbdev_dev[0]);
- snprintf(bbdev_wdev, sizeof(bbdev_wdev), "-b %s", io_cfg->bbdev_dev[0]);
+ snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-b %s", io_cfg->bbdev_dev[0]);
}
- snprintf(bbdev_wdev, sizeof(bbdev_wdev), "%s", "--vdev=baseband_turbo_sw");
+ snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "%s", "--vdev=baseband_turbo_sw");
} else {
rte_panic("Cannot init DPDK incorrect [bbdev_mode %d]\n", io_cfg->bbdev_mode);
}
}
+ if (io_cfg->dpdkIoVaMode == 1){
+ snprintf(iova_mode, RTE_DIM(iova_mode), "%s", "--iova-mode=va");
+ }
+
+ if (io_cfg->dpdkMemorySize){
+ snprintf(socket_mem, RTE_DIM(socket_mem), "--socket-mem=%d", io_cfg->dpdkMemorySize);
+ snprintf(socket_limit, RTE_DIM(socket_limit), "--socket-limit=%d", io_cfg->dpdkMemorySize);
+ }
+
c_mask = (long)(1L << io_cfg->core) |
- (long)(1L << io_cfg->system_core) |
- (long)(1L << io_cfg->pkt_proc_core) |
- (long)(1L << io_cfg->pkt_aux_core) |
- (long)(1L << io_cfg->timing_core);
+ (long)(1L << io_cfg->system_core) |
+ (long)(1L << io_cfg->timing_core);
+
+ nWorkerCore = 1L;
+ for (i = 0; i < coreNum; i++) {
+ if (nWorkerCore & (uint64_t)io_cfg->pkt_proc_core) {
+ c_mask |= nWorkerCore;
+ }
+ nWorkerCore = nWorkerCore << 1;
+ }
- printf("c_mask 0x%lx core %d system_core %d pkt_proc_core %d pkt_aux_core %d timing_core %d\n",
- c_mask, io_cfg->core, io_cfg->system_core, io_cfg->pkt_proc_core, io_cfg->pkt_aux_core, io_cfg->timing_core);
+ printf("total cores %d c_mask 0x%lx core %d [id] system_core %d [id] pkt_proc_core 0x%lx [mask] pkt_aux_core %d [id] timing_core %d [id]\n",
+ coreNum, c_mask, io_cfg->core, io_cfg->system_core, io_cfg->pkt_proc_core, io_cfg->pkt_aux_core, io_cfg->timing_core);
snprintf(core_mask, sizeof(core_mask), "-c 0x%lx", c_mask);
ctx->io_cfg = *io_cfg;
- ctx->ping_state = PING_IDLE;
- ctx->known_peers = 1;
- ctx->busy_poll_till = rte_rdtsc();
- ctx->cp_vtag = cp_vlan;
- ctx->up_vtag = up_vlan;
- for (i = 0; i <= ID_BROADCAST; i++) /* Initialize all as broadcast */
- memset(&ctx->entities[i], 0xFF, sizeof(ctx->entities[0]));
+ for (ivf = 0; ivf < XRAN_VF_MAX; ivf++){
+ for (i = 0; i <= ID_BROADCAST; i++) /* Initialize all as broadcast */
+ memset(&ctx->entities[ivf][i], 0xFF, sizeof(ctx->entities[0][0]));
+ }
printf("%s: Calling rte_eal_init:", __FUNCTION__);
for (i = 0; i < RTE_DIM(argv); i++)
#ifdef RTE_LIBRTE_PDUMP
/* initialize packet capture framework */
- rte_pdump_init(NULL);
+ rte_pdump_init();
#endif
/* Timers. */
PANIC_ON(*lcore_id == RTE_MAX_LCORE, "out of lcores for io_loop()");
+ for (i = 0; i < XRAN_VF_MAX; i++)
+ port[i] = 0xffff;
+
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
- for (i = 0; i < ETHDI_VF_MAX; i ++){
+ for (i = 0; i < XRAN_VF_MAX && i < io_cfg->num_vfs; i++){
if(io_cfg->dpdk_dev[i]){
- if (rte_eth_dev_attach(io_cfg->dpdk_dev[i], &port[i]) != 0 ||
- rte_eth_dev_count_avail() == 0)
- errx(1, "Network port doesn't exist.");
- xran_init_port(port[i], p_lls_cu_addr);
+ struct rte_dev_iterator iterator;
+ uint16_t port_id;
+
+ if (rte_dev_probe(io_cfg->dpdk_dev[i]) != 0 ||
+ rte_eth_dev_count_avail() == 0) {
+ errx(1, "Network port doesn't exist\n");
+ }
+
+ RTE_ETH_FOREACH_MATCHING_DEV(port_id, io_cfg->dpdk_dev[i], &iterator){
+ port[i] = port_id;
+ xran_init_port(port[i]);
+ }
} else {
printf("no DPDK port provided\n");
}
- if(i==0){
- ctx->tx_ring[i] = rte_ring_create("tx_ring_up", NUM_MBUFS,
- rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ);
- ctx->rx_ring[i] = rte_ring_create("rx_ring_up", NUM_MBUFS,
+
+ if(!(i & 1) ){
+ snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "tx_ring_up", i);
+ ctx->tx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING,
rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ);
- ctx->pkt_dump_ring[i] = rte_ring_create("pkt_dump_ring_up", NUM_MBUFS,
+ snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "rx_ring_up", i);
+ ctx->rx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING,
rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ);
}else {
- ctx->tx_ring[i] = rte_ring_create("tx_ring_cp", NUM_MBUFS,
+ snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "tx_ring_cp", i);
+ ctx->tx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING,
rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ);
- ctx->rx_ring[i] = rte_ring_create("rx_ring_cp", NUM_MBUFS,
- rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ);
- ctx->pkt_dump_ring[i] = rte_ring_create("pkt_dump_ring_cp", NUM_MBUFS,
+ snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "rx_ring_cp", i);
+ ctx->rx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING,
rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ);
}
- if(io_cfg->dpdk_dev[i])
+ if(io_cfg->dpdk_dev[i]){
check_port_link_status(port[i]);
+ }
}
} else {
rte_panic("ethdi_dpdk_io_loop() failed to start with RTE_PROC_SECONDARY\n");
PANIC_ON(ctx->tx_ring == NULL, "failed to allocate tx ring");
PANIC_ON(ctx->rx_ring == NULL, "failed to allocate rx ring");
PANIC_ON(ctx->pkt_dump_ring == NULL, "failed to allocate pkt dumping ring");
- for (i = 0; i < ETHDI_VF_MAX; i++){
+ for (i = 0; i < XRAN_VF_MAX && i < io_cfg->num_vfs; i++){
ctx->io_cfg.port[i] = port[i];
print_dbg("port_id 0x%04x\n", ctx->io_cfg.port[i]);
}
- if(io_cfg->dpdk_dev[ETHDI_UP_VF]){
- rte_eth_macaddr_get(port[ETHDI_UP_VF], &ctx->entities[io_cfg->id]);
- ether_addr_copy(p_ru_addr, &ctx->entities[ID_RU]);
+ for (i = 0; i < XRAN_VF_MAX && i < io_cfg->num_vfs; i++){
+ if(io_cfg->dpdk_dev[i]){
+ struct rte_ether_addr *p_addr;
+ rte_eth_macaddr_get(port[i], &ctx->entities[i][io_cfg->id]);
+
+ p_addr = &ctx->entities[i][io_cfg->id];
+ printf("vf %u local SRC MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8
+ " %02"PRIx8" %02"PRIx8" %02"PRIx8"\n",
+ (unsigned)i,
+ p_addr->addr_bytes[0], p_addr->addr_bytes[1], p_addr->addr_bytes[2],
+ p_addr->addr_bytes[3], p_addr->addr_bytes[4], p_addr->addr_bytes[5]);
+
+ p_addr = &p_ru_addr[i];
+ printf("vf %u remote DST MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8
+ " %02"PRIx8" %02"PRIx8" %02"PRIx8"\n",
+ (unsigned)i,
+ p_addr->addr_bytes[0], p_addr->addr_bytes[1], p_addr->addr_bytes[2],
+ p_addr->addr_bytes[3], p_addr->addr_bytes[4], p_addr->addr_bytes[5]);
+
+ rte_ether_addr_copy(&p_ru_addr[i], &ctx->entities[i][ID_O_RU]);
+ }
}
return 1;
int32_t process_dpdk_io(void)
{
struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
- const struct xran_io_loop_cfg *const cfg = &(xran_ethdi_get_ctx()->io_cfg);
- const int port[ETHDI_VF_MAX] = {cfg->port[ETHDI_UP_VF], cfg->port[ETHDI_CP_VF]};
+ struct xran_io_cfg * cfg = &(xran_ethdi_get_ctx()->io_cfg);
+ int32_t* port = &cfg->port[0];
int port_id = 0;
- for (port_id = 0; port_id < ETHDI_VF_MAX; port_id++){
+ rte_timer_manage();
+
+ for (port_id = 0; port_id < XRAN_VF_MAX && port_id < ctx->io_cfg.num_vfs; port_id++){
struct rte_mbuf *mbufs[BURST_RX_IO_SIZE];
if(port[port_id] == 0xFF)
return 0;
+
/* RX */
const uint16_t rxed = rte_eth_rx_burst(port[port_id], 0, mbufs, BURST_RX_IO_SIZE);
if (rxed != 0){
return 0;
}
-#if 0
-static inline void xran_process_rx_burst(struct rte_mbuf *mbufs[], uint16_t n_mbufs,
- uint64_t rx_time)
-{
- int i;
-
- if (!n_mbufs)
- return;
-
- for (i = 0; i < n_mbufs; ++i)
- {
- if (xran_ethdi_filter_packet(mbufs[i], rx_time) == MBUF_FREE)
- rte_pktmbuf_free(mbufs[i]);
- }
-
-#ifdef DPDKIO_LATENCY_DEBUG
- struct timeval tv_now, tv_diff;
-
- gettimeofday(&tv_now, NULL);
- if (n_mbufs > 1)
- nlog("Warning - received %d mbufs in a row", n_mbufs);
-
- timersub(&tv_now, &rx_time, &tv_diff);
- nlog("rx processing took %d usec", tv_diff.tv_usec);
-#endif
-}
-
-/*
- * This is the main DPDK-IO loop.
- * This will sleep if there's no packets incoming and there's
- * no work enqueued, sleep lenth is defined in IDLE_SLEEP_MICROSECS
- */
-int xran_ethdi_dpdk_io_loop(void *io_loop_cfg)
-{
- struct sched_param sched_param;
- int res = 0;
- struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx();
- const struct xran_io_loop_cfg *const cfg = &(xran_ethdi_get_ctx()->io_cfg);
- const int port[ETHDI_VF_MAX] = {cfg->port[ETHDI_UP_VF], cfg->port[ETHDI_CP_VF]};
-
- printf("%s [PORT: %d %d] [CPU %2d] [PID: %6d]\n", __FUNCTION__, port[ETHDI_UP_VF], port[ETHDI_CP_VF] , rte_lcore_id(), getpid());
-
- printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid());
- sched_param.sched_priority = XRAN_THREAD_DEFAULT_PRIO;
- if ((res = pthread_setschedparam(pthread_self(), SCHED_FIFO, &sched_param))) {
- printf("priority is not changed: coreId = %d, result1 = %d\n",rte_lcore_id(), res);
- }
-
- for (;;){
- if(process_dpdk_io()!=0)
- break;
- }
-
- fflush(stderr);
- fflush(stdout);
- puts("IO loop finished");
-
- return 0;
-}
-#endif
-
#define XRAN_THREAD_DEFAULT_PRIO (98)
-/* How often to ping? */
-#define PING_INTERVAL 300 /* (us) */
-#define PING_BUSY_POLL 50 /* (us) how long to actively wait for response */
-
/* If we're not receiving packets for more then this threshold... */
//#define SLEEP_THRESHOLD (rte_get_tsc_hz() / 30) /* = 33.3(3)ms */
/* we go to sleep for this long (usleep). Undef SLEEP_TRESHOLD to disable. */
#define TX_TIMER_INTERVAL ((rte_get_timer_hz() / 1000000000L)*interval_us*1000) /* nanosec */
#define TX_RX_LOOP_TIME rte_get_timer_hz() / 1
-enum xran_ping_states
-{
- PING_IDLE,
- PING_NEEDED,
- AWAITING_PONG
-};
-
-enum xran_ethdi_vf_ports
-{
- ETHDI_UP_VF = 0,
- ETHDI_CP_VF,
- ETHDI_VF_MAX
-};
-
-struct xran_io_loop_cfg
-{
- uint8_t id;
- char *dpdk_dev[ETHDI_VF_MAX];
- char *bbdev_dev[1];
- int bbdev_mode;
- int core;
- int system_core; /* Needed as DPDK will change your starting core. */
- int pkt_proc_core; /* Needed for packet processing thread. */
- int pkt_aux_core; /* Needed for packet dumping for debug purposes. */
- int timing_core; /* Needed for getting precise time */
- int port[ETHDI_VF_MAX]; /* This is auto-detected, no need to set. */
-};
-
/* CAUTION: Keep in sync with the string table below. */
enum xran_entities_id
{
- ID_LLS_CU,
- ID_RU,
+ ID_O_DU,
+ ID_O_RU,
ID_BROADCAST,
ID_MAX
};
static char *const entity_names[] = {
- "xRAN lls-CU sim app",
- "xRAN RU sim app",
+ "ORAN O-DU sim app",
+ "ORAN O-RU sim app",
};
typedef int (*PROCESS_CB)(void * arg);
+/**
+ * Structure storing internal configuration of workers
+ */
+struct xran_worker_config {
+ lcore_function_t *f;
+ void *arg;
+ int32_t state;
+};
+
struct xran_ethdi_ctx
{
- struct xran_io_loop_cfg io_cfg;
- struct ether_addr entities[ID_BROADCAST + 1];
- uint8_t ping_state;
- int ping_times;
- int known_peers;
-
- struct rte_ring *tx_ring[ETHDI_VF_MAX];
- struct rte_ring *rx_ring[ETHDI_VF_MAX];
- struct rte_ring *pkt_dump_ring[ETHDI_VF_MAX];
+ struct xran_io_cfg io_cfg;
+ struct rte_ether_addr entities[XRAN_VF_MAX][ID_BROADCAST + 1];
+
+ struct rte_ring *tx_ring[XRAN_VF_MAX];
+ struct rte_ring *rx_ring[XRAN_VF_MAX];
+ struct rte_ring *pkt_dump_ring[XRAN_VF_MAX];
struct rte_timer timer_autodetect;
struct rte_timer timer_ping;
struct rte_timer timer_sync;
struct rte_timer timer_tx;
- uint64_t busy_poll_till;
+ struct xran_worker_config pkt_wrk_cfg[RTE_MAX_LCORE];
unsigned pkt_stats[PKT_LAST + 1];
-
- uint16_t cp_vtag;
- uint16_t up_vtag;
};
enum {
};
extern enum xran_if_state xran_if_current_state;
-extern uint8_t ping_dst_id;
-extern struct ether_addr entities_addrs[];
static inline struct xran_ethdi_ctx *xran_ethdi_get_ctx(void)
{
typedef int (*ethertype_handler)(struct rte_mbuf *, uint64_t rx_time);
typedef int (*xran_ethdi_handler)(struct rte_mbuf *, int sender, uint64_t rx_time);
-typedef void (xran_ethdi_tx_callback)(struct rte_timer *tim, void *arg);
-
int xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback);
+int32_t xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg,
+ int *lcore_id, struct rte_ether_addr *p_o_du_addr,
+ struct rte_ether_addr *p_ru_addr);
-int xran_ethdi_init_dpdk_io(char *name, const struct xran_io_loop_cfg *io_cfg,
- int *lcore_id, struct ether_addr *p_lls_cu_addr, struct ether_addr *p_ru_addr,
- uint16_t cp_vlan, uint16_t up_vlan);
struct rte_mbuf *xran_ethdi_mbuf_alloc(void);
-int xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype);
-int xran_ethdi_mbuf_send_cp(struct rte_mbuf *mb, uint16_t ethertype);
-#if 0
-void xran_ethdi_stop_tx(void);
-void xran_ethdi_ports_stats(void);
-int xran_ethdi_dpdk_io_loop(void *);
-#endif
-int xran_ethdi_filter_packet(struct rte_mbuf *pkt, uint64_t rx_time);
+int32_t xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id);
+int32_t xran_ethdi_mbuf_send_cp(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id);
+int32_t xran_ethdi_filter_packet(struct rte_mbuf *pkt, uint64_t rx_time);
int32_t process_dpdk_io(void);
-
#ifdef __cplusplus
}
#endif
}
/* Init NIC port, then start the port */
-void xran_init_port(int p_id, struct ether_addr *p_lls_cu_addr)
+void xran_init_port(int p_id)
{
static uint16_t nb_rxd = BURST_SIZE;
static uint16_t nb_txd = BURST_SIZE;
- struct ether_addr addr;
+ struct rte_ether_addr addr;
struct rte_eth_rxmode rxmode =
{ .split_hdr_size = 0,
.max_rx_pkt_len = MAX_RX_LEN,
- .offloads=(DEV_RX_OFFLOAD_JUMBO_FRAME|DEV_RX_OFFLOAD_CRC_STRIP)
+ .offloads=(DEV_RX_OFFLOAD_JUMBO_FRAME /*|DEV_RX_OFFLOAD_CRC_STRIP*/)
};
struct rte_eth_txmode txmode = {
.mq_mode = ETH_MQ_TX_NONE
if (ret < 0)
rte_panic("Cannot start port %u (%d)\n", p_id, ret);
-// rte_eth_promiscuous_enable(p_id);
}
-#if 0
-void xran_memdump(void *addr, int len)
-{
- int i;
- char tmp_buf[len * 2 + len / 16 + 1];
- char *p = tmp_buf;
-
- return;
-#if 0
- for (i = 0; i < len; ++i) {
- sprintf(p, "%.2X ", ((uint8_t *)addr)[i]);
- if (i % 16 == 15)
- *p++ = '\n';
- }
- *p = 0;
- nlog("%s", tmp_buf);
-#endif
-}
/* Prepend ethernet header, possibly vlan tag. */
-void xran_add_eth_hdr(struct ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb)
+void xran_add_eth_hdr_vlan(struct rte_ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb)
{
/* add in the ethernet header */
- struct ether_hdr *const h = (void *)rte_pktmbuf_prepend(mb, sizeof(*h));
+ struct rte_ether_hdr *h = (struct rte_ether_hdr *)rte_pktmbuf_mtod(mb, struct rte_ether_hdr*);
PANIC_ON(h == NULL, "mbuf prepend of ether_hdr failed");
#if defined(DPDKIO_DEBUG) && DPDKIO_DEBUG > 1
{
- char dst[ETHER_ADDR_FMT_SIZE] = "(empty)";
- char src[ETHER_ADDR_FMT_SIZE] = "(empty)";
+ char dst[RTE_ETHER_ADDR_FMT_SIZE] = "(empty)";
+ char src[RTE_ETHER_ADDR_FMT_SIZE] = "(empty)";
- nlog("*** packet for TX below (len %d) ***", rte_pktmbuf_pkt_len(mb));
- ether_format_addr(src, sizeof(src), &h->s_addr);
- ether_format_addr(dst, sizeof(dst), &h->d_addr);
- nlog("src: %s dst: %s ethertype: %.4X", src, dst, ethertype);
+ printf("*** packet for TX below (len %d) ***", rte_pktmbuf_pkt_len(mb));
+ rte_ether_format_addr(src, sizeof(src), &h->s_addr);
+ rte_ether_format_addr(dst, sizeof(dst), &h->d_addr);
+ printf("src: %s dst: %s ethertype: %.4X", src, dst, ethertype);
}
#endif
-#ifdef VLAN_SUPPORT
- mb->vlan_tci = FLEXRAN_UP_VLAN_TAG;
- dlog("Inserting vlan tag of %d", FLEXRAN_UP_VLAN_TAG);
- rte_vlan_insert(&mb);
-#endif
-}
-
-int xran_send_mbuf(struct ether_addr *dst, struct rte_mbuf *mb)
-{
- xran_add_eth_hdr(dst, ETHER_TYPE_ETHDI, mb);
-
- if (rte_eth_tx_burst(mb->port, 0, &mb, 1) == 1)
- return 1;
-
- elog("packet sending failed on port %d", mb->port);
- rte_pktmbuf_free(mb);
-
- return 0; /* fail */
-}
-
-int xran_send_message_burst(int dst_id, int pkt_type, void *body, int len)
-{
- struct rte_mbuf *mbufs[BURST_SIZE];
- int i;
- uint8_t *src = body;
- const struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
-
- /* We're limited by maximum mbuf size on the receive size.
- * We can change this but this would be a bigger rework. */
- RTE_ASSERT(len < MBUF_POOL_ELM_BIG);
-
- /* Allocate the required number of mbufs. */
- const uint8_t count = ceilf((float)len / MAX_DATA_SIZE);
- if (rte_pktmbuf_alloc_bulk(_eth_mbuf_pool, mbufs, count) != 0)
- rte_panic("Failed to allocate %d mbufs\n", count);
-
- nlog("burst transfer with data size %lu", MAX_DATA_SIZE);
- for (i = 0; len > 0; ++i) {
- char *p;
- struct burst_hdr *bhdr;
- struct ethdi_hdr *edi_hdr;
-
- /* Setup the ethdi_hdr. */
- edi_hdr = (void *)rte_pktmbuf_append(mbufs[i], sizeof(*edi_hdr));
- if (edi_hdr == NULL)
- rte_panic("append of ethdi_hdr failed\n");
- edi_hdr->pkt_type = PKT_BURST;
- /* edi_hdr->source_id setup in tx_from_ring */
- edi_hdr->dest_id = dst_id;
-
- /* Setup the burst header */
- bhdr = (void *)rte_pktmbuf_append(mbufs[i], sizeof(*bhdr));
- if (bhdr == NULL) /* append failed. */
- rte_panic("mbuf prepend of burst_hdr failed\n");
- bhdr->original_type = pkt_type;
- bhdr->pkt_idx = i; /* save the index of the burst chunk. */
- bhdr->total_pkts = count;
-
- /* now copy in the actual data */
- const int curr_data_len = RTE_MIN(len, MAX_TX_LEN -
- rte_pktmbuf_pkt_len(mbufs[i]) - sizeof(struct ether_hdr));
- p = (void *)rte_pktmbuf_append(mbufs[i], curr_data_len);
- if (p == NULL)
- rte_panic("mbuf append of %d data bytes failed\n", curr_data_len);
- /* This copy is unavoidable, as we're splitting one big buffer
- * into multiple mbufs. */
- rte_memcpy(p, src, curr_data_len);
-
- dlog("curr_data_len[%d] = %d", i, curr_data_len);
- dlog("packet %d size %d", i, rte_pktmbuf_pkt_len(mbufs[i]));
-
- /* Update our source data pointer and remaining length. */
- len -= curr_data_len;
- src += curr_data_len;
- }
-
- /* Now enqueue the full prepared burst. */
- i = rte_ring_enqueue_bulk(ctx->tx_ring[0], (void **)mbufs, count, NULL);
- PANIC_ON(i != count, "failed to enqueue all mbufs: %d/%d", i, count);
- dlog("%d packets enqueued on port %d.", count, ctx->io_cfg.port);
-
- return 1;
-}
-
-#endif
-
-/* Prepend ethernet header, possibly vlan tag. */
-void xran_add_eth_hdr_vlan(struct ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb, uint16_t vlan_tci)
-{
- /* add in the ethernet header */
- struct ether_hdr *h = (struct ether_hdr *)rte_pktmbuf_mtod(mb, struct ether_hdr*);
-
- PANIC_ON(h == NULL, "mbuf prepend of ether_hdr failed");
-
- /* Fill in the ethernet header. */
- rte_eth_macaddr_get(mb->port, &h->s_addr); /* set source addr */
- h->d_addr = *dst; /* set dst addr */
- h->ether_type = rte_cpu_to_be_16(ethertype); /* ethertype too */
-
-#if defined(DPDKIO_DEBUG) && DPDKIO_DEBUG > 1
- {
- char dst[ETHER_ADDR_FMT_SIZE] = "(empty)";
- char src[ETHER_ADDR_FMT_SIZE] = "(empty)";
-
- nlog("*** packet for TX below (len %d) ***", rte_pktmbuf_pkt_len(mb));
- ether_format_addr(src, sizeof(src), &h->s_addr);
- ether_format_addr(dst, sizeof(dst), &h->d_addr);
- nlog("src: %s dst: %s ethertype: %.4X", src, dst, ethertype);
- }
-#endif
-#ifdef VLAN_SUPPORT
- mb->vlan_tci = vlan_tci;
- dlog("Inserting vlan tag of %d", vlan_tci);
- rte_vlan_insert(&mb);
-#endif
}
#define BURST_SIZE 4096
-//#define VLAN_SUPPORT
-#define FLEXRAN_UP_VLAN_TAG 2
-#define ETHER_TYPE_ETHDI ETHER_TYPE_IPv4 /* hack needed for jumbo frames */
+#define ETHER_TYPE_ETHDI RTE_ETHER_TYPE_IPV4 /* hack needed for jumbo frames */
#define ETHER_TYPE_ECPRI 0xAEFE
#define ETHER_TYPE_SYNC 0xBEFE
#define ETHER_TYPE_START_TX 0xCEFE
-#define NUM_MBUFS 65536
+#define NUM_MBUFS 65535/*16383*/ /*65535*/ /** optimal is n = (2^q - 1) */
+#define NUM_MBUFS_RING NUM_MBUFS+1 /** The size of the ring (must be a power of 2) */
+
#define MBUF_CACHE 256
-#define MBUF_POOL_ELM_SMALL 1500 /* regular ethernet MTU, most compatible */
-#define MBUF_POOL_ELEMENT MAX_RX_LEN
+#define MBUF_POOL_ELM_SMALL (1500 + RTE_PKTMBUF_HEADROOM )/* regular ethernet MTU, most compatible */
+#define MBUF_POOL_ELEMENT (MAX_RX_LEN + RTE_PKTMBUF_HEADROOM)
#define MAX_RX_LEN 9600
#define MAX_TX_LEN (MAX_RX_LEN - 14) /* headroom for rx driver */
void xran_init_mbuf_pool(void);
-void xran_init_port(int port, struct ether_addr *p_lls_cu_addr);
+void xran_init_port(int port);
-void xran_add_eth_hdr_vlan(struct ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb, uint16_t vlan_tci);
+void xran_add_eth_hdr_vlan(struct rte_ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb);
#if 0
void xran_memdump(void *addr, int len);
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief xRAN BFP compression/decompression for C-plane with 16T16R
+ *
+ * @file xran_bfp_cplane16.cpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#include "xran_compression.hpp"
+#include "xran_bfp_utils.hpp"
+#include <complex>
+#include <algorithm>
+#include <immintrin.h>
+
+
+namespace BFP_CPlane_16
+{
+ /// Namespace constants
+ const int k_numDataElements = 32; /// 16 IQ pairs
+
+ inline int
+ maxAbsOneBlock(const __m512i* inData)
+ {
+ /// Compute abs of input data
+ const auto thisRegAbs = _mm512_abs_epi16(*inData);
+ /// Horizontal max across register
+ return BlockFloatCompander::horizontalMax1x32(thisRegAbs);
+ }
+
+ /// Compute exponent value for a set of 16 RB from the maximum absolute value.
+ inline __m512i
+ computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for a set of 4 RB from the maximum absolute value.
+ inline __m512i
+ computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for 1 RB from the maximum absolute value.
+ inline uint8_t
+ computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ ((uint32_t*)&maxAbs)[0] = maxAbsOneBlock(dataInAddr);
+ /// Calculate exponent
+ const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ return ((uint8_t*)&exps)[0];
+ }
+
+
+
+ /// Apply compression to one compression block
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr,
+ const int iqWidth, const uint8_t thisExp, const uint16_t rbWriteMask)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(*dataIn, thisExp);
+ /// Pack compressed data network byte order
+ const auto compDataBytePacked = networkBytePack(compData);
+ /// Now have 1 register worth of bytes separated into 4 chunks (1 per lane)
+ /// Use four offset stores to join
+ const auto thisOutRegAddr = outBlockAddr + 1;
+ _mm_mask_storeu_epi8(thisOutRegAddr, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
+ _mm_mask_storeu_epi8(thisOutRegAddr + iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
+ _mm_mask_storeu_epi8(thisOutRegAddr + (2 * iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+ _mm_mask_storeu_epi8(thisOutRegAddr + (3 * iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 3));
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataInAddr + n, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataInAddr + n, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 1 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompressionN_1RB<networkBytePack>(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, rbWriteMask);
+ }
+
+ /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compressN_16RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask);
+ break;
+
+ case 4:
+ compressN_4RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask);
+ break;
+
+ case 1:
+ compressN_1RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask);
+ break;
+ }
+ }
+
+
+
+ /// Apply 8b compression to 1 compression block.
+ inline void
+ applyCompression8_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(*dataIn, thisExp);
+ /// Truncate to 8bit and store
+ constexpr uint32_t k_writeMask = 0xFFFFFFFF;
+ _mm256_mask_storeu_epi8(outBlockAddr + 1, k_writeMask, _mm512_cvtepi16_epi8(compData));
+ }
+
+ /// Derive and apply 8b compression to 16 compression blocks
+ inline void
+ compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 4 compression blocks
+ inline void
+ compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 1 compression block
+ inline void
+ compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent);
+ }
+
+ /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth.
+ inline void
+ compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compress8_16RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 4:
+ compress8_4RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 1:
+ compress8_1RB(dataIn, dataOut, totShiftBits);
+ break;
+ }
+ }
+
+
+
+ /// Expand 1 compression block
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ inline void
+ applyExpansionN_1RB(const uint8_t* expAddr, __m512i* dataOutAddr, const int maxExpShift)
+ {
+ const auto thisExpShift = maxExpShift - *expAddr;
+ /// Unpack network order packed data
+ const auto inDataUnpacked = networkByteUnpack(expAddr + 1);
+ /// Apply exponent scaling (by appropriate arithmetic shift right)
+ const auto expandedData = _mm512_srai_epi16(inDataUnpacked, thisExpShift);
+ /// Write expanded data to output
+ static constexpr uint8_t k_WriteMask = 0xFF;
+ _mm512_mask_storeu_epi64(dataOutAddr, k_WriteMask, expandedData);
+ }
+
+ /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ void
+ expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int totNumBytesPerBlock, const int maxExpShift)
+ {
+ __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift);
+ }
+ break;
+
+ case 1:
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed, dataOutAddr, maxExpShift);
+ break;
+ }
+ }
+
+
+ /// Apply expansion to 1 compression block
+ inline void
+ applyExpansion8_1RB(const uint8_t* expAddr, __m512i* dataOutAddr)
+ {
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(expAddr + 1);
+ const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn);
+ const auto expData = _mm512_slli_epi16(compData16, *expAddr);
+ static constexpr uint8_t k_WriteMask = 0xFF;
+ _mm512_mask_storeu_epi64(dataOutAddr, k_WriteMask, expData);
+ }
+
+ /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth.
+ void
+ expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut)
+ {
+ __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n);
+ }
+ break;
+
+ case 1:
+ applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr);
+ break;
+ }
+ }
+}
+
+
+/// Main kernel function for 16 antenna C-plane compression.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPCompressCtrlPlane16Avx512(const ExpandedData& dataIn, CompressedData* dataOut)
+{
+ /// Compensation for extra zeros in 32b leading zero count when computing exponent
+ const auto totShiftBits8 = _mm512_set1_epi32(25);
+ const auto totShiftBits9 = _mm512_set1_epi32(24);
+ const auto totShiftBits10 = _mm512_set1_epi32(23);
+ const auto totShiftBits12 = _mm512_set1_epi32(21);
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_16::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+
+ /// Compressed data write mask for each iqWidth option
+ constexpr uint16_t rbWriteMask9 = 0x01FF;
+ constexpr uint16_t rbWriteMask10 = 0x03FF;
+ constexpr uint16_t rbWriteMask12 = 0x0FFF;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_16::compressByAlloc8(dataIn, dataOut, totShiftBits8);
+ break;
+
+ case 9:
+ BFP_CPlane_16::compressByAllocN<BlockFloatCompander::networkBytePack9b>(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, rbWriteMask9);
+ break;
+
+ case 10:
+ BFP_CPlane_16::compressByAllocN<BlockFloatCompander::networkBytePack10b>(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, rbWriteMask10);
+ break;
+
+ case 12:
+ BFP_CPlane_16::compressByAllocN<BlockFloatCompander::networkBytePack12b>(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, rbWriteMask12);
+ break;
+ }
+}
+
+
+/// Main kernel function for 16 antenna C-plane expansion.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPExpandCtrlPlane16Avx512(const CompressedData& dataIn, ExpandedData* dataOut)
+{
+ constexpr int k_maxExpShift9 = 7;
+ constexpr int k_maxExpShift10 = 6;
+ constexpr int k_maxExpShift12 = 4;
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_16::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_16::expandByAlloc8(dataIn, dataOut);
+ break;
+
+ case 9:
+ BFP_CPlane_16::expandByAllocN<BlockFloatCompander::networkByteUnpack9b>(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift9);
+ break;
+
+ case 10:
+ BFP_CPlane_16::expandByAllocN<BlockFloatCompander::networkByteUnpack10b>(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift10);
+ break;
+
+ case 12:
+ BFP_CPlane_16::expandByAllocN<BlockFloatCompander::networkByteUnpack12b>(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift12);
+ break;
+ }
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief xRAN BFP compression/decompression for C-plane with 32T32R
+ *
+ * @file xran_bfp_cplane32.cpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#include "xran_compression.hpp"
+#include "xran_bfp_utils.hpp"
+#include <complex>
+#include <algorithm>
+#include <immintrin.h>
+
+
+namespace BFP_CPlane_32
+{
+ /// Namespace constants
+ const int k_numDataElements = 64; /// 16 IQ pairs
+ const int k_numRegsPerBlock = 2; /// Number of AVX512 registers per compression block (input)
+
+ inline int
+ maxAbsOneBlock(const __m512i* inData)
+ {
+ /// Vertical maxAbs on all registers
+ __m512i maxAbsReg = __m512i();
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ const auto thisRegAbs = _mm512_abs_epi16(inData[n]);
+ maxAbsReg = _mm512_max_epi16(thisRegAbs, maxAbsReg);
+ }
+ /// Horizontal max across remaining register
+ return BlockFloatCompander::horizontalMax1x32(maxAbsReg);
+ }
+
+ /// Compute exponent value for a set of 16 RB from the maximum absolute value
+ inline __m512i
+ computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for a set of 4 RB from the maximum absolute value
+ inline __m512i
+ computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for 1 RB from the maximum absolute value
+ inline uint8_t
+ computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ ((uint32_t*)&maxAbs)[0] = maxAbsOneBlock(dataInAddr);
+ /// Calculate exponent
+ const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ return ((uint8_t*)&exps)[0];
+ }
+
+
+
+ /// Apply compression to one compression block
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr,
+ const int iqWidth, const uint8_t thisExp, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(dataIn[n], thisExp);
+ /// Pack compressed data network byte order
+ const auto compDataBytePacked = networkBytePack(compData);
+ /// Now have 1 register worth of bytes separated into 4 chunks (1 per lane)
+ /// Use four offset stores to join
+ const auto thisOutRegAddr = outBlockAddr + 1 + n * totNumBytesPerReg;
+ _mm_mask_storeu_epi8(thisOutRegAddr, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
+ _mm_mask_storeu_epi8(thisOutRegAddr + iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
+ _mm_mask_storeu_epi8(thisOutRegAddr + (2 * iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+ _mm_mask_storeu_epi8(thisOutRegAddr + (3 * iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 3));
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 1 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompressionN_1RB<networkBytePack>(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, totNumBytesPerReg, rbWriteMask);
+ }
+
+ /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compressN_16RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask);
+ break;
+
+ case 4:
+ compressN_4RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask);
+ break;
+
+ case 1:
+ compressN_1RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask);
+ break;
+ }
+ }
+
+
+
+ /// Apply 8b compression to 1 compression block.
+ inline void
+ applyCompression8_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+ constexpr uint32_t k_writeMask = 0xFFFFFFFF;
+ __m256i* regOutAddr = reinterpret_cast<__m256i*>(outBlockAddr + 1);
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(dataIn[n], thisExp);
+ /// Truncate to 8bit and store
+ _mm256_mask_storeu_epi8(regOutAddr + n, k_writeMask, _mm512_cvtepi16_epi8(compData));
+ }
+ }
+
+ /// Derive and apply 8b compression to 16 compression blocks
+ inline void
+ compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 4 compression blocks
+ inline void
+ compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 1 compression block
+ inline void
+ compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent);
+ }
+
+ /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth.
+ inline void
+ compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compress8_16RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 4:
+ compress8_4RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 1:
+ compress8_1RB(dataIn, dataOut, totShiftBits);
+ break;
+ }
+ }
+
+
+
+ /// Expand 1 compression block
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ inline void
+ applyExpansionN_1RB(const uint8_t* expAddr, __m512i* dataOutAddr, const int maxExpShift, const int totNumBytesPerReg)
+ {
+ static constexpr uint8_t k_WriteMask = 0xFF;
+ const auto thisExpShift = maxExpShift - *expAddr;
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ const auto thisInRegAddr = expAddr + 1 + n * totNumBytesPerReg;
+ /// Unpack network order packed data
+ const auto inDataUnpacked = networkByteUnpack(thisInRegAddr);
+ /// Apply exponent scaling (by appropriate arithmetic shift right)
+ const auto expandedData = _mm512_srai_epi16(inDataUnpacked, thisExpShift);
+ /// Write expanded data to output
+ _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expandedData);
+ }
+ }
+
+ /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ void
+ expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int totNumBytesPerBlock, const int totNumBytesPerReg, const int maxExpShift)
+ {
+ __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg);
+ }
+ break;
+
+ case 1:
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed, dataOutAddr, maxExpShift, totNumBytesPerReg);
+ break;
+ }
+ }
+
+
+ /// Apply expansion to 1 compression block
+ inline void
+ applyExpansion8_1RB(const uint8_t* expAddr, __m512i* dataOutAddr)
+ {
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(expAddr + 1);
+ static constexpr uint8_t k_WriteMask = 0xFF;
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ const auto compData16 = _mm512_cvtepi8_epi16(rawDataIn[n]);
+ const auto expData = _mm512_slli_epi16(compData16, *expAddr);
+ _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expData);
+ }
+ }
+
+ /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth.
+ void
+ expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut)
+ {
+ __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock);
+ }
+ break;
+
+ case 1:
+ applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr);
+ break;
+ }
+ }
+}
+
+
+/// Main kernel function for 32 antenna C-plane compression.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPCompressCtrlPlane32Avx512(const ExpandedData& dataIn, CompressedData* dataOut)
+{
+ /// Compensation for extra zeros in 32b leading zero count when computing exponent
+ const auto totShiftBits8 = _mm512_set1_epi32(25);
+ const auto totShiftBits9 = _mm512_set1_epi32(24);
+ const auto totShiftBits10 = _mm512_set1_epi32(23);
+ const auto totShiftBits12 = _mm512_set1_epi32(21);
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_32::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+ /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8
+ const auto totNumBytesPerReg = dataIn.iqWidth << 2;
+
+ /// Compressed data write mask for each iqWidth option
+ constexpr uint16_t rbWriteMask9 = 0x01FF;
+ constexpr uint16_t rbWriteMask10 = 0x03FF;
+ constexpr uint16_t rbWriteMask12 = 0x0FFF;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_32::compressByAlloc8(dataIn, dataOut, totShiftBits8);
+ break;
+
+ case 9:
+ BFP_CPlane_32::compressByAllocN<BlockFloatCompander::networkBytePack9b>(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask9);
+ break;
+
+ case 10:
+ BFP_CPlane_32::compressByAllocN<BlockFloatCompander::networkBytePack10b>(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask10);
+ break;
+
+ case 12:
+ BFP_CPlane_32::compressByAllocN<BlockFloatCompander::networkBytePack12b>(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask12);
+ break;
+ }
+}
+
+
+/// Main kernel function for 32 antenna C-plane expansion.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPExpandCtrlPlane32Avx512(const CompressedData& dataIn, ExpandedData* dataOut)
+{
+ constexpr int k_maxExpShift9 = 7;
+ constexpr int k_maxExpShift10 = 6;
+ constexpr int k_maxExpShift12 = 4;
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_32::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+ /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8
+ const auto totNumBytesPerReg = dataIn.iqWidth << 2;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_32::expandByAlloc8(dataIn, dataOut);
+ break;
+
+ case 9:
+ BFP_CPlane_32::expandByAllocN<BlockFloatCompander::networkByteUnpack9b>(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift9);
+ break;
+
+ case 10:
+ BFP_CPlane_32::expandByAllocN<BlockFloatCompander::networkByteUnpack10b>(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift10);
+ break;
+
+ case 12:
+ BFP_CPlane_32::expandByAllocN<BlockFloatCompander::networkByteUnpack12b>(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift12);
+ break;
+ }
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief xRAN BFP compression/decompression for C-plane with 64T64R
+ *
+ * @file xran_bfp_cplane64.cpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#include "xran_compression.hpp"
+#include "xran_bfp_utils.hpp"
+#include <complex>
+#include <algorithm>
+#include <immintrin.h>
+
+
+namespace BFP_CPlane_64
+{
+ /// Namespace constants
+ const int k_numDataElements = 128; /// 16 IQ pairs
+ const int k_numRegsPerBlock = 4; /// Number of AVX512 registers per compression block (input)
+
+ inline int
+ maxAbsOneBlock(const __m512i* inData)
+ {
+ /// Vertical maxAbs on all registers
+ __m512i maxAbsReg = __m512i();
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ const auto thisRegAbs = _mm512_abs_epi16(inData[n]);
+ maxAbsReg = _mm512_max_epi16(thisRegAbs, maxAbsReg);
+ }
+ /// Horizontal max across remaining register
+ return BlockFloatCompander::horizontalMax1x32(maxAbsReg);
+ }
+
+ /// Compute exponent value for a set of 16 RB from the maximum absolute value
+ inline __m512i
+ computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for a set of 4 RB from the maximum absolute value
+ inline __m512i
+ computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for 1 RB from the maximum absolute value
+ inline uint8_t
+ computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ ((uint32_t*)&maxAbs)[0] = maxAbsOneBlock(dataInAddr);
+ /// Calculate exponent
+ const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ return ((uint8_t*)&exps)[0];
+ }
+
+
+
+ /// Apply compression to one compression block
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr,
+ const int iqWidth, const uint8_t thisExp, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(dataIn[n], thisExp);
+ /// Pack compressed data network byte order
+ const auto compDataBytePacked = networkBytePack(compData);
+ /// Now have 1 register worth of bytes separated into 4 chunks (1 per lane)
+ /// Use four offset stores to join
+ const auto thisOutRegAddr = outBlockAddr + 1 + n * totNumBytesPerReg;
+ _mm_mask_storeu_epi8(thisOutRegAddr, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
+ _mm_mask_storeu_epi8(thisOutRegAddr + iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
+ _mm_mask_storeu_epi8(thisOutRegAddr + (2 * iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+ _mm_mask_storeu_epi8(thisOutRegAddr + (3 * iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 3));
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 1 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompressionN_1RB<networkBytePack>(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, totNumBytesPerReg, rbWriteMask);
+ }
+
+ /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint16_t rbWriteMask)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compressN_16RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask);
+ break;
+
+ case 4:
+ compressN_4RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask);
+ break;
+
+ case 1:
+ compressN_1RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask);
+ break;
+ }
+ }
+
+
+
+ /// Apply 8b compression to 1 compression block.
+ inline void
+ applyCompression8_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+ constexpr uint32_t k_writeMask = 0xFFFFFFFF;
+ __m256i* regOutAddr = reinterpret_cast<__m256i*>(outBlockAddr + 1);
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(dataIn[n], thisExp);
+ /// Truncate to 8bit and store
+ _mm256_mask_storeu_epi8(regOutAddr + n, k_writeMask, _mm512_cvtepi16_epi8(compData));
+ }
+ }
+
+ /// Derive and apply 8b compression to 16 compression blocks
+ inline void
+ compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 4 compression blocks
+ inline void
+ compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 1 compression block
+ inline void
+ compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent);
+ }
+
+ /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth.
+ inline void
+ compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compress8_16RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 4:
+ compress8_4RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 1:
+ compress8_1RB(dataIn, dataOut, totShiftBits);
+ break;
+ }
+ }
+
+
+
+ /// Expand 1 compression block
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ inline void
+ applyExpansionN_1RB(const uint8_t* expAddr, __m512i* dataOutAddr, const int maxExpShift, const int totNumBytesPerReg)
+ {
+ static constexpr uint8_t k_WriteMask = 0xFF;
+ const auto thisExpShift = maxExpShift - *expAddr;
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ const auto thisInRegAddr = expAddr + 1 + n * totNumBytesPerReg;
+ /// Unpack network order packed data
+ const auto inDataUnpacked = networkByteUnpack(thisInRegAddr);
+ /// Apply exponent scaling (by appropriate arithmetic shift right)
+ const auto expandedData = _mm512_srai_epi16(inDataUnpacked, thisExpShift);
+ /// Write expanded data to output
+ _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expandedData);
+ }
+ }
+
+ /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ void expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int totNumBytesPerBlock, const int totNumBytesPerReg, const int maxExpShift)
+ {
+ __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg);
+ }
+ break;
+
+ case 1:
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed, dataOutAddr, maxExpShift, totNumBytesPerReg);
+ break;
+ }
+ }
+
+
+ /// Apply expansion to 1 compression block
+ inline void
+ applyExpansion8_1RB(const uint8_t* expAddr, __m512i* dataOutAddr)
+ {
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(expAddr + 1);
+ static constexpr uint8_t k_WriteMask = 0xFF;
+#pragma unroll(k_numRegsPerBlock)
+ for (int n = 0; n < k_numRegsPerBlock; ++n)
+ {
+ const auto compData16 = _mm512_cvtepi8_epi16(rawDataIn[n]);
+ const auto expData = _mm512_slli_epi16(compData16, *expAddr);
+ _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expData);
+ }
+ }
+
+ /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth.
+ void
+ expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut)
+ {
+ __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock);
+ }
+ break;
+
+ case 1:
+ applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr);
+ break;
+ }
+ }
+}
+
+
+/// Main kernel function for 64 antenna C-plane compression.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPCompressCtrlPlane64Avx512(const ExpandedData& dataIn, CompressedData* dataOut)
+{
+ /// Compensation for extra zeros in 32b leading zero count when computing exponent
+ const auto totShiftBits8 = _mm512_set1_epi32(25);
+ const auto totShiftBits9 = _mm512_set1_epi32(24);
+ const auto totShiftBits10 = _mm512_set1_epi32(23);
+ const auto totShiftBits12 = _mm512_set1_epi32(21);
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_64::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+ /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8
+ const auto totNumBytesPerReg = dataIn.iqWidth << 2;
+
+ /// Compressed data write mask for each iqWidth option
+ constexpr uint16_t rbWriteMask9 = 0x01FF;
+ constexpr uint16_t rbWriteMask10 = 0x03FF;
+ constexpr uint16_t rbWriteMask12 = 0x0FFF;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_64::compressByAlloc8(dataIn, dataOut, totShiftBits8);
+ break;
+
+ case 9:
+ BFP_CPlane_64::compressByAllocN<BlockFloatCompander::networkBytePack9b>(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask9);
+ break;
+
+ case 10:
+ BFP_CPlane_64::compressByAllocN<BlockFloatCompander::networkBytePack10b>(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask10);
+ break;
+
+ case 12:
+ BFP_CPlane_64::compressByAllocN<BlockFloatCompander::networkBytePack12b>(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask12);
+ break;
+ }
+}
+
+
+/// Main kernel function for 64 antenna C-plane expansion.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPExpandCtrlPlane64Avx512(const CompressedData& dataIn, ExpandedData* dataOut)
+{
+ constexpr int k_maxExpShift9 = 7;
+ constexpr int k_maxExpShift10 = 6;
+ constexpr int k_maxExpShift12 = 4;
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_64::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+ /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8
+ const auto totNumBytesPerReg = dataIn.iqWidth << 2;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_64::expandByAlloc8(dataIn, dataOut);
+ break;
+
+ case 9:
+ BFP_CPlane_64::expandByAllocN<BlockFloatCompander::networkByteUnpack9b>(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift9);
+ break;
+
+ case 10:
+ BFP_CPlane_64::expandByAllocN<BlockFloatCompander::networkByteUnpack10b>(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift10);
+ break;
+
+ case 12:
+ BFP_CPlane_64::expandByAllocN<BlockFloatCompander::networkByteUnpack12b>(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift12);
+ break;
+ }
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief xRAN BFP compression/decompression for C-plane with 8T8R
+ *
+ * @file xran_bfp_cplane8.cpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#include "xran_compression.hpp"
+#include "xran_bfp_utils.hpp"
+#include <complex>
+#include <algorithm>
+#include <immintrin.h>
+
+
+namespace BFP_CPlane_8
+{
+ /// Namespace constants
+ const int k_numDataElements = 16; /// 16 IQ pairs
+
+ inline __m512i
+ maxAbsOneReg(const __m512i maxAbs, const __m512i* inData, const int pairNum)
+ {
+ /// Compute abs of input data
+ const auto thisRegAbs = _mm512_abs_epi16(*inData);
+ /// Swap each IQ pair in each lane (via 32b rotation) and compute max of
+ /// each pair.
+ const auto maxRot16 = _mm512_rol_epi32(thisRegAbs, BlockFloatCompander::k_numBitsIQ);
+ const auto maxAbsIQ = _mm512_max_epi16(thisRegAbs, maxRot16);
+ /// Convert to 32b values
+ const auto maxAbsIQ32 = BlockFloatCompander::maskUpperWord(maxAbsIQ);
+ /// Swap 32b in each 64b chunk via rotation and compute 32b max
+ /// Results in blocks of 64b with 4 repeated 16b max values
+ const auto maxRot32 = _mm512_rol_epi64(maxAbsIQ32, BlockFloatCompander::k_numBitsIQPair);
+ const auto maxAbs32 = _mm512_max_epi32(maxAbsIQ32, maxRot32);
+ /// First 64b permute and max
+ /// Results in blocks of 128b with 8 repeated 16b max values
+ constexpr uint8_t k_perm64A = 0xB1;
+ const auto maxPerm64A = _mm512_permutex_epi64(maxAbs32, k_perm64A);
+ const auto maxAbs64 = _mm512_max_epi64(maxAbs32, maxPerm64A);
+ /// Second 64b permute and max
+ /// Results in blocks of 256b with 16 repeated 16b max values
+ constexpr uint8_t k_perm64B = 0x4E;
+ const auto maxPerm64B = _mm512_permutex_epi64(maxAbs64, k_perm64B);
+ const auto maxAbs128 = _mm512_max_epi64(maxAbs64, maxPerm64B);
+ /// Now register contains repeated max values for two compression blocks
+ /// Permute the desired results into maxAbs
+ const auto k_selectVals = _mm512_set_epi32(24, 16, 24, 16, 24, 16, 24, 16,
+ 24, 16, 24, 16, 24, 16, 24, 16);
+ constexpr uint16_t k_2ValsMsk[8] = { 0x0003, 0x000C, 0x0030, 0x00C0, 0x0300, 0x0C00, 0x3000, 0xC000 };
+ return _mm512_mask_permutex2var_epi32(maxAbs, k_2ValsMsk[pairNum], k_selectVals, maxAbs128);
+ }
+
+ /// Compute exponent value for a set of 16 RB from the maximum absolute value.
+ inline __m512i
+ computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(8)
+ for (int n = 0; n < 8; ++n)
+ {
+ maxAbs = maxAbsOneReg(maxAbs, dataInAddr + n, n);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for a set of 4 RB from the maximum absolute value.
+ inline __m512i
+ computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(2)
+ for (int n = 0; n < 2; ++n)
+ {
+ maxAbs = maxAbsOneReg(maxAbs, dataInAddr + n, n);
+ }
+ /// Calculate exponent
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
+
+ /// Compute exponent value for 1 RB from the maximum absolute value.
+ inline uint8_t
+ computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ maxAbs = maxAbsOneReg(maxAbs, dataInAddr, 0);
+ /// Calculate exponent
+ const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ return ((uint8_t*)&exps)[0];
+ }
+
+
+
+ /// Apply compression to one compression block
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr,
+ const int iqWidth, const uint8_t thisExp, const uint16_t rbWriteMask)
+ {
+ /// Store exponents first
+ *outBlockAddr = thisExp;
+ /// Apply the exponent shift
+ /// First Store the two exponent values in one register
+ const auto compData = _mm512_srai_epi16(*dataIn, thisExp);
+ /// Pack compressed data network byte order
+ const auto compDataBytePacked = networkBytePack(compData);
+ /// Now have 1 register worth of bytes separated into 2 chunks (1 per lane)
+ /// Use two offset stores to join
+ const auto thisOutRegAddr1 = outBlockAddr + 1;
+ _mm_mask_storeu_epi8(thisOutRegAddr1, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
+ _mm_mask_storeu_epi8(thisOutRegAddr1 + iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
+ }
+
+ /// Apply compression to two compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ applyCompressionN_2RB(const __m512i* dataIn, uint8_t* outBlockAddr,
+ const int totNumBytesPerBlock, const int iqWidth, const uint8_t* theseExps, const uint16_t rbWriteMask)
+ {
+ /// Store exponents first
+ *outBlockAddr = theseExps[0];
+ *(outBlockAddr + totNumBytesPerBlock) = theseExps[4];
+ /// Apply the exponent shift
+ /// First Store the two exponent values in one register
+ __m512i thisExp = __m512i();
+ constexpr uint32_t k_firstExpMask = 0x0000FFFF;
+ thisExp = _mm512_mask_set1_epi16(thisExp, k_firstExpMask, theseExps[0]);
+ constexpr uint32_t k_secondExpMask = 0xFFFF0000;
+ thisExp = _mm512_mask_set1_epi16(thisExp, k_secondExpMask, theseExps[4]);
+ const auto compData = _mm512_srav_epi16(*dataIn, thisExp);
+ /// Pack compressed data network byte order
+ const auto compDataBytePacked = networkBytePack(compData);
+ /// Now have 1 register worth of bytes separated into 4 chunks (1 per lane)
+ /// Use four offset stores to join
+ const auto thisOutRegAddr1 = outBlockAddr + 1;
+ const auto thisOutRegAddr2 = outBlockAddr + totNumBytesPerBlock + 1;
+ _mm_mask_storeu_epi8(thisOutRegAddr1, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
+ _mm_mask_storeu_epi8(thisOutRegAddr1 + iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
+ _mm_mask_storeu_epi8(thisOutRegAddr2, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+ _mm_mask_storeu_epi8(thisOutRegAddr2 + iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 3));
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(8)
+ for (int n = 0; n < 8; ++n)
+ {
+ applyCompressionN_2RB<networkBytePack>(dataInAddr + n, dataOut->dataCompressed + n * 2 * totNumBytesPerBlock, totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents) + n * 8, rbWriteMask);
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+#pragma unroll(2)
+ for (int n = 0; n < 2; ++n)
+ {
+ applyCompressionN_2RB<networkBytePack>(dataInAddr + n, dataOut->dataCompressed + n * 2 * totNumBytesPerBlock, totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents) + n * 8, rbWriteMask);;
+ }
+ }
+
+ /// Derive and apply 9, 10, or 12bit compression to 1 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m512i* dataInAddr = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ applyCompressionN_1RB<networkBytePack>(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, rbWriteMask);
+ }
+
+ /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ inline void
+ compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerBlock, const uint16_t rbWriteMask)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compressN_16RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask);
+ break;
+
+ case 4:
+ compressN_4RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask);
+ break;
+
+ case 1:
+ compressN_1RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask);
+ break;
+ }
+ }
+
+
+
+ /// Apply 8b compression to 1 compression block.
+ inline void
+ applyCompression8_1RB(const __m256i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp)
+ {
+ /// Store exponent first
+ *outBlockAddr = thisExp;
+ /// Apply the exponent shift
+ const auto compData = _mm256_srai_epi16(*dataIn, thisExp);
+ /// Truncate to 8bit and store
+ constexpr uint16_t k_writeMask = 0xFFFF;
+ _mm_mask_storeu_epi8(outBlockAddr + 1, k_writeMask, _mm256_cvtepi16_epi8(compData));
+ }
+
+ /// Derive and apply 8b compression to 16 compression blocks
+ inline void
+ compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+ const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 4 compression blocks
+ inline void
+ compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+ const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]);
+ }
+ }
+
+ /// Derive and apply 8b compression to 1 compression block
+ inline void
+ compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ const __m256i* dataInAddr = reinterpret_cast<const __m256i*>(dataIn.dataExpanded);
+ applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent);
+ }
+
+ /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth.
+ inline void
+ compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compress8_16RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 4:
+ compress8_4RB(dataIn, dataOut, totShiftBits);
+ break;
+
+ case 1:
+ compress8_1RB(dataIn, dataOut, totShiftBits);
+ break;
+ }
+ }
+
+
+ /// Expand 1 compression block
+ template<BlockFloatCompander::UnpackFunction256 networkByteUnpack>
+ inline void
+ applyExpansionN_1RB(const uint8_t* expAddr, __m256i* dataOutAddr, const int maxExpShift)
+ {
+ const auto thisExpShift = maxExpShift - *expAddr;
+ /// Unpack network order packed data
+ const auto inDataUnpacked = networkByteUnpack(expAddr + 1);
+ /// Apply exponent scaling (by appropriate arithmetic shift right)
+ const auto expandedData = _mm256_srai_epi16(inDataUnpacked, thisExpShift);
+ /// Write expanded data to output
+ static constexpr uint8_t k_WriteMask = 0x0F;
+ _mm256_mask_storeu_epi64(dataOutAddr, k_WriteMask, expandedData);
+ }
+
+ /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::UnpackFunction256 networkByteUnpack>
+ void expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int totNumBytesPerBlock, const int maxExpShift)
+ {
+ __m256i* dataOutAddr = reinterpret_cast<__m256i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift);
+ }
+ break;
+
+ case 1:
+ applyExpansionN_1RB<networkByteUnpack>(dataIn.dataCompressed, dataOutAddr, maxExpShift);
+ break;
+ }
+ }
+
+
+ /// Apply expansion to 2 compression block
+ inline void
+ applyExpansion8_1RB(const uint8_t* expAddr, __m256i* dataOutAddr)
+ {
+ const __m128i* rawDataIn = reinterpret_cast<const __m128i*>(expAddr + 1);
+ const auto compData16 = _mm256_cvtepi8_epi16(*rawDataIn);
+ const auto expData = _mm256_slli_epi16(compData16, *expAddr);
+ static constexpr uint8_t k_WriteMask = 0x0F;
+ _mm256_mask_storeu_epi64(dataOutAddr, k_WriteMask, expData);
+ }
+
+ /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth.
+ void
+ expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut)
+ {
+ __m256i* dataOutAddr = reinterpret_cast<__m256i*>(dataOut->dataExpanded);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n);
+ }
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n);
+ }
+ break;
+
+ case 1:
+ applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr);
+ break;
+ }
+ }
+}
+
+
+/// Main kernel function for 8 antenna C-plane compression.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPCompressCtrlPlane8Avx512(const ExpandedData& dataIn, CompressedData* dataOut)
+{
+ /// Compensation for extra zeros in 32b leading zero count when computing exponent
+ const auto totShiftBits8 = _mm512_set1_epi32(25);
+ const auto totShiftBits9 = _mm512_set1_epi32(24);
+ const auto totShiftBits10 = _mm512_set1_epi32(23);
+ const auto totShiftBits12 = _mm512_set1_epi32(21);
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_8::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+
+ /// Compressed data write mask for each iqWidth option
+ constexpr uint16_t rbWriteMask9 = 0x01FF;
+ constexpr uint16_t rbWriteMask10 = 0x03FF;
+ constexpr uint16_t rbWriteMask12 = 0x0FFF;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_8::compressByAlloc8(dataIn, dataOut, totShiftBits8);
+ break;
+
+ case 9:
+ BFP_CPlane_8::compressByAllocN<BlockFloatCompander::networkBytePack9b>(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, rbWriteMask9);
+ break;
+
+ case 10:
+ BFP_CPlane_8::compressByAllocN<BlockFloatCompander::networkBytePack10b>(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, rbWriteMask10);
+ break;
+
+ case 12:
+ BFP_CPlane_8::compressByAllocN<BlockFloatCompander::networkBytePack12b>(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, rbWriteMask12);
+ break;
+ }
+}
+
+
+/// Main kernel function for 8 antenna C-plane expansion.
+/// Starts by determining iqWidth specific parameters and functions.
+void
+BlockFloatCompander::BFPExpandCtrlPlane8Avx512(const CompressedData& dataIn, ExpandedData* dataOut)
+{
+ constexpr int k_maxExpShift9 = 7;
+ constexpr int k_maxExpShift10 = 6;
+ constexpr int k_maxExpShift12 = 4;
+
+ /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1
+ const auto totNumBytesPerBlock = ((BFP_CPlane_8::k_numDataElements * dataIn.iqWidth) >> 3) + 1;
+
+ switch (dataIn.iqWidth)
+ {
+ case 8:
+ BFP_CPlane_8::expandByAlloc8(dataIn, dataOut);
+ break;
+
+ case 9:
+ BFP_CPlane_8::expandByAllocN<BlockFloatCompander::networkByteUnpack9b256>(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift9);
+ break;
+
+ case 10:
+ BFP_CPlane_8::expandByAllocN<BlockFloatCompander::networkByteUnpack10b256>(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift10);
+ break;
+
+ case 12:
+ BFP_CPlane_8::expandByAllocN<BlockFloatCompander::networkByteUnpack12b256>(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift12);
+ break;
+ }
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief xRAN BFP compression/decompression [C-code version, no AVX512 optimization]
+ *
+ * @file xran_bfp_ref.cpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#include "xran_compression.hpp"
+#include "xran_bfp_utils.hpp"
+#include <complex>
+#include <algorithm>
+#include <limits.h>
+
+static int16_t saturateAbs(int16_t inVal)
+{
+ int16_t result;
+ if (inVal == std::numeric_limits<int16_t>::min())
+ {
+ result = std::numeric_limits<int16_t>::max();
+ }
+ else
+ {
+ result = (int16_t)std::abs(inVal);
+ }
+ return result;
+}
+
+
+/// Reference compression
+void
+BlockFloatCompander::BFPCompressRef(const ExpandedData& dataIn, CompressedData* dataOut)
+{
+ int dataOutIdx = 0;
+ int16_t iqMask = (int16_t)((1 << dataIn.iqWidth) - 1);
+ int byteShiftUnits = dataIn.iqWidth - 8;
+
+ for (int rb = 0; rb < dataIn.numBlocks; ++rb)
+ {
+ /// Find max abs value for this RB
+ int16_t maxAbs = 0;
+ for (int re = 0; re < dataIn.numDataElements; ++re)
+ {
+ auto dataIdx = rb * dataIn.numDataElements + re;
+ auto dataAbs = saturateAbs(dataIn.dataExpanded[dataIdx]);
+ maxAbs = std::max(maxAbs, dataAbs);
+ }
+
+ /// Find exponent and insert into byte stream
+ auto thisExp = (uint8_t)(std::max(0,(16 - dataIn.iqWidth + 1 - __lzcnt16(maxAbs))));
+ dataOut->dataCompressed[dataOutIdx++] = thisExp;
+
+ /// ARS data by exponent and pack bytes in Network order
+ /// This uses a sliding buffer where one or more bytes are
+ /// extracted after the insertion of each compressed sample
+ static constexpr int k_byteMask = 0xFF;
+ int byteShiftVal = -8;
+ int byteBuffer = { 0 };
+ for (int re = 0; re < dataIn.numDataElements; ++re)
+ {
+ auto dataIdxIn = rb * dataIn.numDataElements + re;
+ auto thisRE = dataIn.dataExpanded[dataIdxIn] >> thisExp;
+ byteBuffer = (byteBuffer << dataIn.iqWidth) + (int)(thisRE & iqMask);
+
+ byteShiftVal += (8 + byteShiftUnits);
+ while (byteShiftVal >= 0)
+ {
+ auto thisByte = (uint8_t)((byteBuffer >> byteShiftVal) & k_byteMask);
+ dataOut->dataCompressed[dataOutIdx++] = thisByte;
+ byteShiftVal -= 8;
+ }
+ }
+ }
+ dataOut->iqWidth = dataIn.iqWidth;
+ dataOut->numBlocks = dataIn.numBlocks;
+ dataOut->numDataElements = dataIn.numDataElements;
+}
+
+
+/// Reference expansion
+void
+BlockFloatCompander::BFPExpandRef(const CompressedData& dataIn, ExpandedData* dataOut)
+{
+ uint32_t iqMask = (uint32_t)(UINT_MAX - ((1 << (32 - dataIn.iqWidth)) - 1));
+ uint32_t byteBuffer = { 0 };
+ int numBytesPerRB = ((dataIn.numDataElements * dataIn.iqWidth) >> 3) + 1;
+ int bitPointer = 0;
+ int dataIdxOut = 0;
+
+ for (int rb = 0; rb < dataIn.numBlocks; ++rb)
+ {
+ auto expIdx = rb * numBytesPerRB;
+ auto signExtShift = 32 - dataIn.iqWidth - dataIn.dataCompressed[expIdx];
+
+ for (int b = 0; b < numBytesPerRB - 1; ++b)
+ {
+ auto dataIdxIn = (expIdx + 1) + b;
+ auto thisByte = (uint16_t)dataIn.dataCompressed[dataIdxIn];
+ byteBuffer = (uint32_t)((byteBuffer << 8) + thisByte);
+ bitPointer += 8;
+ while (bitPointer >= dataIn.iqWidth)
+ {
+ /// byteBuffer currently has enough data in it to extract a sample
+ /// Shift left first to set sign bit at MSB, then shift right to
+ /// sign extend down to iqWidth. Finally recast to int16.
+ int32_t thisSample32 = (int32_t)((byteBuffer << (32 - bitPointer)) & iqMask);
+ int16_t thisSample = (int16_t)(thisSample32 >> signExtShift);
+ bitPointer -= dataIn.iqWidth;
+ dataOut->dataExpanded[dataIdxOut++] = thisSample;
+ }
+ }
+ }
+ dataOut->iqWidth = dataIn.iqWidth;
+ dataOut->numBlocks = dataIn.numBlocks;
+ dataOut->numDataElements = dataIn.numDataElements;
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (c) 2019 Intel.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*******************************************************************************/
+
+/**
+ * @brief xRAN BFP compression/decompression utilities functions
+ *
+ * @file xran_bfp_utils.hpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
+#pragma once
+#include <immintrin.h>
+
+namespace BlockFloatCompander
+{
+ /// Define function signatures for byte packing functions
+ typedef __m512i(*PackFunction)(const __m512i);
+ typedef __m512i(*UnpackFunction)(const uint8_t*);
+ typedef __m256i(*UnpackFunction256)(const uint8_t*);
+
+ /// Calculate exponent based on 16 max abs values using leading zero count.
+ inline __m512i
+ maskUpperWord(const __m512i inData)
+ {
+ const auto k_upperWordMask = _mm512_set_epi64(0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF,
+ 0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF,
+ 0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF,
+ 0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF);
+ return _mm512_and_epi64(inData, k_upperWordMask);
+ }
+
+ /// Calculate exponent based on 16 max abs values using leading zero count.
+ inline __m512i
+ expLzCnt(const __m512i maxAbs, const __m512i totShiftBits)
+ {
+ /// Compute exponent
+ const auto lzCount = _mm512_lzcnt_epi32(maxAbs);
+ return _mm512_subs_epu16(totShiftBits, lzCount);
+ }
+
+ inline int
+ horizontalMax1x32(const __m512i maxAbsReg)
+ {
+ /// Swap each IQ pair in each lane (via 32b rotation) and compute max of
+ /// each pair.
+ const auto maxRot16 = _mm512_rol_epi32(maxAbsReg, BlockFloatCompander::k_numBitsIQ);
+ const auto maxAbsIQ = _mm512_max_epi16(maxAbsReg, maxRot16);
+ /// Convert to 32b by removing repeated values in maxAbs
+ const auto maxAbs32 = maskUpperWord(maxAbsIQ);
+ /// Return reduced max
+ return _mm512_reduce_max_epi32(maxAbs32);
+ }
+
+ /// Pack compressed 9 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ inline __m512i
+ networkBytePack9b(const __m512i compData)
+ {
+ /// Logical shift left to align network order byte parts
+ const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000100020003, 0x0004000500060007,
+ 0x0000000100020003, 0x0004000500060007,
+ 0x0000000100020003, 0x0004000500060007,
+ 0x0000000100020003, 0x0004000500060007);
+ const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft);
+
+ /// First epi8 shuffle of even indexed samples
+ const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0C0D080904050001,
+ 0x0000000000000000, 0x0C0D080904050001,
+ 0x0000000000000000, 0x0C0D080904050001,
+ 0x0000000000000000, 0x0C0D080904050001);
+ constexpr uint64_t k_byteMask1 = 0x00FF00FF00FF00FF;
+ const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1);
+
+ /// Second epi8 shuffle of odd indexed samples
+ const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000000000E, 0x0F0A0B0607020300,
+ 0x000000000000000E, 0x0F0A0B0607020300,
+ 0x000000000000000E, 0x0F0A0B0607020300,
+ 0x000000000000000E, 0x0F0A0B0607020300);
+ constexpr uint64_t k_byteMask2 = 0x01FE01FE01FE01FE;
+ const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2);
+
+ /// Ternary blend of the two shuffled results
+ const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000000000FF, 0x01FC07F01FC07F00,
+ 0x00000000000000FF, 0x01FC07F01FC07F00,
+ 0x00000000000000FF, 0x01FC07F01FC07F00,
+ 0x00000000000000FF, 0x01FC07F01FC07F00);
+ return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8);
+ }
+
+
+ /// Pack compressed 10 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ inline __m512i
+ networkBytePack10b(const __m512i compData)
+ {
+ /// Logical shift left to align network order byte parts
+ const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006,
+ 0x0000000200040006, 0x0000000200040006,
+ 0x0000000200040006, 0x0000000200040006,
+ 0x0000000200040006, 0x0000000200040006);
+ const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft);
+
+ /// First epi8 shuffle of even indexed samples
+ const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x000000000000000C, 0x0D08090004050001,
+ 0x000000000000000C, 0x0D08090004050001,
+ 0x000000000000000C, 0x0D08090004050001,
+ 0x000000000000000C, 0x0D08090004050001);
+ constexpr uint64_t k_byteMask1 = 0x01EF01EF01EF01EF;
+ const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1);
+
+ /// Second epi8 shuffle of odd indexed samples
+ const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000E0F, 0x0A0B000607020300,
+ 0x0000000000000E0F, 0x0A0B000607020300,
+ 0x0000000000000E0F, 0x0A0B000607020300,
+ 0x0000000000000E0F, 0x0A0B000607020300);
+ constexpr uint64_t k_byteMask2 = 0x03DE03DE03DE03DE;
+ const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2);
+
+ /// Ternary blend of the two shuffled results
+ const __m512i k_ternLogSelect = _mm512_set_epi64(0x000000000000FF03, 0xF03F00FF03F03F00,
+ 0x000000000000FF03, 0xF03F00FF03F03F00,
+ 0x000000000000FF03, 0xF03F00FF03F03F00,
+ 0x000000000000FF03, 0xF03F00FF03F03F00);
+ return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8);
+ }
+
+
+ /// Pack compressed 12 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ inline __m512i
+ networkBytePack12b(const __m512i compData)
+ {
+ /// Logical shift left to align network order byte parts
+ const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000400000004, 0x0000000400000004,
+ 0x0000000400000004, 0x0000000400000004,
+ 0x0000000400000004, 0x0000000400000004,
+ 0x0000000400000004, 0x0000000400000004);
+ const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft);
+
+ /// First epi8 shuffle of even indexed samples
+ const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x00000000000C0D00, 0x0809000405000001,
+ 0x00000000000C0D00, 0x0809000405000001,
+ 0x00000000000C0D00, 0x0809000405000001,
+ 0x00000000000C0D00, 0x0809000405000001);
+ constexpr uint64_t k_byteMask1 = 0x06DB06DB06DB06DB;
+ const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1);
+
+ /// Second epi8 shuffle of odd indexed samples
+ const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000E0F000A, 0x0B00060700020300,
+ 0x000000000E0F000A, 0x0B00060700020300,
+ 0x000000000E0F000A, 0x0B00060700020300,
+ 0x000000000E0F000A, 0x0B00060700020300);
+ constexpr uint64_t k_byteMask2 = 0x0DB60DB60DB60DB6;
+ const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2);
+
+ /// Ternary blend of the two shuffled results
+ const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000FF0F00FF, 0x0F00FF0F00FF0F00,
+ 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00,
+ 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00,
+ 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00);
+ return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8);
+ }
+
+
+ /// Unpack compressed 9 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ inline __m512i
+ networkByteUnpack9b(const uint8_t* inData)
+ {
+ /// Align chunks of compressed bytes into lanes to allow for expansion
+ const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(inData);
+ const auto k_expPerm = _mm512_set_epi32(9, 8, 7, 6, 7, 6, 5, 4,
+ 5, 4, 3, 2, 3, 2, 1, 0);
+ const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn);
+
+ /// Byte shuffle to get all bits for each sample into 16b chunks
+ /// Due to previous permute to get chunks of bytes into each lane, there is
+ /// a different shuffle offset in each lane
+ const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A08090708, 0x0607050604050304,
+ 0x090A080907080607, 0x0506040503040203,
+ 0x0809070806070506, 0x0405030402030102,
+ 0x0708060705060405, 0x0304020301020001);
+ const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask);
+
+ /// Logical shift left to set sign bit
+ const __m512i k_slBits = _mm512_set_epi64(0x0007000600050004, 0x0003000200010000,
+ 0x0007000600050004, 0x0003000200010000,
+ 0x0007000600050004, 0x0003000200010000,
+ 0x0007000600050004, 0x0003000200010000);
+ const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits);
+
+ /// Mask to zero unwanted bits
+ const __m512i k_expMask = _mm512_set1_epi16(0xFF80);
+ return _mm512_and_epi64(inSetSign, k_expMask);
+ }
+
+
+ /// Unpack compressed 10 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ inline __m512i
+ networkByteUnpack10b(const uint8_t* inData)
+ {
+ /// Align chunks of compressed bytes into lanes to allow for expansion
+ const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(inData);
+ const auto k_expPerm = _mm512_set_epi32(10, 9, 8, 7, 8, 7, 6, 5,
+ 5, 4, 3, 2, 3, 2, 1, 0);
+ const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn);
+
+ /// Byte shuffle to get all bits for each sample into 16b chunks
+ /// Due to previous permute to get chunks of bytes into each lane, lanes
+ /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes
+ const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A08090708, 0x0506040503040203,
+ 0x0809070806070506, 0x0304020301020001,
+ 0x0A0B090A08090708, 0x0506040503040203,
+ 0x0809070806070506, 0x0304020301020001);
+ const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask);
+
+ /// Logical shift left to set sign bit
+ const __m512i k_slBits = _mm512_set_epi64(0x0006000400020000, 0x0006000400020000,
+ 0x0006000400020000, 0x0006000400020000,
+ 0x0006000400020000, 0x0006000400020000,
+ 0x0006000400020000, 0x0006000400020000);
+ const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits);
+
+ /// Mask to zero unwanted bits
+ const __m512i k_expMask = _mm512_set1_epi16(0xFFC0);
+ return _mm512_and_epi64(inSetSign, k_expMask);
+ }
+
+
+ /// Unpack compressed 12 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ inline __m512i
+ networkByteUnpack12b(const uint8_t* inData)
+ {
+ /// Align chunks of compressed bytes into lanes to allow for expansion
+ const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(inData);
+ const auto k_expPerm = _mm512_set_epi32(12, 11, 10, 9, 9, 8, 7, 6,
+ 6, 5, 4, 3, 3, 2, 1, 0);
+ const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn);
+
+ /// Byte shuffle to get all bits for each sample into 16b chunks
+ /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset
+ const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A07080607, 0x0405030401020001,
+ 0x0A0B090A07080607, 0x0405030401020001,
+ 0x0A0B090A07080607, 0x0405030401020001,
+ 0x0A0B090A07080607, 0x0405030401020001);
+ const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask);
+
+ /// Logical shift left to set sign bit
+ const __m512i k_slBits = _mm512_set_epi64(0x0004000000040000, 0x0004000000040000,
+ 0x0004000000040000, 0x0004000000040000,
+ 0x0004000000040000, 0x0004000000040000,
+ 0x0004000000040000, 0x0004000000040000);
+ const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits);
+
+ /// Mask to zero unwanted bits
+ const __m512i k_expMask = _mm512_set1_epi16(0xFFF0);
+ return _mm512_and_epi64(inSetSign, k_expMask);
+ }
+
+
+ /// Unpack compressed 9 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ /// This unpacking function is for 256b registers
+ inline __m256i
+ networkByteUnpack9b256(const uint8_t* inData)
+ {
+ /// Align chunks of compressed bytes into lanes to allow for expansion
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(inData);
+ const auto k_expPerm = _mm256_set_epi32(5, 4, 3, 2, 3, 2, 1, 0);
+ const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn);
+
+ /// Byte shuffle to get all bits for each sample into 16b chunks
+ /// Due to previous permute to get chunks of bytes into each lane, there is
+ /// a different shuffle offset in each lane
+ const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0809070806070506, 0x0405030402030102,
+ 0x0708060705060405, 0x0304020301020001);
+ const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask);
+
+ /// Logical shift left to set sign bit
+ const __m256i k_slBits = _mm256_set_epi64x(0x0007000600050004, 0x0003000200010000,
+ 0x0007000600050004, 0x0003000200010000);
+ const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits);
+
+ /// Mask to zero unwanted bits
+ const __m256i k_expMask = _mm256_set1_epi16(0xFF80);
+ return _mm256_and_si256(inSetSign, k_expMask);
+ }
+
+
+ /// Unpack compressed 10 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ /// This unpacking function is for 256b registers
+ inline __m256i
+ networkByteUnpack10b256(const uint8_t* inData)
+ {
+ /// Align chunks of compressed bytes into lanes to allow for expansion
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(inData);
+ const auto k_expPerm = _mm256_set_epi32(5, 4, 3, 2, 3, 2, 1, 0);
+ const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn);
+
+ /// Byte shuffle to get all bits for each sample into 16b chunks
+ /// Due to previous permute to get chunks of bytes into each lane, lanes
+ /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes
+ const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0A0B090A08090708, 0x0506040503040203,
+ 0x0809070806070506, 0x0304020301020001);
+ const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask);
+
+ /// Logical shift left to set sign bit
+ const __m256i k_slBits = _mm256_set_epi64x(0x0006000400020000, 0x0006000400020000,
+ 0x0006000400020000, 0x0006000400020000);
+ const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits);
+
+ /// Mask to zero unwanted bits
+ const __m256i k_expMask = _mm256_set1_epi16(0xFFC0);
+ return _mm256_and_si256(inSetSign, k_expMask);
+ }
+
+
+ /// Unpack compressed 12 bit data in network byte order
+ /// See https://soco.intel.com/docs/DOC-2665619
+ /// This unpacking function is for 256b registers
+ inline __m256i
+ networkByteUnpack12b256(const uint8_t* inData)
+ {
+ /// Align chunks of compressed bytes into lanes to allow for expansion
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(inData);
+ const auto k_expPerm = _mm256_set_epi32(6, 5, 4, 3, 3, 2, 1, 0);
+ const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn);
+
+ /// Byte shuffle to get all bits for each sample into 16b chunks
+ /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset
+ const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0A0B090A07080607, 0x0405030401020001,
+ 0x0A0B090A07080607, 0x0405030401020001);
+ const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask);
+
+ /// Logical shift left to set sign bit
+ const __m256i k_slBits = _mm256_set_epi64x(0x0004000000040000, 0x0004000000040000,
+ 0x0004000000040000, 0x0004000000040000);
+ const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits);
+
+ /// Mask to zero unwanted bits
+ const __m256i k_expMask = _mm256_set1_epi16(0xFFF0);
+ return _mm256_and_si256(inSetSign, k_expMask);
+ }
+}
#include <rte_mbuf.h>
#include "xran_mlog_lnx.h"
+static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */
+
#define MBUFS_CNT 16
extern long interval_us;
uint16_t rb,
uint16_t sect_id);
-long rx_counter = 0;
-long tx_counter = 0;
-long tx_bytes_counter = 0;
-long rx_bytes_counter = 0;
-long tx_bytes_per_sec = 0;
-long rx_bytes_per_sec = 0;
-
struct cb_elem_entry *xran_create_cb(XranSymCallbackFn cb_fn, void *cb_data)
{
static int symbol_total_bytes = 0;
int num_bytes = 0;
struct xran_device_ctx * p_x_ctx = xran_dev_get_ctx();
+ struct xran_common_counters *pCnt = &p_x_ctx->fh_counters;
uint8_t CC_ID = 0;
uint8_t Ant_ID = 0;
uint8_t iqWidth = 0;
void *pHandle = NULL;
- uint8_t num_eAxc = xran_get_num_eAxc(pHandle);
int ret = MBUF_FREE;
uint32_t mb_free = 0;
int32_t valid_res = 0;
sect_id);
if(valid_res != 0) {
- print_err("valid_res is wrong [%d] ant %u (%u : %u : %u : %u) seq %u num_bytes %d\n", valid_res, Ant_ID, frame_id, subframe_id, slot_id, symb_id, seq.seq_id, num_bytes);
+ print_dbg("valid_res is wrong [%d] ant %u (%u : %u : %u : %u) seq %u num_bytes %d\n", valid_res, Ant_ID, frame_id, subframe_id, slot_id, symb_id, seq.seq_id, num_bytes);
return MBUF_FREE;
}
symbol_total_bytes += num_bytes;
if (seq.e_bit == 1) {
- print_dbg("Completed receiving symbol %d, size=%d bytes\n",
+ print_dbg("SRS receiving symbol %d, size=%d bytes\n",
symb_id, symbol_total_bytes);
if (symbol_total_bytes) {
} else {
print_err("res != symbol_total_bytes\n");
}
+ pCnt->rx_srs_packets++;
}
symbol_total_bytes = 0;
}
} else {
print_err("res != symbol_total_bytes\n");
}
+ pCnt->rx_prach_packets[Ant_ID]++;
}
symbol_total_bytes = 0;
} else {
} else {
print_err("res != symbol_total_bytes\n");
}
+ pCnt->rx_pusch_packets[Ant_ID]++;
}
symbol_total_bytes = 0;
} else {
int32_t prep_bytes;
- int16_t nPktSize = sizeof(struct ether_hdr) + sizeof(struct xran_ecpri_hdr) +
+ int16_t nPktSize = sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr) +
sizeof(struct radio_app_common_hdr)+ sizeof(struct data_section_hdr) + n_bytes;
uint32_t off;
struct xran_up_pkt_gen_params xp = { 0 };
xp.app_params.filter_id = 0;
xp.app_params.frame_id = frame_id;
xp.app_params.sf_slot_sym.subframe_id = subframe_id;
- xp.app_params.sf_slot_sym.slot_id = slot_id;
+ xp.app_params.sf_slot_sym.slot_id = xran_slotid_convert(slot_id, 0);
xp.app_params.sf_slot_sym.symb_id = symbol_no;
/* convert to network byte order */
xp.sec_hdr.fields.start_prbu = (uint8_t)prb_start;
xp.sec_hdr.fields.sym_inc = 0;
xp.sec_hdr.fields.rb = 0;
+#ifdef FCN_ADAPT
+ xp.sec_hdr.udCompHdr = 0;
+ xp.sec_hdr.reserved = 0;
+#endif
/* compression */
xp.compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth;
uint32_t do_copy = 0;
int32_t n_bytes = ((prb_num == 0) ? MAX_N_FULLBAND_SC : prb_num) * N_SC_PER_PRB * sizeof(struct rb_map);
struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx();
+ struct xran_common_counters *pCnt = &p_x_ctx->fh_counters;
+
if (mb == NULL){
char * pChar = NULL;
MLogPrint(NULL);
errx(1, "incorrect mbuf size %d packets", 1);
}
- pChar = rte_pktmbuf_prepend(mb, sizeof(struct ether_hdr));
+ pChar = rte_pktmbuf_prepend(mb, sizeof(struct rte_ether_hdr));
if(pChar == NULL){
MLogPrint(NULL);
errx(1, "incorrect mbuf size %d packets", 1);
do_copy);
if(sent){
- tx_counter++;
- tx_bytes_counter += rte_pktmbuf_pkt_len(mb);
- p_x_ctx->send_upmbuf2ring(mb, ETHER_TYPE_ECPRI);
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(mb);
+ p_x_ctx->send_upmbuf2ring(mb, ETHER_TYPE_ECPRI, xran_map_ecpriPcid_to_vf(direction, CC_ID, RU_Port_ID));
} else {
}
struct xran_section_gen_info *sect_geninfo, uint8_t cc_id, uint8_t ru_port_id, uint8_t seq_id)
{
int ret = 0, nsection, i;
- uint8_t frame_id = params->hdr.frameId;
uint8_t subframe_id = params->hdr.subframeId;
uint8_t slot_id = params->hdr.slotId;
uint8_t dir = params->dir;
struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx();
+ struct xran_common_counters *pCnt = &p_x_ctx->fh_counters;
nsection = params->numSections;
/* add in the ethernet header */
- struct ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h));
- tx_counter++;
- tx_bytes_counter += rte_pktmbuf_pkt_len(mbuf);
- p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI);
+ struct rte_ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h));
+
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(mbuf);
+ p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, xran_map_ecpriRtcid_to_vf(dir, cc_id, ru_port_id));
for(i=0; i<nsection; i++)
xran_cp_add_section_info(pHandle, dir, cc_id, ru_port_id,
(slot_id + subframe_id*SLOTNUM_PER_SUBFRAME)%XRAN_MAX_SECTIONDB_CTX,
uint8_t startsym, uint8_t numsym, uint16_t prb_start, uint16_t prb_num,int16_t iq_buffer_offset, int16_t iq_buffer_len,
uint16_t beam_id, uint8_t cc_id, uint8_t ru_port_id, uint8_t comp_method, uint8_t iqWidth, uint8_t seq_id, uint8_t symInc)
{
- int ret = 0, nsection, i, loc_sym;
+ int ret = 0, nsection, loc_sym;
params->dir = dir;
uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id,
uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint8_t seq_id)
{
- int i, nsection, ret;
+ int nsection, ret;
struct xran_prach_cp_config *pPrachCPConfig = &(pxran_lib_ctx->PrachCPConfig);
uint16_t timeOffset;
uint16_t nNumerology = pxran_lib_ctx->fh_cfg.frame_conf.nNumerology;
struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx();
struct xran_device_ctx *const pxran_lib_ctx = xran_dev_get_ctx();
int16_t retPoll = 0;
+ int32_t i;
uint64_t t1, t2;
rte_timer_manage();
- /* UP first */
- if (process_ring(ctx->rx_ring[ETHDI_UP_VF]))
- return 0;
- /* CP next */
- if (process_ring(ctx->rx_ring[ETHDI_CP_VF]))
- return 0;
-
if (pxran_lib_ctx->bbdev_dec) {
t1 = MLogTick();
retPoll = pxran_lib_ctx->bbdev_dec();
}
}
+ /* UP first */
+
+ for (i = 0; i < ctx->io_cfg.num_vfs && i < (XRAN_VF_MAX - 1); i = i+2){
+ if (process_ring(ctx->rx_ring[i]))
+ return 0;
+
+ /* CP next */
+ if(ctx->io_cfg.id == O_RU) /* process CP only on O-RU */
+ if (process_ring(ctx->rx_ring[i+1]))
+ return 0;
+ }
+
if (XRAN_STOPPED == xran_if_current_state)
return -1;
int ring_processing_thread(void *args)
{
struct sched_param sched_param;
+ struct xran_device_ctx *const p_xran_dev_ctx = xran_dev_get_ctx();
int res = 0;
+ memset(&sched_param, 0, sizeof(struct sched_param));
+
printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid());
sched_param.sched_priority = XRAN_THREAD_DEFAULT_PRIO;
if ((res = pthread_setschedparam(pthread_self(), SCHED_FIFO, &sched_param))){
printf("priority is not changed: coreId = %d, result1 = %d\n",rte_lcore_id(), res);
}
- for (;;)
+ for (;;){
if(ring_processing_func() != 0)
break;
+ /* work around for some kernel */
+ if(p_xran_dev_ctx->fh_init.io_cfg.io_sleep)
+ nanosleep(&sleeptime,NULL);
+ }
+
puts("Pkt processing thread finished.");
return 0;
}
};
/* Callback function to send mbuf to the ring */
-typedef int (*xran_ethdi_mbuf_send_fn)(struct rte_mbuf *mb, uint16_t ethertype);
+typedef int (*xran_ethdi_mbuf_send_fn)(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id);
/*
* manage one cell's all Ethernet frames for one DL or UL LTE subframe
xran_ethdi_mbuf_send_fn send_cpmbuf2ring; /**< callback to send mbufs of C-Plane packets to the ring */
xran_ethdi_mbuf_send_fn send_upmbuf2ring; /**< callback to send mbufs of U-Plane packets to the ring */
+ uint32_t pkt_proc_core_id; /**< core used for processing DPDK timer cb */
};
-extern long rx_counter;
-extern long tx_counter;
-extern long tx_bytes_counter;
-extern long rx_bytes_counter;
-extern long tx_bytes_per_sec;
-extern long rx_bytes_per_sec;
-
-
extern const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_fdd[XRAN_PRACH_CONFIG_TABLE_SIZE];
extern const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_tdd[XRAN_PRACH_CONFIG_TABLE_SIZE];
extern const xRANPrachConfigTableStruct gxranPrachDataTable_mmw[XRAN_PRACH_CONFIG_TABLE_SIZE];
int32_t ring_processing_func(void);
int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx);
void xran_updateSfnSecStart(void);
-
+uint32_t xran_slotid_convert(uint16_t slot_id, uint16_t dir);
struct cb_elem_entry *xran_create_cb(XranSymCallbackFn cb_fn, void *cb_data);
int xran_destroy_cb(struct cb_elem_entry * cb_elm);
+uint16_t xran_map_ecpriRtcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id);
+uint16_t xran_map_ecpriPcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id);
+
#ifdef __cplusplus
}
#endif
*
*******************************************************************************/
+/**
+ * @brief xRAN BFP compression/decompression U-plane implementation and interface functions
+ *
+ * @file xran_compression.cpp
+ * @ingroup group_source_xran
+ * @author Intel Corporation
+ **/
+
#include "xran_compression.hpp"
+#include "xran_bfp_utils.hpp"
#include "xran_compression.h"
#include <complex>
#include <algorithm>
#include <limits.h>
#include <cstring>
-static int16_t saturateAbs(int16_t inVal)
+namespace BFP_UPlane
{
- int16_t result;
- if (inVal == std::numeric_limits<short>::min())
- {
- result = std::numeric_limits<short>::max();
- }
- else
+ /// Namespace constants
+ const int k_numREReal = 24; /// 12 IQ pairs
+
+ /// Perform horizontal max of 16 bit values across each lane
+ __m512i
+ horizontalMax4x16(const __m512i maxAbsIn)
{
- result = (int16_t)std::abs(inVal);
- }
- return result;
-}
+ /// Swap 64b in each lane and compute max
+ const auto k_perm64b = _mm512_set_epi64(6, 7, 4, 5, 2, 3, 0, 1);
+ auto maxAbsPerm = _mm512_permutexvar_epi64(k_perm64b, maxAbsIn);
+ auto maxAbsHorz = _mm512_max_epi16(maxAbsIn, maxAbsPerm);
+ /// Swap each pair of 32b in each lane and compute max
+ const auto k_perm32b = _mm512_set_epi32(14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1);
+ maxAbsPerm = _mm512_permutexvar_epi32(k_perm32b, maxAbsHorz);
+ maxAbsHorz = _mm512_max_epi16(maxAbsHorz, maxAbsPerm);
-/// Compute exponent value for a set of RB from the maximum absolute value
-void
-computeExponent(const BlockFloatCompander::ExpandedData& dataIn, int8_t* expStore)
-{
- __m512i maxAbs = __m512i();
+ /// Swap each IQ pair in each lane (via 32b rotation) and compute max
+ maxAbsPerm = _mm512_rol_epi32(maxAbsHorz, BlockFloatCompander::k_numBitsIQ);
+ return _mm512_max_epi16(maxAbsHorz, maxAbsPerm);
+ }
- /// Load data and find max(abs(RB))
- const __m512i* rawData = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
- constexpr int k_numRBPerLoop = 4;
- constexpr int k_numInputLoopIts = BlockFloatCompander::k_numRB / k_numRBPerLoop;
-#pragma unroll(k_numInputLoopIts)
- for (int n = 0; n < k_numInputLoopIts; ++n)
+ /// Perform U-plane input data re-ordering and vertical max abs of 16b values
+ /// Works on 4 RB at a time
+ __m512i
+ maxAbsVertical4RB(const __m512i inA, const __m512i inB, const __m512i inC)
{
/// Re-order the next 4RB in input data into 3 registers
/// Input SIMD vectors are:
/// [A A A A B B B B C C C C D D D D]
constexpr uint8_t k_msk1 = 0b11111100; // Copy first lane of src
constexpr int k_shuff1 = 0x41;
- const auto z_w1 = _mm512_mask_shuffle_i64x2(rawData[3 * n + 0], k_msk1, rawData[3 * n + 1], rawData[3 * n + 2], k_shuff1);
+ const auto z_w1 = _mm512_mask_shuffle_i64x2(inA, k_msk1, inB, inC, k_shuff1);
constexpr uint8_t k_msk2 = 0b11000011; // Copy middle two lanes of src
constexpr int k_shuff2 = 0xB1;
- const auto z_w2 = _mm512_mask_shuffle_i64x2(rawData[3 * n + 1], k_msk2, rawData[3 * n + 0], rawData[3 * n + 2], k_shuff2);
+ const auto z_w2 = _mm512_mask_shuffle_i64x2(inB, k_msk2, inA, inC, k_shuff2);
constexpr uint8_t k_msk3 = 0b00111111; // Copy last lane of src
constexpr int k_shuff3 = 0xBE;
- const auto z_w3 = _mm512_mask_shuffle_i64x2(rawData[3 * n + 2], k_msk3, rawData[3 * n + 0], rawData[3 * n + 1], k_shuff3);
+ const auto z_w3 = _mm512_mask_shuffle_i64x2(inC, k_msk3, inA, inB, k_shuff3);
/// Perform max abs on these 3 registers
const auto abs16_1 = _mm512_abs_epi16(z_w1);
const auto abs16_2 = _mm512_abs_epi16(z_w2);
const auto abs16_3 = _mm512_abs_epi16(z_w3);
- const auto maxAbs_12 = _mm512_max_epi16(abs16_1, abs16_2);
- const auto maxAbs_123 = _mm512_max_epi16(maxAbs_12, abs16_3);
-
- /// Perform horizontal max over each lane
- /// Swap 64b in each lane and compute max
- const auto k_perm64b = _mm512_set_epi64(6, 7, 4, 5, 2, 3, 0, 1);
- auto maxAbsPerm = _mm512_permutexvar_epi64(k_perm64b, maxAbs_123);
- auto maxAbsHorz = _mm512_max_epi16(maxAbs_123, maxAbsPerm);
-
- /// Swap each pair of 32b in each lane and compute max
- const auto k_perm32b = _mm512_set_epi32(14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1);
- maxAbsPerm = _mm512_permutexvar_epi32(k_perm32b, maxAbsHorz);
- maxAbsHorz = _mm512_max_epi16(maxAbsHorz, maxAbsPerm);
-
- /// Swap each IQ pair in each lane (via 32b rotation) and compute max
- maxAbsPerm = _mm512_rol_epi32(maxAbsHorz, BlockFloatCompander::k_numBitsIQ);
- maxAbsHorz = _mm512_max_epi16(maxAbsHorz, maxAbsPerm);
-
- /// Insert values into maxAbs
- /// Use sliding mask to insert wanted values into maxAbs
- /// Pairs of values will be inserted and corrected outside of loop
- const auto k_select4RB = _mm512_set_epi32(28, 24, 20, 16, 28, 24, 20, 16,
- 28, 24, 20, 16, 28, 24, 20, 16);
- constexpr uint16_t k_expMsk[k_numInputLoopIts] = { 0x000F, 0x00F0, 0x0F00, 0xF000 };
- maxAbs = _mm512_mask_permutex2var_epi32(maxAbs, k_expMsk[n], k_select4RB, maxAbsHorz);
+ return _mm512_max_epi16(_mm512_max_epi16(abs16_1, abs16_2), abs16_3);
}
- /// Convert to 32b by removing repeated values in maxAbs
- const auto k_upperWordMask = _mm512_set_epi64(0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF,
- 0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF,
- 0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF,
- 0x0000FFFF0000FFFF, 0x0000FFFF0000FFFF);
- maxAbs = _mm512_and_epi64(maxAbs, k_upperWordMask);
-
- /// Compute and store exponent
- const auto totShiftBits = _mm512_set1_epi32(32 - dataIn.iqWidth + 1);
- const auto lzCount = _mm512_lzcnt_epi32(maxAbs);
- const auto exponent = _mm512_sub_epi32(totShiftBits, lzCount);
- constexpr uint16_t k_expWriteMask = 0xFFFF;
- _mm512_mask_cvtepi32_storeu_epi8(expStore, k_expWriteMask, exponent);
-}
-
-
-/// Pack compressed 9 bit data in network byte order
-/// See https://soco.intel.com/docs/DOC-2665619
-__m512i
-networkBytePack9b(const __m512i compData)
-{
- /// Logical shift left to align network order byte parts
- const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000100020003, 0x0004000500060007,
- 0x0000000100020003, 0x0004000500060007,
- 0x0000000100020003, 0x0004000500060007,
- 0x0000000100020003, 0x0004000500060007);
- auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft);
-
- /// First epi8 shuffle of even indexed samples
- const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0C0D080904050001,
- 0x0000000000000000, 0x0C0D080904050001,
- 0x0000000000000000, 0x0C0D080904050001,
- 0x0000000000000000, 0x0C0D080904050001);
- constexpr uint64_t k_byteMask1 = 0x000000FF00FF00FF;
- auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1);
-
- /// Second epi8 shuffle of odd indexed samples
- const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000000000E, 0x0F0A0B0607020300,
- 0x000000000000000E, 0x0F0A0B0607020300,
- 0x000000000000000E, 0x0F0A0B0607020300,
- 0x000000000000000E, 0x0F0A0B0607020300);
- constexpr uint64_t k_byteMask2 = 0x000001FE01FE01FE;
- auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2);
-
- /// Ternary blend of the two shuffled results
- const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000000000FF, 0x01FC07F01FC07F00,
- 0x00000000000000FF, 0x01FC07F01FC07F00,
- 0x00000000000000FF, 0x01FC07F01FC07F00,
- 0x00000000000000FF, 0x01FC07F01FC07F00);
- return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8);
-}
-
-
-/// Pack compressed 10 bit data in network byte order
-/// See https://soco.intel.com/docs/DOC-2665619
-__m512i
-networkBytePack10b(const __m512i compData)
-{
- /// Logical shift left to align network order byte parts
- const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006,
- 0x0000000200040006, 0x0000000200040006,
- 0x0000000200040006, 0x0000000200040006,
- 0x0000000200040006, 0x0000000200040006);
- auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft);
-
- /// First epi8 shuffle of even indexed samples
- const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x000000000000000C, 0x0D08090004050001,
- 0x000000000000000C, 0x0D08090004050001,
- 0x000000000000000C, 0x0D08090004050001,
- 0x000000000000000C, 0x0D08090004050001);
- constexpr uint64_t k_byteMask1 = 0x000001EF01EF01EF;
- auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1);
-
- /// Second epi8 shuffle of odd indexed samples
- const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000E0F, 0x0A0B000607020300,
- 0x0000000000000E0F, 0x0A0B000607020300,
- 0x0000000000000E0F, 0x0A0B000607020300,
- 0x0000000000000E0F, 0x0A0B000607020300);
- constexpr uint64_t k_byteMask2 = 0x000003DE03DE03DE;
- auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2);
-
- /// Ternary blend of the two shuffled results
- const __m512i k_ternLogSelect = _mm512_set_epi64(0x000000000000FF03, 0xF03F00FF03F03F00,
- 0x000000000000FF03, 0xF03F00FF03F03F00,
- 0x000000000000FF03, 0xF03F00FF03F03F00,
- 0x000000000000FF03, 0xF03F00FF03F03F00);
- return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8);
-}
-
-
-/// Pack compressed 12 bit data in network byte order
-/// See https://soco.intel.com/docs/DOC-2665619
-__m512i
-networkBytePack12b(const __m512i compData)
-{
- /// Logical shift left to align network order byte parts
- const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000400000004, 0x0000000400000004,
- 0x0000000400000004, 0x0000000400000004,
- 0x0000000400000004, 0x0000000400000004,
- 0x0000000400000004, 0x0000000400000004);
- auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft);
-
- /// First epi8 shuffle of even indexed samples
- const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x00000000000C0D00, 0x0809000405000001,
- 0x00000000000C0D00, 0x0809000405000001,
- 0x00000000000C0D00, 0x0809000405000001,
- 0x00000000000C0D00, 0x0809000405000001);
- constexpr uint64_t k_byteMask1 = 0x000006DB06DB06DB;
- auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1);
-
- /// Second epi8 shuffle of odd indexed samples
- const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000E0F000A, 0x0B00060700020300,
- 0x000000000E0F000A, 0x0B00060700020300,
- 0x000000000E0F000A, 0x0B00060700020300,
- 0x000000000E0F000A, 0x0B00060700020300);
- constexpr uint64_t k_byteMask2 = 0x00000DB60DB60DB6;
- auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2);
-
- /// Ternary blend of the two shuffled results
- const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000FF0F00FF, 0x0F00FF0F00FF0F00,
- 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00,
- 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00,
- 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00);
- return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8);
-}
-
-
-/// Unpack compressed 9 bit data in network byte order
-/// See https://soco.intel.com/docs/DOC-2665619
-__m512i
-networkByteUnpack9b(const uint8_t* inData)
-{
- /// Align chunks of compressed bytes into lanes to allow for expansion
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(inData);
- const auto k_expPerm = _mm512_set_epi32(15, 14, 13, 12, 7, 6, 5, 4,
- 5, 4, 3, 2, 3, 2, 1, 0);
- auto expData = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn);
-
- /// Byte shuffle to get all bits for each sample into 16b chunks
- /// Due to previous permute to get chunks of bytes into each lane, there is
- /// a different shuffle offset in each lane
- const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0F0E0D0C0B0A0908, 0x0706050403020100,
- 0x090A080907080607, 0x0506040503040203,
- 0x0809070806070506, 0x0405030402030102,
- 0x0708060705060405, 0x0304020301020001);
- expData = _mm512_shuffle_epi8(expData, k_byteShuffleMask);
-
- /// Logical shift left to set sign bit
- const __m512i k_slBits = _mm512_set_epi64(0x0007000600050004, 0x0003000200010000,
- 0x0007000600050004, 0x0003000200010000,
- 0x0007000600050004, 0x0003000200010000,
- 0x0007000600050004, 0x0003000200010000);
- expData = _mm512_sllv_epi16(expData, k_slBits);
-
- /// Mask to zero unwanted bits
- const __m512i k_expMask = _mm512_set1_epi16(0xFF80);
- return _mm512_and_epi64(expData, k_expMask);
-}
+ /// Selects first 32 bit value in each src lane and packs into laneNum of dest
+ __m512i
+ slidePermute(const __m512i src, const __m512i dest, const int laneNum)
+ {
+ const auto k_selectVals = _mm512_set_epi32(28, 24, 20, 16, 28, 24, 20, 16,
+ 28, 24, 20, 16, 28, 24, 20, 16);
+ constexpr uint16_t k_laneMsk[4] = { 0x000F, 0x00F0, 0x0F00, 0xF000 };
+ return _mm512_mask_permutex2var_epi32(dest, k_laneMsk[laneNum], k_selectVals, src);
+ }
-/// Unpack compressed 10 bit data in network byte order
-/// See https://soco.intel.com/docs/DOC-2665619
-__m512i
-networkByteUnpack10b(const uint8_t* inData)
-{
- /// Align chunks of compressed bytes into lanes to allow for expansion
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(inData);
- const auto k_expPerm = _mm512_set_epi32(15, 14, 13, 12, 8, 7, 6, 5,
- 5, 4, 3, 2, 3, 2, 1, 0);
- auto expData = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn);
-
- /// Byte shuffle to get all bits for each sample into 16b chunks
- /// Due to previous permute to get chunks of bytes into each lane, lanes
- /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes
- const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0809070806070506, 0x0304020301020001,
- 0x0809070806070506, 0x0304020301020001,
- 0x0A0B090A08090708, 0x0506040503040203,
- 0x0809070806070506, 0x0304020301020001);
- expData = _mm512_shuffle_epi8(expData, k_byteShuffleMask);
-
- /// Logical shift left to set sign bit
- const __m512i k_slBits = _mm512_set_epi64(0x0006000400020000, 0x0006000400020000,
- 0x0006000400020000, 0x0006000400020000,
- 0x0006000400020000, 0x0006000400020000,
- 0x0006000400020000, 0x0006000400020000);
- expData = _mm512_sllv_epi16(expData, k_slBits);
-
- /// Mask to zero unwanted bits
- const __m512i k_expMask = _mm512_set1_epi16(0xFFC0);
- return _mm512_and_epi64(expData, k_expMask);
-}
+ /// Compute exponent value for a set of 16 RB from the maximum absolute value.
+ /// Max Abs operates in a loop, executing 4 RB per iteration. The results are
+ /// packed into the final output register.
+ __m512i
+ computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ __m512i maxAbs = __m512i();
+ const __m512i* rawData = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ /// Max Abs loop operates on 4RB at a time
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ /// Re-order and vertical max abs
+ auto maxAbsVert = maxAbsVertical4RB(rawData[3 * n + 0], rawData[3 * n + 1], rawData[3 * n + 2]);
+ /// Horizontal max abs
+ auto maxAbsHorz = horizontalMax4x16(maxAbsVert);
+ /// Pack these 4 values into maxAbs
+ maxAbs = slidePermute(maxAbsHorz, maxAbs, n);
+ }
+ /// Calculate exponent
+ const auto maxAbs32 = BlockFloatCompander::maskUpperWord(maxAbs);
+ return BlockFloatCompander::expLzCnt(maxAbs32, totShiftBits);
+ }
-/// Unpack compressed 12 bit data in network byte order
-/// See https://soco.intel.com/docs/DOC-2665619
-__m512i
-networkByteUnpack12b(const uint8_t* inData)
-{
- /// Align chunks of compressed bytes into lanes to allow for expansion
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(inData);
- const auto k_expPerm = _mm512_set_epi32(15, 14, 13, 12, 9, 8, 7, 6,
- 6, 5, 4, 3, 3, 2, 1, 0);
- auto expData = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn);
-
- /// Byte shuffle to get all bits for each sample into 16b chunks
- /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset
- const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A07080607, 0x0405030401020001,
- 0x0A0B090A07080607, 0x0405030401020001,
- 0x0A0B090A07080607, 0x0405030401020001,
- 0x0A0B090A07080607, 0x0405030401020001);
- expData = _mm512_shuffle_epi8(expData, k_byteShuffleMask);
-
- /// Logical shift left to set sign bit
- const __m512i k_slBits = _mm512_set_epi64(0x0004000000040000, 0x0004000000040000,
- 0x0004000000040000, 0x0004000000040000,
- 0x0004000000040000, 0x0004000000040000,
- 0x0004000000040000, 0x0004000000040000);
- expData = _mm512_sllv_epi16(expData, k_slBits);
-
- /// Mask to zero unwanted bits
- const __m512i k_expMask = _mm512_set1_epi16(0xFFF0);
- return _mm512_and_epi64(expData, k_expMask);
-}
+ /// Compute exponent value for a set of 4 RB from the maximum absolute value.
+ /// Note that we do not need to perform any packing of result as we are only
+ /// computing 4 RB. The appropriate offset is taken later when extracting the
+ /// exponent.
+ __m512i
+ computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
+ {
+ const __m512i* rawData = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ /// Re-order and vertical max abs
+ const auto maxAbsVert = maxAbsVertical4RB(rawData[0], rawData[1], rawData[2]);
+ /// Horizontal max abs
+ const auto maxAbsHorz = horizontalMax4x16(maxAbsVert);
+ /// Calculate exponent
+ const auto maxAbs = BlockFloatCompander::maskUpperWord(maxAbsHorz);
+ return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits);
+ }
-/// 8 bit compression
-void
-BlockFloatCompander::BlockFloatCompress_8b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut)
-{
- /// Compute exponent and store for later use
- int8_t storedExp[BlockFloatCompander::k_numRB] = {};
- computeExponent(dataIn, storedExp);
- /// Shift 1RB by corresponding exponent and write exponent and data to output
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// Compute exponent value for 1 RB from the maximum absolute value.
+ /// This works with horizontal max abs only, and needs to include a
+ /// step to select the final exponent from the 4 lanes.
+ uint8_t
+ computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits)
{
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(dataIn.dataExpanded + n * BlockFloatCompander::k_numREReal);
- auto compData = _mm512_srai_epi16(*rawDataIn, storedExp[n]);
- auto thisRBExpAddr = n * (BlockFloatCompander::k_numREReal + 1);
- /// Store exponent first
- dataOut->dataCompressed[thisRBExpAddr] = storedExp[n];
- /// Store compressed RB
- constexpr uint32_t k_rbMask = 0x00FFFFFF; // Write mask for 1RB (24 values)
- _mm256_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_rbMask, _mm512_cvtepi16_epi8(compData));
+ const __m512i* rawData = reinterpret_cast<const __m512i*>(dataIn.dataExpanded);
+ /// Abs
+ const auto rawDataAbs = _mm512_abs_epi16(rawData[0]);
+ /// No need to do a full horizontal max operation here, just do a max IQ step,
+ /// compute the exponents and then use a reduce max over all exponent values. This
+ /// is the fastest way to handle a single RB.
+ const auto rawAbsIQSwap = _mm512_rol_epi32(rawDataAbs, BlockFloatCompander::k_numBitsIQ);
+ const auto maxAbsIQ = _mm512_max_epi16(rawDataAbs, rawAbsIQSwap);
+ /// Calculate exponent
+ const auto maxAbsIQ32 = BlockFloatCompander::maskUpperWord(maxAbsIQ);
+ const auto exps = BlockFloatCompander::expLzCnt(maxAbsIQ32, totShiftBits);
+ /// At this point we have exponent values for the maximum of each IQ pair.
+ /// Run a reduce max step to compute the maximum exponent value in the first
+ /// three lanes - this will give the desired exponent for this RB.
+ constexpr uint16_t k_expMsk = 0x0FFF;
+ return (uint8_t)_mm512_mask_reduce_max_epi32(k_expMsk, exps);
}
-}
-/// 9 bit compression
-void
-BlockFloatCompander::BlockFloatCompress_9b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut)
-{
- /// Compute exponent and store for later use
- int8_t storedExp[BlockFloatCompander::k_numRB] = {};
- computeExponent(dataIn, storedExp);
-
- /// Shift 1RB by corresponding exponent and write exponent and data to output
- /// Output data is packed exponent first followed by corresponding compressed RB
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// Apply compression to 1 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ void
+ applyCompressionN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr, const uint16_t rbWriteMask)
{
- /// Apply exponent shift
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(dataIn.dataExpanded + n * BlockFloatCompander::k_numREReal);
- auto compData = _mm512_srai_epi16(*rawDataIn, storedExp[n]);
-
+ /// Get AVX512 pointer aligned to desired RB
+ const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(dataIn.dataExpanded + numREOffset);
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp);
/// Pack compressed data network byte order
- auto compDataBytePacked = networkBytePack9b(compData);
-
+ const auto compDataBytePacked = networkBytePack(compData);
/// Store exponent first
- constexpr int k_totNumBytesPerRB = 28;
- auto thisRBExpAddr = n * k_totNumBytesPerRB;
- dataOut->dataCompressed[thisRBExpAddr] = storedExp[n];
-
+ dataOut->dataCompressed[thisRBExpAddr] = thisExp;
/// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane)
/// Use three offset stores to join
- constexpr uint16_t k_RbWriteMask = 0x01FF;
- constexpr int k_numDataBytesPerLane = 9;
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + k_numDataBytesPerLane, k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * k_numDataBytesPerLane), k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+ _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
+ _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + dataIn.iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
+ _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * dataIn.iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
}
-}
-/// 10 bit compression
-void
-BlockFloatCompander::BlockFloatCompress_10b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut)
-{
- /// Compute exponent and store for later use
- int8_t storedExp[BlockFloatCompander::k_numRB] = {};
- computeExponent(dataIn, storedExp);
-
- /// Shift 1RB by corresponding exponent and write exponent and data to output
- /// Output data is packed exponent first followed by corresponding compressed RB
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// Apply 9, 10, or 12bit compression to 16 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ void
+ compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask)
{
- /// Apply exponent shift
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(dataIn.dataExpanded + n * BlockFloatCompander::k_numREReal);
- auto compData = _mm512_srai_epi16(*rawDataIn, storedExp[n]);
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * totNumBytesPerRB, rbWriteMask);
+ }
+ }
- /// Pack compressed data network byte order
- auto compDataBytePacked = networkBytePack10b(compData);
- /// Store exponent first
- constexpr int k_totNumBytesPerRB = 31;
- auto thisRBExpAddr = n * k_totNumBytesPerRB;
- dataOut->dataCompressed[thisRBExpAddr] = storedExp[n];
+ /// Apply 9, 10, or 12bit compression to 4 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ void
+ compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask)
+ {
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompressionN_1RB<networkBytePack>(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * totNumBytesPerRB, rbWriteMask);
+ }
+ }
- /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane)
- /// Use three offset stores to join
- constexpr uint16_t k_RbWriteMask = 0x03FF;
- constexpr int k_numDataBytesPerLane = 10;
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + k_numDataBytesPerLane, k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * k_numDataBytesPerLane), k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+
+ /// Apply 9, 10, or 12bit compression to 1 RB
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ void
+ compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ applyCompressionN_1RB<networkBytePack>(dataIn, dataOut, 0, thisExponent, 0, rbWriteMask);
}
-}
-/// 12 bit compression
-void
-BlockFloatCompander::BlockFloatCompress_12b_AVX512(const ExpandedData& dataIn, CompressedData* dataOut)
-{
- /// Compute exponent and store for later use
- int8_t storedExp[BlockFloatCompander::k_numRB] = {};
- computeExponent(dataIn, storedExp);
-
- /// Shift 1RB by corresponding exponent and write exponent and data to output
- /// Output data is packed exponent first followed by corresponding compressed RB
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::PackFunction networkBytePack>
+ void
+ compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask)
{
- /// Apply exponent shift
- const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(dataIn.dataExpanded + n * BlockFloatCompander::k_numREReal);
- auto compData = _mm512_srai_epi16(*rawDataIn, storedExp[n]);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compressN_16RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask);
+ break;
- /// Pack compressed data network byte order
- auto compDataBytePacked = networkBytePack12b(compData);
+ case 4:
+ compressN_4RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask);
+ break;
- /// Store exponent first
- constexpr int k_totNumBytesPerRB = 37;
- auto thisRBExpAddr = n * k_totNumBytesPerRB;
- dataOut->dataCompressed[thisRBExpAddr] = storedExp[n];
+ case 1:
+ compressN_1RB<networkBytePack>(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask);
+ break;
+ }
+ }
+
+ /// Apply compression to 1 RB
+ void
+ applyCompression8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut,
+ const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr)
+ {
+ /// Get AVX512 pointer aligned to desired RB
+ const __m512i* rawDataIn = reinterpret_cast<const __m512i*>(dataIn.dataExpanded + numREOffset);
+ /// Apply the exponent shift
+ const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp);
+ /// Store exponent first
+ dataOut->dataCompressed[thisRBExpAddr] = thisExp;
/// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane)
/// Use three offset stores to join
- constexpr uint16_t k_RbWriteMask = 0x0FFF;
- constexpr int k_numDataBytesPerLane = 12;
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0));
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + k_numDataBytesPerLane, k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1));
- _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * k_numDataBytesPerLane), k_RbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2));
+ constexpr uint32_t k_rbMask = 0x00FFFFFF; // Write mask for 1RB (24 values)
+ _mm256_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_rbMask, _mm512_cvtepi16_epi8(compData));
}
-}
-/// 8 bit expansion
-void
-BlockFloatCompander::BlockFloatExpand_8b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut)
-{
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// 8bit RB compression loop for 16 RB
+ void
+ compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- /// Expand 1RB of data
- auto expAddr = n * (BlockFloatCompander::k_numREReal + 1);
- const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(dataIn.dataCompressed + expAddr + 1);
- const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn);
- const auto expData = _mm512_slli_epi16(compData16, *(dataIn.dataCompressed + expAddr));
- /// Write expanded data to output
- constexpr uint8_t k_rbMask64 = 0b00111111; // 64b write mask for 1RB (24 int16 values)
- _mm512_mask_storeu_epi64(dataOut->dataExpanded + n * BlockFloatCompander::k_numREReal, k_rbMask64, expData);
+ const auto exponents = computeExponent_16RB(dataIn, totShiftBits);
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * (k_numREReal + 1));
+ }
}
-}
-/// 9 bit expansion
-void
-BlockFloatCompander::BlockFloatExpand_9b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut)
-{
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// 8bit RB compression loop for 4 RB
+ void
+ compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- constexpr int k_totNumBytesPerRB = 28;
- auto expAddr = n * k_totNumBytesPerRB;
-
- /// Unpack network order packed data
- auto expData = networkByteUnpack9b(dataIn.dataCompressed + expAddr + 1);
+ const auto exponents = computeExponent_4RB(dataIn, totShiftBits);
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * (k_numREReal + 1));
+ }
+ }
- /// Apply exponent scaling (by appropriate arithmetic shift right)
- constexpr int k_maxExpShift = 7;
- expData = _mm512_srai_epi16(expData, k_maxExpShift - *(dataIn.dataCompressed + expAddr));
- /// Write expanded data to output
- static constexpr uint32_t k_WriteMask = 0x00FFFFFF;
- _mm512_mask_storeu_epi16(dataOut->dataExpanded + n * BlockFloatCompander::k_numREReal, k_WriteMask, expData);
+ /// 8bit RB compression loop for 4 RB
+ void
+ compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
+ {
+ const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits);
+ applyCompression8_1RB(dataIn, dataOut, 0, thisExponent, 0);
}
-}
-/// 10 bit expansion
-void
-BlockFloatCompander::BlockFloatExpand_10b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut)
-{
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth.
+ void
+ compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits)
{
- constexpr int k_totNumBytesPerRB = 31;
- auto expAddr = n * k_totNumBytesPerRB;
-
- /// Unpack network order packed data
- auto expData = networkByteUnpack10b(dataIn.dataCompressed + expAddr + 1);
+ switch (dataIn.numBlocks)
+ {
+ case 16:
+ compress8_16RB(dataIn, dataOut, totShiftBits);
+ break;
- /// Apply exponent scaling (by appropriate arithmetic shift right)
- constexpr int k_maxExpShift = 6;
- expData = _mm512_srai_epi16(expData, k_maxExpShift - *(dataIn.dataCompressed + expAddr));
+ case 4:
+ compress8_4RB(dataIn, dataOut, totShiftBits);
+ break;
- /// Write expanded data to output
- static constexpr uint32_t k_WriteMask = 0x00FFFFFF;
- _mm512_mask_storeu_epi16(dataOut->dataExpanded + n * BlockFloatCompander::k_numREReal, k_WriteMask, expData);
+ case 1:
+ compress8_1RB(dataIn, dataOut, totShiftBits);
+ break;
+ }
}
-}
-/// 12 bit expansion
-void
-BlockFloatCompander::BlockFloatExpand_12b_AVX512(const CompressedData& dataIn, ExpandedData* dataOut)
-{
-#pragma unroll(BlockFloatCompander::k_numRB)
- for (int n = 0; n < BlockFloatCompander::k_numRB; ++n)
+ /// Apply compression to 1 RB
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ void
+ applyExpansionN_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int expAddr, const int thisRBAddr, const int maxExpShift)
{
- constexpr int k_totNumBytesPerRB = 37;
- auto expAddr = n * k_totNumBytesPerRB;
-
/// Unpack network order packed data
- auto expData = networkByteUnpack12b(dataIn.dataCompressed + expAddr + 1);
-
+ const auto dataUnpacked = networkByteUnpack(dataIn.dataCompressed + expAddr + 1);
/// Apply exponent scaling (by appropriate arithmetic shift right)
- constexpr int k_maxExpShift = 4;
- expData = _mm512_srai_epi16(expData, k_maxExpShift - *(dataIn.dataCompressed + expAddr));
-
+ const auto dataExpanded = _mm512_srai_epi16(dataUnpacked, maxExpShift - *(dataIn.dataCompressed + expAddr));
/// Write expanded data to output
static constexpr uint32_t k_WriteMask = 0x00FFFFFF;
- _mm512_mask_storeu_epi16(dataOut->dataExpanded + n * BlockFloatCompander::k_numREReal, k_WriteMask, expData);
+ _mm512_mask_storeu_epi16(dataOut->dataExpanded + thisRBAddr, k_WriteMask, dataExpanded);
}
-}
-/// Reference compression
-void
-BlockFloatCompander::BlockFloatCompress_Basic(const ExpandedData& dataIn, CompressedData* dataOut)
-{
- int dataOutIdx = 0;
- int16_t iqMask = (int16_t)((1 << dataIn.iqWidth) - 1);
- int byteShiftUnits = dataIn.iqWidth - 8;
-
- for (int rb = 0; rb < BlockFloatCompander::k_numRB; ++rb)
+ /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth.
+ template<BlockFloatCompander::UnpackFunction networkByteUnpack>
+ void
+ expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int totNumBytesPerRB, const int maxExpShift)
{
- /// Find max abs value for this RB
- int16_t maxAbs = 0;
- for (int re = 0; re < BlockFloatCompander::k_numREReal; ++re)
- {
- auto dataIdx = rb * BlockFloatCompander::k_numREReal + re;
- auto dataAbs = saturateAbs(dataIn.dataExpanded[dataIdx]);
- maxAbs = std::max(maxAbs, dataAbs);
- }
-
- // Find exponent and insert into byte stream
- auto thisExp = (uint8_t)(std::max(0,(16 - dataIn.iqWidth + 1 - __lzcnt16(maxAbs))));
- dataOut->dataCompressed[dataOutIdx++] = thisExp;
-
- /// ARS data by exponent and pack bytes in Network order
- /// This uses a sliding buffer where one or more bytes are
- /// extracted after the insertion of each compressed sample
- static constexpr int k_byteMask = 0xFF;
- int byteShiftVal = -8;
- int byteBuffer = { 0 };
- for (int re = 0; re < BlockFloatCompander::k_numREReal; ++re)
+ switch (dataIn.numBlocks)
{
- auto dataIdxIn = rb * BlockFloatCompander::k_numREReal + re;
- auto thisRE = dataIn.dataExpanded[dataIdxIn] >> thisExp;
- byteBuffer = (byteBuffer << dataIn.iqWidth) + (int)(thisRE & iqMask);
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
+ {
+ applyExpansionN_1RB<networkByteUnpack>(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift);
+ }
+ break;
- byteShiftVal += (8 + byteShiftUnits);
- while (byteShiftVal >= 0)
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
{
- auto thisByte = (uint8_t)((byteBuffer >> byteShiftVal) & k_byteMask);
- dataOut->dataCompressed[dataOutIdx++] = thisByte;
- byteShiftVal -= 8;
+ applyExpansionN_1RB<networkByteUnpack>(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift);
}
+ break;
+
+ case 1:
+ applyExpansionN_1RB<networkByteUnpack>(dataIn, dataOut, 0, 0, maxExpShift);
+ break;
}
}
- dataOut->iqWidth = dataIn.iqWidth;
-}
-/// Reference expansion
-void
-BlockFloatCompander::BlockFloatExpand_Basic(const CompressedData& dataIn, ExpandedData* dataOut)
-{
- uint32_t iqMask = (uint32_t)(UINT_MAX - ((1 << (32 - dataIn.iqWidth)) - 1));
- uint32_t byteBuffer = { 0 };
- int numBytesPerRB = (3 * dataIn.iqWidth) + 1;
- int bitPointer = 0;
- int dataIdxOut = 0;
- for (int rb = 0; rb < BlockFloatCompander::k_numRB; ++rb)
+ /// Apply expansion to 1 RB and store
+ void
+ applyExpansion8_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut,
+ const int expAddr, const int thisRBAddr)
{
- auto expIdx = rb * numBytesPerRB;
- auto signExtShift = 32 - dataIn.iqWidth - dataIn.dataCompressed[expIdx];
+ const __m256i* rawDataIn = reinterpret_cast<const __m256i*>(dataIn.dataCompressed + expAddr + 1);
+ const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn);
+ const auto expData = _mm512_slli_epi16(compData16, *(dataIn.dataCompressed + expAddr));
+ constexpr uint8_t k_rbMask64 = 0b00111111; // 64b write mask for 1RB (24 int16 values)
+ _mm512_mask_storeu_epi64(dataOut->dataExpanded + thisRBAddr, k_rbMask64, expData);
+ }
- for (int b = 0; b < numBytesPerRB - 1; ++b)
+
+ /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth.
+ void
+ expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut)
+ {
+ switch (dataIn.numBlocks)
{
- auto dataIdxIn = (expIdx + 1) + b;
- auto thisByte = (uint16_t)dataIn.dataCompressed[dataIdxIn];
- byteBuffer = (uint32_t)((byteBuffer << 8) + thisByte);
- bitPointer += 8;
- while (bitPointer >= dataIn.iqWidth)
+ case 16:
+#pragma unroll(16)
+ for (int n = 0; n < 16; ++n)
{
- /// byteBuffer currently has enough data in it to extract a sample
- /// Shift left first to set sign bit at MSB, then shift right to
- /// sign extend down to iqWidth. Finally recast to int16.
- int32_t thisSample32 = (int32_t)((byteBuffer << (32 - bitPointer)) & iqMask);
- int16_t thisSample = (int16_t)(thisSample32 >> signExtShift);
- bitPointer -= dataIn.iqWidth;
- dataOut->dataExpanded[dataIdxOut++] = thisSample;
+ applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal);
}
+ break;
+
+ case 4:
+#pragma unroll(4)
+ for (int n = 0; n < 4; ++n)
+ {
+ applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal);
+ }
+ break;
+
+ case 1:
+ applyExpansion8_1RB(dataIn, dataOut, 0, 0);
+ break;
}
}
}
-/// Reference compression
+
+
+/// Main kernel function for compression.
+/// Starts by determining iqWidth specific parameters and functions.
void
-BlockFloatCompanderBFW::BlockFloatCompress_Basic(const BlockFloatCompanderBFW::ExpandedData& dataIn, BlockFloatCompanderBFW::CompressedData* dataOut)
+BlockFloatCompander::BFPCompressUserPlaneAvx512(const ExpandedData& dataIn, CompressedData* dataOut)
{
- int dataOutIdx = 0;
- int16_t iqMask = (int16_t)((1 << dataIn.iqWidth) - 1);
- int byteShiftUnits = dataIn.iqWidth - 8;
-
- for (int rb = 0; rb < BlockFloatCompanderBFW::k_numRB; ++rb)
+ /// Compensation for extra zeros in 32b leading zero count when computing exponent
+ const auto totShiftBits8 = _mm512_set1_epi32(25);
+ const auto totShiftBits9 = _mm512_set1_epi32(24);
+ const auto totShiftBits10 = _mm512_set1_epi32(23);
+ const auto totShiftBits12 = _mm512_set1_epi32(21);
+
+ /// Total number of compressed bytes per RB for each iqWidth option
+ constexpr int totNumBytesPerRB9 = 28;
+ constexpr int totNumBytesPerRB10 = 31;
+ constexpr int totNumBytesPerRB12 = 37;
+
+ /// Compressed data write mask for each iqWidth option
+ constexpr uint16_t rbWriteMask9 = 0x01FF;
+ constexpr uint16_t rbWriteMask10 = 0x03FF;
+ constexpr uint16_t rbWriteMask12 = 0x0FFF;
+
+ switch (dataIn.iqWidth)
{
- /// Find max abs value for this RB
- int16_t maxAbs = 0;
- for (int re = 0; re < BlockFloatCompanderBFW::k_numREReal; ++re)
- {
- auto dataIdx = rb * BlockFloatCompanderBFW::k_numREReal + re;
- auto dataAbs = saturateAbs(dataIn.dataExpanded[dataIdx]);
- maxAbs = std::max(maxAbs, dataAbs);
- }
+ case 8:
+ BFP_UPlane::compressByAlloc8(dataIn, dataOut, totShiftBits8);
+ break;
- // Find exponent and insert into byte stream
- auto thisExp = (uint8_t)(std::max(0,(16 - dataIn.iqWidth + 1 - __lzcnt16(maxAbs))));
- dataOut->dataCompressed[dataOutIdx++] = thisExp;
-
- /// ARS data by exponent and pack bytes in Network order
- /// This uses a sliding buffer where one or more bytes are
- /// extracted after the insertion of each compressed sample
- static constexpr int k_byteMask = 0xFF;
- int byteShiftVal = -8;
- int byteBuffer = { 0 };
- for (int re = 0; re < BlockFloatCompanderBFW::k_numREReal; ++re)
- {
- auto dataIdxIn = rb * BlockFloatCompanderBFW::k_numREReal + re;
- auto thisRE = dataIn.dataExpanded[dataIdxIn] >> thisExp;
- byteBuffer = (byteBuffer << dataIn.iqWidth) + (int)(thisRE & iqMask);
+ case 9:
+ BFP_UPlane::compressByAllocN<BlockFloatCompander::networkBytePack9b>(dataIn, dataOut, totShiftBits9, totNumBytesPerRB9, rbWriteMask9);
+ break;
- byteShiftVal += (8 + byteShiftUnits);
- while (byteShiftVal >= 0)
- {
- auto thisByte = (uint8_t)((byteBuffer >> byteShiftVal) & k_byteMask);
- dataOut->dataCompressed[dataOutIdx++] = thisByte;
- byteShiftVal -= 8;
- }
- }
+ case 10:
+ BFP_UPlane::compressByAllocN<BlockFloatCompander::networkBytePack10b>(dataIn, dataOut, totShiftBits10, totNumBytesPerRB10, rbWriteMask10);
+ break;
+
+ case 12:
+ BFP_UPlane::compressByAllocN<BlockFloatCompander::networkBytePack12b>(dataIn, dataOut, totShiftBits12, totNumBytesPerRB12, rbWriteMask12);
+ break;
}
- dataOut->iqWidth = dataIn.iqWidth;
}
-/// Reference expansion
+
+
+/// Main kernel function for expansion.
+/// Starts by determining iqWidth specific parameters and functions.
void
-BlockFloatCompanderBFW::BlockFloatExpand_Basic(const BlockFloatCompanderBFW::CompressedData& dataIn, BlockFloatCompanderBFW::ExpandedData* dataOut)
+BlockFloatCompander::BFPExpandUserPlaneAvx512(const CompressedData& dataIn, ExpandedData* dataOut)
{
- uint32_t iqMask = (uint32_t)(UINT_MAX - ((1 << (32 - dataIn.iqWidth)) - 1));
- uint32_t byteBuffer = { 0 };
- int numBytesPerRB = (3 * dataIn.iqWidth) + 1;
- int bitPointer = 0;
- int dataIdxOut = 0;
+ constexpr int k_totNumBytesPerRB9 = 28;
+ constexpr int k_totNumBytesPerRB10 = 31;
+ constexpr int k_totNumBytesPerRB12 = 37;
+
+ constexpr int k_maxExpShift9 = 7;
+ constexpr int k_maxExpShift10 = 6;
+ constexpr int k_maxExpShift12 = 4;
- for (int rb = 0; rb < BlockFloatCompanderBFW::k_numRB; ++rb)
+ switch (dataIn.iqWidth)
{
- auto expIdx = rb * numBytesPerRB;
- auto signExtShift = 32 - dataIn.iqWidth - dataIn.dataCompressed[expIdx];
+ case 8:
+ BFP_UPlane::expandByAlloc8(dataIn, dataOut);
+ break;
- for (int b = 0; b < numBytesPerRB - 1; ++b)
- {
- auto dataIdxIn = (expIdx + 1) + b;
- auto thisByte = (uint16_t)dataIn.dataCompressed[dataIdxIn];
- byteBuffer = (uint32_t)((byteBuffer << 8) + thisByte);
- bitPointer += 8;
- while (bitPointer >= dataIn.iqWidth)
- {
- /// byteBuffer currently has enough data in it to extract a sample
- /// Shift left first to set sign bit at MSB, then shift right to
- /// sign extend down to iqWidth. Finally recast to int16.
- int32_t thisSample32 = (int32_t)((byteBuffer << (32 - bitPointer)) & iqMask);
- int16_t thisSample = (int16_t)(thisSample32 >> signExtShift);
- bitPointer -= dataIn.iqWidth;
- dataOut->dataExpanded[dataIdxOut++] = thisSample;
- }
- }
- }
-}
+ case 9:
+ BFP_UPlane::expandByAllocN<BlockFloatCompander::networkByteUnpack9b>(dataIn, dataOut, k_totNumBytesPerRB9, k_maxExpShift9);
+ break;
-#define RB_NUM_ROUNDUP(rb) \
- (BlockFloatCompander::k_numRB * ((rb + BlockFloatCompander::k_numRB - 1) / BlockFloatCompander::k_numRB))
+ case 10:
+ BFP_UPlane::expandByAllocN<BlockFloatCompander::networkByteUnpack10b>(dataIn, dataOut, k_totNumBytesPerRB10, k_maxExpShift10);
+ break;
+ case 12:
+ BFP_UPlane::expandByAllocN<BlockFloatCompander::networkByteUnpack12b>(dataIn, dataOut, k_totNumBytesPerRB12, k_maxExpShift12);
+ break;
+ }
+}
/** callback function type for Symbol packet */
typedef void (*xran_bfp_compress_fn)(const BlockFloatCompander::ExpandedData& dataIn,
BlockFloatCompander::CompressedData* dataOut);
+/** callback function type for Symbol packet */
+typedef void (*xran_bfp_decompress_fn)(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut);
+
int32_t
xranlib_compress_avx512(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response)
BlockFloatCompander::ExpandedData expandedDataInput;
BlockFloatCompander::CompressedData compressedDataOut;
xran_bfp_compress_fn com_fn = NULL;
- int16_t numRBs = request->numRBs;
+ uint16_t totalRBs = request->numRBs;
+ uint16_t remRBs = totalRBs;
int16_t len = 0;
+ int16_t block_idx_bytes = 0;
- switch (request->iqWidth){
+ switch (request->iqWidth) {
case 8:
- expandedDataInput.iqWidth = 8;
- com_fn = BlockFloatCompander::BlockFloatCompress_8b_AVX512;
- break;
case 9:
- expandedDataInput.iqWidth = 9;
- com_fn = BlockFloatCompander::BlockFloatCompress_9b_AVX512;
- break;
case 10:
- expandedDataInput.iqWidth = 10;
- com_fn = BlockFloatCompander::BlockFloatCompress_10b_AVX512;
- break;
case 12:
- expandedDataInput.iqWidth = 12;
- com_fn = BlockFloatCompander::BlockFloatCompress_12b_AVX512;
+ com_fn = BlockFloatCompander::BFPCompressUserPlaneAvx512;
break;
default:
- expandedDataInput.iqWidth = request->iqWidth;
- com_fn = BlockFloatCompander::BlockFloatCompress_Basic;
+ com_fn = BlockFloatCompander::BFPCompressRef;
break;
}
- for (int16_t block_idx = 0;
- block_idx < RB_NUM_ROUNDUP(numRBs)/BlockFloatCompander::k_numRB /*+ 1*/; /* 16 RBs at time */
- block_idx++) {
+ expandedDataInput.iqWidth = request->iqWidth;
+ expandedDataInput.numDataElements = 24;
+
+ while (remRBs){
+ expandedDataInput.dataExpanded = &request->data_in[block_idx_bytes];
+ compressedDataOut.dataCompressed = (uint8_t*)&response->data_out[len];
+ if(remRBs >= 16){
+ expandedDataInput.numBlocks = 16;
+ com_fn(expandedDataInput, &compressedDataOut);
+ len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)16);
+ block_idx_bytes += 16*expandedDataInput.numDataElements;
+ remRBs -= 16;
+ }else if(remRBs >= 4){
+ expandedDataInput.numBlocks = 4;
+ com_fn(expandedDataInput, &compressedDataOut);
+ len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)4);
+ block_idx_bytes +=4*expandedDataInput.numDataElements;
+ remRBs -=4;
+ }else if (remRBs >= 1){
+ expandedDataInput.numBlocks = 1;
+ com_fn(expandedDataInput, &compressedDataOut);
+ len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)1);
+ block_idx_bytes +=1*expandedDataInput.numDataElements;
+ remRBs = remRBs - 1;
+ }
+ }
+
+ response->len = ((3 * expandedDataInput.iqWidth) + 1) * totalRBs;
+
+ return 0;
+}
+
+int32_t
+xranlib_decompress_avx512(const struct xranlib_decompress_request *request,
+ struct xranlib_decompress_response *response)
+{
+ BlockFloatCompander::CompressedData compressedDataInput;
+ BlockFloatCompander::ExpandedData expandedDataOut;
- expandedDataInput.dataExpanded =
- &request->data_in[block_idx*BlockFloatCompander::k_numSampsExpanded];
- compressedDataOut.dataCompressed =
- (uint8_t*)&response->data_out[len];
+ xran_bfp_decompress_fn decom_fn = NULL;
+ uint16_t totalRBs = request->numRBs;
+ uint16_t remRBs = totalRBs;
+ int16_t len = 0;
+ int16_t block_idx_bytes = 0;
+
+ switch (request->iqWidth) {
+ case 8:
+ case 9:
+ case 10:
+ case 12:
+ decom_fn = BlockFloatCompander::BFPExpandUserPlaneAvx512;
+ break;
+ default:
+ decom_fn = BlockFloatCompander::BFPExpandRef;
+ break;
+ }
- com_fn(expandedDataInput, &compressedDataOut);
- len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_numRB,(int16_t)numRBs);
+ compressedDataInput.iqWidth = request->iqWidth;
+ compressedDataInput.numDataElements = 24;
+
+ while(remRBs) {
+ compressedDataInput.dataCompressed = (uint8_t*)&request->data_in[block_idx_bytes];
+ expandedDataOut.dataExpanded = &response->data_out[len];
+ if(remRBs >= 16){
+ compressedDataInput.numBlocks = 16;
+ decom_fn(compressedDataInput, &expandedDataOut);
+ len += 16*compressedDataInput.numDataElements;
+ block_idx_bytes += ((3 * compressedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)16);
+ remRBs -= 16;
+ }else if(remRBs >= 4){
+ compressedDataInput.numBlocks = 4;
+ decom_fn(compressedDataInput, &expandedDataOut);
+ len += 4*compressedDataInput.numDataElements;
+ block_idx_bytes += ((3 * compressedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)4);
+ remRBs -=4;
+ }else if (remRBs >= 1){
+ compressedDataInput.numBlocks = 1;
+ decom_fn(compressedDataInput, &expandedDataOut);
+ len += 1*compressedDataInput.numDataElements;
+ block_idx_bytes += ((3 * compressedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)1);
+ remRBs = remRBs - 1;
+ }
}
- response->len = ((3 * expandedDataInput.iqWidth) + 1) * numRBs;
+ response->len = totalRBs * compressedDataInput.numDataElements * sizeof(int16_t);
return 0;
}
-/** callback function type for Symbol packet */
-typedef void (*xran_bfp_compress_bfw_fn)(const BlockFloatCompanderBFW::ExpandedData& dataIn, BlockFloatCompanderBFW::CompressedData* dataOut);
-
int32_t
xranlib_compress_avx512_bfw(const struct xranlib_compress_request *request,
struct xranlib_compress_response *response)
{
- BlockFloatCompanderBFW::ExpandedData expandedDataInput;
- BlockFloatCompanderBFW::CompressedData compressedDataKern;
- xran_bfp_compress_bfw_fn com_fn = NULL;
-
-#if 0
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m){
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n){
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] =
- request->data_in[m*BlockFloatCompander::k_numREReal+n];
- }
- }
-#endif
+ BlockFloatCompander::ExpandedData expandedDataInput;
+ BlockFloatCompander::CompressedData compressedDataOut;
+ xran_bfp_compress_fn com_fn = NULL;
- expandedDataInput.dataExpanded = request->data_in;
- compressedDataKern.dataCompressed = (uint8_t*)response->data_out;
+ if (request->numRBs != 1){
+ printf("Unsupported numRBs %d\n", request->numRBs);
+ return -1;
+ }
- com_fn = BlockFloatCompanderBFW::BlockFloatCompress_Basic;
- switch (request->iqWidth){
+ switch (request->iqWidth) {
case 8:
- expandedDataInput.iqWidth = 8;
- break;
case 9:
- expandedDataInput.iqWidth = 9;
- //com_fn = BlockFloatCompanderBFW::BlockFloatExpand_9b_AVX512
- break;
case 10:
- expandedDataInput.iqWidth = 10;
- break;
case 12:
- expandedDataInput.iqWidth = 12;
- break;
- default:
- printf("bfwIqWidth is not supported %d\n", request->iqWidth);
- return -1;
- break;
+ switch (request->numDataElements) {
+ case 16:
+ com_fn = BlockFloatCompander::BFPCompressCtrlPlane8Avx512;
+ break;
+ case 32:
+ com_fn = BlockFloatCompander::BFPCompressCtrlPlane16Avx512;
+ break;
+ case 64:
+ com_fn = BlockFloatCompander::BFPCompressCtrlPlane32Avx512;
+ break;
+ case 128:
+ com_fn = BlockFloatCompander::BFPCompressCtrlPlane64Avx512;
+ break;
+ case 24:
+ default:
+ printf("Unsupported numDataElements %d\n", request->numDataElements);
+ return -1;
+ break;
+ }
+ break;
+ default:
+ printf("Unsupported iqWidth %d\n", request->iqWidth);
+ return -1;
+ break;
}
- com_fn(expandedDataInput, &compressedDataKern);
- response->len = ((BlockFloatCompanderBFW::k_numRE/16*4*expandedDataInput.iqWidth)+1)*BlockFloatCompanderBFW::k_numRB;
+ expandedDataInput.iqWidth = request->iqWidth;
+ expandedDataInput.numDataElements = request->numDataElements;
+ expandedDataInput.numBlocks = 1;
+ expandedDataInput.dataExpanded = &request->data_in[0];
+ compressedDataOut.dataCompressed = (uint8_t*)&response->data_out[0];
- return 0;
-}
+ com_fn(expandedDataInput, &compressedDataOut);
-/** callback function type for Symbol packet */
-typedef void (*xran_bfp_decompress_fn)(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut);
+ response->len = (((expandedDataInput.numDataElements * expandedDataInput.iqWidth) >> 3) + 1)
+ * request->numRBs;
+ return 0;
+}
int32_t
-xranlib_decompress_avx512(const struct xranlib_decompress_request *request,
- struct xranlib_decompress_response *response)
+xranlib_decompress_avx512_bfw(const struct xranlib_decompress_request *request,
+ struct xranlib_decompress_response *response)
{
-
BlockFloatCompander::CompressedData compressedDataInput;
BlockFloatCompander::ExpandedData expandedDataOut;
-
xran_bfp_decompress_fn decom_fn = NULL;
- int16_t numRBs = request->numRBs;
- int16_t len = 0;
- switch (request->iqWidth){
+ if (request->numRBs != 1){
+ printf("Unsupported numRBs %d\n", request->numRBs);
+ return -1;
+ }
+
+ switch (request->iqWidth) {
case 8:
- compressedDataInput.iqWidth = 8;
- decom_fn = BlockFloatCompander::BlockFloatExpand_8b_AVX512;
- break;
case 9:
- compressedDataInput.iqWidth = 9;
- decom_fn = BlockFloatCompander::BlockFloatExpand_9b_AVX512;
- break;
case 10:
- compressedDataInput.iqWidth = 10;
- decom_fn = BlockFloatCompander::BlockFloatExpand_10b_AVX512;
- break;
case 12:
- compressedDataInput.iqWidth = 12;
- decom_fn = BlockFloatCompander::BlockFloatExpand_12b_AVX512;
- break;
- default:
- compressedDataInput.iqWidth = request->iqWidth;
- decom_fn = BlockFloatCompander::BlockFloatExpand_Basic;
- break;
+ switch (request->numDataElements) {
+ case 16:
+ decom_fn = BlockFloatCompander::BFPExpandCtrlPlane8Avx512;
+ break;
+ case 32:
+ decom_fn = BlockFloatCompander::BFPExpandCtrlPlane16Avx512;
+ break;
+ case 64:
+ decom_fn = BlockFloatCompander::BFPExpandCtrlPlane32Avx512;
+ break;
+ case 128:
+ decom_fn = BlockFloatCompander::BFPExpandCtrlPlane64Avx512;
+ break;
+ case 24:
+ default:
+ printf("Unsupported numDataElements %d\n", request->numDataElements);
+ return -1;
+ break;
+ }
+ break;
+ default:
+ printf("Unsupported iqWidth %d\n", request->iqWidth);
+ return -1;
+ break;
}
- for (int16_t block_idx = 0;
- block_idx < RB_NUM_ROUNDUP(numRBs)/BlockFloatCompander::k_numRB;
- block_idx++) {
+ compressedDataInput.iqWidth = request->iqWidth;
+ compressedDataInput.numDataElements = request->numDataElements;
+ compressedDataInput.numBlocks = 1;
+ compressedDataInput.dataCompressed = (uint8_t*)&request->data_in[0];
+ expandedDataOut.dataExpanded = &response->data_out[0];
- compressedDataInput.dataCompressed = (uint8_t*)&request->data_in[block_idx*(((3 * compressedDataInput.iqWidth ) + 1) * BlockFloatCompander::k_numRB)];
- expandedDataOut.dataExpanded = &response->data_out[len];
+ decom_fn(compressedDataInput, &expandedDataOut);
- decom_fn(compressedDataInput, &expandedDataOut);
- len += std::min((int16_t)BlockFloatCompander::k_numSampsExpanded, (int16_t)(numRBs*BlockFloatCompander::k_numREReal));
- }
-
- response->len = numRBs * BlockFloatCompander::k_numREReal* sizeof(int16_t);
+ response->len = request->numRBs * compressedDataInput.numDataElements * sizeof(int16_t);
return 0;
}
+
print_err("Fail to allocate the space for section extension 1");
return (XRAN_STATUS_RESOURCE);
}
- bfp_com_req.data_in = (int16_t*)p_bfw_iq_src;
- bfp_com_req.len = bfwNumPerRb*4;
- bfp_com_req.compMethod = p_ext1->bfwCompMeth;
- bfp_com_req.iqWidth = p_ext1->bfwIqWidth;
+ bfp_com_req.data_in = (int16_t*)p_bfw_iq_src;
+ bfp_com_req.numRBs = 1;
+ bfp_com_req.numDataElements = bfwNumPerRb*2;
+ bfp_com_req.len = bfwNumPerRb*4;
+ bfp_com_req.compMethod = p_ext1->bfwCompMeth;
+ bfp_com_req.iqWidth = p_ext1->bfwIqWidth;
print_dbg("req 0x%08p iqWidth %d\n",bfp_com_req.data_in, bfp_com_req.iqWidth);
bfp_com_rsp.data_out = (int8_t*)p_bfw_content;
if(xranlib_compress_avx512_bfw(&bfp_com_req, &bfp_com_rsp) == 0){
comp_len = bfp_com_rsp.len;
- print_dbg("comp_len %d\n", comp_len);
+ print_dbg("comp_len %d parm_size %d\n", comp_len, parm_size);
} else {
print_err("compression failed\n");
return (XRAN_STATUS_FAIL);
rte_panic("ext1 should be aligned on 4-bytes boundary");
p_ext1->extLen = cur_ext_len / XRAN_SECTIONEXT_ALIGN;
- print_dbg("p_ext1->extLen %d\n", p_ext1->extLen);
+ print_dbg("[%d] %p iq %p p_ext1->extLen %d\n",idxRb, p_ext1, p_ext1+1, p_ext1->extLen);
/* update for next RB */
p_ext1_dst_cur += cur_ext_len;
return (freqOffset);
}
-static int xran_copy_sectionext_1(struct rte_mbuf *mbuf,
+static int xran_append_sectionext_1(struct rte_mbuf *mbuf,
struct xran_sectionext1_info *params, int last_flag)
{
- int32_t total_len;
- int8_t *p_dst = (int8_t *)rte_pktmbuf_append(mbuf, params->bfwIQ_sz);
- if(p_dst == NULL) {
- print_err("Fail to allocate the space for section extension 1 [%d]", params->bfwIQ_sz);
- return (XRAN_STATUS_RESOURCE);
- }
- if(params->p_bfwIQ){
- /* copy formated extType1 with all the headers */
- rte_memcpy(p_dst, params->p_bfwIQ, params->bfwIQ_sz);
+ int32_t total_len = 0;
+
+ if(params->bfwIQ_sz) {
+ int8_t *p_dst = (int8_t *)rte_pktmbuf_append(mbuf, params->bfwIQ_sz);
+
+ if(p_dst == NULL) {
+ print_err("Fail to allocate the space for section extension 1 [%d]", params->bfwIQ_sz);
+ return (XRAN_STATUS_RESOURCE);
+ }
+
+ /* extType1 with all the headers created by xran_cp_populate_section_ext_1() earlier */
total_len = params->bfwIQ_sz;
}
- else
- total_len = 0;
-
return (total_len);
}
return (total_len);
}
+static int xran_prepare_sectionext_3(struct rte_mbuf *mbuf,
+ struct xran_sectionext3_info *params, int last_flag)
+{
+ int total_len;
+ int adj;
+
+
+ if(params->layerId == XRAN_LAYERID_0
+ || params->layerId == XRAN_LAYERID_TXD) { /* first data layer */
+
+ struct xran_cp_radioapp_section_ext3_first *ext3_f;
+ uint64_t *tmp;
+
+ total_len = sizeof(struct xran_cp_radioapp_section_ext3_first);
+ ext3_f = (struct xran_cp_radioapp_section_ext3_first *)rte_pktmbuf_append(mbuf, total_len);
+ if(ext3_f == NULL) {
+ print_err("Fail to allocate the space for section extension 3");
+ return (XRAN_STATUS_RESOURCE);
+ }
+
+ ext3_f->layerId = params->layerId;
+ ext3_f->ef = last_flag;
+ ext3_f->extType = XRAN_CP_SECTIONEXTCMD_3;
+ ext3_f->crsSymNum = params->crsSymNum;
+ ext3_f->crsShift = params->crsShift;
+ ext3_f->crsReMask = params->crsReMask;
+ ext3_f->txScheme = params->txScheme;
+ ext3_f->numLayers = params->numLayers;
+ ext3_f->codebookIndex = params->codebookIdx;
+
+ if(params->numAntPort == 2) {
+ ext3_f->beamIdAP3 = params->beamIdAP1;
+ ext3_f->beamIdAP2 = 0;
+ ext3_f->beamIdAP1 = 0;
+ ext3_f->extLen = 3;
+ adj = 4;
+ total_len -= adj;
+ }
+ else {
+ ext3_f->beamIdAP3 = params->beamIdAP1;
+ ext3_f->beamIdAP2 = params->beamIdAP2;
+ ext3_f->beamIdAP1 = params->beamIdAP3;
+ ext3_f->extLen = 4;
+ adj = 0;
+ }
+ ext3_f->reserved0 = 0;
+ ext3_f->reserved1 = 0;
+ ext3_f->reserved2 = 0;
+
+ /* convert byte order */
+ tmp = (uint64_t *)ext3_f;
+ *tmp = rte_cpu_to_be_64(*tmp); tmp++;
+ *tmp = rte_cpu_to_be_64(*tmp);
+
+ if(adj)
+ rte_pktmbuf_trim(mbuf, adj);
+ }
+ else { /* non-first data layer */
+ struct xran_cp_radioapp_section_ext3_non_first *ext3_nf;
+
+ total_len = sizeof(struct xran_cp_radioapp_section_ext3_non_first);
+ ext3_nf = (struct xran_cp_radioapp_section_ext3_non_first *)rte_pktmbuf_append(mbuf, total_len);
+ if(ext3_nf == NULL) {
+ print_err("Fail to allocate the space for section extension 3");
+ return (XRAN_STATUS_RESOURCE);
+ }
+
+ ext3_nf->layerId = params->layerId;
+ ext3_nf->ef = last_flag;
+ ext3_nf->extType = XRAN_CP_SECTIONEXTCMD_3;
+ ext3_nf->numLayers = params->numLayers;
+ ext3_nf->codebookIndex = params->codebookIdx;
+
+ ext3_nf->extLen = sizeof(struct xran_cp_radioapp_section_ext3_non_first)/XRAN_SECTIONEXT_ALIGN;
+
+ *(uint32_t *)ext3_nf = rte_cpu_to_be_32(*(uint32_t *)ext3_nf);
+ }
+
+ return (total_len);
+}
+
static int xran_prepare_sectionext_4(struct rte_mbuf *mbuf,
struct xran_sectionext4_info *params, int last_flag)
{
switch(params->exData[i].type) {
case XRAN_CP_SECTIONEXTCMD_1:
- ext_size = xran_copy_sectionext_1(mbuf, params->exData[i].data, last_flag);
- //xran_prepare_sectionext_1(mbuf, params->exData[i].data, last_flag);
+ ext_size = xran_append_sectionext_1(mbuf, params->exData[i].data, last_flag);
break;
case XRAN_CP_SECTIONEXTCMD_2:
ext_size = xran_prepare_sectionext_2(mbuf, params->exData[i].data, last_flag);
break;
+ case XRAN_CP_SECTIONEXTCMD_3:
+ ext_size = xran_prepare_sectionext_3(mbuf, params->exData[i].data, last_flag);
+ break;
case XRAN_CP_SECTIONEXTCMD_4:
ext_size = xran_prepare_sectionext_4(mbuf, params->exData[i].data, last_flag);
break;
case XRAN_CP_SECTIONEXTCMD_5:
ext_size = xran_prepare_sectionext_5(mbuf, params->exData[i].data, last_flag);
break;
- case XRAN_CP_SECTIONEXTCMD_0:
- case XRAN_CP_SECTIONEXTCMD_3:
default:
print_err("Extension Type %d is not supported!", params->exData[i].type);
ret = XRAN_STATUS_INVALID_PARAM;
apphdr->filterIndex = params->hdr.filterIdx;
apphdr->frameId = params->hdr.frameId;
apphdr->subframeId = params->hdr.subframeId;
- apphdr->slotId = params->hdr.slotId;
+ apphdr->slotId = xran_slotid_convert(params->hdr.slotId, 0);
apphdr->startSymbolId = params->hdr.startSymId;
apphdr->numOfSections = params->numSections;
apphdr->sectionType = params->sectionType;
ext2 = (struct xran_cp_radioapp_section_ext2 *)ext;
data = (uint8_t *)ext;
- *(uint32_t *)ext2 = rte_cpu_to_be_32(*(uint32_t *)ext2);
+ *(uint32_t *)ext2 = rte_be_to_cpu_32(*(uint32_t *)ext2);
len = 0;
total_len = ext2->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */
+ (extinfo->bfAz3ddWidth ? extinfo->bfAz3ddWidth+1 : 0)
+ (extinfo->bfZe3ddWidth ? extinfo->bfZe3ddWidth+ 1: 0);
if(val_size) {
- val = rte_cpu_to_be_32(*(uint32_t *)data);
+ val = rte_be_to_cpu_32(*(uint32_t *)data);
val >>= (32 - val_size);
if(extinfo->bfZe3ddWidth) {
}
+int xran_parse_section_ext3(void *ext,
+ struct xran_sectionext3_info *extinfo)
+{
+ int len;
+ int total_len;
+
+ total_len = 0;
+ len = *((uint8_t *)ext + 1);
+
+ switch(len) {
+ case 1: /* non-first data layer */
+ {
+ struct xran_cp_radioapp_section_ext3_non_first *ext3_nf;
+
+ ext3_nf = (struct xran_cp_radioapp_section_ext3_non_first *)ext;
+ *(uint32_t *)ext3_nf = rte_be_to_cpu_32(*(uint32_t *)ext3_nf);
+
+ total_len = ext3_nf->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */
+
+ extinfo->codebookIdx= ext3_nf->codebookIndex;
+ extinfo->layerId = ext3_nf->layerId;
+ extinfo->numLayers = ext3_nf->numLayers;
+ }
+ break;
+
+ case 3: /* first data layer with two antenna */
+ case 4: /* first data layer with four antenna */
+ {
+ struct xran_cp_radioapp_section_ext3_first *ext3_f;
+ uint16_t *beamid;
+
+ ext3_f = (struct xran_cp_radioapp_section_ext3_first *)ext;
+ *(uint64_t *)ext3_f = rte_be_to_cpu_64(*(uint64_t *)ext3_f);
+
+ total_len = ext3_f->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */
+
+ extinfo->codebookIdx= ext3_f->codebookIndex;
+ extinfo->layerId = ext3_f->layerId;
+ extinfo->numLayers = ext3_f->numLayers;
+ extinfo->txScheme = ext3_f->txScheme;
+ extinfo->crsReMask = ext3_f->crsReMask;
+ extinfo->crsShift = ext3_f->crsShift;
+ extinfo->crsSymNum = ext3_f->crsSymNum;
+
+ /* beam IDs are stored from 10th octet */
+ beamid = (uint16_t *)((uint8_t *)ext + 10);
+
+ extinfo->beamIdAP1 = rte_be_to_cpu_16(*beamid++);
+ if(len == 4) {
+ extinfo->beamIdAP2 = rte_be_to_cpu_16(*beamid++);
+ extinfo->beamIdAP3 = rte_be_to_cpu_16(*beamid);
+ extinfo->numAntPort = 4;
+ }
+ else {
+ extinfo->numAntPort = 2;
+ }
+ }
+ break;
+
+ default:
+ print_err("Invalid length of extension 3 - %d", len);
+ }
+
+ return (total_len);
+}
+
int xran_parse_section_ext4(void *ext,
struct xran_sectionext4_info *extinfo)
{
ext4 = (struct xran_cp_radioapp_section_ext4 *)ext;
- *(uint32_t *)ext4 = rte_cpu_to_be_32(*(uint32_t *)ext4);
+ *(uint32_t *)ext4 = rte_be_to_cpu_32(*(uint32_t *)ext4);
len = 0;
total_len = ext4->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */
extinfo->modCompScaler = ext4->modCompScaler;
extinfo->csf = ext4->csf;
-// extinfo->pad0;
len += sizeof(struct xran_cp_radioapp_section_ext4);
if(len != total_len) {
uint8_t *data;
uint16_t i;
-
ext_hdr = (struct xran_cp_radioapp_section_ext_hdr *)ext;
- *(uint16_t *)ext_hdr = rte_cpu_to_be_16(*(uint16_t *)ext_hdr);
+ *(uint16_t *)ext_hdr = rte_be_to_cpu_16(*(uint16_t *)ext_hdr);
total_len = ext_hdr->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */
- // one set has 3.5 bytes, so enforcing double to do integer calculation
+ /* one set has 3.5 bytes, so enforcing double to do integer calculation */
parm_size = ((total_len-sizeof(struct xran_cp_radioapp_section_ext_hdr))*2) / 7;
if(parm_size > XRAN_MAX_MODCOMP_ADDPARMS) {
i = 0;
while(i < parm_size) {
// For odd number set, more data can be copied
- *((uint64_t *)&ext5) = rte_cpu_to_be_64(*((uint64_t *)data));
+ *((uint64_t *)&ext5) = rte_be_to_cpu_64(*((uint64_t *)data));
extinfo->mc[i].mcScaleOffset = ext5.mcScaleOffset1;
extinfo->mc[i].csf = ext5.csf1;
data += sizeof(struct xran_cp_radioapp_section_ext5);
}
- // check the values of last set
- // due to alignment, it cannot be identified by the length that 3 or 4, 11 or 12 and etc
- // don't check mcScaleOffset might not be zero (some part is out of zero-padding)
+ /* check the values of last set
+ * due to alignment, it cannot be identified by the length that 3 or 4, 11 or 12 and etc
+ * don't check mcScaleOffset might not be zero (some part is out of zero-padding) */
i--;
if(i < XRAN_MAX_MODCOMP_ADDPARMS) {
if(extinfo->mc[i].csf == 0 && extinfo->mc[i].mcScaleReMask == 0)
section->exData[numext].data = §ion->m_ext2[numext];
len = xran_parse_section_ext2(ptr, section->exData[numext].data);
break;
+ case XRAN_CP_SECTIONEXTCMD_3:
+ section->exData[numext].data = §ion->m_ext3[numext];
+ len = xran_parse_section_ext3(ptr, section->exData[numext].data);
+ break;
case XRAN_CP_SECTIONEXTCMD_4:
section->exData[numext].data = §ion->m_ext4[numext];
len = xran_parse_section_ext4(ptr, section->exData[numext].data);
len = xran_parse_section_ext5(ptr, section->exData[numext].data);
break;
- case XRAN_CP_SECTIONEXTCMD_0:
- case XRAN_CP_SECTIONEXTCMD_3:
default:
print_err("Extension %d is not supported!", ext_type);
len = 0;
return (XRAN_STATUS_INVALID_PACKET);
}
- *((uint32_t *)apphdr) = rte_cpu_to_be_32(*((uint32_t *)apphdr));
+ *((uint32_t *)apphdr) = rte_be_to_cpu_32(*((uint32_t *)apphdr));
if(apphdr->payloadVer != XRAN_PAYLOAD_VER) {
print_err("Invalid Payload version - %d", apphdr->payloadVer);
#define PID_TIME_SYSTIME_POLL 2104
#define PID_TIME_SYSTIME_STOP 2105
#define PID_TIME_ARM_TIMER 2106
+#define PID_TIME_ARM_TIMER_DEADLINE 2107
+
#define PID_RADIO_FREQ_RX_PKT 2400
#define DIV_ROUND_OFFSET(X,Y) ( X/Y + ((X%Y)?1:0) )
-#define XranOffsetSym(offSym, otaSym, numSymTotal) (((int32_t)offSym > (int32_t)otaSym) ? \
- ((int32_t)otaSym + ((int32_t)numSymTotal) - (uint32_t)offSym) : \
- (((int32_t)otaSym - (int32_t)offSym) >= numSymTotal) ? \
- (((int32_t)otaSym - (int32_t)offSym) - numSymTotal) : \
- ((int32_t)otaSym - (int32_t)offSym))
-
#define MAX_NUM_OF_XRAN_CTX (2)
#define XranIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_XRAN_CTX-1)) ? 0 : (ctx+1))
#define XranDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_XRAN_CTX-1) : (ctx-1))
GPS is 18 larger. 315 964 800 - 18 = 315 964 782
*/
#define UNIX_TO_GPS_SECONDS_OFFSET 315964782UL
+#define NUM_OF_FRAMES_PER_SFN_PERIOD 1024
#define NUM_OF_FRAMES_PER_SECOND 100
//#define XRAN_CREATE_RBMAP /**< generate slot map base on symbols */
uint32_t tti_to_process;
};
+enum xran_in_period
+{
+ XRAN_IN_PREV_PERIOD = 0,
+ XRAN_IN_CURR_PERIOD,
+ XRAN_IN_NEXT_PERIOD
+};
+
static xran_cc_handle_t pLibInstanceHandles[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {NULL};
static struct xran_device_ctx g_xran_dev_ctx[XRAN_PORTS_NUM] = { 0 };
struct xran_timer_ctx timer_ctx[MAX_NUM_OF_XRAN_CTX];
+struct xran_timer_ctx cb_timer_ctx[10*MAX_NUM_OF_XRAN_CTX];
+
static struct rte_timer tti_to_phy_timer[10];
static struct rte_timer sym_timer;
{
}
-static struct rte_mbuf_ext_shared_info share_data[XRAN_N_FE_BUF_LEN];
+static struct rte_mbuf_ext_shared_info share_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+static struct rte_mbuf_ext_shared_info cp_share_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+
void xran_timer_arm(struct rte_timer *tim, void* arg);
void tti_to_phy_cb(struct rte_timer *tim, void *arg);
void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore);
+
// Return SFN at current second start, 10 bits, [0, 1023]
static inline uint16_t xran_getSfnSecStart(void)
{
}
void xran_updateSfnSecStart(void)
{
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters;
uint64_t currentSecond = timing_get_current_second();
// Assume always positive
uint64_t gpsSecond = currentSecond - UNIX_TO_GPS_SECONDS_OFFSET;
uint16_t sfn = (uint16_t)(nFrames % (xran_max_frame + 1));
xran_SFN_at_Sec_Start = sfn;
- tx_bytes_per_sec = tx_bytes_counter;
- rx_bytes_per_sec = rx_bytes_counter;
- tx_bytes_counter = 0;
- rx_bytes_counter = 0;
+ pCnt->tx_bytes_per_sec = pCnt->tx_bytes_counter;
+ pCnt->rx_bytes_per_sec = pCnt->rx_bytes_counter;
+ pCnt->tx_bytes_counter = 0;
+ pCnt->rx_bytes_counter = 0;
}
static inline int32_t xran_getSlotIdxSecond(void)
return (&(xran_dev_get_ctx()->fh_cfg));
}
+static inline int32_t XranOffsetSym(int32_t offSym, int32_t otaSym, int32_t numSymTotal, enum xran_in_period* pInPeriod)
+{
+ int32_t sym;
+
+ // Suppose the offset is usually small
+ if (unlikely(offSym > otaSym))
+ {
+ sym = numSymTotal - offSym + otaSym;
+ *pInPeriod = XRAN_IN_PREV_PERIOD;
+ }
+ else
+ {
+ sym = otaSym - offSym;
+
+ if (unlikely(sym >= numSymTotal))
+ {
+ sym -= numSymTotal;
+ *pInPeriod = XRAN_IN_NEXT_PERIOD;
+ }
+ else
+ {
+ *pInPeriod = XRAN_IN_CURR_PERIOD;
+ }
+ }
+
+ return sym;
+}
+
uint16_t xran_get_beamid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id)
{
return (0); // NO BEAMFORMING
return (XRAN_STATUS_SUCCESS);
}
+int xran_init_prach_lte(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx)
+{
+ /* update Rach for LTE */
+ return xran_init_prach(pConf, p_xran_dev_ctx);
+}
int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx)
{
if(xran_upul_seq_id_num[cc_id][ant_id] == seq_id) { /* expected sequence */
return (XRAN_STATUS_SUCCESS);
} else {
- print_err("expected seqid %u received %u, slot %u, ant %u cc %u", xran_upul_seq_id_num[cc_id][ant_id], seq_id, slot_id, ant_id, cc_id);
+ print_dbg("expected seqid %u received %u, slot %u, ant %u cc %u", xran_upul_seq_id_num[cc_id][ant_id], seq_id, slot_id, ant_id, cc_id);
xran_upul_seq_id_num[cc_id][ant_id] = seq_id; // for next
return (-1);
}
}
}
+uint32_t xran_slotid_convert(uint16_t slot_id, uint16_t dir) //dir = 0, from PHY slotid to xran spec slotid as defined in 5.3.2, dir=1, from xran slotid to phy slotid
+{
+#ifdef FCN_ADAPT
+ return slot_id;
+#endif
+
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ uint8_t mu = p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology;
+ uint8_t FR = 1;
+ if (mu > 2)
+ FR=2;
+ if (dir == 0)
+ {
+ if (FR == 1)
+ {
+ return (slot_id << (2-mu));
+ }
+ else
+ {
+ return (slot_id << (3-mu));
+ }
+ }
+ else
+ {
+ if (FR == 1)
+ {
+ return (slot_id >> (2-mu));
+ }
+ else
+ {
+ return (slot_id >> (3-mu));
+ }
+ }
+
+}
static struct xran_section_gen_info cpSections[XRAN_MAX_NUM_SECTIONS];
static struct xran_cp_gen_params cpInfo;
*used_tick += get_ticks_diff(xran_tick(), t3);
}
+#if 0
if(XranGetSymNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT) == 3){
if(p_xran_dev_ctx->phy_tti_cb_done == 0){
/* rearm timer to deliver TTI event to PHY */
*used_tick += get_ticks_diff(xran_tick(), t3);
}
}
+#endif
+
t3 = xran_tick();
if (xran_process_tx_sym(timer_ctx))
struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)arg;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ unsigned tim_lcore = (p_xran_dev_ctx->fh_init.io_cfg.pkt_proc_core) ? p_xran_dev_ctx->pkt_proc_core_id :
+ p_xran_dev_ctx->fh_init.io_cfg.timing_core;
MLogTask(PID_TTI_TIMER, t1, MLogTick());
/* To match TTbox */
mlogVar[mlogVarCnt++] = 0;
MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
- if(p_xran_dev_ctx->fh_init.io_cfg.id == ID_LLS_CU)
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == ID_O_DU)
next_tti = xran_lib_ota_tti + 1;
else
next_tti = xran_lib_ota_tti;
print_dbg("[%d]SFN %d sf %d slot %d\n",next_tti, frame_id, subframe_id, slot_id);
- if(p_xran_dev_ctx->fh_init.io_cfg.id == ID_LLS_CU){
+ if(p_xran_dev_ctx->fh_init.io_cfg.id == ID_O_DU){
pTCtx[(xran_lib_ota_tti & 1)].tti_to_process = next_tti;
} else {
pTCtx[(xran_lib_ota_tti & 1)].tti_to_process = pTCtx[(xran_lib_ota_tti & 1)^1].tti_to_process;
}
p_xran_dev_ctx->phy_tti_cb_done = 0;
- xran_timer_arm_ex(&tti_to_phy_timer[xran_lib_ota_tti % 10], tti_to_phy_cb, (void*)pTCtx, p_xran_dev_ctx->fh_init.io_cfg.timing_core);
+ xran_timer_arm_ex(&tti_to_phy_timer[xran_lib_ota_tti % 10], tti_to_phy_cb, (void*)pTCtx, tim_lcore);
//slot index is increased to next slot at the beginning of current OTA slot
xran_lib_ota_tti++;
MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick());
}
+void xran_timer_arm_for_deadline(struct rte_timer *tim, void* arg)
+{
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ uint64_t t3 = MLogTick();
+ static int timer_cnt = 0;
+ unsigned tim_lcore = (p_xran_dev_ctx->fh_init.io_cfg.pkt_proc_core) ? p_xran_dev_ctx->pkt_proc_core_id :
+ p_xran_dev_ctx->fh_init.io_cfg.timing_core;
+
+ int32_t rx_tti;
+ int32_t cc_id;
+ uint32_t nFrameIdx;
+ uint32_t nSubframeIdx;
+ uint32_t nSlotIdx;
+ uint64_t nSecond;
+
+
+ xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME
+ + nSubframeIdx*SLOTNUM_PER_SUBFRAME
+ + nSlotIdx;
+
+ cb_timer_ctx[timer_cnt].tti_to_process = rx_tti;
+
+ if (xran_if_current_state == XRAN_RUNNING){
+ rte_timer_cb_t fct = (rte_timer_cb_t)arg;
+ rte_timer_init(tim);
+ rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, &cb_timer_ctx[timer_cnt++]);
+ if (timer_cnt >= 10*MAX_NUM_OF_XRAN_CTX)
+ timer_cnt = 0;
+ }
+
+ MLogTask(PID_TIME_ARM_TIMER_DEADLINE, t3, MLogTick());
+}
+
+
void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore)
{
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick());
}
+uint16_t xran_map_ecpriRtcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id)
+{
+ return XRAN_CP_VF;
+}
+
+uint16_t xran_map_ecpriPcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id)
+{
+ return XRAN_UP_VF;
+}
+
int xran_cp_create_and_send_section(void *pHandle, uint8_t ru_port_id, int dir, int tti, int cc_id,
struct xran_prb_map *prbMap, enum xran_category category, uint8_t ctx_id)
{
- struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx();
+ struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx();
+ struct xran_common_counters *pCnt = &p_x_ctx->fh_counters;
struct xran_cp_gen_params params;
struct xran_section_gen_info sect_geninfo[1];
struct rte_mbuf *mbuf;
int ret = 0;
- uint32_t i, j, loc_sym;
+
+ uint32_t i, loc_sym;
uint32_t nsection = 0;
struct xran_prb_elm *pPrbMapElem = NULL;
struct xran_prb_elm *pPrbMapElemPrev = NULL;
print_err("prbMap is NULL\n");
return (-1);
}
+
for (i=0; i<nsection; i++)
{
pPrbMapElem = &prbMap->prbMap[i];
sect_geninfo[0].info.startSymId = params.hdr.startSymId; // for database
sect_geninfo[0].info.iqWidth = params.hdr.iqWidth; // for database
sect_geninfo[0].info.compMeth = params.hdr.compMeth; // for database
+
sect_geninfo[0].info.id = i; /*xran_alloc_sectionid(pHandle, dir, cc_id, ru_port_id, slot_id);*/
if(sect_geninfo[0].info.id > 7)
/* no extention sections for category */
sect_geninfo[0].info.ef = 0;
sect_geninfo[0].exDataSize = 0;
+ mbuf = xran_ethdi_mbuf_alloc();
} else if (category == XRAN_CATEGORY_B) {
/*add extantion section for BF Weights if update is needed */
if(pPrbMapElem->bf_weight_update){
+ struct rte_mbuf_ext_shared_info * p_share_data = &cp_share_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id];
+
+ if (pPrbMapElem->bf_weight.p_ext_start){
+ /* use buffer with BF Weights for mbuf */
+ mbuf = xran_attach_cp_ext_buf(pPrbMapElem->bf_weight.p_ext_start,
+ pPrbMapElem->bf_weight.p_ext_section, pPrbMapElem->bf_weight.ext_section_sz, p_share_data);
+ } else {
+ print_err("Alloc fail!\n");
+ return (-1);
+ }
+
memset(&m_ext1, 0, sizeof (struct xran_sectionext1_info));
m_ext1.bfwNumber = pPrbMapElem->bf_weight.nAntElmTRx;
m_ext1.bfwiqWidth = pPrbMapElem->iqWidth;
sect_geninfo[0].info.ef = 1;
sect_geninfo[0].exDataSize = 1;
} else {
+ mbuf = xran_ethdi_mbuf_alloc();
sect_geninfo[0].info.ef = 0;
sect_geninfo[0].exDataSize = 0;
}
return (-1);
}
- params.numSections = 1;//nsection;
- params.sections = sect_geninfo;
-
- mbuf = xran_ethdi_mbuf_alloc();
if(unlikely(mbuf == NULL)) {
print_err("Alloc fail!\n");
return (-1);
}
+ params.numSections = 1;//nsection;
+ params.sections = sect_geninfo;
+
ret = xran_prepare_ctrl_pkt(mbuf, ¶ms, cc_id, ru_port_id, seq_id);
if(ret < 0) {
print_err("Fail to build control plane packet - [%d:%d:%d] dir=%d\n",
frame_id, subframe_id, slot_id, dir);
} else {
/* add in the ethernet header */
- struct ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h));
- tx_counter++;
- tx_bytes_counter += rte_pktmbuf_pkt_len(mbuf);
- p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI);
+ struct rte_ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h));
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(mbuf);
+ p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, xran_map_ecpriRtcid_to_vf(dir, cc_id, ru_port_id));
/*for(i=0; i<nsection; i++)*/
xran_cp_add_section_info(pHandle,
{
long t1 = MLogTick();
int tti, buf_id;
- int i, ret;
uint32_t slot_id, subframe_id, frame_id;
int cc_id;
uint8_t ctx_id;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
xran_status_t status;
/* half of RX for current TTI as measured against current OTA time */
- int32_t rx_tti = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT);
+ int32_t rx_tti;
int32_t cc_id;
uint32_t nFrameIdx;
uint32_t nSubframeIdx;
uint32_t nSlotIdx;
uint64_t nSecond;
- uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ /*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME
+ nSubframeIdx*SLOTNUM_PER_SUBFRAME
- + nSlotIdx;
+ + nSlotIdx;*/
+
+ struct xran_timer_ctx* p_timer_ctx = (struct xran_timer_ctx*)arg;
+ rx_tti = p_timer_ctx->tti_to_process;
if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
return;
for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) {
if(p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] == 0){
struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id];
+ pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
pTag->symbol = 0; /* last 7 sym means full slot of Symb */
status = XRAN_STATUS_SUCCESS;
uint32_t nSlotIdx;
uint64_t nSecond;
- uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
+ xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME
+ nSubframeIdx*SLOTNUM_PER_SUBFRAME
+ nSlotIdx;
/* U-Plane */
for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) {
struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id];
+ pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
pTag->symbol = 7; /* last 7 sym means full slot of Symb */
status = XRAN_STATUS_SUCCESS;
if(p_xran_dev_ctx->pPrachCallback[cc_id]){
struct xran_cb_tag *pTag = p_xran_dev_ctx->pPrachCallbackTag[cc_id];
+ pTag->cellId = cc_id;
pTag->slotiId = rx_tti;
pTag->symbol = 7; /* last 7 sym means full slot of Symb */
p_xran_dev_ctx->pPrachCallback[cc_id](p_xran_dev_ctx->pPrachCallbackTag[cc_id], status);
}
+
+ if(p_xran_dev_ctx->pSrsCallback[cc_id]){
+ struct xran_cb_tag *pTag = p_xran_dev_ctx->pSrsCallbackTag[cc_id];
+ pTag->cellId = cc_id;
+ pTag->slotiId = rx_tti;
+ pTag->symbol = 7; /* last 7 sym means full slot of Symb */
+ p_xran_dev_ctx->pSrsCallback[cc_id](p_xran_dev_ctx->pSrsCallbackTag[cc_id], status);
+ }
}
MLogTask(PID_UP_UL_FULL_DEAD_LINE_CB, t1, MLogTick());
{
long t1 = MLogTick();
int tti, buf_id;
- int i, ret;
+ int ret;
uint32_t slot_id, subframe_id, frame_id;
int32_t cc_id;
int ant_id, prach_port_id;
/* start new section information list */
xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, ant_id, ctx_id);
num_list = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_UL, tti, cc_id,
- (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData,
+ (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData,
p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id);
} /* if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_UL) == 1 */
} /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */
xran_core_used = rte_lcore_id();
printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid());
+ memset(&sched_param, 0, sizeof(struct sched_param));
+
/* set main thread affinity mask to CPU2 */
- sched_param.sched_priority = 98;
+ sched_param.sched_priority = XRAN_THREAD_DEFAULT_PRIO;
CPU_ZERO(&cpuset);
CPU_SET(p_xran_dev_ctx->fh_init.io_cfg.timing_core, &cpuset);
{
printf("pthread_setaffinity_np failed: coreId = 2, result1 = %d\n",result1);
}
- if ((result1 = pthread_setschedparam(pthread_self(), 1, &sched_param)))
+ if ((result1 = pthread_setschedparam(pthread_self(), SCHED_FIFO, &sched_param)))
{
printf("priority is not changed: coreId = 2, result1 = %d\n",result1);
}
}
/* Full slot UL OTA + delay_up_ul */
- cb_elm = xran_create_cb(xran_timer_arm, rx_ul_deadline_full_cb);
+ cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_full_cb);
if(cb_elm){
LIST_INSERT_HEAD(&p_xran_dev_ctx->sym_cb_list_head[0][sym_up_ul],
cb_elm,
}
/* Half slot UL OTA + delay_up_ul*/
- cb_elm = xran_create_cb(xran_timer_arm, rx_ul_deadline_half_cb);
+ cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_half_cb);
if(cb_elm){
LIST_INSERT_HEAD(&p_xran_dev_ctx->sym_cb_list_head[0][sym_up_ul + N_SYM_PER_SLOT/2],
cb_elm,
}
}
- printf("Closing timing source thread...tx counter %lu, rx counter %lu\n", tx_counter, rx_counter);
+ printf("Closing timing source thread...\n");
return res;
}
return MBUF_FREE;
}
- rx_bytes_counter += rte_pktmbuf_pkt_len(pkt);
+ xran_dev_get_ctx()->fh_counters.rx_bytes_counter += rte_pktmbuf_pkt_len(pkt);
switch(ecpri_hdr->cmnhdr.ecpri_mesg_type) {
case ECPRI_IQ_DATA:
// t1 = MLogTick();
t1 = MLogTick();
if(xran_dev_get_ctx()->fh_init.io_cfg.id == O_RU) {
ret = process_cplane(pkt);
+ xran_dev_get_ctx()->fh_counters.rx_counter++;
} else {
print_err("O-DU recevied C-Plane message!");
}
print_err("TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id);
}
-/* if (symb_id == p_xran_dev_ctx->prach_last_symbol[CC_ID] ){
- p_xran_dev_ctx->rx_packet_prach_tracker[tti % XRAN_N_FE_BUF_LEN][CC_ID][symb_id]++;
- if(p_xran_dev_ctx->rx_packet_prach_tracker[tti % XRAN_N_FE_BUF_LEN][CC_ID][symb_id] >= xran_get_num_eAxc(pHandle)){
- if(p_xran_dev_ctx->pPrachCallback[0])
- p_xran_dev_ctx->pPrachCallback[0](p_xran_dev_ctx->pPrachCallbackTag[0], status);
- p_xran_dev_ctx->rx_packet_prach_tracker[tti % XRAN_N_FE_BUF_LEN][CC_ID][symb_id] = 0;
- }
- }
-*/
return size;
}
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
uint32_t tti = 0;
xran_status_t status;
- void *pHandle = NULL;
struct rte_mbuf *mb = NULL;
uint16_t iq_sample_size_bits = 16;
print_err("incorrect dev type %d\n", pctx->fh_init.io_cfg.id);
}
- rx_counter++;
+ pCnt->rx_counter++;
pCnt->Rx_on_time++;
pCnt->Total_msgs_rcvd++;
pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]);
}
} else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){
- if (/*likely (p_xran_dev_ctx->fh_init.mtu >=
- p_xran_dev_ctx->fh_cfg.nULRBs * N_SC_PER_PRB*(iq_sample_size_bits/8)*2)
- && p_xran_dev_ctx->fh_init.io_cfg.id == O_DU*/ 1) {
- if (pRbMap->nPrbElm == 1){
+ if (pRbMap->nPrbElm == 1){
+ if (likely (p_xran_dev_ctx->fh_init.mtu >=
+ p_xran_dev_ctx->fh_cfg.nULRBs * N_SC_PER_PRB*(iq_sample_size_bits/8)*2))
+ {
/* no fragmentation */
mb = p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl;
if(mb){
p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl = mbuf;
*mb_free = MBUF_KEEP;
} else {
+ /* packet can be fragmented copy RBs */
+ rte_memcpy(pos, iq_data_start, size);
+ *mb_free = MBUF_FREE;
+ }
+ } else {
prbMapElm = &pRbMap->prbMap[sect_id];
struct xran_section_desc *p_sec_desc = prbMapElm->p_sec_desc[symb_id];
if(p_sec_desc){
}
*mb_free = MBUF_KEEP;
}
- } else {
- /* packet can be fragmented copy RBs */
- rte_memcpy(pos, iq_data_start, size);
- *mb_free = MBUF_FREE;
- }
}
} else {
print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size);
static inline int
xran_send_burst(struct xran_device_ctx *dev, uint16_t n, uint16_t port)
{
+ struct xran_common_counters * pCnt = NULL;
struct rte_mbuf **m_table;
struct rte_mbuf *m;
int32_t i = 0;
int j;
int32_t ret = 0;
+
+ if(dev)
+ pCnt = &dev->fh_counters;
+ else
+ rte_panic("incorrect dev\n");
+
m_table = (struct rte_mbuf **)dev->tx_mbufs[port].m_table;
for(i = 0; i < n; i++){
rte_mbuf_sanity_check(m_table[i], 0);
/*rte_pktmbuf_dump(stdout, m_table[i], 256);*/
- tx_counter++;
- tx_bytes_counter += rte_pktmbuf_pkt_len(m_table[i]);
- ret += dev->send_upmbuf2ring(m_table[i], ETHER_TYPE_ECPRI);
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(m_table[i]);
+ ret += dev->send_upmbuf2ring(m_table[i], ETHER_TYPE_ECPRI, port);
}
-
if (unlikely(ret < n)) {
print_err("ret < n\n");
}
int32_t do_srs)
{
int32_t retval = 0;
- uint64_t t1 = MLogTick();
void *pHandle = NULL;
char *pos = NULL;
char *p_sec_iq = NULL;
- char *p_sect_iq = NULL;
+ //char *p_sect_iq = NULL;
void *mb = NULL;
+ void *send_mb = NULL;
int prb_num = 0;
uint16_t iq_sample_size_bits = 16; // TODO: make dynamic per
uint8_t num_ant_elm = 0;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters;
struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
num_ant_elm = xran_get_num_ant_elm(pHandle);
struct rte_mbuf *tmp = NULL;
rte_iova_t ext_buff_iova = 0;
- struct rte_mbuf_ext_shared_info * p_share_data = &share_data[tti % XRAN_N_FE_BUF_LEN];
+ struct rte_mbuf_ext_shared_info * p_share_data = &share_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id];
if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
direction = XRAN_DIR_DL; /* O-DU */
if(xran_fs_get_symbol_type(cc_id, tti, sym_id) == ((p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)? XRAN_SYMBOL_TYPE_DL : XRAN_SYMBOL_TYPE_UL)
|| xran_fs_get_symbol_type(cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD){
- if(iq_sample_size_bits != 16)
- print_err("Incorrect iqWidth %d\n", iq_sample_size_bits );
-
pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
mb = (void*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
prb_map = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers->pData;
p_sec_desc = prb_map_elm->p_sec_desc[sym_id];
- if(p_sec_desc == NULL){
- rte_panic("p_sec_desc == NULL\n");
- }
-
#if 1
p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset);
rte_pktmbuf_reset_headroom(eth_oran_hdr);
- tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct ether_hdr));
+ tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct rte_ether_hdr));
if (unlikely (( tmp) == NULL)) {
rte_panic("Failed rte_pktmbuf_prepend \n");
}
- mb = eth_oran_hdr;
+ send_mb = eth_oran_hdr;
+
+
+ uint8_t seq_id = (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ?
+ xran_get_updl_seqid(pHandle, cc_id, ant_id) :
+ xran_get_upul_seqid(pHandle, cc_id, ant_id);
+
+
/* first all PRBs */
- prepare_symbol_ex(direction, sec_id,
- mb,
+ int32_t num_bytes = prepare_symbol_ex(direction, sec_id,
+ send_mb,
(struct rb_map *)p_sec_iq,
prb_map_elm->compMethod,
prb_map_elm->iqWidth,
frame_id, subframe_id, slot_id, sym_id,
prb_map_elm->nRBStart, prb_map_elm->nRBSize,
cc_id, ant_id,
- (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ?
- xran_get_updl_seqid(pHandle, cc_id, ant_id) :
- xran_get_upul_seqid(pHandle, cc_id, ant_id),
+ seq_id,
0);
- rte_mbuf_sanity_check((struct rte_mbuf *)mb, 0);
- tx_counter++;
- tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)mb);
- p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)mb, ETHER_TYPE_ECPRI);
+ rte_mbuf_sanity_check((struct rte_mbuf *)send_mb, 0);
+ pCnt->tx_counter++;
+ pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)send_mb);
+ p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)send_mb, ETHER_TYPE_ECPRI, xran_map_ecpriPcid_to_vf(direction, cc_id, ant_id));
#else
p_sect_iq = pos + p_sec_desc->iq_buffer_offset;
prb_num = prb_map_elm->nRBSize;
mb = (void*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_elm_id].sBufferList.pBuffers[sym_id].pCtrl;
if( prb_num > 136 || prb_num == 0) {
- uint16_t sec_id = xran_alloc_sectionid(pHandle, direction, cc_id, ant_id, slot_id);
+ uint16_t sec_id = xran_alloc_sectionid(pHandle, direction, cc_id, ant_elm_id, slot_id);
/* first 136 PRBs */
send_symbol_ex(direction,
sec_id,
return retval;
}
+struct rte_mbuf *
+xran_attach_cp_ext_buf(int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len,
+ struct rte_mbuf_ext_shared_info * p_share_data)
+{
+ struct rte_mbuf *mb_oran_hdr_ext = NULL;
+ struct rte_mbuf *tmp = NULL;
+ int8_t *ext_buff = NULL;
+ rte_iova_t ext_buff_iova = 0;
+
+ ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header) +
+ sizeof(struct xran_cp_radioapp_section1));
+
+ ext_buff_len += (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header) +
+ sizeof(struct xran_cp_radioapp_section1)) + 18;
+
+ mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_small);
+
+ if (unlikely (( mb_oran_hdr_ext) == NULL)) {
+ rte_panic("Failed rte_pktmbuf_alloc\n");
+ }
+
+ p_share_data->free_cb = extbuf_free_callback;
+ p_share_data->fcb_opaque = NULL;
+ rte_mbuf_ext_refcnt_set(p_share_data, 1);
+
+ ext_buff_iova = rte_malloc_virt2iova(p_ext_buff_start);
+ if (unlikely (( ext_buff_iova) == 0)) {
+ rte_panic("Failed rte_mem_virt2iova \n");
+ }
+
+ if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) {
+ rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
+ }
+
+ rte_pktmbuf_attach_extbuf(mb_oran_hdr_ext,
+ ext_buff,
+ ext_buff_iova + RTE_PTR_DIFF(ext_buff , p_ext_buff_start),
+ ext_buff_len,
+ p_share_data);
+
+ rte_pktmbuf_reset_headroom(mb_oran_hdr_ext);
+
+ return mb_oran_hdr_ext;
+}
+
+
+struct rte_mbuf *
+xran_attach_up_ext_buf(int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len,
+ struct rte_mbuf_ext_shared_info * p_share_data,
+ enum xran_compression_method compMeth)
+{
+ struct rte_mbuf *mb_oran_hdr_ext = NULL;
+ struct rte_mbuf *tmp = NULL;
+ int8_t *ext_buff = NULL;
+ rte_iova_t ext_buff_iova = 0;
+
+ ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct radio_app_common_hdr) +
+ sizeof(struct data_section_hdr));
+
+ ext_buff_len += RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct radio_app_common_hdr) +
+ sizeof(struct data_section_hdr) + 18;
+
+ if(compMeth != XRAN_COMPMETHOD_NONE) {
+ ext_buff -= sizeof (struct data_section_compression_hdr);
+ ext_buff_len += sizeof (struct data_section_compression_hdr);
+ }
+
+ mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_small);
+
+ if (unlikely (( mb_oran_hdr_ext) == NULL)) {
+ rte_panic("Failed rte_pktmbuf_alloc\n");
+ }
+
+ p_share_data->free_cb = extbuf_free_callback;
+ p_share_data->fcb_opaque = NULL;
+ rte_mbuf_ext_refcnt_set(p_share_data, 1);
+
+ ext_buff_iova = rte_mempool_virt2iova(p_ext_buff_start);
+ if (unlikely (( ext_buff_iova) == 0)) {
+ rte_panic("Failed rte_mem_virt2iova \n");
+ }
+
+ if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) {
+ rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
+ }
+
+ rte_pktmbuf_attach_extbuf(mb_oran_hdr_ext,
+ ext_buff,
+ ext_buff_iova + RTE_PTR_DIFF(ext_buff , p_ext_buff_start),
+ ext_buff_len,
+ p_share_data);
+
+ rte_pktmbuf_reset_headroom(mb_oran_hdr_ext);
+
+ tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(mb_oran_hdr_ext, sizeof(struct rte_ether_hdr));
+ if (unlikely (( tmp) == NULL)) {
+ rte_panic("Failed rte_pktmbuf_prepend \n");
+ }
+
+ return mb_oran_hdr_ext;
+}
int32_t xran_process_tx_sym_cp_on(uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id,
uint32_t slot_id, uint32_t sym_id)
{
int32_t retval = 0;
- uint64_t t1 = MLogTick();
struct rte_mbuf *eth_oran_hdr = NULL;
char *ext_buff = NULL;
struct xran_section_info *sectinfo = NULL;
struct xran_device_ctx *p_xran_dev_ctx = xran_dev_get_ctx();
-
- struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig);
- struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg);
enum xran_pkt_dir direction;
- struct rte_mbuf_ext_shared_info * p_share_data = &share_data[tti % XRAN_N_FE_BUF_LEN];
+ struct rte_mbuf_ext_shared_info * p_share_data = &share_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id];
if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) {
direction = XRAN_DIR_DL; /* O-DU */
pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
mb = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl;
-#if 1
- p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset);
-
- /* calculete offset for external buffer */
+ p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset);
ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len;
- ext_buff = p_sec_iq - (RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
- sizeof (struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr));
-
- ext_buff_len += RTE_PKTMBUF_HEADROOM +
- sizeof (struct xran_ecpri_hdr) +
- sizeof (struct radio_app_common_hdr) +
- sizeof(struct data_section_hdr) + 18;
- if(sectinfo->compMeth != XRAN_COMPMETHOD_NONE){
- ext_buff -= sizeof (struct data_section_compression_hdr);
- ext_buff_len += sizeof (struct data_section_compression_hdr);
- }
-
- eth_oran_hdr = rte_pktmbuf_alloc(_eth_mbuf_pool_small);
-
- if (unlikely (( eth_oran_hdr) == NULL)) {
- rte_panic("Failed rte_pktmbuf_alloc\n");
- }
-
- p_share_data->free_cb = extbuf_free_callback;
- p_share_data->fcb_opaque = NULL;
- rte_mbuf_ext_refcnt_set(p_share_data, 1);
-
- ext_buff_iova = rte_mempool_virt2iova(mb);
- if (unlikely (( ext_buff_iova) == 0)) {
- rte_panic("Failed rte_mem_virt2iova \n");
- }
-
- if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) {
- rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n");
- }
-
- rte_pktmbuf_attach_extbuf(eth_oran_hdr,
- ext_buff,
- ext_buff_iova + RTE_PTR_DIFF(ext_buff , mb),
- ext_buff_len,
- p_share_data);
-
- rte_pktmbuf_reset_headroom(eth_oran_hdr);
-
- tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct ether_hdr));
- if (unlikely (( tmp) == NULL)) {
- rte_panic("Failed rte_pktmbuf_prepend \n");
- }
- mb = eth_oran_hdr;
-#else
- rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */
-#endif
+ mb = xran_attach_up_ext_buf((int8_t *)mb, (int8_t *) p_sec_iq,
+ (uint16_t) ext_buff_len,
+ p_share_data, (enum xran_compression_method) sectinfo->compMeth);
/* first all PRBs */
prepare_symbol_ex(direction, sectinfo->id,
mb,
for (i = len; i < len + len2; i ++) {
struct rte_mbuf *m;
m = p_xran_dev_ctx->tx_mbufs[0].m_table[i];
- struct ether_hdr *eth_hdr = (struct ether_hdr *)
- rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct ether_hdr));
+ struct rte_ether_hdr *eth_hdr = (struct rte_ether_hdr *)
+ rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr));
if (eth_hdr == NULL) {
rte_panic("No headroom in mbuf.\n");
}
}
/* Transmit packets */
- xran_send_burst(p_xran_dev_ctx, (uint16_t)len, 0);
+ xran_send_burst(p_xran_dev_ctx, (uint16_t)len, xran_map_ecpriPcid_to_vf(direction, cc_id, ant_id));
p_xran_dev_ctx->tx_mbufs[0].len = 0;
retval = 1;
} /* while(section) */
int32_t cc_id = 0;
uint8_t num_eAxc = 0;
uint8_t num_CCPorts = 0;
- uint8_t num_ant_elm = 0;
uint32_t frame_id = 0;
uint32_t subframe_id = 0;
uint32_t slot_id = 0;
uint32_t sym_idx = 0;
uint8_t ctx_id;
- enum xran_pkt_dir direction;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ enum xran_in_period inPeriod;
if(p_xran_dev_ctx->xran2phy_mem_ready == 0)
return 0;
/* O-RU: send symb after OTA time with delay (UL) */
/* O-DU: send symb in advance of OTA time (DL) */
- sym_idx = XranOffsetSym(p_xran_dev_ctx->sym_up, xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT*SLOTNUM_PER_SUBFRAME*1000);
+ sym_idx = XranOffsetSym(p_xran_dev_ctx->sym_up, xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT*SLOTNUM_PER_SUBFRAME*1000, &inPeriod);
tti = XranGetTtiNum(sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT);
slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME);
subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME);
- frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME);
+
+ uint16_t sfnSecStart = xran_getSfnSecStart();
+ if (unlikely(inPeriod == XRAN_IN_NEXT_PERIOD))
+ {
+ // For DU
+ sfnSecStart = (sfnSecStart + NUM_OF_FRAMES_PER_SECOND) & 0x3ff;
+ }
+ else if (unlikely(inPeriod == XRAN_IN_PREV_PERIOD))
+ {
+ // For RU
+ if (sfnSecStart >= NUM_OF_FRAMES_PER_SECOND)
+ {
+ sfnSecStart -= NUM_OF_FRAMES_PER_SECOND;
+ }
+ else
+ {
+ sfnSecStart += NUM_OF_FRAMES_PER_SFN_PERIOD - NUM_OF_FRAMES_PER_SECOND;
+ }
+ }
+ frame_id = XranGetFrameNum(tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME);
// ORAN frameId, 8 bits, [0, 255]
frame_id = (frame_id & 0xff);
int res = 0;
printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid());
+ memset(&sched_param, 0, sizeof(struct sched_param));
sched_param.sched_priority = XRAN_THREAD_DEFAULT_PRIO;
- if ((res = pthread_setschedparam(pthread_self(), 1, &sched_param)))
+ if ((res = pthread_setschedparam(pthread_self(), SCHED_FIFO, &sched_param)))
{
printf("priority is not changed: coreId = %d, result1 = %d\n",rte_lcore_id(), res);
}
int32_t i;
int32_t j;
- struct xran_io_loop_cfg *p_io_cfg = (struct xran_io_loop_cfg *)&p_xran_fh_init->io_cfg;
+ struct xran_io_cfg *p_io_cfg = (struct xran_io_cfg *)&p_xran_fh_init->io_cfg;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
- cpu_set_t system_cpuset;
- pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t), &system_cpuset);
- for (j = 0; j < CPU_SETSIZE; j++)
- if (CPU_ISSET(j, &system_cpuset))
- break;
-
- int32_t lcore_id = j;
-
+ int32_t lcore_id = 0;
char filename[64];
int64_t offset_sec, offset_nsec;
xran_ethdi_init_dpdk_io(p_xran_fh_init->filePrefix,
p_io_cfg,
&lcore_id,
- (struct ether_addr *)p_xran_fh_init->p_o_du_addr,
- (struct ether_addr *)p_xran_fh_init->p_o_ru_addr,
- p_xran_fh_init->cp_vlan_tag,
- p_xran_fh_init->up_vlan_tag);
+ (struct rte_ether_addr *)p_xran_fh_init->p_o_du_addr,
+ (struct rte_ether_addr *)p_xran_fh_init->p_o_ru_addr);
else
xran_ethdi_init_dpdk_io(p_xran_fh_init->filePrefix,
p_io_cfg,
&lcore_id,
- (struct ether_addr *)p_xran_fh_init->p_o_ru_addr,
- (struct ether_addr *)p_xran_fh_init->p_o_du_addr,
- p_xran_fh_init->cp_vlan_tag,
- p_xran_fh_init->up_vlan_tag);
+ (struct rte_ether_addr *)p_xran_fh_init->p_o_ru_addr,
+ (struct rte_ether_addr *)p_xran_fh_init->p_o_du_addr);
for(i = 0; i < 10; i++ )
rte_timer_init(&tti_to_phy_timer[i]);
}
}
- printf("Set debug stop %d, debug stop count %d\n", p_xran_fh_init->debugStop, p_xran_fh_init->debugStopCount);
- timing_set_debug_stop(p_xran_fh_init->debugStop, p_xran_fh_init->debugStopCount);
for (uint32_t nCellIdx = 0; nCellIdx < XRAN_MAX_SECTOR_NR; nCellIdx++){
xran_fs_clear_slot_type(nCellIdx);
snprintf(pool_name, RTE_MEMPOOL_NAMESIZE, "ru_%d_cc_%d_idx_%d",
pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex);
- nAllocBufferSize = nBufferSize + sizeof(struct ether_hdr) +
+ nAllocBufferSize = nBufferSize + sizeof(struct rte_ether_hdr) +
sizeof (struct xran_ecpri_hdr) +
sizeof (struct radio_app_common_hdr) +
sizeof(struct data_section_hdr) + 256;
if(mb){
char * start = rte_pktmbuf_append(mb, pXranCc->bufferPoolElmSz[nPoolIndex]);
- char * ethhdr = rte_pktmbuf_prepend(mb, sizeof(struct ether_hdr));
+ char * ethhdr = rte_pktmbuf_prepend(mb, sizeof(struct rte_ether_hdr));
if(start && ethhdr){
char * iq_offset = rte_pktmbuf_mtod(mb, char * );
/* skip headers */
- iq_offset = iq_offset + sizeof(struct ether_hdr) +
+ iq_offset = iq_offset + sizeof(struct rte_ether_hdr) +
sizeof (struct xran_ecpri_hdr) +
sizeof (struct radio_app_common_hdr) +
sizeof(struct data_section_hdr);
void *pCallbackTag)
{
XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle;
- xran_status_t nStatus = XRAN_STATUS_SUCCESS;
int j, i = 0, z, k;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
- print_dbg("%s\n", __FUNCTION__);
+ print_dbg("%s\n",__FUNCTION__);
if(NULL == pHandle)
{
p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFrontHaulTxBuffers[j][i][z][0];
- p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList = *pSrcBuffer[z][j];
+ if(pSrcBuffer[z][j])
+ p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList = *pSrcBuffer[z][j];
/* C-plane TX */
p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFrontHaulTxPrbMapBuffers[j][i][z][0];
- p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pSrcCpBuffer[z][j];
+ if(pSrcCpBuffer[z][j])
+ p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pSrcCpBuffer[z][j];
/* U-plane RX */
p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFrontHaulRxBuffers[j][i][z][0];
- p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
+ if(pDstBuffer[z][j])
+ p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
/* C-plane RX */
p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFrontHaulRxPrbMapBuffers[j][i][z][0];
- p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pDstCpBuffer[z][j];
+ if(pDstCpBuffer[z][j])
+ p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pDstCpBuffer[z][j];
}
}
p_xran_dev_ctx->xran2phy_mem_ready = 1;
- return nStatus;
+ return XRAN_STATUS_SUCCESS;
}
int32_t xran_5g_prach_req (void * pHandle,
void *pCallbackTag)
{
XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle;
- xran_status_t nStatus = XRAN_STATUS_SUCCESS;
int j, i = 0, z;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR; // ant number.
p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHPrachRxBuffers[j][i][z][0];
- p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
+ if(pDstBuffer[z][j])
+ p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
}
}
p_xran_dev_ctx->pPrachCallback[i] = pCallback;
p_xran_dev_ctx->pPrachCallbackTag[i] = pCallbackTag;
- return 0;
+ return XRAN_STATUS_SUCCESS;
}
void *pCallbackTag)
{
XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle;
- xran_status_t nStatus = XRAN_STATUS_SUCCESS;
int j, i = 0, z;
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANT_ARRAY_ELM_NR; // ant number.
p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHSrsRxBuffers[j][i][z][0];
- p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
+ if(pDstBuffer[z][j])
+ p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j];
}
}
p_xran_dev_ctx->pSrsCallback[i] = pCallback;
p_xran_dev_ctx->pSrsCallbackTag[i] = pCallbackTag;
- return 0;
+ return XRAN_STATUS_SUCCESS;
}
uint32_t xran_get_time_stats(uint64_t *total_time, uint64_t *used_time, uint32_t *core_used, uint32_t clear)
return rte_malloc("External buffer", buf_len, RTE_CACHE_LINE_SIZE);
}
+void xran_free(void *addr)
+{
+ return rte_free(addr);
+}
+
+
+uint8_t *xran_add_cp_hdr_offset(uint8_t *dst)
+{
+ dst += (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_section1_header) +
+ sizeof(struct xran_cp_radioapp_section1));
+
+ dst = RTE_PTR_ALIGN_CEIL(dst, 64);
+
+ return dst;
+}
+
uint8_t *xran_add_hdr_offset(uint8_t *dst, int16_t compMethod)
{
dst+= (RTE_PKTMBUF_HEADROOM +
memcpy(pFhCfg, pConf, sizeof(struct xran_fh_config));
if(pConf->log_level)
- printf(" %s: O-RU Category %s\n", __FUNCTION__, (pFhCfg->ru_conf.xranCat == XRAN_CATEGORY_A) ? "A" : "B");
+ printf(" %s: %s Category %s\n", __FUNCTION__,
+ (pFhCfg->ru_conf.xranTech == XRAN_RAN_5GNR) ? "5G NR" : "LTE",
+ (pFhCfg->ru_conf.xranCat == XRAN_CATEGORY_A) ? "A" : "B");
nNumerology = xran_get_conf_numerology(pHandle);
}
/* setup PRACH configuration for C-Plane */
- xran_init_prach(pConf, p_xran_dev_ctx);
+ if(pConf->ru_conf.xranTech == XRAN_RAN_5GNR)
+ xran_init_prach(pConf, p_xran_dev_ctx);
+ else if (pConf->ru_conf.xranTech == XRAN_RAN_LTE)
+ xran_init_prach_lte(pConf, p_xran_dev_ctx);
+
xran_init_srs(pConf, p_xran_dev_ctx);
xran_cp_init_sectiondb(pHandle);
/* Start packet processing thread */
if((uint16_t)xran_ethdi_get_ctx()->io_cfg.port[XRAN_UP_VF] != 0xFFFF &&
(uint16_t)xran_ethdi_get_ctx()->io_cfg.port[XRAN_CP_VF] != 0xFFFF ){
- if(pConf->log_level){
- print_dbg("XRAN_UP_VF: 0x%04x\n", xran_ethdi_get_ctx()->io_cfg.port[XRAN_UP_VF]);
- print_dbg("XRAN_CP_VF: 0x%04x\n", xran_ethdi_get_ctx()->io_cfg.port[XRAN_CP_VF]);
+ if(/*pConf->log_level*/1){
+ printf("XRAN_UP_VF: 0x%04x\n", xran_ethdi_get_ctx()->io_cfg.port[XRAN_UP_VF]);
+ printf("XRAN_CP_VF: 0x%04x\n", xran_ethdi_get_ctx()->io_cfg.port[XRAN_CP_VF]);
}
+
+
if (rte_eal_remote_launch(xran_timing_source_thread, xran_dev_get_ctx(), xran_ethdi_get_ctx()->io_cfg.timing_core))
rte_panic("thread_run() failed to start\n");
+
+ /* Start packet processing thread */
+ if(xran_ethdi_get_ctx()->io_cfg.pkt_proc_core){
+ /* start pkt workers */
+ uint64_t nWorkerCore = 1LL;
+ uint32_t coreNum = sysconf(_SC_NPROCESSORS_CONF);
+ for (i = 0; i < coreNum; i++) {
+ if (nWorkerCore & (uint64_t)xran_ethdi_get_ctx()->io_cfg.pkt_proc_core) {
+ if (rte_eal_remote_launch(ring_processing_thread, NULL, i))
+ rte_panic("ring_processing_thread() failed to start\n");
+ xran_ethdi_get_ctx()->pkt_wrk_cfg[i].f = ring_processing_thread;
+ xran_ethdi_get_ctx()->pkt_wrk_cfg[i].arg = NULL;
+ xran_ethdi_get_ctx()->pkt_wrk_cfg[i].state = 1;
+ if(p_xran_dev_ctx->pkt_proc_core_id == 0)
+ p_xran_dev_ctx->pkt_proc_core_id = i;
+ }
+ nWorkerCore = nWorkerCore << 1;
+ }
+ }
} else if(pConf->log_level){
printf("Eth port was not open. Processing thread was not started\n");
}
int32_t xran_start(void *pHandle)
{
+ struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
if(xran_get_if_state() == XRAN_RUNNING) {
print_err("Already STARTED!!");
return (-1);
}
+ if(p_xran_dev_ctx->fh_init.debugStop){
+ printf("Set debug stop %d, debug stop count %d\n", p_xran_dev_ctx->fh_init.debugStop, p_xran_dev_ctx->fh_init.debugStopCount);
+ timing_set_debug_stop(p_xran_dev_ctx->fh_init.debugStop, p_xran_dev_ctx->fh_init.debugStopCount);
+ }
+
xran_if_current_state = XRAN_RUNNING;
return 0;
}
long pid = atol(entry->d_name);
if (0 == pid)
continue;
- snprintf(full_path, sizeof(full_path), "%s/%ld/%s", PROC_DIR, pid, COMM_FILE);
+ sprintf(full_path, "%s/%ld/%s", PROC_DIR, pid, COMM_FILE);
FILE *proc_name_file = fopen(full_path, "r");
if (NULL == proc_name_file)
continue;
static struct timespec* p_temp_time;
+static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */
+
static unsigned long current_second = 0;
static unsigned long started_second = 0;
static uint8_t numerlogy = 0;
{
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
- long nsec = p_time->tv_nsec + p_xran_dev_ctx->offset_nsec;
- p_time->tv_sec += p_xran_dev_ctx->offset_sec;
- if (nsec >= 1e9)
+ if (p_time->tv_nsec >= p_xran_dev_ctx->offset_nsec)
+ {
+ p_time->tv_nsec -= p_xran_dev_ctx->offset_nsec;
+ p_time->tv_sec -= p_xran_dev_ctx->offset_sec;
+ }
+ else
{
- nsec -=1e9;
- p_time->tv_sec += 1;
+ p_time->tv_nsec += 1e9 - p_xran_dev_ctx->offset_nsec;
+ p_time->tv_sec -= p_xran_dev_ctx->offset_sec + 1;
}
- p_time->tv_nsec = nsec;
return;
}
long poll_next_tick(long interval_ns, unsigned long *used_tick)
{
struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
+ struct xran_common_counters* pCnt = &p_xran_dev_ctx->fh_counters;
+
long target_time;
long delta;
static int counter = 0;
timing_adjust_gps_second(p_cur_time);
delta = (p_cur_time->tv_sec * NSEC_PER_SEC + p_cur_time->tv_nsec) - target_time;
if(delta > 0 || (delta < 0 && abs(delta) < THRESHOLD)) {
- if (debugStop &&(debugStopCount > 0) && (tx_counter >= debugStopCount)){
+ if (debugStop &&(debugStopCount > 0) && (pCnt->tx_counter >= debugStopCount)){
uint64_t t1;
- printf("STOP:[%ld.%09ld], debugStopCount %d, tx_counter %ld\n", p_cur_time->tv_sec, p_cur_time->tv_nsec, debugStopCount, tx_counter);
+ printf("STOP:[%ld.%09ld], debugStopCount %d, tx_counter %ld\n", p_cur_time->tv_sec, p_cur_time->tv_nsec, debugStopCount, pCnt->tx_counter);
t1 = MLogTick();
rte_pause();
MLogTask(PID_TIME_SYSTIME_STOP, t1, MLogTick());
uint64_t t1, t2;
t1 = xran_tick();
- ring_processing_func();
+ if(p_xran_dev_ctx->fh_init.io_cfg.pkt_proc_core == 0)
+ ring_processing_func();
+
process_dpdk_io();
+ /* work around for some kernel */
+ if(p_xran_dev_ctx->fh_init.io_cfg.io_sleep)
+ nanosleep(&sleeptime,NULL);
+
t2 = xran_tick();
*used_tick += get_ticks_diff(t2, t1);
}
+
}
}
#include "xran_up_api.h"
#include "xran_printf.h"
#include "xran_mlog_lnx.h"
+#include "xran_common.h"
extern uint32_t xran_lib_ota_tti;
uint8_t comp_meth)
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
- struct xran_ecpri_hdr *ecpri_hdr = (struct xran_ecpri_hdr *)(pChar + sizeof(struct ether_hdr));
+ struct xran_ecpri_hdr *ecpri_hdr = (struct xran_ecpri_hdr *)(pChar + sizeof(struct rte_ether_hdr));
uint16_t ecpri_payl_size = payl_size
+ sizeof(struct data_section_hdr)
+ sizeof(struct radio_app_common_hdr)
const struct radio_app_common_hdr *app_hdr_input)
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
- struct radio_app_common_hdr *app_hdr = (struct radio_app_common_hdr *)(pChar + sizeof(struct ether_hdr)
+ struct radio_app_common_hdr *app_hdr = (struct radio_app_common_hdr *)(pChar + sizeof(struct rte_ether_hdr)
+ sizeof (struct xran_ecpri_hdr));
if (NULL == app_hdr)
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
struct data_section_hdr *section_hdr = (struct data_section_hdr *)
- (pChar + sizeof(struct ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr));
+ (pChar + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr));
if (NULL == section_hdr)
return 1;
uint32_t do_copy)
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
- void *iq_sam_buf = (pChar + sizeof(struct ether_hdr) + sizeof (struct xran_ecpri_hdr)
+ void *iq_sam_buf = (pChar + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr)
+ sizeof(struct radio_app_common_hdr)
+ sizeof(struct data_section_hdr));
}
}
-#if 0
- /* do not expect to do copy anymore */
else if(iq_buf_byte_order == XRAN_NE_BE_BYTE_ORDER){
if(do_copy) {
rte_memcpy(iq_sam_buf, (uint8_t *)iq_data_start, iq_data_num_bytes);
}
}
-#endif
return iq_data_num_bytes;
}
{
char *pChar = rte_pktmbuf_mtod(mbuf, char*);
struct data_section_compression_hdr *compression_hdr = (struct data_section_compression_hdr *)
- (pChar + sizeof(struct ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr)
+ (pChar + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr)
+ sizeof(struct data_section_hdr));
if (NULL == compression_hdr)
*subframe_id = radio_hdr->sf_slot_sym.subframe_id;
if (slot_id)
- *slot_id = radio_hdr->sf_slot_sym.slot_id;
+ *slot_id = xran_slotid_convert(radio_hdr->sf_slot_sym.slot_id, 1);
if (symb_id)
*symb_id = radio_hdr->sf_slot_sym.symb_id;
-/******************************************************************************
-*
-* Copyright (c) 2019 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
+/*******************************************************************************
+ *
+ * <COPYRIGHT_TAG>
+ *
+ *******************************************************************************/
#include <cmath>
#include <fstream>
-/******************************************************************************
-*
-* Copyright (c) 2019 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
+/*******************************************************************************
+ *
+ * <COPYRIGHT_TAG>
+ *
+ *******************************************************************************/
/* This is the new utility file for all tests, all new common functionality has to go here.
When contributing to the common.hpp please focus on readability and maintainability rather than
}
}
+ template <typename T>
+ T get_input_parameter(const std::string &subsection_name, const std::string ¶meter_name)
+ {
+ try
+ {
+ return get_parameter<T>("parameters", subsection_name, parameter_name);
+ }
+ catch (std::domain_error &e)
+ {
+ std::cout << "[----------] get_input_parameter (" << subsection_name << "." << parameter_name
+ << ") failed: " << e.what()
+ << ". Did you mispell the parameter name?" << std::endl;
+ throw;
+ }
+ catch(reading_input_file_exception &e)
+ {
+ std::cout << "[----------] get_input_parameter (" << subsection_name << "." << parameter_name
+ << ") failed: " << e.what() << std::endl;
+ throw;
+ }
+ }
+
+ template <typename T>
+ T get_input_parameter(const std::string &subsection_name, const int index, const std::string ¶meter_name)
+ {
+ try
+ {
+ return get_parameter<T>("parameters", subsection_name, index, parameter_name);
+ }
+ catch (std::domain_error &e)
+ {
+ std::cout << "[----------] get_input_parameter (" << subsection_name << "[" << index << "]." << parameter_name
+ << ") failed: " << e.what()
+ << ". Did you mispell the parameter name?" << std::endl;
+ throw;
+ }
+ catch(reading_input_file_exception &e)
+ {
+ std::cout << "[----------] get_input_parameter (" << subsection_name << "[" << index << "]." << parameter_name
+ << ") failed: " << e.what() << std::endl;
+ throw;
+ }
+ }
+ int get_input_parameter_size(const std::string &subsection_name, const std::string ¶meter_name)
+ {
+ try
+ {
+ auto array_size = conf[test_type][GetParam()]["parameters"][subsection_name][parameter_name].size();
+ return (array_size);
+ }
+ catch (std::domain_error &e)
+ {
+ std::cout << "[----------] get_input_parameter_size (" << subsection_name << "." << parameter_name
+ << ") failed: " << e.what()
+ << ". Did you mispell the parameter name?" << std::endl;
+ return (-1);
+ }
+ catch(reading_input_file_exception &e)
+ {
+ std::cout << "[----------] get_input_parameter_size (" << subsection_name << "." << parameter_name
+ << ") failed: " << e.what() << std::endl;
+ throw;
+ }
+ }
+ int get_input_subsection_size(const std::string &subsection_name)
+ {
+ try
+ {
+ auto array_size = conf[test_type][GetParam()]["parameters"][subsection_name].size();
+ return (array_size);
+ }
+ catch (std::domain_error &e)
+ {
+ std::cout << "[----------] get_input_subsection_size (" << subsection_name
+ << ") failed: " << e.what()
+ << ". Did you mispell the subsection name?" << std::endl;
+ return (-1);
+ }
+ catch(reading_input_file_exception &e)
+ {
+ std::cout << "[----------] get_input_subsection_size (" << subsection_name
+ << ") failed: " << e.what() << std::endl;
+ throw;
+ }
+ }
+
template <typename T>
T get_reference_parameter(const std::string ¶meter_name)
{
return data_reader<T>::read_parameter(GetParam(), type, parameter_name);
}
+ template<typename T>
+ struct data_reader2 {
+ static T read_parameter(const int index, const std::string &type,
+ const std::string &subsection_name,
+ const std::string ¶meter_name)
+ {
+ return conf[test_type][index][type][subsection_name][parameter_name];
+ }
+ };
+
+ template<typename T>
+ struct data_reader2<std::vector<T>> {
+ static std::vector<T> read_parameter(const int index, const std::string &type,
+ const std::string &subsection_name,
+ const std::string ¶meter_name)
+ {
+ auto array_size = conf[test_type][index][type][subsection_name][parameter_name].size();
+
+ std::vector<T> result(array_size);
+
+ for(unsigned number = 0; number < array_size; number++)
+ result.at(number) = conf[test_type][index][type][subsection_name][parameter_name][number];
+
+ return result;
+ }
+ };
+
+ template<typename T>
+ struct data_reader2<T*> {
+ static T* read_parameter(const int index, const std::string &type,
+ const std::string &subsection_name,
+ const std::string ¶meter_name)
+ {
+ return (T*) read_data_to_aligned_array(conf[test_type][index][type][subsection_name][parameter_name]);
+ }
+ };
+ template <typename T>
+ T get_parameter(const std::string &type, const std::string &subsection_name, const std::string ¶meter_name)
+ {
+ return data_reader2<T>::read_parameter(GetParam(), type, subsection_name, parameter_name);
+ }
+
+ template<typename T>
+ struct data_reader3 {
+ static T read_parameter(const int index, const std::string &type,
+ const std::string &subsection_name,
+ const int subindex,
+ const std::string ¶meter_name)
+ {
+ return conf[test_type][index][type][subsection_name][subindex][parameter_name];
+ }
+ };
+
+ template<typename T>
+ struct data_reader3<std::vector<T>> {
+ static std::vector<T> read_parameter(const int index, const std::string &type,
+ const std::string &subsection_name,
+ const int subindex,
+ const std::string ¶meter_name)
+ {
+ auto array_size = conf[test_type][index][type][subsection_name][subindex][parameter_name].size();
+
+ std::vector<T> result(array_size);
+
+ for(unsigned number = 0; number < array_size; number++)
+ result.at(number) = conf[test_type][index][type][subsection_name][subindex][parameter_name][number];
+
+ return result;
+ }
+ };
+
+ template<typename T>
+ struct data_reader3<T*> {
+ static T* read_parameter(const int index, const std::string &type,
+ const std::string &subsection_name,
+ const int subindex,
+ const std::string ¶meter_name)
+ {
+ return (T*) read_data_to_aligned_array(conf[test_type][index][type][subsection_name][subindex][parameter_name]);
+ }
+ };
+ template <typename T>
+ T get_parameter(const std::string &type, const std::string &subsection_name, const int subindex, const std::string ¶meter_name)
+ {
+ return data_reader3<T>::read_parameter(GetParam(), type, subsection_name, subindex, parameter_name);
+ }
+
void print_and_store_results(const std::string &isa,
const std::string ¶meters,
const std::string &module_name,
-/******************************************************************************
+/*******************************************************************************
*
-* Copyright (c) 2019 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
+* <COPYRIGHT_TAG>
*
*******************************************************************************/
-
/*! \file common_typedef_xran.h
\brief This header file defines those data type both used by eNB and UE.
*/
-/******************************************************************************
-*
-* Copyright (c) 2019 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
+/*******************************************************************************
+ *
+ * <COPYRIGHT_TAG>
+ *
+ *******************************************************************************/
#ifndef XRAN_LIB_WRAP_HPP
#define XRAN_LIB_WRAP_HPP
BbuIoBufCtrlStruct m_sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
BbuIoBufCtrlStruct m_sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
+ /* Cat B */
+ BbuIoBufCtrlStruct m_sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
+
/* buffers lists */
struct xran_flat_buffer m_sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
struct xran_flat_buffer m_sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_flat_buffer m_sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
struct xran_flat_buffer m_sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
+ /* Cat B SRS buffers */
+ struct xran_flat_buffer m_sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
+
void *m_nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector
uint32_t m_nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool
uint16_t *u16dptr;
uint8_t *u8dptr;
+ uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul());
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr);
+
std::cout << "XRAN front haul xran_mm_init" << std::endl;
status = xran_mm_init(m_xranhandle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);
eInterfaceType = XRANFTHTX_OUT;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
m_nSW_ToFpga_FTH_TxBufferLen);
if(status != XRAN_STATUS_SUCCESS) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
return (-1);
}
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
+ for(z = 0; z < xran_max_antenna_nr; z++){
m_sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0;
m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
if(XRAN_STATUS_SUCCESS != status) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
return (-1);
eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
sizeof(struct xran_prb_map));
if(status != XRAN_STATUS_SUCCESS) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
return (-1);
}
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
+ for(z = 0; z < xran_max_antenna_nr; z++) {
m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
eInterfaceType = XRANFTHRX_IN;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
m_nSW_ToFpga_FTH_TxBufferLen); /* ????, actual alloc size is m_nFpgaToSW_FTH_RxBUfferLen */
if(status != XRAN_STATUS_SUCCESS) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
}
for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
+ for(z = 0; z < xran_max_antenna_nr; z++) {
m_sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0;
m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
eInterfaceType = XRANFTHTX_SEC_DESC_IN;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
if(XRAN_STATUS_SUCCESS != status) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
return (-1);
eInterfaceType = XRANFTHRX_PRB_MAP_IN;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
sizeof(struct xran_prb_map));
if(status != XRAN_STATUS_SUCCESS) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
}
for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
+ for(z = 0; z < xran_max_antenna_nr; z++) {
m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
eInterfaceType = XRANFTHRACH_IN;
status = xran_bm_init(m_nInstanceHandle[0][i],
&m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
- XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
+ XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT,
FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
if(status != XRAN_STATUS_SUCCESS) {
std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
return (-1);
}
for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
+ for(z = 0; z < xran_max_antenna_nr; z++) {
m_sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
- m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR;
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr;
m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFHPrachRxBuffers[j][i][z][0];
for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {
m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN;
/* DPDK configuration */
m_dpdk_dev_up = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdk_dev_up");
m_dpdk_dev_cp = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdk_dev_cp");
+ m_xranInit.io_cfg.num_vfs = 2;
m_xranInit.io_cfg.dpdk_dev[XRAN_UP_VF] = (m_dpdk_dev_up == "") ? NULL : (char *)&m_dpdk_dev_up;
m_xranInit.io_cfg.dpdk_dev[XRAN_CP_VF] = (m_dpdk_dev_cp == "") ? NULL : (char *)&m_dpdk_dev_cp;
struct xran_prb_map *pRbMap = NULL;
+ uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul());
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr);
+
+
/* Update member variables */
if(pCfg)
memcpy(&m_xranConf, pCfg, sizeof(struct xran_fh_config));
/* Init RB map */
for(cc_id = 0; cc_id <nSectorNum; cc_id++) {
for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) {
- for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++) {
- flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
+ for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) {
+ flowId = xran_max_antenna_nr*cc_id + ant_id;
/* C-plane DL */
pRbMap = (struct xran_prb_map *)m_sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
void Open(xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up,
- void *fh_rx_callback, void *fh_rx_prach_callback)
+ void *fh_rx_callback, void *fh_rx_prach_callback, void *fh_srs_callback)
{
struct xran_fh_config *pXranConf;
int32_t nSectorNum;
int i, j, k, z;
+
+ uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul());
+ uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr);
+
struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
+ struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
#if 0
xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
#endif
nSectorNum = get_num_cc();
+ for(i=0; i<nSectorNum; i++)
+ {
+ for(j=0; j<XRAN_N_FE_BUF_LEN; j++)
+ {
+ for(z = 0; z < xran_max_antenna_nr; z++){
+ pFthTxBuffer[i][z][j] = NULL;
+ pFthTxPrbMapBuffer[i][z][j] = NULL;
+ pFthRxBuffer[i][z][j] = NULL;
+ pFthRxPrbMapBuffer[i][z][j] = NULL;
+ pFthRxRachBuffer[i][z][j] = NULL;
+ }
+ for(z = 0; z < xran_max_ant_array_elm_nr; z++){
+ pFthRxSrsBuffer[i][z][j] = NULL;
+ }
+ }
+ }
+
for(i=0; i<nSectorNum; i++) {
for(j=0; j<XRAN_N_FE_BUF_LEN; j++) {
- for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
+ for(z = 0; z < xran_max_antenna_nr; z++) {
pFthTxBuffer[i][z][j] = &(m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
pFthTxPrbMapBuffer[i][z][j] = &(m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxBuffer[i][z][j] = &(m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxPrbMapBuffer[i][z][j] = &(m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
pFthRxRachBuffer[i][z][j] = &(m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
}
+ for(z = 0; z < xran_max_ant_array_elm_nr && xran_max_ant_array_elm_nr; z++){
+ pFthRxSrsBuffer[i][z][j] = &(m_sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList);
+ }
}
}
xran_5g_prach_req(m_nInstanceHandle[0][i], pFthRxRachBuffer[i],
(void (*)(void *, xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i][0]);
}
+
+ /* add SRS callback here */
+ for (i = 0; i<nSectorNum && xran_max_ant_array_elm_nr; i++) {
+ xran_5g_srs_req(m_nInstanceHandle[0][i], pFthRxSrsBuffer[i],
+ (void (*)(void *, xran_status_t))fh_srs_callback,&pFthRxSrsBuffer[i][0]);
+ }
+
}
+
+
xran_register_cb_mbuf2ring(send_cp, send_up);
xran_open(m_xranhandle, &m_xranConf);
int get_duplextype() { return(m_xranConf.frame_conf.nFrameDuplexType); }
int get_num_cc() { return(m_xranConf.nCC); }
int get_num_eaxc() { return(m_xranConf.neAxc); }
+ int get_num_eaxc_ul() { return(m_xranConf.neAxcUl); }
int get_num_dlrbs() { return(m_xranConf.nDLRBs); }
int get_num_ulrbs() { return(m_xranConf.nULRBs); }
int get_num_antelmtrx() { return(m_xranConf.nAntElmTRx); }
-/******************************************************************************
-*
-* Copyright (c) 2019 Intel.
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-*******************************************************************************/
-
+/*******************************************************************************
+ *
+ * <COPYRIGHT_TAG>
+ *
+ *******************************************************************************/
#include <rte_config.h>
#include <rte_eal.h>
#include <rte_debug.h>
#
#******************************************************************************/
-"""This script run test cases with O-DU and O-RU
+"""This script runs test cases with O-DU and O-RU
"""
import logging
import sys
import shutil
from itertools import dropwhile
from datetime import datetime
+from time import gmtime, strftime
import json
+from threading import Timer
+import socket
+
+timeout_sec = 60*3 #3 min max
+
+nLteNumRbsPerSymF1 = [
+ # 5MHz 10MHz 15MHz 20 MHz
+ [25, 50, 75, 100] # LTE Numerology 0 (15KHz)
+]
nNumRbsPerSymF1 = [
# 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
nRChBwOptions_values_mu2and3 = [0,1,2,3]
nRChBwOptions_mu2and3 = dict(zip(nRChBwOptions_keys_mu2and3, nRChBwOptions_values_mu2and3))
+# values for Jenkins server
+eth_cp_dev = ["0000:19:02.1", "0000:19:0a.1"]
+eth_up_dev = ["0000:19:02.0", "0000:19:0a.0"]
+
# table of all test cases
-# (cat, mu, bw, test case)
-all_test_cases = [(0, 0, 5, 0),
- (0, 0, 10, 0),
- (0, 0, 20, 0),
- (0, 1, 100, 0),
- (0, 3, 100, 0),
- (1, 1, 100, 0)]
+# (ran, cat, mu, bw, test case)
+#Cat A
+NR_test_cases_A = [(0, 0, 0, 5, 0),
+ (0, 0, 0, 10, 0),
+ (0, 0, 0, 10, 12),
+ (0, 0, 0, 20, 0),
+ (0, 0, 0, 20, 12),
+ (0, 0, 1, 100, 0),
+ (0, 0, 3, 100, 0),
+]
+
+LTE_test_cases_A = [(1, 0, 0, 5, 0),
+ (1, 0, 0, 10, 0),
+ (1, 0, 0, 20, 0),
+]
+
#Cat B
-""" all_test_cases = [(1, 1, 100, 0),
- (1, 1, 100, 1),
- (1, 1, 100, 101),
- (1, 1, 100, 102),
- (1, 1, 100, 103),
- (1, 1, 100, 104),
- (1, 1, 100, 105),
- #(1, 1, 100, 106), 25G not enough
- (1, 1, 100, 107),
- (1, 1, 100, 108),
- #(1, 1, 100, 109), 25G not enough
- (1, 1, 100, 201),
- #(1, 1, 100, 202), 25G not enough
- (1, 1, 100, 203),
- (1, 1, 100, 204),
- (1, 1, 100, 205),
- (1, 1, 100, 206),
- (1, 1, 100, 211),
- #(1, 1, 100, 212), 25G not enough
- (1, 1, 100, 213),
- (1, 1, 100, 214),
- (1, 1, 100, 215),
- (1, 1, 100, 216)
+NR_test_cases_B = [(0, 1, 1, 100, 0),
+ (0, 1, 1, 100, 2),
+ (0, 1, 1, 100, 1),
+ (0, 1, 1, 100, 101),
+ (0, 1, 1, 100, 102),
+ (0, 1, 1, 100, 103),
+ (0, 1, 1, 100, 104),
+ (0, 1, 1, 100, 105),
+ #(0, 1, 1, 100, 106), 25G not enough
+ (0, 1, 1, 100, 107),
+ (0, 1, 1, 100, 108),
+ #(0, 1, 1, 100, 109), 25G not enough
+ (0, 1, 1, 100, 201),
+ #(0, 1, 1, 100, 202), 25G not enough
+ #(0, 1, 1, 100, 203),
+ (0, 1, 1, 100, 204),
+ (0, 1, 1, 100, 205),
+ (0, 1, 1, 100, 206),
+ (0, 1, 1, 100, 211),
+ #(0, 1, 1, 100, 212), 25G not enough
+ (0, 1, 1, 100, 213),
+ (0, 1, 1, 100, 214),
+ (0, 1, 1, 100, 215),
+ (0, 1, 1, 100, 216)
+]
+
+LTE_test_cases_B = [(1, 1, 0, 5, 0),
+ (1, 1, 0, 10, 0),
+ (1, 1, 0, 20, 0),
]
- """
-dic_dir = dict({0:'DL', 1:'UL'})
-dic_xu = dict({0:'o-du', 1:'o-ru'})
+
+V_test_cases_B = [
+ # (0, 1, 1, 100, 301), 25G not enough
+ (0, 1, 1, 100, 302),
+ (0, 1, 1, 100, 303),
+ (0, 1, 1, 100, 304),
+ (0, 1, 1, 100, 305),
+ (0, 1, 1, 100, 306)
+]
+
+all_test_cases = NR_test_cases_A + LTE_test_cases_A + LTE_test_cases_B + NR_test_cases_B + V_test_cases_B
+
+dic_dir = dict({0:'DL', 1:'UL'})
+dic_xu = dict({0:'o-du', 1:'o-ru'})
+dic_ran_tech = dict({0:'5g_nr', 1:'lte'})
def init_logger(console_level, logfile_level):
"""Initializes console and logfile logger with given logging levels"""
# Parser configuration
parser = argparse.ArgumentParser(description="Run test cases: category numerology bandwidth test_num")
+ parser.add_argument("--ran", type=int, default=0, help="Radio Access Tehcnology 0 (5G NR) or 1 (LTE)", metavar="ran", dest="rantech")
parser.add_argument("--cat", type=int, default=0, help="Category: 0 (A) or 1 (B)", metavar="cat", dest="category")
parser.add_argument("--mu", type=int, default=0, help="numerology [0,1,3]", metavar="num", dest="numerology")
parser.add_argument("--bw", type=int, default=20, help="bandwidth [5,10,20,100]", metavar="bw", dest="bandwidth")
parser.add_argument("--testcase", type=int, default=0, help="test case number", metavar="testcase", dest="testcase")
+ parser.add_argument("--verbose", type=int, default=0, help="enable verbose output", metavar="verbose", dest="verbose")
# Parse arguments
options = parser.parse_args(args)
#parser.print_help()
- logging.debug("Options: category=%d num=%d bw=%d testcase=%d",
- options.category, options.numerology, options.bandwidth, options.testcase)
+ logging.debug("Options: ran=%d category=%d num=%d bw=%d testcase=%d",
+ options.rantech, options.category, options.numerology, options.bandwidth, options.testcase)
return options
def is_comment(s):
class GetOutOfLoops( Exception ):
pass
-def compare_resuts(cat, mu, bw, tcase, xran_path, test_cfg, direction):
- res = 0
+def get_re_map(nRB, direction):
+ prb_map = []
+ PrbElemContent = []
+ if direction == 0:
+ #DL
+ if 'nPrbElemDl' in globals():
+ nPrbElm = nPrbElemDl
+ for i in range(0, nPrbElm):
+ elm = str('PrbElemDl'+str(i))
+ #print(elm)
+ if elm in globals():
+ PrbElemContent.insert(i,list(globals()[elm]))
+ xRBStart = PrbElemContent[i][0]
+ xRBSize = PrbElemContent[i][1]
+ #print(PrbElemContent,"RBStart: ", xRBStart, "RBSize: ",xRBSize, list(range(xRBStart, xRBStart + xRBSize)))
+ prb_map = prb_map + list(range(xRBStart*12, xRBStart*12 + xRBSize*12))
+ else:
+ nPrbElm = 0;
+
+ elif direction == 1:
+ #UL
+ if 'nPrbElemUl' in globals():
+ nPrbElm = nPrbElemUl
+ for i in range(0, nPrbElm):
+ elm = str('PrbElemUl'+str(i))
+ #print(elm)
+ if (elm in globals()):
+ PrbElemContent.insert(i,list(globals()[elm]))
+ xRBStart = PrbElemContent[i][0]
+ xRBSize = PrbElemContent[i][1]
+ #print(PrbElemContent,"RBStart: ", xRBStart, "RBSize: ",xRBSize, list(range(xRBStart, xRBStart + xRBSize)))
+ prb_map = prb_map + list(range(xRBStart*12, xRBStart*12 + xRBSize*12))
+ else:
+ nPrbElm = 0;
- if mu < 3:
- nDlRB = nNumRbsPerSymF1[mu][nRChBwOptions.get(str(nDLBandwidth))]
- nUlRB = nNumRbsPerSymF1[mu][nRChBwOptions.get(str(nULBandwidth))]
- elif (mu >=2) & (mu <= 3):
- nDlRB = nNumRbsPerSymF2[mu - 2][nRChBwOptions_mu2and3.get(str(nDLBandwidth))]
- nUlRB = nNumRbsPerSymF2[mu - 2][nRChBwOptions_mu2and3.get(str(nULBandwidth))]
- print(nDlRB, nUlRB)
- else:
- print("Incorrect arguments\n")
- res = -1
- return res
+ if nPrbElm == 0 :
+ prb_map = list(range(0, nRB*12))
+
+ return prb_map
+
+def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction):
+ res = 0
+ re_map = []
+ if rantech==1:
+ if mu == 0:
+ nDlRB = nLteNumRbsPerSymF1[mu][nRChBwOptions.get(str(nDLBandwidth))]
+ nUlRB = nLteNumRbsPerSymF1[mu][nRChBwOptions.get(str(nULBandwidth))]
+ else:
+ print("Incorrect arguments\n")
+ res = -1
+ return res
+ elif rantech==0:
+ if mu < 3:
+ nDlRB = nNumRbsPerSymF1[mu][nRChBwOptions.get(str(nDLBandwidth))]
+ nUlRB = nNumRbsPerSymF1[mu][nRChBwOptions.get(str(nULBandwidth))]
+ elif (mu >=2) & (mu <= 3):
+ nDlRB = nNumRbsPerSymF2[mu - 2][nRChBwOptions_mu2and3.get(str(nDLBandwidth))]
+ nUlRB = nNumRbsPerSymF2[mu - 2][nRChBwOptions_mu2and3.get(str(nULBandwidth))]
+ print(nDlRB, nUlRB)
+ else:
+ print("Incorrect arguments\n")
+ res = -1
+ return res
if 'compression' in globals():
comp = compression
else:
comp = 0
+ if 'srsEanble' in globals():
+ srs_enb = srsEanble
+ else:
+ srs_enb = 0
+
print("compare results: {} [compression {}]\n".format(dic_dir.get(direction), comp))
#if cat == 1:
else:
flowId = ccNum*antNum
+ if direction == 0:
+ re_map = get_re_map(nDlRB, direction)
+ elif direction == 1:
+ re_map = get_re_map(nUlRB, direction)
+ else:
+ raise Exception('Direction is not supported %d'.format(direction))
+
for i in range(0, flowId):
#read ref and test files
tst = []
continue
#print("Check:","[",i,"]", slot_idx, sym_idx)
- for line_idx in range(0, nRB*12):
+ for line_idx in re_map:
offset = (slot_idx*nRB*12*14) + sym_idx*nRB*12 + line_idx
- line_tst = tst[offset].rstrip()
- line_ref = ref[offset].rstrip()
+ try:
+ line_tst = tst[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on tst: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(tst))
+ raise GetOutOfLoops
+ try:
+ line_ref = ref[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on ref: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(ref))
+ raise GetOutOfLoops
+
if comp == 1:
- # discard LSB bits as BFP compression is not Bit Exact
+ # discard LSB bits as BFP compression is not "bit exact"
tst_i_value = int(line_tst.split(" ")[0]) & 0xFF80
tst_q_value = int(line_tst.split(" ")[1]) & 0xFF80
ref_i_value = int(line_ref.split(" ")[0]) & 0xFF80
ref_q_value = int(line_ref.split(" ")[1]) & 0xFF80
- print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ #print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
if (tst_i_value != ref_i_value) or (tst_q_value != ref_q_value) :
print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
res = -1
print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst:", line_tst, "ref:", line_ref)
res = -1
raise GetOutOfLoops
+ except GetOutOfLoops:
+ return res
+
+ #if (direction == 0) | (cat == 0) | (srs_enb == 0): #DL or Cat A
+ #done
+ return res
+
+ print("compare results: {} [compression {}]\n".format('SRS', comp))
+
+ #srs
+ symbMask = srsSym
+ try:
+ flowId = ccNum*antElmTRx
+ for i in range(0, flowId):
+ #read ref and test files
+ tst = []
+ ref = []
+
+ if direction == 1:
+ # UL
+ nRB = nUlRB
+ file_tst = xran_path+"/app/logs/"+"o-du-srs_log_ant"+str(i)+".txt"
+ file_ref = xran_path+"/app/logs/"+"o-ru-play_srs_ant"+str(i)+".txt"
+ else:
+ raise Exception('Direction is not supported %d'.format(direction))
+
+ print("test result :", file_tst)
+ print("test reference:", file_ref)
+ if os.path.exists(file_tst):
+ try:
+ file_tst = open(file_tst, 'r')
+ except OSError:
+ print ("Could not open/read file:", file_tst)
+ sys.exit()
+ else:
+ print(file_tst, "doesn't exist")
+ res = -1
+ return res
+ if os.path.exists(file_ref):
+ try:
+ file_ref = open(file_ref, 'r')
+ except OSError:
+ print ("Could not open/read file:", file_ref)
+ sys.exit()
+ else:
+ print(file_tst, "doesn't exist")
+ res = -1
+ return res
+
+ tst = file_tst.readlines()
+ ref = file_ref.readlines()
+
+ print(len(tst))
+ print(len(ref))
+
+ file_tst.close();
+ file_ref.close();
+
+ print(numSlots)
+
+ for slot_idx in range(0, numSlots):
+ for sym_idx in range(0, 14):
+ if symbMask & (1 << sym_idx):
+ print("SRS check sym ", sym_idx)
+ if nFrameDuplexType==1:
+ #skip sym if TDD
+ if direction == 0:
+ #DL
+ sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx]
+ if(sym_dir != 0):
+ continue
+ elif direction == 1:
+ #UL
+ sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx]
+ if(sym_dir != 1):
+ continue
+
+ #print("Check:","[",i,"]", slot_idx, sym_idx)
+ for line_idx in range(0, nRB*12):
+ offset = (slot_idx*nRB*12*14) + sym_idx*nRB*12 + line_idx
+ try:
+ line_tst = tst[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on tst: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(tst))
+ raise GetOutOfLoops
+ try:
+ line_ref = ref[offset].rstrip()
+ except IndexError:
+ res = -1
+ print("FAIL:","IndexError on ref: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(ref))
+ raise GetOutOfLoops
+ if False : #SRS sent as not compressed
+ #comp == 1:
+ # discard LSB bits as BFP compression is not Bit Exact
+ tst_i_value = int(line_tst.split(" ")[0]) & 0xFF80
+ tst_q_value = int(line_tst.split(" ")[1]) & 0xFF80
+ ref_i_value = int(line_ref.split(" ")[0]) & 0xFF80
+ ref_q_value = int(line_ref.split(" ")[1]) & 0xFF80
+
+ print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ if (tst_i_value != ref_i_value) or (tst_q_value != ref_q_value) :
+ print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ")
+ res = -1
+ raise GetOutOfLoops
+ else:
+ #if line_idx == 0:
+ #print("Check:", offset,"[",i,"]", slot_idx, sym_idx,":",line_tst, line_ref)
+ if line_ref != line_tst:
+ print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst:", line_tst, "ref:", line_ref)
+ res = -1
+ raise GetOutOfLoops
except GetOutOfLoops:
pass
+
return res
-def parse_dat_file(cat, mu, bw, tcase, xran_path, test_cfg):
+def parse_dat_file(rantech, cat, mu, bw, tcase, xran_path, test_cfg):
#parse config files
logging.info("parse config files %s\n", test_cfg[0])
lineList = list()
return local_env
-def make_copy_mlog(cat, mu, bw, tcase, xran_path):
+def del_dat_file_vars(local_env):
+
+ for k, v in local_env.items():
+ del globals()[k]
+
+ return 0
+
+def make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path):
res = 0
src_bin = xran_path+"/app/mlog-o-du-c0.bin"
src_csv = xran_path+"/app/mlog-o-du-hist.csv"
- dst_bin = xran_path+"/app/mlog-o-du-c0-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin"
- dst_csv = xran_path+"/app/mlog-o-du-hist-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv"
+ dst_bin = xran_path+"/app/mlog-o-du-c0-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin"
+ dst_csv = xran_path+"/app/mlog-o-du-hist-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv"
try:
d_bin = shutil.copyfile(src_bin, dst_bin)
except IOError:
logging.info("MLog is not present\n")
res = 1
+ return res
else:
logging.info("Mlog was copied\n")
+ print("Destination path:", d_bin)
+ print("Destination path:", d_csv)
+
+ d_bin = shutil.copyfile(src_bin, dst_bin)
+ d_csv = shutil.copyfile(src_csv, dst_csv)
+
src_bin = xran_path+"/app/mlog-o-ru-c0.bin"
src_csv = xran_path+"/app/mlog-o-ru-hist.csv"
- dst_bin = xran_path+"/app/mlog-o-ru-c0-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin"
- dst_csv = xran_path+"/app/mlog-o-ru-hist-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv"
+ dst_bin = xran_path+"/app/mlog-o-ru-c0-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin"
+ dst_csv = xran_path+"/app/mlog-o-ru-hist-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv"
+ d_bin = shutil.copyfile(src_bin, dst_bin)
+ d_csv = shutil.copyfile(src_csv, dst_csv)
try:
d_bin = shutil.copyfile(src_bin, dst_bin)
except IOError:
logging.info("MLog is not present\n")
res = 1
+ return res
else:
logging.info("Mlog was copied\n")
-
return res
-def run_tcase(cat, mu, bw, tcase, xran_path):
- if cat == 1:
- test_config = xran_path+"/app/usecase/cat_b/mu{0:d}_{1:d}mhz".format(mu, bw)
- elif cat == 0 :
- test_config = xran_path+"/app/usecase/mu{0:d}_{1:d}mhz".format(mu, bw)
+def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path):
+
+ if rantech == 1: #LTE
+ if cat == 1:
+ test_config =xran_path+"/app/usecase/lte_b/mu{0:d}_{1:d}mhz".format(mu, bw)
+ elif cat == 0 :
+ test_config =xran_path+"/app/usecase/lte_a/mu{0:d}_{1:d}mhz".format(mu, bw)
+ else:
+ print("Incorrect cat arguments\n")
+ return -1
+ elif rantech == 0: #5G NR
+ if cat == 1:
+ test_config =xran_path+"/app/usecase/cat_b/mu{0:d}_{1:d}mhz".format(mu, bw)
+ elif cat == 0 :
+ test_config =xran_path+"/app/usecase/mu{0:d}_{1:d}mhz".format(mu, bw)
+ else:
+ print("Incorrect cat argument\n")
+ return -1
else:
- print("Incorrect arguments\n")
+ print("Incorrect rantech argument\n")
+ return -1
if(tcase > 0) :
test_config = test_config+"/"+str(tcase)
logging.debug("Started script: master.py, XRAN path %s", xran_path)
test_cfg = []
- #TODO: add detection of ETH ports
- eth_cp_dev = ["0000:22:02.1", "0000:22:0a.1"]
- eth_up_dev = ["0000:22:02.0", "0000:22:0a.0"]
test_cfg.append(test_config+"/config_file_o_du.dat")
test_cfg.append(test_config+"/config_file_o_ru.dat")
processes = []
logfile_xu = []
log_file_name = []
+ timer = []
+ os.system('pkill -9 "sample-app"')
os.system('rm -rf ./logs')
for i in range(2):
- log_file_name.append("sampleapp_log_{}_cat_{}_mu{}_{}mhz_tst_{}.log".format(dic_xu.get(i),cat, mu, bw, tcase))
+ log_file_name.append("sampleapp_log_{}_{}_cat_{}_mu{}_{}mhz_tst_{}.log".format(dic_ran_tech.get(rantech), dic_xu.get(i),cat, mu, bw, tcase))
with open(log_file_name[i], "w") as f:
+ run_cmd = [app, "-c", test_cfg[i], "-p", "2", eth_up_dev[i], eth_cp_dev[i]]
#, stdout=f, stderr=f
- p = subprocess.Popen([app, test_cfg[i], eth_up_dev[i], eth_cp_dev[i]], stdout=f, stderr=f)
+ if (verbose==1):
+ p = subprocess.Popen(run_cmd)
+ else:
+ p = subprocess.Popen(run_cmd, stdout=f, stderr=f)
+ t = Timer(timeout_sec, p.kill)
+ t.start()
+ timer.append(t)
logfile_xu.insert(i, f)
processes.append((p, logfile_xu[i]))
- logging.info("Running O-DU and O-RU see output in: %s %s\n", logfile_xu[0].name, logfile_xu[1].name)
+ logging.info("Running O-DU and O-RU see output in:\n O-DU: %s\n O-RU: %s\n", xran_path+"/app/"+logfile_xu[0].name, xran_path+"/app/"+logfile_xu[1].name)
+ #while (gmtime().tm_sec % 30) <> 0:
+ #pass
+ print(strftime("%a, %d %b %Y %H:%M:%S +0000", gmtime()))
+ i = 0
for p, f in processes:
- p.wait()
p.communicate()[0]
+ p.wait()
if p.returncode != 0:
print("Application {} failed p.returncode:{}".format(dic_xu.get(i), p.returncode))
print("FAIL")
- logging.info("FAIL\n")
- logging.shutdown()
- sys.exit(p.returncode)
-
+ #logging.info("FAIL\n")
+ #logging.shutdown()
+ #sys.exit(p.returncode)
+ i += 1
f.close()
+ for i in range(2):
+ timer[i].cancel();
+ timer[i].cancel();
+
logging.info("O-DU and O-RU are done\n")
- make_copy_mlog(cat, mu, bw, tcase, xran_path)
+ make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path)
- usecase_cfg = parse_dat_file(cat, mu, bw, tcase, xran_path, test_cfg)
+ usecase_cfg = parse_dat_file(rantech, cat, mu, bw, tcase, xran_path, test_cfg)
- res = compare_resuts(cat, mu, bw, tcase, xran_path, test_cfg, 0)
+ res = compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, 0)
if res != 0:
os.chdir(wd)
print("FAIL")
return res
- res = compare_resuts(cat, mu, bw, tcase, xran_path, test_cfg, 1)
+ res = compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, 1)
if res != 0:
os.chdir(wd)
print("FAIL")
os.chdir(wd)
print("PASS")
+
+ del_dat_file_vars(usecase_cfg)
+
return res
def main():
tcase = 0
"""Processes input files to produce IACA files"""
# Find path to XRAN
- xran_path = os.getenv("XRAN_DIR")
+ if os.getenv("XRAN_DIR") is not None:
+ xran_path = os.getenv("XRAN_DIR")
+ else:
+ print("please set 'export XRAN_DIR' in the OS")
+ return -1
# Set up logging with given level (DEBUG, INFO, ERROR) for console end logfile
init_logger(logging.INFO, logging.DEBUG)
- logging.info("Started script: master.py, XRAN path %s", xran_path)
+ host_name = socket.gethostname()
+ logging.info("host: %s Started script: master.py from XRAN path %s",host_name, xran_path)
+
+ #custom config for dev station
+ if host_name == "sc12-xran-sub6":
+ eth_cp_dev[0] = "0000:21:02.1"
+ eth_cp_dev[1] = "0000:21:0a.1"
+ eth_up_dev[0] = "0000:21:02.0"
+ eth_up_dev[1] = "0000:21:0a.0"
# Parse input arguments
if len(sys.argv) == 1 :
print("Run All test cases {}\n".format(run_total))
else:
options = parse_args(sys.argv[1:])
+ rantech = options.rantech
cat = options.category
mu = options.numerology
bw = options.bandwidth
tcase = options.testcase
+ verbose = options.verbose
if (run_total):
for test_run_ix in range(0, run_total):
- cat = all_test_cases[test_run_ix][0]
- mu = all_test_cases[test_run_ix][1]
- bw = all_test_cases[test_run_ix][2]
- tcase = all_test_cases[test_run_ix][3]
-
- res = run_tcase(cat, mu, bw, tcase, xran_path)
+ rantech = all_test_cases[test_run_ix][0]
+ cat = all_test_cases[test_run_ix][1]
+ mu = all_test_cases[test_run_ix][2]
+ bw = all_test_cases[test_run_ix][3]
+ tcase = all_test_cases[test_run_ix][4]
+ verbose = 0
+
+ logging.info("Test# %d out of %d: ran %d cat %d mu %d bw %d test case %d\n",test_run_ix, run_total, rantech, cat, mu, bw, tcase)
+ res = run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path)
if (res != 0):
- test_results.append((cat, mu, bw, tcase,'FAIL'))
- break;
+ test_results.append((rantech, cat, mu, bw, tcase,'FAIL'))
+ continue
+
+ test_results.append((rantech, cat, mu, bw, tcase,'PASS'))
- test_results.append((cat, mu, bw, tcase,'PASS'))
+ with open('testresult.txt', 'w') as reshandle:
+ json.dump(test_results, reshandle)
else:
- res = run_tcase(cat, mu, bw, tcase, xran_path)
+ res = run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path)
if (res != 0):
- test_results.append((cat, mu, bw, tcase,'FAIL'))
- test_results.append((cat, mu, bw, tcase,'PASS'))
+ test_results.append((rantech, cat, mu, bw, tcase,'FAIL'))
+ test_results.append((rantech, cat, mu, bw, tcase,'PASS'))
- with open('testresult.txt', 'w') as reshandle:
- json.dump(test_results, reshandle)
+ with open('testresult.txt', 'w') as reshandle:
+ json.dump(test_results, reshandle)
return res
CPPFLAGS += -isystem $(GTEST_ROOT)/include
# Flags passed to the C++ compiler.
-CXXFLAGS += -g -std=gnu++11 -Wall -Wextra -fstack-protector-strong -z noexecstack -Wformat -Wformat-security -Werror=format-security -fno-strict-overflow -fwrapv -pthread -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I $(COMMON_TEST_DIR) -I$(RTE_INC)
+CXXFLAGS += -g -std=gnu++11 -Wall -Wextra -pthread -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I $(COMMON_TEST_DIR) -I$(RTE_INC)
# All tests produced by this Makefile. Remember to add new tests you
# created to the list.
GTEST_HEADERS = $(GTEST_ROOT)/include/gtest/*.h \
$(GTEST_ROOT)/include/gtest/internal/*.h
-RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_mempool_ring -Wl,-lrte_pci -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_net -Wl,-lrte_distributor -Wl,-lrte_reorder -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_jobstats -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,-lrte_vhost -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_cryptodev -Wl,-lrte_mempool -Wl,-lrte_ring -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_null -Wl,-lrte_pdump -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+#RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_mempool_ring -Wl,-lrte_pci -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_net -Wl,-lrte_distributor -Wl,-lrte_reorder -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_jobstats -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,-lrte_vhost -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_cryptodev -Wl,-lrte_mempool -Wl,-lrte_ring -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_null -Wl,-lrte_pdump -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,-lrte_flow_classify -Wl,--whole-archive -Wl,-lrte_pipeline -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_table -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_port -Wl,--no-whole-archive -Wl,-lrte_pdump -Wl,-lrte_distributor -Wl,-lrte_ip_frag -Wl,-lrte_meter -Wl,-lrte_lpm -Wl,--whole-archive -Wl,-lrte_acl -Wl,--no-whole-archive -Wl,-lrte_jobstats -Wl,-lrte_metrics -Wl,-lrte_bitratestats -Wl,-lrte_latencystats -Wl,-lrte_power -Wl,-lrte_efd -Wl,-lrte_bpf -Wl,--whole-archive -Wl,-lrte_cfgfile -Wl,-lrte_gro -Wl,-lrte_gso -Wl,-lrte_hash -Wl,-lrte_member -Wl,-lrte_vhost -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_net -Wl,-lrte_ethdev -Wl,-lrte_bbdev -Wl,-lrte_cryptodev -Wl,-lrte_security -Wl,-lrte_compressdev -Wl,-lrte_eventdev -Wl,-lrte_rawdev -Wl,-lrte_timer -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_pci -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_reorder -Wl,-lrte_sched -Wl,-lrte_kni -Wl,-lrte_common_octeontx -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_bus_dpaa -Wl,-lrte_common_dpaax -Wl,-lrte_stack -Wl,-lrte_bus_fslmc -Wl,-lrte_mempool_bucket -Wl,-lrte_mempool_stack -Wl,-lrte_mempool_dpaa -Wl,-lrte_mempool_dpaa2 -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_ark -Wl,-lrte_pmd_iavf -Wl,-lrte_pmd_avp -Wl,-lrte_pmd_axgbe -Wl,-lrte_pmd_bnxt -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_dpaa -Wl,-lrte_pmd_dpaa2 -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ena -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_failsafe -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_kni -Wl,-lrte_pmd_lio -Wl,-lrte_pmd_nfp -Wl,-lrte_pmd_null -Wl,-lrte_pmd_qede -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_softnic -Wl,-lrte_pmd_tap -Wl,-lrte_pmd_thunderx_nicvf -Wl,-lrte_pmd_vdev_netvsc -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_vhost -Wl,-lrte_pmd_ifc -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_bus_vmbus -Wl,-lrte_pmd_netvsc -Wl,-lrte_pmd_bbdev_null -Wl,-lrte_pmd_null_crypto -Wl,-lrte_pmd_crypto_scheduler -Wl,-lrte_pmd_dpaa2_sec -Wl,-lrte_pmd_dpaa_sec -Wl,-lrte_pmd_virtio_crypto -Wl,-lrte_pmd_octeontx_zip -Wl,-lrte_pmd_qat -Wl,-lrte_pmd_skeleton_event -Wl,-lrte_pmd_sw_event -Wl,-lrte_pmd_octeontx_ssovf -Wl,-lrte_pmd_dpaa_event -Wl,-lrte_pmd_dpaa2_event -Wl,-lrte_mempool_octeontx -Wl,-lrte_pmd_octeontx -Wl,-lrte_pmd_opdl_event -Wl,-lrte_rawdev_skeleton -Wl,-lrte_rawdev_dpaa2_cmdif -Wl,-lrte_rawdev_dpaa2_qdma -Wl,-lrte_bus_ifpga -Wl,--no-whole-archive -Wl,-lrt -Wl,-lm -Wl,-lnuma -Wl,-ldl -Wl,
CFLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \
-fdata-sections \
# u_plane_performance.cc \
CPP_SRC = $(COMMON_TEST_DIR)/common.cpp \
- $(USER_DIR)/xran_compression.cpp
+ $(USER_DIR)/xran_compression.cpp \
+ $(USER_DIR)/xran_bfp_ref.cpp \
+ $(USER_DIR)/xran_bfp_cplane8.cpp \
+ $(USER_DIR)/xran_bfp_cplane16.cpp \
+ $(USER_DIR)/xran_bfp_cplane32.cpp \
+ $(USER_DIR)/xran_bfp_cplane64.cpp
C_OBJS := $(patsubst %.c,%.o,$(C_SRC))
CC_OBJS := $(patsubst %.cc,%.o,$(CC_SRC))
@echo [CLEAN]
rm -f $(TESTS) *.o $(COMMON_TEST_DIR)/*.o $(USER_DIR)/*.o $(USER_ETH)/*.o
+.PHONY: xclean
+xclean: clean
+
.PHONY : echo_start_build
echo_start_build :
@echo Build Tests with
#include <stdint.h>
+#define DELETE_ARRAY(x) { if(x) { delete[] x; x = nullptr; } }
const std::string module_name = "C-Plane";
struct xran_section_gen_info *m_pSectGenInfo = NULL;
struct xran_section_gen_info *m_pSectResult = NULL;
+ struct sectinfo {
+ uint16_t sectionId;
+ uint8_t rb;
+ uint8_t symInc;
+ uint16_t startPrbc;
+ uint16_t numPrbc;
+ uint16_t reMask;
+ uint8_t numSymbol;
+ uint16_t beamId;
+ int freqOffset;
+ std::vector<uint8_t> exts;
+ };
+
+ struct extcfginfo {
+ int type;
+ std::string name;
+ union {
+ struct xran_sectionext1_info ext1;
+ struct xran_sectionext2_info ext2;
+ struct xran_sectionext3_info ext3;
+ struct xran_sectionext4_info ext4;
+ struct xran_sectionext5_info ext5;
+ } u;
+ };
protected:
int m_maxSections = 8; /* not used */
struct xran_recv_packet_info m_pktInfo;
struct xran_cp_gen_params m_result;
+ struct xran_sectionext1_info m_temp_ext1[XRAN_MAX_PRBS];
+
uint8_t m_dir;
std::string m_dirStr;
uint8_t m_sectionType;
uint8_t m_ccId, m_antId;
uint8_t m_seqId;
uint8_t m_frameId, m_subframeId, m_slotId;
- uint8_t m_symStart, m_symNum;
- uint16_t *m_prbStart = NULL, *m_prbNum = NULL;
+ uint8_t m_symStart;
uint8_t m_iqWidth, m_compMethod;
- uint16_t m_beamId;
- uint16_t m_reMask = 0xfff;
- uint16_t m_sectionId;
uint8_t m_filterIndex;
uint16_t m_timeOffset;
uint8_t m_fftSize;
uint8_t m_scs;
uint16_t m_cpLength;
- int m_freqOffset;
+
+ struct sectinfo *m_sections;
+ struct extcfginfo *m_extcfgs;
+ int m_nextcfgs;
uint16_t m_ext1_dst_len = 0;
- int8_t *m_p_ext1_dst = NULL;
- int16_t *m_p_bfw_iq_src = NULL;
+ int8_t *m_p_ext1_dst = nullptr;
+ int16_t *m_p_bfw_iq_src = nullptr;
struct xran_sectionext1_info m_ext1;
- struct xran_sectionext2_info m_ext2;
- struct xran_sectionext4_info m_ext4;
- struct xran_sectionext5_info m_ext5;
int16_t m_bfwIQ[XRAN_MAX_BFW_N*2];
init_test("C_Plane");
- m_numSections = get_input_parameter<int>("num_sections");
- ASSERT_FALSE(m_numSections == 0);
-
m_dirStr = get_input_parameter<std::string>("direction");
if(!m_dirStr.compare("DL")) m_dir = XRAN_DIR_DL;
m_compMethod = get_input_parameter<uint8_t>("comp_method");
m_iqWidth = get_input_parameter<uint8_t>("iq_width");
- m_sectionId = get_input_parameter<uint8_t>("section_id");
- m_symNum = get_input_parameter<uint8_t>("symbol_num");
- m_beamId = get_input_parameter<uint16_t>("beam_id");
-
- /* reading configurations of start prb and the number of prbs */
- std::vector<int> prbstart = get_input_parameter<std::vector<int>>("prb_start");
- std::vector<int> prbnum = get_input_parameter<std::vector<int>>("prb_num");
- /* number of sections and the pair of start/number of prb shall be matched */
- ASSERT_TRUE((m_numSections == prbstart.size())
- && (m_numSections == prbnum.size())
- && (prbstart.size() == prbnum.size()));
-
- m_prbStart = new uint16_t [m_numSections];
- m_prbNum = new uint16_t [m_numSections];
- for(i=0; i < m_numSections; i++) {
- m_prbStart[i] = prbstart[i];
- m_prbNum[i] = prbnum[i];
- }
-
switch(m_sectionType) {
case XRAN_CP_SECTIONTYPE_1:
m_filterIndex = XRAN_FILTERINDEX_STANDARD;
m_fftSize = get_input_parameter<uint8_t>("fft_size");
m_scs = get_input_parameter<uint8_t>("scs");
m_cpLength = get_input_parameter<uint16_t>("cp_length");
- m_freqOffset = get_input_parameter<int>("freq_offset");
break;
default:
- FAIL() << "Invalid Section Type - " << m_sectionType << "\n";
+ FAIL() << "Invalid Section Type - " << m_sectionType << std::endl;
+ }
+
+ m_numSections = get_input_subsection_size("sections");
+ ASSERT_FALSE(m_numSections == 0);
+
+ m_sections = new struct sectinfo [m_numSections];
+ for(i=0; i<m_numSections; i++) {
+ m_sections[i].sectionId = get_input_parameter<uint16_t>("sections", i, "sectionId");
+ m_sections[i].rb = get_input_parameter<uint16_t>("sections", i, "rb");
+ m_sections[i].symInc = get_input_parameter<uint16_t>("sections", i, "symInc");
+ m_sections[i].startPrbc = get_input_parameter<uint16_t>("sections", i, "startPrbc");
+ m_sections[i].numPrbc = get_input_parameter<uint16_t>("sections", i, "numPrbc");
+ m_sections[i].reMask = get_input_parameter<uint16_t>("sections", i, "reMask");
+ m_sections[i].numSymbol = get_input_parameter<uint16_t>("sections", i, "numSymbol");
+ m_sections[i].beamId = get_input_parameter<uint16_t>("sections", i, "beamId");
+
+ switch(m_sectionType) {
+ case XRAN_CP_SECTIONTYPE_3:
+ m_sections[i].freqOffset = get_input_parameter<uint16_t>("sections", i, "freqOffset");
+ break;
+ }
+
+ m_sections[i].exts = get_input_parameter<std::vector<uint8_t>>("sections", i, "exts");
+ }
+
+ /* reading configurations of section extension */
+ m_nextcfgs = get_input_subsection_size("extensions");
+ if(m_nextcfgs) {
+ m_extcfgs = new struct extcfginfo [m_nextcfgs];
+
+ for(i=0; i < m_nextcfgs; i++) {
+ std::vector<uint16_t> csf;
+ std::vector<uint16_t> mcScaleReMask;
+ std::vector<uint16_t> mcScaleOffset;
+
+ m_extcfgs[i].type = get_input_parameter<int>("extensions", i, "type");
+ m_extcfgs[i].name = get_input_parameter<std::string>("extensions", i, "name");
+
+ switch(m_extcfgs[i].type) {
+ case XRAN_CP_SECTIONEXTCMD_1:
+ /* Skip section extension type 1 since it has separate function */
+ std::cout << "### Skip Extension 1 configuration !!\n" << std::endl;
+ continue;
+
+ case XRAN_CP_SECTIONEXTCMD_2:
+ m_extcfgs[i].u.ext2.bfAzPtWidth = get_input_parameter<uint8_t>("extensions", i, "bfAzPtWidth") & 0x7;
+ m_extcfgs[i].u.ext2.bfAzPt = get_input_parameter<uint8_t>("extensions", i, "bfAzPt") & 0xf;
+ m_extcfgs[i].u.ext2.bfZePtWidth = get_input_parameter<uint8_t>("extensions", i, "bfZePtWidth") & 0x7;
+ m_extcfgs[i].u.ext2.bfZePt = get_input_parameter<uint8_t>("extensions", i, "bfZePt") & 0xf;
+ m_extcfgs[i].u.ext2.bfAz3ddWidth = get_input_parameter<uint8_t>("extensions", i, "bfAz3ddWidth") & 0x7;
+ m_extcfgs[i].u.ext2.bfAz3dd = get_input_parameter<uint8_t>("extensions", i, "bfAz3dd") & 0xf;
+ m_extcfgs[i].u.ext2.bfZe3ddWidth = get_input_parameter<uint8_t>("extensions", i, "bfZe3ddWidth") & 0x7;
+ m_extcfgs[i].u.ext2.bfZe3dd = get_input_parameter<uint8_t>("extensions", i, "bfZe3dd") & 0xf;
+ m_extcfgs[i].u.ext2.bfAzSI = get_input_parameter<uint8_t>("extensions", i, "bfAzSI") & 0x7;
+ m_extcfgs[i].u.ext2.bfZeSI = get_input_parameter<uint8_t>("extensions", i, "bfZeSI") & 0x7;
+ break;
+
+ case XRAN_CP_SECTIONEXTCMD_3:
+ m_extcfgs[i].u.ext3.codebookIdx = get_input_parameter<uint8_t> ("extensions", i, "codebookIdx");
+ m_extcfgs[i].u.ext3.layerId = get_input_parameter<uint8_t> ("extensions", i, "layerId") & 0xf;
+ m_extcfgs[i].u.ext3.numLayers = get_input_parameter<uint8_t> ("extensions", i, "numLayers") & 0xf;
+ m_extcfgs[i].u.ext3.txScheme = get_input_parameter<uint8_t> ("extensions", i, "txScheme") & 0xf;
+ m_extcfgs[i].u.ext3.crsReMask = get_input_parameter<uint16_t>("extensions", i, "crsReMask") & 0xfff;
+ m_extcfgs[i].u.ext3.crsShift = get_input_parameter<uint8_t> ("extensions", i, "crsShift") & 0x1;
+ m_extcfgs[i].u.ext3.crsSymNum = get_input_parameter<uint8_t> ("extensions", i, "crsSymNum") & 0xf;
+ m_extcfgs[i].u.ext3.numAntPort = get_input_parameter<uint16_t>("extensions", i, "numAntPort");
+ m_extcfgs[i].u.ext3.beamIdAP1 = get_input_parameter<uint16_t>("extensions", i, "beamIdAP1");
+ m_extcfgs[i].u.ext3.beamIdAP2 = get_input_parameter<uint16_t>("extensions", i, "beamIdAP2");
+ m_extcfgs[i].u.ext3.beamIdAP3 = get_input_parameter<uint16_t>("extensions", i, "beamIdAP3");
+ break;
+
+ case XRAN_CP_SECTIONEXTCMD_4:
+ m_extcfgs[i].u.ext4.csf = get_input_parameter<uint8_t> ("extensions", i, "csf") & 0xf;
+ m_extcfgs[i].u.ext4.modCompScaler= get_input_parameter<uint16_t>("extensions", i, "modCompScaler") & 0x7fff;
+ break;
+
+ case XRAN_CP_SECTIONEXTCMD_5:
+ m_extcfgs[i].u.ext5.num_sets = get_input_parameter<uint8_t>("extensions", i, "num_sets");
+ if(m_extcfgs[i].u.ext5.num_sets > XRAN_MAX_MODCOMP_ADDPARMS)
+ FAIL() << "Invalid number of sets in extension 5!";
+
+ csf = get_input_parameter<std::vector<uint16_t>>("extensions", i, "csf");
+ mcScaleReMask = get_input_parameter<std::vector<uint16_t>>("extensions", i, "mcScaleReMask");
+ mcScaleOffset = get_input_parameter<std::vector<uint16_t>>("extensions", i, "mcScaleOffset");
+
+ if(csf.size() != m_extcfgs[i].u.ext5.num_sets
+ || mcScaleReMask.size() != m_extcfgs[i].u.ext5.num_sets
+ || mcScaleOffset.size() != m_extcfgs[i].u.ext5.num_sets)
+ FAIL() << "Invalid configuration in extension 5 - different size!";
+
+ for(int ii=0; ii < m_extcfgs[i].u.ext5.num_sets; ii++) {
+ m_extcfgs[i].u.ext5.mc[ii].csf = csf[ii];
+ m_extcfgs[i].u.ext5.mc[ii].mcScaleReMask = mcScaleReMask[ii];
+ m_extcfgs[i].u.ext5.mc[ii].mcScaleOffset = mcScaleOffset[ii];
+ }
+ break;
+
+ default:
+ FAIL() << "Invalid Section Type Extension - " << m_extcfgs[i].type << std::endl;
+ continue;
+ } /* switch(m_extcfgs[i].type) */
+ } /* for(i=0; i < m_nextcfgs; i++) */
+ }
+ else {
+ m_extcfgs = nullptr;
}
/* allocate and prepare required data storage */
- m_pSectGenInfo = new struct xran_section_gen_info [m_numSections];
+ m_pSectGenInfo = new struct xran_section_gen_info [m_numSections];
ASSERT_NE(m_pSectGenInfo, nullptr);
- m_params.sections = m_pSectGenInfo;
+ m_params.sections = m_pSectGenInfo;
- m_pSectResult = new struct xran_section_gen_info [m_numSections];
+ m_pSectResult = new struct xran_section_gen_info [m_numSections];
ASSERT_NE(m_pSectResult, nullptr);
- m_result.sections = m_pSectResult;
+ m_result.sections = m_pSectResult;
- m_ext1_dst_len = 9600;
- m_p_ext1_dst = new int8_t [m_ext1_dst_len];
- m_p_bfw_iq_src = new int16_t [9600/2];
+ m_ext1_dst_len = 9600;
+ m_p_ext1_dst = new int8_t [m_ext1_dst_len];
+ m_p_bfw_iq_src = new int16_t [9600/2];
/* allocating an mbuf for packet generatrion */
- m_pTestBuffer = xran_ethdi_mbuf_alloc();
-
- ASSERT_FALSE(m_pTestBuffer == NULL);
+ m_pTestBuffer = xran_ethdi_mbuf_alloc();
+ ASSERT_FALSE(m_pTestBuffer == nullptr);
}
void TearDown() override
{
- int i, j;
-
- if(m_pTestBuffer != NULL)
+ if(m_pTestBuffer != nullptr) {
rte_pktmbuf_free(m_pTestBuffer);
-
- if(m_prbStart)
- delete[] m_prbStart;
- if(m_prbNum)
- delete[] m_prbNum;
-
- if(m_p_bfw_iq_src)
- delete[] m_p_bfw_iq_src;
-
- if(m_p_ext1_dst)
- delete[] m_p_ext1_dst;
-
- if(m_pSectGenInfo)
- delete[] m_pSectGenInfo;
-
- if(m_pSectResult) {
- delete[] m_pSectResult;
+ m_pTestBuffer = nullptr;
}
+ DELETE_ARRAY(m_extcfgs);
+ DELETE_ARRAY(m_sections);
+ DELETE_ARRAY(m_p_bfw_iq_src);
+ DELETE_ARRAY(m_p_ext1_dst);
+ DELETE_ARRAY(m_pSectGenInfo);
+ DELETE_ARRAY(m_pSectResult);
}
- int prepare_sections(bool extflag);
- int prepare_extensions(int sect_num);
+ int prepare_sections(void);
+ int prepare_extensions(void);
void verify_sections(void);
};
-int C_plane::prepare_extensions(int sect_num)
+int C_plane::prepare_extensions()
{
- int i, numext;
- int N;
-
-
- N = 8;
-
- // extension 1
- m_ext1.bfwNumber = 4*N; // 4 ant, 8 UEs
- m_ext1.bfwiqWidth = 16;
- m_ext1.bfwCompMeth = XRAN_BFWCOMPMETHOD_NONE;
- /* XRAN_BFWCOMPMETHOD_BLKFLOAT
- * XRAN_BFWCOMPMETHOD_BLKSCALE
- * XRAN_BFWCOMPMETHOD_ULAW
- * XRAN_BFWCOMPMETHOD_BEAMSPACE
- */
- m_ext1.p_bfwIQ = m_bfwIQ;
-
- switch (m_ext1.bfwCompMeth) {
- case XRAN_BFWCOMPMETHOD_BLKFLOAT:
- m_ext1.bfwCompParam.exponent = 0xa;
- break;
- case XRAN_BFWCOMPMETHOD_BLKSCALE:
- m_ext1.bfwCompParam.blockScaler = 0xa5;
- break;
- case XRAN_BFWCOMPMETHOD_ULAW:
- m_ext1.bfwCompParam.compBitWidthShift = 0x55;
- case XRAN_BFWCOMPMETHOD_BEAMSPACE:
- for(i=0; i<N; i++)
- m_ext1.bfwCompParam.activeBeamspaceCoeffMask[i] = 0xa0 + i;
- break;
- }
+ int i, numext, sect_num;
+ int ext_id;
- for(i=0; i<N*4; i++) {
- m_ext1.p_bfwIQ[i*2] = 0xcafe;
- m_ext1.p_bfwIQ[i*2+1] = 0xbeef;
- }
+ for(sect_num=0; sect_num < m_numSections; sect_num++) {
+ numext = 0;
- // extension 2
- m_ext2.bfAzPtWidth = 7;
- m_ext2.bfAzPt = 0x55 & m_bitmask[m_ext2.bfAzPtWidth];
- m_ext2.bfZePtWidth = 7;
- m_ext2.bfZePt = 0xaa & m_bitmask[m_ext2.bfAzPtWidth];
- m_ext2.bfAz3ddWidth = 7;
- m_ext2.bfAz3dd = 0x5a & m_bitmask[m_ext2.bfAzPtWidth];
- m_ext2.bfZe3ddWidth = 7;
- m_ext2.bfZe3dd = 0xa5 & m_bitmask[m_ext2.bfAzPtWidth];
- m_ext2.bfAzSI = 0x2 & m_bitmask[3];
- m_ext2.bfZeSI = 0x5 & m_bitmask[3];
-
- // extension 4
- m_ext4.csf = 1;
- m_ext4.modCompScaler = 0x5aa5;
-
- // extension 5
- m_ext5.num_sets = 2;
- for(i=0; i<m_ext5.num_sets; i++) {
- m_ext5.mc[i].csf = i%2;
- m_ext5.mc[i].mcScaleReMask = 0xa5a + i;
- m_ext5.mc[i].mcScaleOffset = 0x5a5a + i;
- }
+ for(i=0; i < m_sections[sect_num].exts.size(); i++) {
- numext = 0;
-
- m_params.sections[sect_num].exData[numext].type = XRAN_CP_SECTIONEXTCMD_1;
- m_params.sections[sect_num].exData[numext].len = sizeof(m_ext1);
- m_params.sections[sect_num].exData[numext].data = &m_ext1;
- numext++;
-
- m_params.sections[sect_num].exData[numext].type = XRAN_CP_SECTIONEXTCMD_2;
- m_params.sections[sect_num].exData[numext].len = sizeof(m_ext2);
- m_params.sections[sect_num].exData[numext].data = &m_ext2;
- numext++;
-
- m_params.sections[sect_num].exData[numext].type = XRAN_CP_SECTIONEXTCMD_4;
- m_params.sections[sect_num].exData[numext].len = sizeof(m_ext4);
- m_params.sections[sect_num].exData[numext].data = &m_ext4;
- numext++;
-
- m_params.sections[sect_num].exData[numext].type = XRAN_CP_SECTIONEXTCMD_5;
- m_params.sections[sect_num].exData[numext].len = sizeof(m_ext5);
- m_params.sections[sect_num].exData[numext].data = &m_ext5;
- numext++;
+ ext_id = m_sections[sect_num].exts[i];
+ if(ext_id >= m_nextcfgs) {
+ std::cout << "Invalid section extension configuration index - " << ext_id << " [max " << m_nextcfgs-1 << "]" << std::endl;
+ return (-1);
+ }
- m_params.sections[sect_num].exDataSize = numext;
+ switch(m_extcfgs[ext_id].type) {
+ case XRAN_CP_SECTIONEXTCMD_1:
+ std::cout << "Skip Extension 1 !!" << std::endl;
+ continue;
+ case XRAN_CP_SECTIONEXTCMD_2:
+ m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext2);
+ m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext2;
+ break;
+ case XRAN_CP_SECTIONEXTCMD_3:
+ m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext3);
+ m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext3;
+ break;
+ case XRAN_CP_SECTIONEXTCMD_4:
+ m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext4);
+ m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext4;
+ break;
+ case XRAN_CP_SECTIONEXTCMD_5:
+ m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext5);
+ m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext5;
+ break;
+ default:
+ std::cout << "Invalid Section Extension Type - " << (int)m_extcfgs[ext_id].type << std::endl;
+ return (-1);
+ } /* switch(m_extcfgs[ext_id].type) */
+
+ m_params.sections[sect_num].exData[numext].type = m_extcfgs[ext_id].type;
+ numext++;
+ } /* for(i=0; i < m_sections[sect_num].exts.size(); i++) */
+
+ if(numext) {
+ m_params.sections[sect_num].exDataSize = numext;
+ m_params.sections[sect_num].info.ef = 1;
+ }
+ else {
+ m_params.sections[sect_num].exDataSize = 0;
+ m_params.sections[sect_num].info.ef = 0;
+ }
+ } /* for(sect_num=0; sect_num < m_numSections; sect_num++) */
return (0);
}
-int C_plane::prepare_sections(bool extflag)
+
+int C_plane::prepare_sections(void)
{
int numsec;
m_params.sections[numsec].info.startSymId = m_params.hdr.startSymId; // for database
m_params.sections[numsec].info.iqWidth = m_params.hdr.iqWidth; // for database
m_params.sections[numsec].info.compMeth = m_params.hdr.compMeth; // for database
- m_params.sections[numsec].info.id = m_sectionId++;
- m_params.sections[numsec].info.rb = XRAN_RBIND_EVERY;
- m_params.sections[numsec].info.symInc = XRAN_SYMBOLNUMBER_NOTINC;
- m_params.sections[numsec].info.startPrbc = m_prbStart[numsec];
- m_params.sections[numsec].info.numPrbc = m_prbNum[numsec];
- m_params.sections[numsec].info.numSymbol = m_symNum;
- m_params.sections[numsec].info.reMask = m_reMask;
- m_params.sections[numsec].info.beamId = m_beamId;
+ m_params.sections[numsec].info.id = m_sections[numsec].sectionId;
+ m_params.sections[numsec].info.rb = m_sections[numsec].rb;
+ m_params.sections[numsec].info.symInc = m_sections[numsec].symInc;
+ m_params.sections[numsec].info.startPrbc = m_sections[numsec].startPrbc;
+ m_params.sections[numsec].info.numPrbc = m_sections[numsec].numPrbc;
+ m_params.sections[numsec].info.reMask = m_sections[numsec].reMask;
+ m_params.sections[numsec].info.numSymbol = m_sections[numsec].numSymbol;
+ m_params.sections[numsec].info.beamId = m_sections[numsec].beamId;
+
switch(m_sectionType) {
case XRAN_CP_SECTIONTYPE_1:
break;
case XRAN_CP_SECTIONTYPE_3:
- m_params.sections[numsec].info.freqOffset = m_freqOffset;
+ m_params.sections[numsec].info.freqOffset = m_sections[numsec].freqOffset;
break;
default:
return (-1);
}
-
- /* section extension */
- if(/*extflag == true*/0) {
- m_params.sections[numsec].info.ef = 1;
- prepare_extensions(numsec);
- }
- else {
- m_params.sections[numsec].info.ef = 0;
- m_params.sections[numsec].exDataSize = 0;
- }
}
m_params.numSections = numsec;
ASSERT_TRUE(m_result.numSections == m_params.numSections);
for(i=0; i < m_result.numSections; i++) {
EXPECT_TRUE(m_result.sections[i].info.id == m_params.sections[i].info.id);
- EXPECT_TRUE(m_result.sections[i].info.rb == XRAN_RBIND_EVERY);
- EXPECT_TRUE(m_result.sections[i].info.symInc == XRAN_SYMBOLNUMBER_NOTINC);
+ EXPECT_TRUE(m_result.sections[i].info.rb == m_params.sections[i].info.rb);
+ EXPECT_TRUE(m_result.sections[i].info.symInc == m_params.sections[i].info.symInc);
EXPECT_TRUE(m_result.sections[i].info.startPrbc == m_params.sections[i].info.startPrbc);
- EXPECT_TRUE(m_result.sections[i].info.numPrbc == m_params.sections[i].info.numPrbc);
+ if(m_params.sections[i].info.numPrbc > 255)
+ EXPECT_TRUE(m_result.sections[i].info.numPrbc == 0);
+ else
+ EXPECT_TRUE(m_result.sections[i].info.numPrbc == m_params.sections[i].info.numPrbc);
EXPECT_TRUE(m_result.sections[i].info.numSymbol == m_params.sections[i].info.numSymbol);
EXPECT_TRUE(m_result.sections[i].info.reMask == m_params.sections[i].info.reMask);
EXPECT_TRUE(m_result.sections[i].info.beamId == m_params.sections[i].info.beamId);
}
if(m_params.sections[i].info.ef) {
- // printf("[%d] %d == %d\n",i, m_result.sections[i].exDataSize, m_params.sections[i].exDataSize);
+ //printf("[%d] %d == %d\n",i, m_result.sections[i].exDataSize, m_params.sections[i].exDataSize);
EXPECT_TRUE(m_result.sections[i].exDataSize == m_params.sections[i].exDataSize);
for(j=0; j < m_params.sections[i].exDataSize; j++) {
ext1_params = (struct xran_sectionext1_info *)m_params.sections[i].exData[j].data;
ext1_result = (struct xran_sectionext1_info *)m_result.sections[i].exData[j].data;
- EXPECT_TRUE(ext1_result->bfwiqWidth == ext1_params->bfwiqWidth);
- EXPECT_TRUE(ext1_result->bfwCompMeth == ext1_params->bfwCompMeth);
+ EXPECT_TRUE(ext1_result->bfwiqWidth == ext1_params->bfwiqWidth);
+ EXPECT_TRUE(ext1_result->bfwCompMeth == ext1_params->bfwCompMeth);
N = ext1_params->bfwNumber;
switch(ext1_params->bfwCompMeth) {
case XRAN_BFWCOMPMETHOD_BLKFLOAT:
+ //printf("[%d, %d] %d == %d\n",i, j, ext1_result->bfwCompParam.exponent, ext1_params->bfwCompParam.exponent);
EXPECT_TRUE(ext1_result->bfwCompParam.exponent == ext1_params->bfwCompParam.exponent);
break;
iq_size = N*ext1_params->bfwiqWidth*2; // total in bits
parm_size = iq_size>>3; // total in bytes (/8)
if(iq_size%8) parm_size++; // round up
- EXPECT_TRUE(std::memcmp(ext1_result->p_bfwIQ, ext1_params->p_bfwIQ, parm_size));
-
+ EXPECT_FALSE(std::memcmp(ext1_result->p_bfwIQ, ext1_params->p_bfwIQ, parm_size));
}
break;
}
break;
+ case XRAN_CP_SECTIONEXTCMD_3:
+ {
+ struct xran_sectionext3_info *ext3_params, *ext3_result;
+
+ ext3_params = (struct xran_sectionext3_info *)m_params.sections[i].exData[j].data;
+ ext3_result = (struct xran_sectionext3_info *)m_result.sections[i].exData[j].data;
+
+ EXPECT_TRUE(ext3_result->layerId == ext3_params->layerId);
+ EXPECT_TRUE(ext3_result->codebookIdx== ext3_params->codebookIdx);
+ EXPECT_TRUE(ext3_result->numLayers == ext3_params->numLayers);
+
+ if(ext3_params->layerId == XRAN_LAYERID_0
+ || ext3_params->layerId == XRAN_LAYERID_TXD) { /* first data layer */
+ EXPECT_TRUE(ext3_result->txScheme == ext3_params->txScheme);
+ EXPECT_TRUE(ext3_result->crsReMask == ext3_params->crsReMask);
+ EXPECT_TRUE(ext3_result->crsShift == ext3_params->crsShift);
+ EXPECT_TRUE(ext3_result->crsSymNum == ext3_params->crsSymNum);
+
+ EXPECT_TRUE(ext3_result->numAntPort == ext3_params->numAntPort);
+
+ EXPECT_TRUE(ext3_result->beamIdAP1 == ext3_params->beamIdAP1);
+
+ if(ext3_params->numAntPort == 4) {
+ EXPECT_TRUE(ext3_result->beamIdAP2 == ext3_params->beamIdAP2);
+ EXPECT_TRUE(ext3_result->beamIdAP3 == ext3_params->beamIdAP3);
+ }
+ }
+ }
+ break;
+
case XRAN_CP_SECTIONEXTCMD_4:
{
struct xran_sectionext4_info *ext4_params, *ext4_result;
EXPECT_TRUE(ext4_result->modCompScaler == ext4_params->modCompScaler);
}
break;
+
case XRAN_CP_SECTIONEXTCMD_5:
{
struct xran_sectionext5_info *ext5_params, *ext5_result;
TEST_P(C_plane, Section_Ext1)
{
int i = 0, idRb;
- int32_t len = 0;
int16_t *ptr = NULL;
int32_t nRbs = 36;
- int32_t nAntElm = 32;
+ int32_t nAntElm = 64;
int8_t iqWidth = 16;
int8_t compMethod = XRAN_COMPMETHOD_NONE;
int8_t *p_ext1_dst = NULL;
- int16_t *bfw_payload = NULL;
+ int8_t *bfw_payload = NULL;
int32_t expected_len = (3+1)*nRbs + nAntElm*nRbs*4;
+ int16_t ext_len = 9600;
+ int16_t ext_sec_total = 0;
+ int8_t * ext_buf = nullptr;
+ int8_t * ext_buf_init = nullptr;
+
struct xran_section_gen_info* loc_pSectGenInfo = m_params.sections;
- struct xran_sectionext1_info m_ext1;
+ struct xran_sectionext1_info m_prep_ext1;
struct xran_cp_radioapp_section_ext1 *p_ext1;
+ struct rte_mbuf_ext_shared_info share_data;
+ struct rte_mbuf *mbuf = NULL;
/* Configure section information */
- if(prepare_sections(false) < 0) {
+ if(prepare_sections() < 0) {
FAIL() << "Invalid Section configuration\n";
}
- ptr = m_p_bfw_iq_src;
- for (idRb =0; idRb < nRbs*nAntElm*2; idRb++){
- ptr[idRb] = i;
- i++;
+ if(prepare_extensions() < 0) {
+ FAIL() << "Invalid Section extension configuration\n";
}
- len = xran_cp_populate_section_ext_1(m_p_ext1_dst,
- m_ext1_dst_len,
- m_p_bfw_iq_src,
- nRbs,
- nAntElm,
- iqWidth,
- compMethod);
-
- ASSERT_TRUE(len == expected_len);
+ if(loc_pSectGenInfo->info.type == XRAN_CP_SECTIONTYPE_1) {
+ /* extType 1 only with Section 1 for now */
- p_ext1_dst = m_p_ext1_dst;
- idRb = 0;
- do {
- p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst;
- bfw_payload = (int16_t*)(p_ext1+1);
- p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
- idRb++;
- }while(p_ext1->ef != XRAN_EF_F_LAST);
+ ext_buf = ext_buf_init = (int8_t*) xran_malloc(ext_len);
+ if (ext_buf) {
+ ptr = m_p_bfw_iq_src;
- ASSERT_TRUE(idRb == nRbs);
-
- /* Update section information */
- memset(&m_ext1, 0, sizeof (struct xran_sectionext1_info));
- m_ext1.bfwNumber = nAntElm;
- m_ext1.bfwiqWidth = iqWidth;
- m_ext1.bfwCompMeth = compMethod;
- m_ext1.p_bfwIQ = (int16_t*)m_p_ext1_dst;
- m_ext1.bfwIQ_sz = len;
-
- loc_pSectGenInfo->exData[0].type = XRAN_CP_SECTIONEXTCMD_1;
- loc_pSectGenInfo->exData[0].len = sizeof(m_ext1);
- loc_pSectGenInfo->exData[0].data = &m_ext1;
-
- loc_pSectGenInfo->info.ef = 1;
- loc_pSectGenInfo->exDataSize = 1;
+ for (idRb =0; idRb < nRbs*nAntElm*2; idRb++){
+ ptr[idRb] = i;
+ i++;
+ }
- m_params.numSections = 1;
+ ext_buf += (RTE_PKTMBUF_HEADROOM +
+ sizeof (struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_common_header) +
+ sizeof(struct xran_cp_radioapp_section1));
+
+ ext_len -= (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_common_header) +
+ sizeof(struct xran_cp_radioapp_section1));
+
+ ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
+ ext_len,
+ m_p_bfw_iq_src,
+ nRbs,
+ nAntElm,
+ iqWidth,
+ compMethod);
+
+ ASSERT_TRUE(ext_sec_total == expected_len);
+ p_ext1_dst = ext_buf;
+
+ memset(&m_temp_ext1[0], 0, sizeof (struct xran_sectionext1_info)*XRAN_MAX_PRBS);
+
+ idRb = 0;
+ do {
+ p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst;
+ bfw_payload = (int8_t*)(p_ext1+1);
+ p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+
+ m_temp_ext1[idRb].bfwNumber = nAntElm;
+ m_temp_ext1[idRb].bfwiqWidth = iqWidth;
+ m_temp_ext1[idRb].bfwCompMeth = compMethod;
+ m_temp_ext1[idRb].p_bfwIQ = (int16_t*)bfw_payload;
+ m_temp_ext1[idRb].bfwIQ_sz = p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+
+ loc_pSectGenInfo->exData[idRb].type = XRAN_CP_SECTIONEXTCMD_1;
+ loc_pSectGenInfo->exData[idRb].len = sizeof(m_temp_ext1[idRb]);
+ loc_pSectGenInfo->exData[idRb].data = &m_temp_ext1[idRb];
+
+ idRb++;
+ }while(p_ext1->ef != XRAN_EF_F_LAST);
+ ASSERT_TRUE(idRb == nRbs);
+
+ mbuf = xran_attach_cp_ext_buf(ext_buf_init, ext_buf, ext_sec_total, &share_data);
+
+ /* Update section information */
+ memset(&m_prep_ext1, 0, sizeof (struct xran_sectionext1_info));
+ m_prep_ext1.bfwNumber = nAntElm;
+ m_prep_ext1.bfwiqWidth = iqWidth;
+ m_prep_ext1.bfwCompMeth = compMethod;
+ m_prep_ext1.p_bfwIQ = (int16_t*)ext_buf;
+ m_prep_ext1.bfwIQ_sz = ext_sec_total;
+
+
+ loc_pSectGenInfo->exData[0].type = XRAN_CP_SECTIONEXTCMD_1;
+ loc_pSectGenInfo->exData[0].len = sizeof(m_prep_ext1);
+ loc_pSectGenInfo->exData[0].data = &m_prep_ext1;
+
+ loc_pSectGenInfo->info.ef = 1;
+ loc_pSectGenInfo->exDataSize = 1; /* append all extType1 as one shot
+ (as generated via xran_cp_populate_section_ext_1)*/
+
+ m_params.numSections = 1;
+
+ /* Generating C-Plane packet */
+ ASSERT_TRUE(xran_prepare_ctrl_pkt(/*m_pTestBuffer*/mbuf, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
+
+ /** to match O-RU parsing */
+ loc_pSectGenInfo->exDataSize = nRbs;
+ loc_pSectGenInfo->exData[0].len = sizeof(m_temp_ext1[0]);
+ loc_pSectGenInfo->exData[0].data = &m_temp_ext1[0];
+
+ /* Parsing generated packet */
+ EXPECT_TRUE(xran_parse_cp_pkt(/*m_pTestBuffer*/mbuf, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS);
+ } else {
+ FAIL() << "xran_malloc failed\n";
+ }
- /* Generating C-Plane packet */
- ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
+ /* Verify the result */
+ verify_sections();
- /* Parsing generated packet */
- EXPECT_TRUE(xran_parse_cp_pkt(m_pTestBuffer, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS);
-
- /* Verify the result */
- //verify_sections();
+ if(ext_buf_init)
+ xran_free(ext_buf_init);
+ }
}
TEST_P(C_plane, Section_Ext1_9bit)
{
int i = 0, idRb;
- int32_t len = 0;
int16_t *ptr = NULL;
int32_t nRbs = 36;
- int32_t nAntElm = 32;
+ int32_t nAntElm = 64;
int8_t iqWidth = 9;
int8_t compMethod = XRAN_COMPMETHOD_BLKFLOAT;
int8_t *p_ext1_dst = NULL;
- int16_t *bfw_payload = NULL;
+ int8_t *bfw_payload = NULL;
int32_t expected_len = ((nAntElm/16*4*iqWidth)+1)*nRbs + /* bfwCompParam + IQ = */
sizeof(struct xran_cp_radioapp_section_ext1)*nRbs; /* ext1 Headers */
+ int16_t ext_len = 9600;
+ int16_t ext_sec_total = 0;
+ int8_t * ext_buf = nullptr;
+ int8_t * ext_buf_init = nullptr;
+
struct xran_section_gen_info* loc_pSectGenInfo = m_params.sections;
- struct xran_sectionext1_info m_ext1;
+ struct xran_sectionext1_info m_prep_ext1;
struct xran_cp_radioapp_section_ext1 *p_ext1;
+ struct rte_mbuf_ext_shared_info share_data;
+ struct rte_mbuf *mbuf = NULL;
/* Configure section information */
- if(prepare_sections(false) < 0) {
+ if(prepare_sections() < 0) {
FAIL() << "Invalid Section configuration\n";
}
- ptr = m_p_bfw_iq_src;
- for (idRb =0; idRb < nRbs*nAntElm*2; idRb++){
- ptr[idRb] = i;
- i++;
+ if(prepare_extensions() < 0) {
+ FAIL() << "Invalid Section extension configuration\n";
}
- len = xran_cp_populate_section_ext_1(m_p_ext1_dst,
- m_ext1_dst_len,
- m_p_bfw_iq_src,
- nRbs,
- nAntElm,
- iqWidth,
- compMethod);
+ if(loc_pSectGenInfo->info.type == XRAN_CP_SECTIONTYPE_1) {
+ /* extType 1 only with Section 1 for now */
+
+ ext_buf = ext_buf_init = (int8_t*) xran_malloc(ext_len);
+ if (ext_buf) {
+ ptr = m_p_bfw_iq_src;
- ASSERT_TRUE(len == expected_len);
+ for (idRb =0; idRb < nRbs*nAntElm*2; idRb++){
+ ptr[idRb] = i;
+ i++;
+ }
- p_ext1_dst = m_p_ext1_dst;
- idRb = 0;
- do {
- p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst;
- bfw_payload = (int16_t*)(p_ext1+1);
- p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
- idRb++;
- }while(p_ext1->ef != XRAN_EF_F_LAST);
+ ext_buf += (RTE_PKTMBUF_HEADROOM +
+ sizeof (struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_common_header) +
+ sizeof(struct xran_cp_radioapp_section1));
- ASSERT_TRUE(idRb == nRbs);
+ ext_len -= (RTE_PKTMBUF_HEADROOM +
+ sizeof(struct xran_ecpri_hdr) +
+ sizeof(struct xran_cp_radioapp_common_header) +
+ sizeof(struct xran_cp_radioapp_section1));
- /* Update section information */
- memset(&m_ext1, 0, sizeof (struct xran_sectionext1_info));
- m_ext1.bfwNumber = nAntElm;
- m_ext1.bfwiqWidth = iqWidth;
- m_ext1.bfwCompMeth = compMethod;
- m_ext1.p_bfwIQ = (int16_t*)m_p_ext1_dst;
- m_ext1.bfwIQ_sz = len;
+ ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
+ ext_len,
+ m_p_bfw_iq_src,
+ nRbs,
+ nAntElm,
+ iqWidth,
+ compMethod);
- loc_pSectGenInfo->exData[0].type = XRAN_CP_SECTIONEXTCMD_1;
- loc_pSectGenInfo->exData[0].len = sizeof(m_ext1);
- loc_pSectGenInfo->exData[0].data = &m_ext1;
+ ASSERT_TRUE(ext_sec_total == expected_len);
+ p_ext1_dst = ext_buf;
- loc_pSectGenInfo->info.ef = 1;
- loc_pSectGenInfo->exDataSize = 1;
+ memset(&m_temp_ext1[0], 0, sizeof (struct xran_sectionext1_info)*XRAN_MAX_PRBS);
- m_params.numSections = 1;
+ idRb = 0;
+ do {
+ p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst;
+ bfw_payload = (int8_t*)(p_ext1+1);
+ p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
- /* Generating C-Plane packet */
- ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
+ m_temp_ext1[idRb].bfwNumber = nAntElm;
+ m_temp_ext1[idRb].bfwiqWidth = iqWidth;
+ m_temp_ext1[idRb].bfwCompMeth = compMethod;
- /* Parsing generated packet */
- EXPECT_TRUE(xran_parse_cp_pkt(m_pTestBuffer, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS);
+ m_temp_ext1[idRb].bfwCompParam.exponent = *bfw_payload++ & 0xF;
- /* Verify the result */
- //verify_sections();
-}
+ m_temp_ext1[idRb].p_bfwIQ = (int16_t*)bfw_payload;
+ m_temp_ext1[idRb].bfwIQ_sz = p_ext1->extLen*XRAN_SECTIONEXT_ALIGN;
+ loc_pSectGenInfo->exData[idRb].type = XRAN_CP_SECTIONEXTCMD_1;
+ loc_pSectGenInfo->exData[idRb].len = sizeof(m_temp_ext1[idRb]);
+ loc_pSectGenInfo->exData[idRb].data = &m_temp_ext1[idRb];
+ idRb++;
+ }while(p_ext1->ef != XRAN_EF_F_LAST);
+ ASSERT_TRUE(idRb == nRbs);
-TEST_P(C_plane, PacketGen)
-{
- int i;
+ mbuf = xran_attach_cp_ext_buf(ext_buf_init, ext_buf, ext_sec_total, &share_data);
+
+ /* Update section information */
+ memset(&m_prep_ext1, 0, sizeof (struct xran_sectionext1_info));
+ m_prep_ext1.bfwNumber = nAntElm;
+ m_prep_ext1.bfwiqWidth = iqWidth;
+ m_prep_ext1.bfwCompMeth = compMethod;
+ m_prep_ext1.p_bfwIQ = (int16_t*)ext_buf;
+ m_prep_ext1.bfwIQ_sz = ext_sec_total;
+
+
+ loc_pSectGenInfo->exData[0].type = XRAN_CP_SECTIONEXTCMD_1;
+ loc_pSectGenInfo->exData[0].len = sizeof(m_prep_ext1);
+ loc_pSectGenInfo->exData[0].data = &m_prep_ext1;
+ loc_pSectGenInfo->info.ef = 1;
+ loc_pSectGenInfo->exDataSize = 1; /* append all extType1 as one shot
+ (as generated via xran_cp_populate_section_ext_1)*/
+ m_params.numSections = 1;
+
+ /* Generating C-Plane packet */
+ ASSERT_TRUE(xran_prepare_ctrl_pkt(/*m_pTestBuffer*/mbuf, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
+
+ /** to match O-RU parsing */
+ loc_pSectGenInfo->exDataSize = nRbs;
+ loc_pSectGenInfo->exData[0].len = sizeof(m_temp_ext1[0]);
+ loc_pSectGenInfo->exData[0].data = &m_temp_ext1[0];
+
+ /* Parsing generated packet */
+ EXPECT_TRUE(xran_parse_cp_pkt(/*m_pTestBuffer*/mbuf, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS);
+ } else {
+ FAIL() << "xran_malloc failed\n";
+ }
+
+ /* Verify the result */
+ verify_sections();
+
+ if(ext_buf_init)
+ xran_free(ext_buf_init);
+ }
+}
+
+
+TEST_P(C_plane, PacketGen)
+{
/* Configure section information */
- if(prepare_sections(false) < 0) {
+ if(prepare_sections() < 0) {
FAIL() << "Invalid Section configuration\n";
}
+ if(prepare_extensions() < 0) {
+ FAIL() << "Invalid Section extension configuration\n";
+ }
/* Generating C-Plane packet */
ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS);
TEST_P(C_plane, PacketGen_Ext)
{
- int i;
-
-
/* Configure section information */
- if(prepare_sections(true) < 0) {
+ if(prepare_sections() < 0) {
FAIL() << "Invalid Section configuration\n";
}
/***************************************************************************
* Performance Test cases
***************************************************************************/
+
TEST_P(C_plane, Perf)
{
/* Configure section information */
- if(prepare_sections(false) < 0) {
+ if(prepare_sections() < 0) {
FAIL() << "Invalid Section configuration\n";
}
+ if(prepare_extensions() < 0) {
+ FAIL() << "Invalid Section extension configuration\n";
+ }
/* using wrapper function to reset mbuf */
performance("C", module_name,
&xran_ut_prepare_cp, m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId);
}
+
TEST_P(C_plane, Perf_Ext)
{
/* Configure section information */
- if(prepare_sections(true) < 0) {
+ if(prepare_sections() < 0) {
FAIL() << "Invalid Section configuration\n";
}
&xran_ut_prepare_cp, m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId);
}
-
INSTANTIATE_TEST_CASE_P(UnitTest, C_plane,
testing::ValuesIn(get_sequence(C_plane::get_number_of_cases("C_Plane"))));
/* call back functions */
-int send_mbuf_up(struct rte_mbuf *mbuf, uint16_t type)
+int send_mbuf_up(struct rte_mbuf *mbuf, uint16_t type, uint16_t vf_id)
{
rte_pktmbuf_free(mbuf);
return (1);
}
-int send_mbuf_cp_perf(struct rte_mbuf *mbuf, uint16_t type)
+int send_mbuf_cp_perf(struct rte_mbuf *mbuf, uint16_t type, uint16_t vf_id)
{
rte_pktmbuf_free(mbuf);
return (1);
return;
}
+void utcp_fh_srs_callback(void *pCallbackTag, xran_status_t status)
+{
+ return;
+}
+
void utcp_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
{
rte_pause();
{
xranlib->Init(&m_xranConf);
xranlib->Open(send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_cp_dl);
{
xranlib->Init(&m_xranConf);
xranlib->Open(send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_cp_ul);
/* need to disable CP to make U-Plane work without CP */
xranlib->apply_cpenable(false);
xranlib->Open(send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_up_dl);
/* Enable CP by force to make UP work by CP's section information */
xranlib->apply_cpenable(true);
xranlib->Open(send_mbuf_cp_perf, send_mbuf_up,
- (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback);
+ (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback);
performance("C", module_name, xran_ut_tx_cpup_dl);
for (int n = 0; n < numVals; ++n)
{
if (std::abs(inVec1[n] & 0xFF00) - std::abs(inVec2[n] & 0xFF00)){;
- printf("%d %d\n", inVec1[n] & 0xFF00, inVec2[n] & 0xFF00);
+ printf("[%d]: %d %d\n",n, inVec1[n] & 0xFF00, inVec2[n] & 0xFF00);
checkSum += 1;
}
}
}
};
-class BfpPerf : public KernelTests
-{
-protected:
- void SetUp() override {
- init_test("bfp_performace");
- }
-
- /* It's called after an execution of the each test case.*/
- void TearDown() override {
- }
-};
-CACHE_ALIGNED int16_t loc_dataExpandedIn[288*BlockFloatCompander::k_numREReal];
-CACHE_ALIGNED int16_t loc_dataExpandedRes[288*BlockFloatCompander::k_numREReal];
-CACHE_ALIGNED uint8_t loc_dataCompressedDataOut[2*288*BlockFloatCompander::k_numREReal];
+CACHE_ALIGNED int16_t loc_dataExpandedIn[288*128];
+CACHE_ALIGNED int16_t loc_dataExpandedRes[288*128];
+CACHE_ALIGNED uint8_t loc_dataCompressedDataOut[2*288*128];
class BfpPerfEx : public KernelTests
{
//printf("iqWidth %d numRBs %d\n", iqWidth, numRBs);
- for (int m = 0; m < 18*BlockFloatCompander::k_numRB; ++m) {
+ for (int m = 0; m < 18*BlockFloatCompander::k_maxNumBlocks; ++m) {
auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n) {
- expandedData.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
+ for (int n = 0; n < 24; ++n) {
+ expandedData.dataExpanded[m*24+n] = int16_t(randInt16(gen) >> shiftVal);
}
}
BlockFloatCompander::CompressedData compressedData;
compressedData.dataCompressed = &loc_dataCompressedDataOut[0];
- std::memset(&loc_dataCompressedDataOut[0], 0, 288*BlockFloatCompander::k_numREReal);
- std::memset(&loc_dataExpandedRes[0], 0, 288*BlockFloatCompander::k_numREReal);
+ std::memset(&loc_dataCompressedDataOut[0], 0, 288*24);
+ std::memset(&loc_dataExpandedRes[0], 0, 288*24);
std::memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request));
std::memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
}
};
-TEST_P(BfpCheck, AVX512_12bit)
-{
- int resSum = 0;
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
-
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
- {
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
- }
+class BfpPerfCp : public KernelTests
+{
+protected:
+ struct xranlib_decompress_request bfp_decom_req;
+ struct xranlib_decompress_response bfp_decom_rsp;
+ struct xranlib_compress_request bfp_com_req;
+ struct xranlib_compress_response bfp_com_rsp;
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 12b iqWidth Kernel\n";
- expandedDataInput.iqWidth = 12;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_12b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_12b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-}
+ void SetUp() override {
+ init_test("bfp_performace_cp");
+ int32_t resSum = 0;
+ int16_t len = 0;
+ int16_t compMethod = XRAN_COMPMETHOD_BLKFLOAT;
+ int16_t iqWidth = get_input_parameter<int16_t>("iqWidth");
+ int16_t AntElm = get_input_parameter<int16_t>("AntElm");
+ int16_t numDataElements = 0;
+ int16_t numRBs = 1;
+ // Create random number generator
+ std::random_device rd;
+ std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
+ std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
+ std::uniform_int_distribution<int> randExpShift(0, 4);
-TEST_P(BfpCheck, AVX512_10bit)
-{
- int resSum = 0;
+ BlockFloatCompander::ExpandedData expandedData;
+ expandedData.dataExpanded = &loc_dataExpandedIn[0];
+ BlockFloatCompander::ExpandedData expandedDataRes;
+ expandedDataRes.dataExpanded = &loc_dataExpandedRes[0];
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
+ //printf("iqWidth %d numRBs %d\n", iqWidth, numRBs);
+ numDataElements = 2*AntElm;
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
- {
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
+ // Generate input data
+ for (int m = 0; m < numRBs; ++m)
{
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
+ auto shiftVal = randExpShift(gen);
+ for (int n = 0; n < numDataElements; ++n)
+ {
+ expandedData.dataExpanded[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal);
+ }
}
- }
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 10b iqWidth Kernel\n";
- expandedDataInput.iqWidth = 10;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_10b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_10b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
-// performance("AVX512", module_name, BlockFloatCompander::BlockFloatCompress_10b_AVX512, expandedDataInput, &compressedDataKern);
-}
+ BlockFloatCompander::CompressedData compressedData;
+ compressedData.dataCompressed = &loc_dataCompressedDataOut[0];
-TEST_P(BfpCheck, AVX512_9bit)
-{
- int resSum = 0;
+ std::memset(&loc_dataCompressedDataOut[0], 0, 288*128);
+ std::memset(&loc_dataExpandedRes[0], 0, 288*128);
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
+ std::memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request));
+ std::memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
+ std::memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
+ std::memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
- {
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
- }
+ bfp_com_req.data_in = (int16_t *)expandedData.dataExpanded;
+ bfp_com_req.numRBs = numRBs;
+ bfp_com_req.numDataElements = numDataElements;
+ bfp_com_req.len = AntElm*4;
+ bfp_com_req.compMethod = compMethod;
+ bfp_com_req.iqWidth = iqWidth;
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 9b iqWidth Kernel\n";
- expandedDataInput.iqWidth = 9;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_9b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_9b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-}
+ bfp_com_rsp.data_out = (int8_t *)(compressedData.dataCompressed);
+ bfp_com_rsp.len = 0;
+ bfp_decom_req.data_in = (int8_t *)(compressedData.dataCompressed);
+ bfp_decom_req.numRBs = numRBs;
+ bfp_decom_req.numDataElements = numDataElements;
+ bfp_decom_req.len = (((numDataElements * iqWidth) >> 3) + 1) * numRBs;
+ bfp_decom_req.compMethod = compMethod;
+ bfp_decom_req.iqWidth = iqWidth;
-TEST_P(BfpCheck, AVX512_8bit)
-{
- int resSum = 0;
+ bfp_decom_rsp.data_out = (int16_t *)expandedDataRes.dataExpanded;
+ bfp_decom_rsp.len = 0;
+ }
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
+ /* It's called after an execution of the each test case.*/
+ void TearDown() override {
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
- {
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
}
+};
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 8;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_8b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_8b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-}
-
-TEST_P(BfpPerf, AVX512_8bit_compression)
+struct ErrorData
{
- int resSum = 0;
-
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
+ int checkSum;
+ float errorAccum;
+ int errorCount;
+};
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+template <typename T>
+void compareData(T* inVecRef, T* inVecTest, ErrorData& err, int numVals)
+{
+ for (int n = 0; n < numVals; ++n)
+ {
+ auto valDiff = std::abs(inVecRef[n] - inVecTest[n]);
+ err.checkSum += valDiff;
+ if (inVecRef[n] != 0)
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ err.errorAccum += (float)valDiff / std::abs((float)inVecRef[n]);
+ err.errorCount++;
}
-
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 8;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_8b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_8b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatCompress_8b_AVX512, expandedDataInput, &compressedDataKern);
+ }
}
+template void compareData(int8_t*, int8_t*, ErrorData&, int);
+template void compareData(int16_t*, int16_t*, ErrorData&, int);
-TEST_P(BfpPerf, AVX512_8bit_decompression)
+int checkPass(ErrorData& err, int testType)
{
- int resSum = 0;
-
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
-
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+ if (testType == 0)
+ {
+ if (err.checkSum == 0)
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ /*std::cout << "PASS "; */
+ return 0;
}
-
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 8;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_8b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_8b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatExpand_8b_AVX512, compressedDataRef, &expandedDataKern);
-}
-
-
-
-TEST_P(BfpPerf, AVX512_9bit_compression)
-{
- int resSum = 0;
-
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
-
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+ else
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ std::cout << "FAIL ";
+ return 1;
}
-
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 9;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_9b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_9b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatCompress_9b_AVX512, expandedDataInput, &compressedDataKern);
-}
-
-
-TEST_P(BfpPerf, AVX512_9bit_decompression)
-{
- int resSum = 0;
-
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
-
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+ }
+ else
+ {
+ //std::cout << err.errorAccum / err.errorCount;
+ if (err.errorAccum / err.errorCount < 0.1)
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ /*std::cout << " PASS ";*/
+ return 0;
}
-
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 9;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_9b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_9b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatExpand_9b_AVX512, compressedDataRef, &expandedDataKern);
-}
-
-
-TEST_P(BfpPerf, AVX512_10bit_compression)
-{
- int resSum = 0;
-
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
-
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+ else
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ std::cout << " FAIL ";
+ return 1;
}
-
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 10;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_10b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_10b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatCompress_10b_AVX512, expandedDataInput, &compressedDataKern);
+ }
}
-TEST_P(BfpPerf, AVX512_10bit_decompression)
+int runTest(const int iqWidth, const int numRB, const int numDataElements, const int totNumBlocks)
{
- int resSum = 0;
+ BlockFloatCompander::ExpandedData expandedDataInput;
+ BlockFloatCompander::CompressedData compressedDataRef;
+ BlockFloatCompander::CompressedData compressedDataKern;
+ BlockFloatCompander::ExpandedData expandedDataRef;
+ BlockFloatCompander::ExpandedData expandedDataKern;
+
+ ErrorData errRef = ErrorData();
+ ErrorData errComp = ErrorData();
+ ErrorData errExp = ErrorData();
// Create random number generator
std::random_device rd;
std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
+ std::uniform_int_distribution<int16_t> randInt16(-32767, 32767);
std::uniform_int_distribution<int> randExpShift(0, 4);
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+ expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
+ compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
+ compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
+ expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
+ expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
+
+ expandedDataInput.iqWidth = iqWidth;
+ expandedDataInput.numBlocks = numRB;
+ expandedDataInput.numDataElements = numDataElements;
+ int totExpValsPerCall = numRB * numDataElements;
+ int totCompValsPerCall = (((numDataElements * iqWidth) >> 3) + 1) * numRB;
+
+ // Run kernel verif loop
+ for (int blk = 0; blk < totNumBlocks; ++blk)
+ {
+ // Generate input data
+ for (int m = 0; m < numRB; ++m)
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ auto shiftVal = randExpShift(gen);
+ for (int n = 0; n < numDataElements; ++n)
+ {
+ expandedDataInput.dataExpanded[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal);
+ }
}
-
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 10;
// Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
+ BlockFloatCompander::BFPCompressRef(expandedDataInput, &compressedDataRef);
+ BlockFloatCompander::BFPExpandRef(compressedDataRef, &expandedDataRef);
// Generate kernel output
- BlockFloatCompander::BlockFloatCompress_10b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_10b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatExpand_10b_AVX512, compressedDataRef, &expandedDataKern);
+ switch (numDataElements)
+ {
+ case 16:
+ BlockFloatCompander::BFPCompressCtrlPlane8Avx512(expandedDataInput, &compressedDataKern);
+ BlockFloatCompander::BFPExpandCtrlPlane8Avx512(compressedDataRef, &expandedDataKern);
+ break;
+ case 24:
+ BlockFloatCompander::BFPCompressUserPlaneAvx512(expandedDataInput, &compressedDataKern);
+ BlockFloatCompander::BFPExpandUserPlaneAvx512(compressedDataRef, &expandedDataKern);
+ break;
+ case 32:
+ BlockFloatCompander::BFPCompressCtrlPlane16Avx512(expandedDataInput, &compressedDataKern);
+ BlockFloatCompander::BFPExpandCtrlPlane16Avx512(compressedDataRef, &expandedDataKern);
+ break;
+ case 64:
+ BlockFloatCompander::BFPCompressCtrlPlane32Avx512(expandedDataInput, &compressedDataKern);
+ BlockFloatCompander::BFPExpandCtrlPlane32Avx512(compressedDataRef, &expandedDataKern);
+ break;
+ case 128:
+ BlockFloatCompander::BFPCompressCtrlPlane64Avx512(expandedDataInput, &compressedDataKern);
+ BlockFloatCompander::BFPExpandCtrlPlane64Avx512(compressedDataRef, &expandedDataKern);
+ break;
+ }
+ // Check data
+ compareData(expandedDataInput.dataExpanded, expandedDataRef.dataExpanded, errRef, totExpValsPerCall);
+ compareData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, errComp, totCompValsPerCall);
+ compareData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, errRef, totExpValsPerCall);
+ }
+ // Verify Reference
+ int resSum = 0;
+ /*std::cout << "Valid Reference: ";*/
+ resSum += checkPass(errRef, 1);
+ // Verify Kernel
+ /*std::cout << "Compression: ";*/
+ resSum += checkPass(errComp, 0);
+ /*std::cout << "Expansion: ";*/
+ resSum += checkPass(errExp, 0);
+ /*std::cout << "\n";*/
+
+ return resSum;
}
-TEST_P(BfpPerf, AVX512_12bit_compression)
+TEST_P(BfpCheck, AVX512_bfp_main)
{
int resSum = 0;
-
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
-
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
+ int iqWidth[4] = { 8, 9, 10, 12 };
+ int numRB[3] = { 1, 4, 16 };
+ int numDataElementsUPlane = 24;
+ int numDataElementsCPlane8 = 16;
+ int numDataElementsCPlane16 = 32;
+ int numDataElementsCPlane32 = 64;
+ int numDataElementsCPlane64 = 128;
+ int totNumBlocks = 100;
+
+ for (int iqw = 0; iqw < 4; ++iqw)
+ {
+ for (int nrb = 0; nrb < 3; ++nrb)
{
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
- }
+ //std::cout << "\n";
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 12;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_12b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_12b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatCompress_12b_AVX512, expandedDataInput, &compressedDataKern);
-}
+ // USER PLANE TESTS
+ //std::cout << "U-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsUPlane << ": ";
+ resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsUPlane, totNumBlocks);
+ // CONTROL PLANE TESTS : 8 Antennas
+ //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane8 << ": ";
+ resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane8, totNumBlocks);
-TEST_P(BfpPerf, AVX512_12bit_decompression)
-{
- int resSum = 0;
+ // CONTROL PLANE TESTS : 16 Antennas
+ //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane16 << ": ";
+ resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane16, totNumBlocks);
- // Create random number generator
- std::random_device rd;
- std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
- std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
- std::uniform_int_distribution<int> randExpShift(0, 4);
+ // CONTROL PLANE TESTS : 32 Antennas
+ //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane32 << ": ";
+ resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane32, totNumBlocks);
- // Generate random test data for compression kernel
- BlockFloatCompander::ExpandedData expandedDataInput;
- expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0];
- for (int m = 0; m < BlockFloatCompander::k_numRB; ++m)
- {
- auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n)
- {
- expandedDataInput.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
- }
+ // CONTROL PLANE TESTS : 64 Antennas
+ //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane64 << ": ";
+ resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane64, totNumBlocks);
}
+ }
- BlockFloatCompander::CompressedData compressedDataRef;
- compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataRef;
- expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0];
- BlockFloatCompander::CompressedData compressedDataKern;
- compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0];
- BlockFloatCompander::ExpandedData expandedDataKern;
- expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0];
-
- //std::cout << "Verifying AVX512 8bit Kernel\n";
- expandedDataInput.iqWidth = 12;
- // Generate reference
- BlockFloatCompander::BlockFloatCompress_Basic(expandedDataInput, &compressedDataRef);
- BlockFloatCompander::BlockFloatExpand_Basic(compressedDataRef, &expandedDataRef);
- // Generate kernel output
- BlockFloatCompander::BlockFloatCompress_12b_AVX512(expandedDataInput, &compressedDataKern);
- BlockFloatCompander::BlockFloatExpand_12b_AVX512(compressedDataRef, &expandedDataKern);
- // Verify
- auto totNumBytes = ((3 * compressedDataRef.iqWidth) + 1) * BlockFloatCompander::k_numRB;
- //std::cout << "Compression: ";
- resSum += checkData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, totNumBytes);
- //std::cout << "Expansion: ";
- resSum += checkData(expandedDataRef.dataExpanded, expandedDataKern.dataExpanded, BlockFloatCompander::k_numSampsExpanded);
-
- ASSERT_EQ(0, resSum);
-
- performance("AVX512", module_name, BlockFloatCompander::BlockFloatExpand_12b_AVX512, compressedDataRef, &expandedDataKern);
+ ASSERT_EQ(0, resSum);
}
TEST_P(BfpCheck, AVX512_sweep_xranlib)
struct xranlib_compress_request bfp_com_req;
struct xranlib_compress_response bfp_com_rsp;
+ int numDataElements = 24;
+
// Create random number generator
std::random_device rd;
std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
//printf("[%d]numRBs %d [%d] iqWidth %d\n",tc, numRBs[tc], iq_w_id, iqWidth[iq_w_id]);
// Generate random test data for compression kernel
- for (int m = 0; m < 18*BlockFloatCompander::k_numRB; ++m) {
+ for (int m = 0; m < 18*BlockFloatCompander::k_maxNumBlocks; ++m) {
auto shiftVal = randExpShift(gen);
- for (int n = 0; n < BlockFloatCompander::k_numREReal; ++n) {
- expandedData.dataExpanded[m*BlockFloatCompander::k_numREReal+n] = int16_t(randInt16(gen) >> shiftVal);
+ for (int n = 0; n < numDataElements; ++n) {
+ expandedData.dataExpanded[m*numDataElements+n] = int16_t(randInt16(gen) >> shiftVal);
}
}
BlockFloatCompander::CompressedData compressedData;
compressedData.dataCompressed = &loc_dataCompressedDataOut[0];
- std::memset(&loc_dataCompressedDataOut[0], 0, 288*BlockFloatCompander::k_numREReal);
- std::memset(&loc_dataExpandedRes[0], 0, 288*BlockFloatCompander::k_numREReal);
+ std::memset(&loc_dataCompressedDataOut[0], 0, 288*numDataElements);
+ std::memset(&loc_dataExpandedRes[0], 0, 288*numDataElements);
std::memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request));
std::memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
bfp_com_req.data_in = (int16_t *)expandedData.dataExpanded;
bfp_com_req.numRBs = numRBs[tc];
+ bfp_com_req.numDataElements = 24;
bfp_com_req.len = numRBs[tc]*12*2*2;
bfp_com_req.compMethod = compMethod;
bfp_com_req.iqWidth = iqWidth[iq_w_id];
bfp_decom_req.data_in = (int8_t *)(compressedData.dataCompressed);
bfp_decom_req.numRBs = numRBs[tc];
bfp_decom_req.len = bfp_com_rsp.len;
+ bfp_decom_req.numDataElements = 24;
bfp_decom_req.compMethod = compMethod;
bfp_decom_req.iqWidth = iqWidth[iq_w_id];
xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp);
- resSum += checkDataApprox(expandedData.dataExpanded, expandedDataRes.dataExpanded, numRBs[tc]*BlockFloatCompander::k_numREReal);
+ resSum += checkDataApprox(expandedData.dataExpanded, expandedDataRes.dataExpanded, numRBs[tc]*numDataElements);
ASSERT_EQ(numRBs[tc]*12*2*2, bfp_decom_rsp.len);
ASSERT_EQ(0, resSum);
}
}
+TEST_P(BfpCheck, AVX512_cp_sweep_xranlib)
+{
+ int32_t resSum = 0;
+ int16_t len = 0;
+
+ int16_t compMethod = XRAN_COMPMETHOD_BLKFLOAT;
+ int16_t iqWidth[] = {8, 9, 10, 12};
+ int16_t numRB = 1;
+ int16_t antElm[] = {8, 16, 32, 64};
+
+ struct xranlib_decompress_request bfp_decom_req;
+ struct xranlib_decompress_response bfp_decom_rsp;
+
+ struct xranlib_compress_request bfp_com_req;
+ struct xranlib_compress_response bfp_com_rsp;
+ int32_t numDataElements;
+
+ // Create random number generator
+ std::random_device rd;
+ std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd()
+ std::uniform_int_distribution<int16_t> randInt16(-32768, 32767);
+ std::uniform_int_distribution<int> randExpShift(0, 4);
+
+ BlockFloatCompander::ExpandedData expandedData;
+ expandedData.dataExpanded = &loc_dataExpandedIn[0];
+ BlockFloatCompander::ExpandedData expandedDataRes;
+ expandedDataRes.dataExpanded = &loc_dataExpandedRes[0];
+
+ for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){
+ for (int tc = 0; tc < sizeof(antElm)/sizeof(antElm[0]); tc ++){
+
+ numDataElements = 2*antElm[tc];
+
+ // Generate input data
+ for (int m = 0; m < numRB; ++m)
+ {
+ auto shiftVal = randExpShift(gen);
+ for (int n = 0; n < numDataElements; ++n)
+ {
+ expandedData.dataExpanded[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal);
+ }
+ }
+
+ BlockFloatCompander::CompressedData compressedData;
+ compressedData.dataCompressed = &loc_dataCompressedDataOut[0];
+
+ std::memset(&loc_dataCompressedDataOut[0], 0, 288*numDataElements);
+ std::memset(&loc_dataExpandedRes[0], 0, 288*numDataElements);
+
+ std::memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request));
+ std::memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
+ std::memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
+ std::memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
+
+ bfp_com_req.data_in = (int16_t *)expandedData.dataExpanded;
+ bfp_com_req.numRBs = numRB;
+ bfp_com_req.numDataElements = numDataElements;
+ bfp_com_req.len = antElm[tc]*4;
+ bfp_com_req.compMethod = compMethod;
+ bfp_com_req.iqWidth = iqWidth[iq_w_id];
+
+ bfp_com_rsp.data_out = (int8_t *)(compressedData.dataCompressed);
+ bfp_com_rsp.len = 0;
+
+ xranlib_compress_avx512_bfw(&bfp_com_req, &bfp_com_rsp);
+
+ bfp_decom_req.data_in = (int8_t *)(compressedData.dataCompressed);
+ bfp_decom_req.numRBs = numRB;
+ bfp_decom_req.numDataElements = numDataElements;
+ bfp_decom_req.len = bfp_com_rsp.len;
+ bfp_decom_req.compMethod = compMethod;
+ bfp_decom_req.iqWidth = iqWidth[iq_w_id];
+
+ bfp_decom_rsp.data_out = (int16_t *)expandedDataRes.dataExpanded;
+ bfp_decom_rsp.len = 0;
+
+ xranlib_decompress_avx512_bfw(&bfp_decom_req, &bfp_decom_rsp);
+
+ resSum += checkDataApprox(expandedData.dataExpanded, expandedDataRes.dataExpanded, numRB*numDataElements);
+
+ ASSERT_EQ(antElm[tc]*4, bfp_decom_rsp.len);
+ ASSERT_EQ(0, resSum);
+ }
+ }
+}
+
TEST_P(BfpPerfEx, AVX512_Comp)
{
performance("AVX512", module_name, xranlib_compress_avx512, &bfp_com_req, &bfp_com_rsp);
performance("AVX512", module_name, xranlib_decompress_avx512, &bfp_decom_req, &bfp_decom_rsp);
}
-INSTANTIATE_TEST_CASE_P(UnitTest, BfpCheck,
- testing::ValuesIn(get_sequence(BfpCheck::get_number_of_cases("bfp_functional"))));
+TEST_P(BfpPerfCp, AVX512_CpComp)
+{
+ performance("AVX512", module_name, xranlib_compress_avx512_bfw, &bfp_com_req, &bfp_com_rsp);
+}
-INSTANTIATE_TEST_CASE_P(UnitTest, BfpPerf,
- testing::ValuesIn(get_sequence(BfpPerf::get_number_of_cases("bfp_performace"))));
+TEST_P(BfpPerfCp, AVX512_CpDeComp)
+{
+ performance("AVX512", module_name, xranlib_decompress_avx512_bfw, &bfp_decom_req, &bfp_decom_rsp);
+}
+INSTANTIATE_TEST_CASE_P(UnitTest, BfpCheck,
+ testing::ValuesIn(get_sequence(BfpCheck::get_number_of_cases("bfp_functional"))));
INSTANTIATE_TEST_CASE_P(UnitTest, BfpPerfEx,
- testing::ValuesIn(get_sequence(BfpPerf::get_number_of_cases("bfp_performace_ex"))));
+ testing::ValuesIn(get_sequence(BfpPerfEx::get_number_of_cases("bfp_performace_ex"))));
+INSTANTIATE_TEST_CASE_P(UnitTest, BfpPerfCp,
+ testing::ValuesIn(get_sequence(BfpPerfCp::get_number_of_cases("bfp_performace_cp"))));
"iq_width": 16,
"comp_meth": 0,
"fft_size": 1024,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"Tadv_cp_dl": 0,
"T2a_min_cp_dl": 0,
"T2a_max_cp_dl": 0,
],
"C_Plane": [
+ {
+ "name": "DL_StockA",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 0,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 273,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0,
+ "exts": [ ]
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_StockB",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 0,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 7,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 7,
+ "numPrbc": 255,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_StockC",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 0,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 4,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 8,
+ "numPrbc": 255,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_StockD",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 6,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 1,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 1,
+ "numPrbc": 4,
+ "reMask": 2730,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 3,
+ "rb": 1,
+ "symInc": 0,
+ "startPrbc": 5,
+ "numPrbc": 10,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 4,
+ "rb": 1,
+ "symInc": 0,
+ "startPrbc": 6,
+ "numPrbc": 9,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 5,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 24,
+ "numPrbc": 46,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 6,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 66,
+ "numPrbc": 207,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_StockE",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 5,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 7,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 7,
+ "numPrbc": 255,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 3,
+ "rb": 0,
+ "symInc": 1,
+ "startPrbc": 0,
+ "numPrbc": 7,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 4,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 7,
+ "numPrbc": 255,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_StockF",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 5,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 20,
+ "reMask": 2730,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 25,
+ "numPrbc": 15,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 3,
+ "rb": 0,
+ "symInc": 1,
+ "startPrbc": 40,
+ "numPrbc": 95,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 4,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 162,
+ "numPrbc": 111,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 5,
+ "rb": 0,
+ "symInc": 1,
+ "startPrbc": 0,
+ "numPrbc": 5,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 6,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 25,
+ "numPrbc": 15,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 7,
+ "rb": 0,
+ "symInc": 1,
+ "startPrbc": 40,
+ "numPrbc": 95,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 8,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 162,
+ "numPrbc": 111,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 9,
+ "rb": 0,
+ "symInc": 1,
+ "startPrbc": 0,
+ "numPrbc": 5,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 10,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 10,
+ "numPrbc": 30,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 11,
+ "rb": 0,
+ "symInc": 1,
+ "startPrbc": 40,
+ "numPrbc": 95,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ },
+ {
+ "sectionId": 12,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 162,
+ "numPrbc": 111,
+ "reMask": 4095,
+ "numSymbol": 1,
+ "beamId": 0
+ }
+ ]
+ }
+ },
{
"name": "DL_SectionType1_SingleSection",
"parameters": {
"direction": "DL",
"section_type": 1,
- "num_sections": 1,
"cc_id": 0,
"ant_id": 0,
"seq_id": 0,
"subframe_id": 0,
"slot_id": 0,
"symbol_start": 0,
- "symbol_num": 14,
- "prb_start": [ 0 ],
- "prb_num": [ 66 ],
"comp_method": 0,
- "beam_id": 0,
- "section_id": 0,
- "iq_width": 16
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 66,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ }
+ ]
}
},
{
"parameters": {
"direction": "UL",
"section_type": 1,
- "num_sections": 1,
"cc_id": 0,
"ant_id": 0,
"seq_id": 0,
"subframe_id": 0,
"slot_id": 0,
"symbol_start": 0,
- "symbol_num": 14,
- "prb_start": [ 0 ],
- "prb_num": [ 66 ],
"comp_method": 0,
- "beam_id": 0,
- "section_id": 0,
- "iq_width": 16
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 66,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ }
+ ]
}
},
{
"parameters": {
"direction": "DL",
"section_type": 1,
- "num_sections": 3,
"cc_id": 0,
"ant_id": 0,
"seq_id": 0,
"subframe_id": 0,
"slot_id": 0,
"symbol_start": 0,
- "symbol_num": 14,
- "prb_start": [ 0, 22, 44 ],
- "prb_num": [ 22, 22, 22 ],
"comp_method": 0,
- "beam_id": 0,
- "section_id": 0,
- "iq_width": 16
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 22,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 22,
+ "numPrbc": 22,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ },
+ {
+ "sectionId": 3,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 44,
+ "numPrbc": 22,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ }
+ ]
}
},
{
"parameters": {
"direction": "UL",
"section_type": 1,
- "num_sections": 4,
"cc_id": 0,
"ant_id": 0,
"seq_id": 0,
"subframe_id": 0,
"slot_id": 0,
"symbol_start": 0,
- "symbol_num": 14,
- "prb_start": [ 0, 25, 50, 75 ],
- "prb_num": [ 25, 25, 25, 25 ],
"comp_method": 0,
- "beam_id": 0,
- "section_id": 0,
- "iq_width": 16
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 25,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ },
+ {
+ "sectionId": 2,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 25,
+ "numPrbc": 25,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ },
+ {
+ "sectionId": 3,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 50,
+ "numPrbc": 25,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ },
+ {
+ "sectionId": 4,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 75,
+ "numPrbc": 25,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_SectionType1_SingleSection_Ext3",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 0,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 273,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0,
+ "exts": [ 0 ]
+ }
+ ],
+ "extensions": [
+ {
+ "name": "ext3",
+ "type": 3,
+ "codebookIdx": 165,
+ "layerId": 2,
+ "numLayers": 2,
+ "txScheme": 1,
+ "crsReMask": 10,
+ "crsShift": 0,
+ "crsSymNum": 5,
+ "numAntPort": 4,
+ "beamIdAP1": 100,
+ "beamIdAP2": 200,
+ "beamIdAP3": 300
+ }
+ ]
+ }
+ },
+ {
+ "name": "DL_SectionType1_SingleSection_ExtAll",
+ "parameters": {
+ "direction": "DL",
+ "section_type": 1,
+ "cc_id": 0,
+ "ant_id": 0,
+ "seq_id": 0,
+ "frame_id": 0,
+ "subframe_id": 0,
+ "slot_id": 0,
+ "symbol_start": 0,
+ "comp_method": 0,
+ "iq_width": 16,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 273,
+ "reMask": 4095,
+ "numSymbol": 14,
+ "beamId": 0,
+ "exts": [ 0, 1, 2, 3 ]
+ }
+ ],
+ "extensions": [
+ {
+ "name": "ext2",
+ "type": 2,
+ "bfAzPtWidth": 7,
+ "bfAzPt": 10,
+ "bfZePtWidth": 7,
+ "bfZePt": 20,
+ "bfAz3ddWidth": 7,
+ "bfAz3dd": 30,
+ "bfZe3ddWidth": 7,
+ "bfZe3dd": 40,
+ "bfAzSI": 2,
+ "bfZeSI": 5
+ },
+ {
+ "name": "ext3",
+ "type": 3,
+ "codebookIdx": 165,
+ "layerId": 2,
+ "numLayers": 2,
+ "txScheme": 1,
+ "crsReMask": 10,
+ "crsShift": 0,
+ "crsSymNum": 5,
+ "numAntPort": 4,
+ "beamIdAP1": 100,
+ "beamIdAP2": 200,
+ "beamIdAP3": 300
+ },
+ {
+ "name": "ext4",
+ "type": 4,
+ "csf": 1,
+ "modCompScaler":1365
+ },
+ {
+ "name": "ext5",
+ "type": 5,
+ "num_sets": 2,
+ "csf": [ 1, 0 ],
+ "mcScaleReMask":[ 15, 7 ],
+ "mcScaleOffset":[ 100, 200 ]
+ }
+ ]
}
},
{
"parameters": {
"direction": "UL",
"section_type": 3,
- "num_sections": 1,
"cc_id": 0,
"ant_id": 0,
"seq_id": 0,
"subframe_id": 0,
"slot_id": 0,
"symbol_start": 7,
- "symbol_num": 6,
- "prb_start": [ 0 ],
- "prb_num": [ 12 ],
"comp_method": 0,
- "beam_id": 0,
- "section_id": 0,
"iq_width": 16,
"filter_index": 3,
"time_offset": 2026,
- "freq_offset": -792,
"fft_size": 10,
"scs": 3,
- "cp_length": 0
+ "cp_length": 0,
+ "sections": [
+ {
+ "sectionId": 1,
+ "rb": 0,
+ "symInc": 0,
+ "startPrbc": 0,
+ "numPrbc": 12,
+ "reMask": 4095,
+ "numSymbol": 6,
+ "beamId": 0,
+ "freqOffset": -792
+ }
+ ]
}
}
],
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"antelm_trx": 32,
"iq_width": 16,
"comp_meth": 0,
- "totalBfWeights": 32,
+ "totalBfWeights": 64,
"num_slots": 10,
"bfw_prefix_dl": "test_vectors/mu1_100_32/dl_bfw_ue_",
"bfw_prefix_ul": "test_vectors/mu1_100_32/ul_bfw_ue_"
"parameters": {
}
}
- ],
+ ],
+
+ "bfp_performace_cp": [
+ {
+ "name": "AntElm_8_IQ_8",
+ "parameters": {
+ "AntElm": 8,
+ "iqWidth": 8
+ }
+ },
+ {
+ "name": "AntElm_16_IQ_8",
+ "parameters": {
+ "AntElm": 16,
+ "iqWidth": 8
+ }
+ },
+ {
+ "name": "AntElm_32_IQ_8",
+ "parameters": {
+ "AntElm": 32,
+ "iqWidth": 8
+ }
+ },
+ {
+ "name": "AntElm_64_IQ_8",
+ "parameters": {
+ "AntElm": 64,
+ "iqWidth": 8
+ }
+ },
+ {
+ "name": "AntElm_8_IQ_9",
+ "parameters": {
+ "AntElm": 8,
+ "iqWidth": 9
+ }
+ },
+ {
+ "name": "AntElm_16_IQ_9",
+ "parameters": {
+ "AntElm": 16,
+ "iqWidth": 9
+ }
+ },
+ {
+ "name": "AntElm_32_IQ_9",
+ "parameters": {
+ "AntElm": 32,
+ "iqWidth": 9
+ }
+ },
+ {
+ "name": "AntElm_64_IQ_9",
+ "parameters": {
+ "AntElm": 64,
+ "iqWidth": 9
+ }
+ },
+ {
+ "name": "AntElm_8_IQ_10",
+ "parameters": {
+ "AntElm": 8,
+ "iqWidth": 10
+ }
+ },
+ {
+ "name": "AntElm_16_IQ_10",
+ "parameters": {
+ "AntElm": 16,
+ "iqWidth": 10
+ }
+ },
+ {
+ "name": "AntElm_32_IQ_10",
+ "parameters": {
+ "AntElm": 32,
+ "iqWidth": 10
+ }
+ },
+ {
+ "name": "AntElm_64_IQ_10",
+ "parameters": {
+ "AntElm": 64,
+ "iqWidth": 10
+ }
+ },
+ {
+ "name": "AntElm_8_IQ_12",
+ "parameters": {
+ "AntElm": 8,
+ "iqWidth": 12
+ }
+ },
+ {
+ "name": "AntElm_16_IQ_12",
+ "parameters": {
+ "AntElm": 16,
+ "iqWidth": 12
+ }
+ },
+ {
+ "name": "AntElm_32_IQ_12",
+ "parameters": {
+ "AntElm": 32,
+ "iqWidth": 12
+ }
+ },
+ {
+ "name": "AntElm_64_IQ_12",
+ "parameters": {
+ "AntElm": 64,
+ "iqWidth": 12
+ }
+ }
+ ],
"bfp_performace_ex": [
{
"name": "RB_16_IQ_8",
"parameters": {
"nRBsize": 16,
- "iqWidth": 8
+ "iqWidth": 8
}
- },
+ },
{
"name": "RB_18_IQ_8",
"parameters": {
"name": "RB_32_IQ_8",
"parameters": {
"nRBsize": 32,
- "iqWidth": 8
+ "iqWidth": 8
}
- },
+ },
{
"name": "RB_36_IQ_8",
"parameters": {
"name": "RB_48_IQ_8",
"parameters": {
"nRBsize": 48,
- "iqWidth": 8
+ "iqWidth": 8
}
- },
+ },
{
"name": "RB_70_IQ_8",
"parameters": {
"nRBsize": 70,
"iqWidth": 8
}
- },
+ },
{
"name": "RB_113_IQ_8",
"parameters": {
"nRBsize": 113,
"iqWidth": 8
}
- },
+ },
{
"name": "RB_273_IQ_8",
"parameters": {
"name": "RB_6_IQ_9",
"parameters": {
"nRBsize": 6,
- "iqWidth": 9
+ "iqWidth": 9
}
- },
+ },
{
"name": "RB_12_IQ_9",
"parameters": {
"nRBsize": 12,
- "iqWidth": 9
+ "iqWidth": 9
}
- },
+ },
{
"name": "RB_16_IQ_9",
"parameters": {
"nRBsize": 16,
- "iqWidth": 9
+ "iqWidth": 9
}
- },
+ },
{
"name": "RB_18_IQ_9",
"parameters": {
"name": "RB_32_IQ_9",
"parameters": {
"nRBsize": 32,
- "iqWidth": 9
+ "iqWidth": 9
}
- },
+ },
{
"name": "RB_36_IQ_9",
"parameters": {
"name": "RB_48_IQ_9",
"parameters": {
"nRBsize": 48,
- "iqWidth": 9
+ "iqWidth": 9
}
- },
+ },
{
"name": "RB_54_IQ_9",
"parameters": {
"nRBsize": 70,
"iqWidth": 9
}
- },
+ },
{
"name": "RB_72_IQ_9",
"parameters": {
"name": "RB_113_IQ_9",
"parameters": {
"nRBsize": 113,
- "iqWidth": 9
+ "iqWidth": 9
}
- },
+ },
{
"name": "RB_114_IQ_9",
"parameters": {
"name": "RB_16_IQ_10",
"parameters": {
"nRBsize": 16,
- "iqWidth": 10
+ "iqWidth": 10
}
- },
+ },
{
"name": "RB_18_IQ_10",
"parameters": {
"name": "RB_32_IQ_10",
"parameters": {
"nRBsize": 32,
- "iqWidth": 10
+ "iqWidth": 10
}
- },
+ },
{
"name": "RB_36_IQ_10",
"parameters": {
"nRBsize": 48,
"iqWidth": 10
}
- },
+ },
{
"name": "RB_70_IQ_10",
"parameters": {
"nRBsize": 70,
"iqWidth": 10
}
- },
+ },
{
"name": "RB_113_IQ_10",
"parameters": {
"nRBsize": 113,
- "iqWidth": 10
+ "iqWidth": 10
}
- },
+ },
{
"name": "RB_273_IQ_10",
"parameters": {
"nRBsize": 16,
"iqWidth": 12
}
- },
+ },
{
"name": "RB_18_IQ_12",
"parameters": {
"nRBsize": 32,
"iqWidth": 12
}
- },
+ },
{
"name": "RB_36_IQ_12",
"parameters": {
"nRBsize": 48,
"iqWidth": 12
}
- },
+ },
{
"name": "RB_70_IQ_12",
"parameters": {
"nRBsize": 70,
"iqWidth": 12
}
- },
+ },
{
"name": "RB_113_IQ_12",
"parameters": {
"nRBsize": 113,
- "iqWidth": 12
+ "iqWidth": 12
}
- },
+ },
{
"name": "RB_273_IQ_12",
"parameters": {
"nRBsize": 16,
"iqWidth": 14
}
- },
+ },
{
"name": "RB_18_IQ_14",
"parameters": {
"nRBsize": 32,
"iqWidth": 14
}
- },
+ },
{
"name": "RB_36_IQ_14",
"parameters": {
"nRBsize": 48,
"iqWidth": 14
}
- },
+ },
{
"name": "RB_70_IQ_14",
"parameters": {
"nRBsize": 70,
"iqWidth": 14
}
- },
+ },
{
"name": "RB_113_IQ_14",
"parameters": {
"nRBsize": 113,
- "iqWidth": 14
+ "iqWidth": 14
}
- },
+ },
{
"name": "RB_273_IQ_14",
"parameters": {
return;
}
+void xran_fh_srs_callback(void *pCallbackTag, xran_status_t status)
+{
+ rte_pause();
+ return;
+}
+
+
void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
{
void SetUp() override
{
xranlib->Init();
- xranlib->Open(nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_rx_prach_callback);
+ xranlib->Open(nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_rx_prach_callback, (void *)xran_fh_srs_callback);
}
/* It's called after an execution of the each test case.*/
*
*******************************************************************************/
-
#include "common.hpp"
#include "xran_common.h"
#include "xran_up_api.h"
return;
}
iq_offset = rte_pktmbuf_mtod(test_buffer, char * );
- iq_offset = iq_offset + sizeof(struct ether_hdr) +
+ iq_offset = iq_offset + sizeof(struct rte_ether_hdr) +
sizeof (struct xran_ecpri_hdr) +
sizeof (struct radio_app_common_hdr) +
sizeof(struct data_section_hdr);
pChar = rte_pktmbuf_mtod(test_buffer, char*);
- ecpri_hdr = (struct xran_ecpri_hdr *)(pChar + sizeof(struct ether_hdr));
- app_hdr = (struct radio_app_common_hdr *)(pChar + sizeof(struct ether_hdr)
+ ecpri_hdr = (struct xran_ecpri_hdr *)(pChar + sizeof(struct rte_ether_hdr));
+ app_hdr = (struct radio_app_common_hdr *)(pChar + sizeof(struct rte_ether_hdr)
+ sizeof (struct xran_ecpri_hdr));
- section_hdr = (struct data_section_hdr *)(pChar + sizeof(struct ether_hdr) +
+ section_hdr = (struct data_section_hdr *)(pChar + sizeof(struct rte_ether_hdr) +
sizeof (struct xran_ecpri_hdr) +
sizeof(struct radio_app_common_hdr));
#!/bin/bash
-export DIR_ROOT=/home/oran_release
+export DIR_ROOT=/home/
#set the L1 binary root DIR
export DIR_ROOT_L1_BIN=$DIR_ROOT/FlexRAN
#set the phy root DIR
export DIR_ROOT_PHY=$DIR_ROOT/phy
-#set the FEC SDK root DIR
-export DIR_ROOT_FEC_SDK=$DIR_ROOT/FlexRAN-FEC-SDK-19-04/sdk
#set the DPDK root DIR
-#export DIR_ROOT_DPDK=$DIR_ROOT/dpdk-18.08
+#export DIR_ROOT_DPDK=/home/dpdk-19.11
#set the GTEST root DIR
-#export DIR_ROOT_GTEST=$DIR_ROOT/gtest/gtest-1.7.0
+#export DIR_ROOT_GTEST=/home/gtest/gtest-1.7.0
export DIR_WIRELESS_TEST_5G=$DIR_ROOT_L1_BIN/testcase
export DIR_WIRELESS_SDK=$DIR_ROOT_L1_BIN/sdk/build-avx512-icc
export DIR_WIRELESS_TABLE_5G=$DIR_ROOT_L1_BIN/l1/bin/nr5g/gnb/l1/table
#source /opt/intel/system_studio_2019/bin/iccvars.sh intel64 -platform linux
export XRAN_DIR=$DIR_ROOT_PHY/fhi_lib
-
+export XRAN_LIB_SO=true
export RTE_TARGET=x86_64-native-linuxapp-icc
#export RTE_SDK=$DIR_ROOT_DPDK
#export DESTDIR=""
-export WIRELESS_SDK_TARGET_ISA=avx512
-export FLEXRAN_SDK=$DIR_ROOT_FEC_SDK/build-avx512-icc/install
#export GTEST_ROOT=$DIR_ROOT_GTEST
export ORAN_5G_FAPI=true
export DIR_WIRELESS_WLS=$DIR_ROOT_PHY/wls_lib
export DEBUG_MODE=true
-export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS:$XRAN_DIR/lib/build
export DIR_WIRELESS=$DIR_ROOT_L1_BIN/l1
export DIR_WIRELESS_ORAN_5G_FAPI=$DIR_ROOT_PHY/fapi_5g
-export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_ROOT_L1_BIN/libs/cpa_sub6/rec/lib/lib
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_ROOT_L1_BIN/libs/cpa/bin
+++ /dev/null
-../build/fapi//home/Luis/Integration/oran_wls_lib/test/fapi/fapi_main.o: \
- /home/Luis/Integration/oran_wls_lib/test/fapi/fapi_main.c \
- /usr/include/stdc-predef.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_eal.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_config.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_compat.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_common.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_per_lcore.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_bus.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_log.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_dev.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_pci_dev_feature_defs.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_cfgfile.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_string_fns.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_lcore.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_launch.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_debug.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_branch_prediction.h \
- /home/Luis/Integration/oran_wls_lib/wls.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_atomic.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/generic/rte_atomic.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_atomic_64.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_memzone.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_memory.h \
- /home/Luis/Integration/oran_wls_lib/ttypes.h \
- /home/Luis/Integration/oran_wls_lib/syslib.h \
- /home/Luis/Integration/oran_wls_lib/wls_lib.h
+++ /dev/null
-../build/mac//home/Luis/Integration/oran_wls_lib/test/mac/mac_main.o: \
- /home/Luis/Integration/oran_wls_lib/test/mac/mac_main.c \
- /usr/include/stdc-predef.h /home/Luis/Integration/oran_wls_lib/wls_lib.h \
- /home/Luis/Integration/oran_wls_lib/test/mac/mac_wls.h \
- /home/Luis/Integration/oran_5g_fapi/include/fapi_interface.h
-../build/mac//home/Luis/Integration/oran_wls_lib/test/mac/mac_wls.o: \
- /home/Luis/Integration/oran_wls_lib/test/mac/mac_wls.c \
- /usr/include/stdc-predef.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_eal.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_config.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_compat.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_common.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_per_lcore.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_bus.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_log.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_dev.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_pci_dev_feature_defs.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_cfgfile.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_string_fns.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_lcore.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_launch.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_debug.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_branch_prediction.h \
- /home/Luis/Integration/oran_wls_lib/wls.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_atomic.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/generic/rte_atomic.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_atomic_64.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_memzone.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_memory.h \
- /home/Luis/Integration/oran_wls_lib/ttypes.h \
- /home/Luis/Integration/oran_wls_lib/syslib.h \
- /home/Luis/Integration/oran_wls_lib/wls_lib.h \
- /home/Luis/Integration/oran_wls_lib/test/mac/mac_wls.h \
- /home/Luis/Integration/oran_5g_fapi/include/fapi_interface.h
+++ /dev/null
-../build/phy//home/Luis/Integration/oran_wls_lib/test/phy/phy_main.o: \
- /home/Luis/Integration/oran_wls_lib/test/phy/phy_main.c \
- /usr/include/stdc-predef.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_eal.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_config.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_compat.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_common.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_per_lcore.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_bus.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_log.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_dev.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_pci_dev_feature_defs.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_cfgfile.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_string_fns.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_lcore.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_launch.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_debug.h \
- /home/samuelwo/dpdk-18.08/x86_64-native-linuxapp-icc/include/rte_branch_prediction.h \
- /home/Luis/Integration/oran_wls_lib/wls_lib.h
CFLAGS := $(CFLAGS) -Werror
endif
-RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+#RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls
LINUX_WLS_FAPI_APP_SRC := \
return count;
}
- if (pNextMsg->msg_type != FAPI_MSG_HEADER_IND)
+ if (pNextMsg->msg_type != FAPI_VENDOR_MSG_HEADER_IND)
{
pMsgHeader = (void *) (pNextMsg + 1);
count++;
{
nPduLen = p_list_elm->msg_len + sizeof(fapi_api_queue_elem_t);
pPayload = (void *) p_list_elm;
- nMsgType = FAPI_MSG_PHY_ZBC_BLOCK_REQ;
+ nMsgType = FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ;
if (p_list_elm->p_next)
isLast = 0;
//#include "common_typedef.h"
#include "fapi_interface.h"
+#include "fapi_vendor_extension.h"
#define SUCCESS 0
#define FAILURE 1
CFLAGS := $(CFLAGS) -Werror
endif
-RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+#RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
+RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive
LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls
LINUX_WLS_MAC_APP_SRC := \
return 0;
}
-static int wls_VirtToPhys(const void* virtAddr, uint64_t* physAddr)
+static int wls_VirtToIova(const void* virtAddr, uint64_t* iovaAddr)
{
- int mapFd;
- uint64_t page;
- unsigned int pageSize;
- unsigned long virtualPageNumber;
-
- mapFd = open("/proc/self/pagemap", O_RDONLY);
- if (mapFd < 0) {
- PLIB_ERR("Could't open pagemap file\n");
+ *iovaAddr = rte_mem_virt2iova(virtAddr);
+ if (*iovaAddr==RTE_BAD_IOVA)
return -1;
- }
-
- /*get standard page size*/
- pageSize = getpagesize();
-
- virtualPageNumber = (unsigned long) virtAddr / pageSize;
-
- lseek(mapFd, virtualPageNumber * sizeof (uint64_t), SEEK_SET);
-
- if (read(mapFd, &page, sizeof (uint64_t)) < 0) {
- close(mapFd);
- PLIB_ERR("Could't read pagemap file\n");
- return -1;
- }
-
- *physAddr = ((page & 0x007fffffffffffffULL) * pageSize);
-
- close(mapFd);
-
return 0;
}
inorder to get pagemap*/
*(unsigned char*) pHugePageTlb[count].pageVa = 1;
- if (wls_VirtToPhys((uint64_t*) pHugePageTlb[count].pageVa,
+ if (wls_VirtToIova((uint64_t*) pHugePageTlb[count].pageVa,
&pHugePageTlb[count].pagePa) == -1) {
PLIB_ERR("Virtual to physical conversion failed\n");
return NULL;
Code Review / o-du / phy.git / commitdiff