1 /******************************************************************************
3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * This file consist of FAPI configuration APIs macros, structure typedefs and
25 #ifndef _NR5G_FAPI_INTELNAL_H_
26 #define _NR5G_FAPI_INTELNAL_H_
28 #include "fapi_interface.h"
29 #include "nr5g_fapi_common_types.h"
31 #define RELEASE_15 0x0001
33 #define MAX_UL_SLOT_INFO_COUNT 10 //Maximum no of Slots for which UL_TTI.request info has to
34 #define FAPI_MAX_NUM_PUSCH_PDU 255 //as per Table 3-44
35 #define FAPI_MAX_NUM_PUCCH_PDU 255 //as per Table 3-44
36 #define FAPI_MAX_NUM_SRS_PDU 255 //as per Table 3-73
37 #define FAPI_MAX_NUM_RACH_PDU 255 //as per Table 3-74
39 // Updated per 5G FAPI
41 FAPI_UL_TTI_REQ_PRACH_PDU_TYPE = 0,
42 FAPI_UL_TTI_REQ_PUSCH_PDU_TYPE,
43 FAPI_UL_TTI_REQ_PUCCH_PDU_TYPE,
44 FAPI_UL_TTI_REQ_SRS_PDU_TYPE
45 } fapiULTtiReqPduType_e;
47 // Updated per 5G FAPI
49 FAPI_UCI_IND_ON_PUSCH_PDU_TYPE = 0,
50 FAPI_UCI_IND_ON_PUCCH_FMT_0_1_PDU_TYPE,
51 FAPI_UCI_IND_ON_PUCCH_FMT_2_3_4_PDU_TYPE
52 } fapiUciIndPdu_Type_e;
60 // Release/Features support
62 FAPI_NOT_SUPPORTED = 0,
68 * FAPI state is maintained per fapi instance. If FAPI messages are received in
69 * wrong state an ERROR.indication message will be sent by FAPI.
71 typedef enum _fapi_states {
73 FAPI_STATE_CONFIGURED,
77 // Information of optional and mandatory status for a TLV
79 FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,
80 FAPI_IDLE_STATE_ONLY_MANDATORY,
81 FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,
82 FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,
83 FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,
84 FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL
87 // PARAMETERS INFORMATION
88 #define FAPI_NORMAL_CYCLIC_PREFIX_MASK 0x01
89 #define FAPI_EXTENDED_CYCLIC_PREFIX_MASK 0x02
91 // In 5G FAPI FrameDuplexType as part of Cell Configuration
92 typedef enum _fapi_duplex_ {
97 // Subcarrier spacing information
98 #define FAPI_15KHZ_MASK 0x01
99 #define FAPI_30KHZ_MASK 0x02
100 #define FAPI_60KHZ_MASK 0x04
101 #define FAPI_120KHZ_MASK 0x08
103 // Bandwitdth information
104 #define FAPI_5MHZ_BW_MASK 0x0001
105 #define FAPI_10MHZ_BW_MASK 0x0002
106 #define FAPI_15MHZ_BW_MASK 0x0004
107 #define FAPI_20MHZ_BW_MASK 0x0010
108 #define FAPI_40MHZ_BW_MASK 0x0020
109 #define FAPI_50MHZ_BW_MASK 0x0040
110 #define FAPI_60MHZ_BW_MASK 0x0080
111 #define FAPI_70MHZ_BW_MASK 0x0100
112 #define FAPI_80MHZ_BW_MASK 0x0200
113 #define FAPI_90MHZ_BW_MASK 0x0400
114 #define FAPI_100MHZ_BW_MASK 0x0800
115 #define FAPI_200MHZ_BW_MASK 0x1000
116 #define FAPI_400MHZ_BW_MASK 0x2000
119 #define FAPI_CCE_MAPPING_INTERLEAVED_MASK 0x01
120 #define FAPI_CCE_MAPPING_NONINTERLVD_MASK 0x02
121 // Upper Bound for PDCCH Channels per Slot
122 #define FAPI_MAX_PDCCHS_PER_SLOT_MASK 0xff
125 #define FAPI_FORMAT_0_MASK 0x01
126 #define FAPI_FORMAT_1_MASK 0x02
127 #define FAPI_FORMAT_2_MASK 0x04
128 #define FAPI_FORMAT_3_MASK 0x08
129 #define FAPI_FORMAT_4_MASK 0x10
130 // Upper Bound for PUCCH Channels per Slot
131 #define FAPI_MAX_PUCCHS_PER_SLOT_MASK 0xff
134 #define FAPI_PDSCH_MAPPING_TYPE_A_MASK 0x01
135 #define FAPI_PDSCH_MAPPING_TYPE_B_MASK 0x02
136 #define FAPI_PDSCH_ALLOC_TYPE_0_MASK 0x01
137 #define FAPI_PDSCH_ALLOC_TYPE_1_MASK 0x02
138 #define FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01
139 #define FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02
140 #define FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK 0x01
141 #define FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK 0x02
142 #define FAPI_PDSCH_DMRS_MAX_LENGTH_1 0
143 #define FAPI_PDSCH_DMRS_MAX_LENGTH_2 1
144 #define FAPI_DMRS_ADDITIONAL_POS_0_MASK 0x01
145 #define FAPI_DMRS_ADDITIONAL_POS_1_MASK 0x02
146 #define FAPI_DMRS_ADDITIONAL_POS_2_MASK 0x04
147 #define FAPI_DMRS_ADDITIONAL_POS_3_MASK 0x08
148 // Upper Limit for PDSCHS TBs per Slot
149 #define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK 0xff
150 #define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH 2
152 #define FAPI_MAX_PHY_INSTANCES 12
154 typedef enum modulationOrder {
161 #define FAPI_MAX_MUMIMO_USERS_MASK 0xff
164 #define FAPI_PUSCH_MAPPING_TYPE_A_MASK 0x01
165 #define FAPI_PUSCH_MAPPING_TYPE_B_MASK 0x02
166 #define FAPI_PUSCH_ALLOC_TYPE_0_MASK 0x01
167 #define FAPI_PUSCH_ALLOC_TYPE_1_MASK 0x02
168 #define FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01
169 #define FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02
170 #define FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK 0x01
171 #define FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK 0x02
172 #define FAPI_PUSCH_DMRS_MAX_LENGTH_1 0
173 #define FAPI_PUSCH_DMRS_MAX_LENGTH_2 1
174 // Upper limit for PUSCHMAXPTRSPORTS
175 #define FAPI_PUSCH_MAX_PTRS_PORTS_UB 2
176 //Upper Limit for PDSCHS TBs per Slot
177 #define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK 0xff
179 typedef enum aggregationFactor {
180 FAPI_PUSCH_AGG_FACTOR_1 = 0,
181 FAPI_PUSCH_AGG_FACTOR_2,
182 FAPI_PUSCH_AGG_FACTOR_4,
183 FAPI_PUSCH_AGG_FACTOR_8
184 } fapiPuschAggFactor_t;
187 #define FAPI_PRACH_LF_FORMAT_0_MASK 0x01
188 #define FAPI_PRACH_LF_FORMAT_1_MASK 0x02
189 #define FAPI_PRACH_LF_FORMAT_2_MASK 0x04
190 #define FAPI_PRACH_LF_FORMAT_3_MASK 0x08
192 #define FAPI_PRACH_SF_FORMAT_A1_MASK 0x01
193 #define FAPI_PRACH_SF_FORMAT_A2_MASK 0x02
194 #define FAPI_PRACH_SF_FORMAT_A3_MASK 0x04
195 #define FAPI_PRACH_SF_FORMAT_B1_MASK 0x08
196 #define FAPI_PRACH_SF_FORMAT_B2_MASK 0x10
197 #define FAPI_PRACH_SF_FORMAT_B3_MASK 0x20
198 #define FAPI_PRACH_SF_FORMAT_B4_MASK 0x40
199 #define FAPI_PRACH_SF_FORMAT_C0_MASK 0x80
200 #define FAPI_PRACH_SF_FORMAT_C2_MASK 0x100
202 typedef enum prachMaxOccasionsPerSlot {
203 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_1 = 0,
204 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_2,
205 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_4,
206 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_8
207 } fapi_prachMaxFdOccasionsPerSlot_t;
209 // Measurement Parameters
210 #define FAPI_RSSI_REPORT_IN_DBM_MASK 0x01
211 #define FAPI_RSSI_REPORT_IN_DBFS_MASK 0x02
213 // CONFIGURATION INFORMATION CARRIER CONFIGURATION BANDWIDTH
214 #define FAPI_BANDWIDTH_5_MHZ 5
215 #define FAPI_BANDWIDTH_10_MHZ 10
216 #define FAPI_BANDWIDTH_15_MHZ 15
217 #define FAPI_BANDWIDTH_20_MHZ 20
218 #define FAPI_BANDWIDTH_25_MHZ 25
219 #define FAPI_BANDWIDTH_30_MHZ 30
220 #define FAPI_BANDWIDTH_40_MHZ 40
221 #define FAPI_BANDWIDTH_50_MHZ 50
222 #define FAPI_BANDWIDTH_60_MHZ 60
223 #define FAPI_BANDWIDTH_70_MHZ 70
224 #define FAPI_BANDWIDTH_80_MHZ 80
225 #define FAPI_BANDWIDTH_90_MHZ 90
226 #define FAPI_BANDWIDTH_100_MHZ 100
227 #define FAPI_BANDWIDTH_200_MHZ 200
228 #define FAPI_BANDWIDTH_400_MHZ 400
230 #define FAPI_SUBCARRIER_SPACING_15 0
231 #define FAPI_SUBCARRIER_SPACING_30 1
232 #define FAPI_SUBCARRIER_SPACING_60 2
233 #define FAPI_SUBCARRIER_SPACING_120 3
235 #define FAPI_FFT_SIZE_512 512
236 #define FAPI_FFT_SIZE_1024 1024
237 #define FAPI_FFT_SIZE_2048 2048
238 #define FAPI_FFT_SIZE_4096 4096
239 // Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1
241 #define FAPI_MIN_FREQUENCY_PT_A 450000
243 #define FAPI_MAX_FREQUENCY_PT_A 52600000
244 // dlk0, ulk0 per 38.211 Section 5.3.1
246 #define FAPI_K0_MAX 23699
247 // dlGridSize, ulGridSize per 38.211 Section 4.4.2
249 #define FAPI_GRIDSIZE_MAX 275
250 // Number of Transmit Antennas
251 // Define upper mask based on variable type
252 #define FAPI_NUM_ANT_MASK 0xffff
253 // CELL CONFIGURATION
254 // Physical Cell ID from 38.211 Section 7.4.2.1
256 #define FAPI_MAX_CELL_ID 1007
258 // SSB POWER RANGE in dBm
259 #define FAPI_SS_PBCH_LOWEST_POWER -60
260 #define FAPI_SS_PBCH_MAX_POWER 50
261 // BCH PAYLOAD for 5G the MAC always generates the BCH Payload
262 #define FAPI_BCH_PAYLOAD_GEN_BY_MAC 0
263 #define FAPI_BCH_PAYLOAD_WITH_PHY_GEN_TIMING 1
264 #define FAPI_BCH_PAYLOAD_ENTIRELY_GEN_BY_PHY 2
266 #define FAPI_SCSCOMMON_MASK 0x03
267 // PRACH CONFIGURATION
268 #define FAPI_PRACH_LONG_SEQUENCE 0
269 #define FAPI_PRACH_SHORT_SEQUENCE 1
270 #define FAPI_PRACH_SUBC_SPACING_MAX 4
271 // Restricted Set Configuration
272 #define FAPI_PRACH_RESTRICTED_SET_UNRESTRICTED 0
273 #define FAPI_PRACH_RESTRICTED_SET_TYPE_A 1
274 #define FAPI_PRACH_RESTRICTED_SET_TYPE_B 2
275 // Root Sequence Index
277 #define FAPI_PRACH_ROOT_SEQ_INDEX_MAX 837
280 #define FAPI_K1_UPPER_BOUND 272
281 // PRACH Zero Corr Configuration
283 #define FAPI_PRACHZEROCORRCONF_MASK 0x0f
284 // Number of Unused Root Sequences Mask
285 #define FAPI_UNUSEDROOTSEQUENCES_MASK 0x0f
288 FAPI_SSB_PER_RACH_1_OVER_8 = 0,
289 FAPI_SSB_PER_RACH_1_OVER_4,
290 FAPI_SSB_PER_RACH_1_OVER_2,
299 FAPI_PUCCH_FORMAT_TYPE_0 = 0,
300 FAPI_PUCCH_FORMAT_TYPE_1,
301 FAPI_PUCCH_FORMAT_TYPE_2,
302 FAPI_PUCCH_FORMAT_TYPE_3,
303 FAPI_PUCCH_FORMAT_TYPE_4,
304 } nr5g_fapi_uci_format_t;
308 uint16_t initial_cyclic_shift;
309 uint8_t nr_of_symbols;
310 uint8_t start_symbol_index;
311 uint8_t time_domain_occ_idx;
312 } nr5g_fapi_pucch_resources_t;
314 // Ssb Offset Point A max
315 #define FAPI_SSB_OFFSET_POINTA_MAX 2199
316 // betaPSS i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1
317 #define FAPI_BETAPSS_0_DB 0
318 #define FAPI_BETAPSS_3_DB 1
320 #define FAPI_SSB_PERIOD_5_MS 0
321 #define FAPI_SSB_PERIOD_10_MS 1
322 #define FAPI_SSB_PERIOD_20_MS 2
323 #define FAPI_SSB_PERIOD_40_MS 3
324 #define FAPI_SSB_PERIOD_80_MS 4
325 #define FAPI_SSB_PERIOD_160_MS 5
326 // Ssb Subcarrier Offset per 38.211 Section 7.4.3.1
327 // SsbSubcarrierOffset mask
328 #define FAPI_SSB_SUBCARRIER_OFFSET_MASK 0x1f
330 #define MIB_PAYLOAD_MASK 0xfff0
332 #define FAPI_BEAM_ID_MASK 0x3f
335 #define FAPI_TDD_PERIOD_0_P_5_MS 0
336 #define FAPI_TDD_PERIOD_0_P_625_MS 1
337 #define FAPI_TDD_PERIOD_1_MS 2
338 #define FAPI_TDD_PERIOD_1_P_25_MS 3
339 #define FAPI_TDD_PERIOD_2_MS 4
340 #define FAPI_TDD_PERIOD_2_P_5_MS 5
341 #define FAPI_TDD_PERIOD_5_MS 6
342 #define FAPI_TDD_PERIOD_10_MS 7
343 // Slot Configuration
344 #define FAPI_DL_SLOT 0
345 #define FAPI_UL_SLOT 1
346 #define FAPI_GUARD_SLOT 2
347 // Measurement configuration
348 #define FAPI_NO_RSSI_REPORTING 0
349 #define FAPI_RSSI_REPORTED_IN_DBM 1
350 #define FAPI_RSSI_REPORTED_IN_DBFS 2
352 #define FAPI_SFN_MASK 0x03ff
353 // Status and Error Codes for either .response or ERROR.indication
354 // Updated per 5g FAPI Table 3-31
365 } fapiStatusAndErrorCodes_e;
367 // Digital Beam Table (DBT) PDU
368 // Number of Digital Beam Mask
369 // Number of TX RUS Mask
371 // Digital Beam Index weights Real and Imaginary Mask
373 // Precoding Matrix (PM) PDU
374 // Precoding Matrix ID Mask
375 // Number of Layers Mask
376 // Number of Antenna Ports at the precoder output Mask
377 // Precoder Weights Real and Imaginary Mask
378 #define FAPI_U16_MASK 0xffff
382 #define FAPI_SLOT_MAX_VALUE 159
387 #define FAPI_U8_MASK 0xff
390 FAPI_DL_TTI_REQ_PDCCH_PDU_TYPE = 0,
391 FAPI_DL_TTI_REQ_PDSCH_PDU_TYPE,
392 FAPI_DL_TTI_REQ_CSI_RS_PDU_TYPE,
393 FAPI_DL_TTI_REQ_SSB_PDU_TYPE
394 } fapiDlTtiReqPduType_e;
397 // Define Maximum number of Ues per Group
398 #define FAPI_MAX_NUMBER_OF_UES_PER_GROUP 12
401 #define FAPI_BWPSIZE_MAX 275
402 #define FAPI_BWPSIZE_START_MAX 274
403 #define FAPI_SUBCARRIER_SPACING_MAX 4
404 #define FAPI_CYCLIC_PREFIX_NORMAL 0
405 #define FAPI_CYCLIC_PREFIX_EXTENDED 1
406 #define FAPI_MAX_SYMBOL_START_INDEX 13
408 #define FAPI_CORESET_DURATION_1_SYMBOL 1
409 #define FAPI_CORESET_DURATION_2_SYMBOLS 2
410 #define FAPI_CORESET_DURATION_3_SYMBOLS 3
412 #define FAPI_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0
413 #define FAPI_CCE_REG_MAPPING_TYPE_INTERLEAVED 1
414 #define FAPI_REG_BUNDLE_SIZE_2 2
415 #define FAPI_REG_BUNDLE_SIZE_3 3
416 #define FAPI_REG_BUNDLE_SIZE_6 6
418 #define FAPI_INTERLEAVER_SIZE_2 2
419 #define FAPI_INTERLEAVER_SIZE_3 3
420 #define FAPI_INTERLEAVER_SIZE_6 6
422 #define FAPI_CORESET_TYPE_0_CONF_BY_PBCH_OR_SIB1 0
423 #define FAPI_CORESET_TYPE_1 1
425 #define FAPI_PREC_GRANULARITY_SAME_AS_REG_BUNDLE 0
426 #define FAPI_PREC_GRANULARITY_ALL_CONTIG_RBS 1
428 #define FAPI_CCE_INDEX_MAX 135
429 #define FAPI_PDCCH_AGG_LEVEL_1 1
430 #define FAPI_PDCCH_AGG_LEVEL_2 2
431 #define FAPI_PDCCH_AGG_LEVEL_4 4
432 #define FAPI_PDCCH_AGG_LEVEL_8 8
433 #define FAPI_PDCCH_AGG_LEVEL_16 16
435 #define FAPI_BETA_PDCCH_1_0_MAX 17
437 #define FAPI_POWER_CTRL_OFF_SS_MINUS_3_DB 0
438 #define FAPI_POWER_CTRL_OFF_SS_0_DB 1
439 #define FAPI_POWER_CTRL_OFF_SS_3_DB 2
440 #define FAPI_POWER_CTRL_OFF_SS_6_DB 3
442 #define FAPI_MAX_NUMBER_OF_CODEWORDS 2
444 #define FAPI_MAX_MCS_INDEX 31
445 #define FAPI_MCS_INDEX_MASK 0x1f
447 #define FAPI_MCS_TABLE_NOT_QAM_256 0
448 #define FAPI_MCS_TABLE_QAM_256 1
449 #define FAPI_MCS_TABLE_QAM_64_LOW_SE 2
451 #define FAPI_REDUNDANCY_INDEX_MASK 0x03
452 #define FAPI_MAX_DL_LAYERS 8
453 #define FAPI_MAX_UL_LAYERS 4
454 //#define FAPI_MAX_DMRS_PORTS 12
455 #define FAPI_MAX_DMRS_PORTS MAX_DL_PER_UE_DMRS_PORT_NUM
456 #define FAPI_MAX_PTRS_PORTS 12
458 #define FAPI_TRANSMISSION_SCHEME_1 1
460 #define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A 0
461 #define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC 1
463 #define FAPI_DL_DMRS_SYMB_POS_MASK 0x3fff
465 #define FAPI_MAX_DMRS_CDM_GRPS_WO_DATA 3
467 #define FAPI_DMRS_PORTS_MASK 0x0fff
469 #define FAPI_RES_ALLOC_TYPE_0 0
470 #define FAPI_RES_ALLOC_TYPE_1 1
472 #define FAPI_VRB_TO_PRB_MAP_NON_INTERLVD 0
473 #define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_2 1
474 #define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_4 2
476 #define FAPI_MAX_START_SYMBOL_INDEX 13
477 #define FAPI_MAX_NR_OF_SYMBOLS 14
478 #define FAPI_PTRS_PORT_INDEX_MASK 0x3f
479 #define FAPI_PTRS_TIME_DENSITY_1 0
480 #define FAPI_PTRS_TIME_DENSITY_2 1
481 #define FAPI_PTRS_TIME_DENSITY_4 2
482 #define FAPI_PTRS_FREQ_DENSITY_2 0
483 #define FAPI_PTRS_FREQ_DENSITY_4 1
484 #define FAPI_PTRS_RE_OFFSET_MASK 0x03
485 #define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK 0x03
486 // PDSCH Power Control Offset
487 #define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB 0
488 #define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB 1
489 #define FAPI_PWR_CTRL_OFFSET_MINUS_6_DB 2
490 #define FAPI_PWR_CTRL_OFFSET_MINUS_5_DB 3
491 #define FAPI_PWR_CTRL_OFFSET_MINUS_4_DB 4
492 #define FAPI_PWR_CTRL_OFFSET_MINUS_3_DB 5
493 #define FAPI_PWR_CTRL_OFFSET_MINUS_2_DB 6
494 #define FAPI_PWR_CTRL_OFFSET_MINUS_1_DB 7
495 #define FAPI_PWR_CTRL_OFFSET_0_DB 8
496 #define FAPI_PWR_CTRL_OFFSET_1_DB 9
497 #define FAPI_PWR_CTRL_OFFSET_2_DB 10
498 #define FAPI_PWR_CTRL_OFFSET_3_DB 11
499 #define FAPI_PWR_CTRL_OFFSET_4_DB 12
500 #define FAPI_PWR_CTRL_OFFSET_5_DB 13
501 #define FAPI_PWR_CTRL_OFFSET_6_DB 14
502 #define FAPI_PWR_CTRL_OFFSET_7_DB 15
503 #define FAPI_PWR_CTRL_OFFSET_8_DB 16
504 #define FAPI_PWR_CTRL_OFFSET_9_DB 17
505 #define FAPI_PWR_CTRL_OFFSET_10_DB 18
506 #define FAPI_PWR_CTRL_OFFSET_11_DB 19
507 #define FAPI_PWR_CTRL_OFFSET_12_DB 20
508 #define FAPI_PWR_CTRL_OFFSET_13_DB 21
509 #define FAPI_PWR_CTRL_OFFSET_14_DB 22
510 #define FAPI_PWR_CTRL_OFFSET_15_DB 23
511 // Power Control Offset SS
512 #define FAPI_PWR_CTRL_OFFSET_SS_MINUS_3_DB 0
513 #define FAPI_PWR_CTRL_OFFSET_SS_0_DB 1
514 #define FAPI_PWR_CTRL_OFFSET_SS_3_DB 2
515 #define FAPI_PWR_CTRL_OFFSET_SS_6_DB 3
517 #define FAPI_CSI_TRS 0
518 #define FAPI_CSI_NON_ZERO_POWER 1
519 #define FAPI_CSI_ZERO_POWER 2
520 // Row entry into CSI Resource Location Table
521 #define FAPI_CSIRLT_ROW_MAX_VALUE 18
522 #define FAPI_CSI_FREQ_DOMAIN_MASK 0x0fff
523 #define FAPI_CSI_SYMB_L1_MIN 2
524 #define FAPI_CSI_SYMB_L1_MAX 12
526 #define FAPI_CDM_TYPE_NO_CDM 0
527 #define FAPI_CDM_TYPE_FD_CDM 1
528 #define FAPI_CDM_TYPE_CDM4_FD2_TD2 2
529 #define FAPI_CDM_TYPE_CDM8_FD2_TD4 3
531 #define FAPI_FD_DOT5_EVEN_RB 0
532 #define FAPI_FD_DOT5_ODD_RB 1
533 #define FAPI_FD_ONE 2
534 #define FAPI_FD_THREE 3
537 #define FAPI_SSB_BLOCK_INDEX_MASK 0x3f
538 #define FAPI_SSB_SC_OFFSET_MASK 0x1f
541 #define FAPI_MAX_NUM_UE_GROUPS_INCLUDED 8
542 #define FAPI__MAX_NUM_UE_IN_GROUP 6
544 #define FAPI_MAX_NUM_PRACH_OCAS 7
546 #define FAPI_PRACH_FORMAT_A1 0
547 #define FAPI_PRACH_FORMAT_A2 1
548 #define FAPI_PRACH_FORMAT_A3 2
549 #define FAPI_PRACH_FORMAT_B1 3
550 #define FAPI_PRACH_FORMAT_B2 4
551 #define FAPI_PRACH_FORMAT_B3 5
552 #define FAPI_PRACH_FORMAT_B4 6
553 #define FAPI_PRACH_FORMAT_C0 7
554 #define FAPI_PRACH_FORMAT_C2 8
556 #define FAPI_MAX_PRACH_FD_OCCASION_INDEX 7
557 #define FAPI_MAX_ZC_ZONE_CONFIG_NUMBER 419
560 #define FAPI_PUSCH_BIT_DATA_PRESENT_MASK 0x0001
561 #define FAPI_PUSCH_UCI_DATA_PRESENT_MASK 0x0002
562 #define FAPI_PUSCH_PTRS_INCLUDED_FR2_MASK 0x0004
563 #define FAPI_PUSCH_DFTS_OFDM_TX_MASK 0x0008
565 #define FAPI_MAX_QAM_MOD_ORDER 8
566 #define FAPI_MCS_INDEX_MASK 0x1f
568 #define FAPI_MCS_TABLE_NOT_QAM256 0
569 #define FAPI_MCS_TABLE_QAM256 1
570 #define FAPI_MCS_TABLE_QAM64_LOWSE 2
571 #define FAPI_MCS_TABLE_NOT_QAM256_W_XFRM_PRECOD 3
572 #define FAPI_MCS_TABLE_QAM64_LOWSE_W_XFRM_PRECOD 4
573 #define FAPI_PUSCH_MAX_NUM_LAYERS 4
575 #define FAPI_UL_DMRS_SYMB_POS_MASK 0x3fff
576 #define FAPI_UL_DMRS_CONFIG_TYPE_1 0
577 #define FAPI_UL_DMRS_CONFIG_TYPE_2 1
578 #define FAPI_MAX_DMRS_CDM_GRPS_NO_DATA 3
579 #define FAPI_UL_DMRS_PORTS_MASK 0x07ff
580 #define FAPI_UL_TX_DIRECT_CURR_LOCATION_MAX 3299
581 #define FAPI_UL_TX_DIRECT_CURR_LOC_OUTSIDE_CARRIER 3300
582 #define FAPI_UL_TX_DIRECT_CURR_LOC_UNDETERMINED 3301
584 #define FAPI_RV_INDEX_MASK 0x03
585 #define FAPI_HARQ_PROCESS_ID_MASK 0x0f
587 #define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_SMALL_BLOCK_MAX 11
588 #define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_POLAR_MAX 1706
590 #define FAPI_ALPHA_SCALE_0_5 0
591 #define FAPI_ALPHA_SCALE_0_65 1
592 #define FAPI_ALPHA_SCALE_0_8 2
593 #define FAPI_ALPHA_SCALE_1_0 3
594 // BETA OFFSET HARQ ACK
595 #define FAPI_BETA_OFFSET_HARQ_ACK_MAX 15
596 #define FAPI_BETA_OFFSET_CSIX_MAX 18
598 // PUSCH PTRS INFORMATION 38.212 Section 7.3.1.1.2
599 #define FAPI_MAX_NUMBER_PTRS_PORT_INDEX 11 // 0..11
600 // UL PTRS POWER 5G FAPI Table 3-49
601 #define FAPI_UL_PTRS_PWR_0_DB 0
602 #define FAPI_UL_PTRS_PWR_3_DB 1
603 #define FAPI_UL_PTRS_PWR_4_77_DB 2
604 #define FAPI_UL_PTRS_PWR_6_DB 3
605 // DFTSOFDM INFO 5g FAPI Table 3-50
606 #define FAPI_MAX_LOW_PAPR_GROUP_NUMBER 29 // 0..29
607 #define FAPI_MAX_LOW_PAPR_SEQ_NUMBER 87 // 3*LOW_PAPR_GRP_NUM
608 #define FAPI_MAX_UL PTRS_SAMP_DENSITY 8
609 #define FAPI_MAX_UL_PTRS_TD_XFRM_PRECOD 4
611 // PUCCH PDU Table 3-51
612 #define FAPI_MAX_PUCCH_FORMAT_TYPE 4
613 #define FAPI_MULTI_SLOT_TX_IND_NO_MULTI_SLOT 0
614 #define FAPI_MULTI_SLOT_TX_IND_TX_START 1
615 #define FAPI_MULTI_SLOT_TX_IND_TX_CONT 2
616 #define FAPI_MULTI_SLOT_TX_IND_TX_END 3
617 #define FAPI_MAX_NUM_PRB_FOR_A_PUCCH 16
618 #define FAPI_MAX_PUCCH_DUR_F0_AND_F2 2
619 #define FAPI_MIN_PUCCH_DUR_F1_F3_F4 4
620 #define FAPI_MAX_PUCCH_DUR_F1_F3_F4 14
621 #define FAPI_MAX_INIT_CYCLIC_SHIFT_F0_F1_F3_F4 11
622 #define FAPI_MAX_OCC_INDEX_F1 6
623 #define FAPI_MAX_PRE_DFT_OCC_IDX_F4 3
624 #define FAPI_MAX_PRE_DFT_OCC_LEN_F4 4
625 #define FAPI_MAX_DMRS_CYC_SHIFT_F4 9
626 #define FAPI_BIT_LEN_HARQ_PL_ZERO 0
627 #define FAPI_BIT_LEN_HARQ_PL_F0_F1_2_BITS 1
628 #define FAPI_BIT_LEN_HARQ_PL_F2_F3_F4_1706_BITS 2
629 #define FAPI_BIT_LEN_CSI_PX_PL_NO_CSI 0
630 #define FAPI_BIT_LEN_CSI_PX_PL_1706_BITS 1
633 #define FAPI_1_SRS_ANT_PORT 0
634 #define FAPI_2_SRS_ANT_PORTS 1
635 #define FAPI_4_SRS_ANT_PORTS 2
636 #define FAPI_SRS_NO_REPETITIONS 0
637 #define FAPI_SRS_2_REPETITIONS 2
638 #define FAPI_SRS_4_REPETITIONS 4
639 #define FAPI_SRS_CONFIG_INDEX_MASK 0x3f
640 #define FAPI_SRS_BW_INDEX_MASK 0x03
641 #define FAPI_TX_COMB_SIZE_2 0
642 #define FAPI_TX_COMB_SIZE_4 1
643 #define FAPI_MAX_SRS_FREQ_POSITION 67
644 #define FAPI_MAX_SRS_FD_SHIFT 268
645 #define FAPI_SRS_FREQ_HOPPING_MASK 0x03
646 #define FAPI_SRS_NO_HOPPING 0
647 #define FAPI_SRS_GRP_OR_SEQ_HOPPING 1
648 #define FAPI_SRS_SEQ_HOPPING 2
649 #define FAPI_SRS_RES_ALLOC_APERIODIC 0
650 #define FAPI_SRS_RES_ALLOC_SEMI_PERSISTENT 1
651 #define FAPI_SRS_RES_ALLOC_PERIODIC 2
652 #define FAPI_MAX_LSOT_OFFSET_VALUE 2559
654 // RX_DATA Indication
655 #define FAPI_UL_CQI_INVALID 255
656 #define FAPI_TIMING_ADVANCE_INVALID 0xffff
657 #define FAPI_MAX_TIMING_ADVANCE 63
658 #define FAPI_MAX_RSSI 1280
661 #define FAPI_RACH_FREQ_INDEX_MAX 7
662 #define FAPI_RACH_DETECTED_PREAMBLES_MASK 0x3f
663 #define FAPI_RACH_TIMING_ADVANCE_MAX 3846
664 #define FAPI_RACH_PREAMBLE_POWER_INVALID 0xffffffff
665 #define FAPI_RACH_PREAMBLE_TIMING_ADVANCE_INVALID 0xffff
666 #define FAPI_RACH_PREAMBLE_POWER_MAX 170000
668 // SR, HARQ, and CSI Part 1/2 PDUs Table 3-66
669 #define FAPI_SR_MASK 0x01
670 #define FAPI_HARQ_MASK 0x02
671 #define FAPI_CSI_PART1 0x04
672 #define FAPI_CSI_PART2 0x08
673 #define FAPI_PUCCH_FORMAT2 0
674 #define FAPI_PUCCH_FORMAT3 1
675 #define FAPI_PUCCH_FORMAT4 2
676 #define FAPI_PUCCH_FORMAT_MASK 0x03
678 // SR PDU For Format 0 or 1 Table 3-67
679 #define FAPI_SR_CONFIDENCE_LEVEL_GOOD 0
680 #define FAPI_SR_CONFIDENCE_LEVEL_BAD 1
681 #define FAPI_SR_CONFIDENCE_LEVEL_INVALID 0xff
683 // HARQ PDU for Format 0 or 1 Table 3-68
684 #define FAPI_HARQ_VALUE_PASS 0
685 #define FAPI_HARQ_VALUE_FAIL 1
686 #define FAPI_HARQ_VALUE_NOT_PRESENT 2
688 // SR PDU for Format 2,3 or 4 Table 3-69
689 #define FAPI_SR_PAYLOAD_MAX 1
691 // HARQ PDU for Format 2,3 or 4 Table 3-70
692 #define FAPI_HARQ_CRC_PASS 0
693 #define FAPI_HARQ_CRC_FAIL 1
694 #define FAPI_HARQ_CRC_NOT_PRESENT 2
695 #define FAPI_HARQ_PAYLOAD_MAX 214
697 // CSI Part 1 PDU Table 3-71 and 3-72
698 #define FAPI_CSI_PARTX_CRC_PASS 0
699 #define FAPI_CSI_PARTX_CRC_FAIL 1
700 #define FAPI_CSI_PARTX_CRC_NOT_PRESENT 2
701 #define FAPI_CSI_PARTX_PAYLOAD_MAX 214
704 MEM_STAT_CONFIG_REQ = 0,
707 MEM_STAT_SHUTDOWN_REQ,
708 MEM_STAT_DL_CONFIG_REQ,
709 MEM_STAT_UL_CONFIG_REQ,
712 MEM_STAT_DL_IQ_SAMPLES,
713 MEM_STAT_UL_IQ_SAMPLES,
717 #endif //_NR5G_FAPI_INTELNAL_H_