1 /******************************************************************************
3 * Copyright (c) 2020 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
21 #include "xran_fh_o_du.h"
22 #include "xran_cp_api.h"
23 #include "xran_lib_wrap.hpp"
24 #include "xran_common.h"
35 const std::string module_name = "init_sys_functional";
37 extern enum xran_if_state xran_if_current_state;
39 int32_t physide_sym_call_back(void * param, struct xran_sense_of_time *time)
45 int physide_dl_tti_call_back(void * param)
51 int physide_ul_half_slot_call_back(void * param)
57 int physide_ul_full_slot_call_back(void * param)
63 void xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
69 void xran_fh_bfw_callback(void *pCallbackTag, xran_status_t status)
75 void xran_fh_srs_callback(void *pCallbackTag, xran_status_t status)
82 void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
88 class Init_Sys_Check : public KernelTests
95 xranlib->Open(0, nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_bfw_callback, (void *)xran_fh_rx_prach_callback, (void *)xran_fh_srs_callback);
98 /* It's called after an execution of the each test case.*/
99 void TearDown() override
107 BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
108 BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
109 BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
110 BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
111 BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
113 BbuIoBufCtrlStruct sFHCpRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
114 BbuIoBufCtrlStruct sFHCpTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
116 struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
117 struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
118 struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
119 struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
120 struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
122 void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector
123 uint32_t nBufPoolIndex[XRAN_MAX_SECTOR_NR][xranLibWraper::MAX_SW_XRAN_INTERFACE_NUM];
124 uint16_t nInstanceNum;
127 TEST_P(Init_Sys_Check, Test_Open_Close)
129 struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
130 /* check stat of lib */
131 ASSERT_EQ(1, p_xran_dev_ctx->enableCP);
132 ASSERT_EQ(1, p_xran_dev_ctx->xran2phy_mem_ready);
135 TEST_P(Init_Sys_Check, Test_xran_mm_init)
138 ret = xran_mm_init (xranlib->get_xranhandle(), (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);
142 /* this case cannot be tested since memory cannot be initialized twice */
143 /* memory initialization is moved to the wrapper class */
145 TEST_P(Init_Sys_Check, Test_xran_bm_init_alloc_free)
150 uint32_t nSW_ToFpga_FTH_TxBufferLen = 13168; /* 273*12*4 + 64*/
154 struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
155 struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
156 struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
157 struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
158 struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
159 struct xran_buffer_list *pFthRxRachBufferDecomp[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
161 Init_Sys_Check::nInstanceNum = xranlib->get_num_cc();
163 for (k = 0; k < XRAN_PORTS_NUM; k++) {
164 ret = xran_sector_get_instances (xranlib->get_xranhandle(), Init_Sys_Check::nInstanceNum, &(Init_Sys_Check::nInstanceHandle[k][0]));
166 ASSERT_EQ(1, Init_Sys_Check::nInstanceNum);
170 ret = xran_bm_init(Init_Sys_Check::nInstanceHandle[0][0],
171 &Init_Sys_Check::nBufPoolIndex[0][0],
172 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
175 ret = xran_bm_allocate_buffer(Init_Sys_Check::nInstanceHandle[0][0], Init_Sys_Check::nBufPoolIndex[0][0],&ptr, &mb);
177 ASSERT_NE(ptr, nullptr);
178 ASSERT_NE(mb, nullptr);
180 ret = xran_bm_free_buffer(Init_Sys_Check::nInstanceHandle[0][0], ptr, mb);
185 for(int i=0; i< xranlib->get_num_cc(); i++)
187 for(int j=0; j<XRAN_N_FE_BUF_LEN; j++)
189 for(int z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
190 pFthTxBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
191 pFthTxPrbMapBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
192 pFthRxBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
193 pFthRxPrbMapBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
194 pFthRxRachBuffer[i][z][j] = &(Init_Sys_Check::sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
195 pFthRxRachBufferDecomp[i][z][j] = &(Init_Sys_Check::sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList);
200 if(NULL != Init_Sys_Check::nInstanceHandle[0])
202 for (int i = 0; i < xranlib->get_num_cc(); i++)
204 ret = xran_5g_fronthault_config (Init_Sys_Check::nInstanceHandle[0][i],
206 pFthTxPrbMapBuffer[i],
208 pFthRxPrbMapBuffer[i],
209 xran_fh_rx_callback, &pFthRxBuffer[i][0]);
214 // add prach callback here
215 for (int i = 0; i < xranlib->get_num_cc(); i++)
217 ret = xran_5g_prach_req(Init_Sys_Check::nInstanceHandle[0][i], pFthRxRachBuffer[i], pFthRxRachBufferDecomp[i],
218 xran_fh_rx_prach_callback,&pFthRxRachBuffer[i][0]);
227 TEST_P(Init_Sys_Check, Test_xran_get_common_counters)
230 struct xran_common_counters x_counters;
232 ret = xran_get_common_counters(xranlib->get_xranhandle(), &x_counters);
235 ASSERT_EQ(0, x_counters.Rx_on_time);
236 ASSERT_EQ(0, x_counters.Rx_early);
237 ASSERT_EQ(0, x_counters.Rx_late);
238 ASSERT_EQ(0, x_counters.Rx_corrupt);
239 ASSERT_EQ(0, x_counters.Rx_pkt_dupl);
240 ASSERT_EQ(0, x_counters.Total_msgs_rcvd);
243 TEST_P(Init_Sys_Check, Test_xran_get_slot_idx)
245 #define NUM_OF_SUBFRAME_PER_FRAME 10
246 int32_t nNrOfSlotInSf = 1;
249 uint32_t nSubframeIdx;
253 uint32_t nXranTime = xran_get_slot_idx(0, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
254 nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf
255 + nSubframeIdx*nNrOfSlotInSf
258 ASSERT_EQ(0, nSfIdx);
261 TEST_P(Init_Sys_Check, Test_xran_reg_physide_cb)
263 struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
265 ret = xran_reg_physide_cb(xranlib->get_xranhandle(), physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
267 ASSERT_EQ((long long)physide_dl_tti_call_back, (long long)p_xran_dev_ctx->ttiCb[XRAN_CB_TTI]);
268 ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_TTI]);
269 ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_TTI]);
271 ret = xran_reg_physide_cb(xranlib->get_xranhandle(), physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);
273 ASSERT_EQ((long long)physide_ul_half_slot_call_back, (long long)p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]);
274 ASSERT_EQ((long long)NULL, (long long)p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]);
275 ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX]);
277 ret = xran_reg_physide_cb(xranlib->get_xranhandle(), physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX);
279 ASSERT_EQ((long long)physide_ul_full_slot_call_back,(long long) p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX]);
280 ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_FULL_SLOT_RX]);
281 ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_FULL_SLOT_RX]);
285 TEST_P(Init_Sys_Check, Test_xran_reg_sym_cb){
287 ret = xran_reg_sym_cb(xranlib->get_xranhandle(), physide_sym_call_back, NULL, NULL, 11, XRAN_CB_SYM_RX_WIN_END);
291 TEST_P(Init_Sys_Check, Test_xran_mm_destroy){
293 ret = xran_mm_destroy(xranlib->get_xranhandle());
297 TEST_P(Init_Sys_Check, Test_xran_start_stop){
299 ASSERT_EQ(XRAN_STOPPED, xran_if_current_state);
300 ret = xranlib->Start();
302 ASSERT_EQ(XRAN_RUNNING, xran_if_current_state);
303 ret = xranlib->Stop();
305 ASSERT_EQ(XRAN_STOPPED, xran_if_current_state);
308 INSTANTIATE_TEST_CASE_P(UnitTest, Init_Sys_Check,
309 testing::ValuesIn(get_sequence(Init_Sys_Check::get_number_of_cases("init_sys_functional"))));