1 /******************************************************************************
3 * Copyright (c) 2020 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * @brief XRAN layer common functionality for both lls-CU and RU as well as C-plane and
23 * @ingroup group_source_xran
24 * @author Intel Corporation
29 #include <arpa/inet.h>
33 #include "xran_frame_struct.h"
34 #include "xran_printf.h"
38 XRAN_BW_5_0_MHZ = 5, XRAN_BW_10_0_MHZ = 10, XRAN_BW_15_0_MHZ = 15, XRAN_BW_20_0_MHZ = 20, XRAN_BW_25_0_MHZ = 25,
39 XRAN_BW_30_0_MHZ = 30, XRAN_BW_40_0_MHZ = 40, XRAN_BW_50_0_MHZ = 50, XRAN_BW_60_0_MHZ = 60, XRAN_BW_70_0_MHZ = 70,
40 XRAN_BW_80_0_MHZ = 80, XRAN_BW_90_0_MHZ = 90, XRAN_BW_100_0_MHZ = 100, XRAN_BW_200_0_MHZ = 200, XRAN_BW_400_0_MHZ = 400
43 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
44 static uint16_t nNumRbsPerSymF1[3][13] =
46 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
47 {25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0}, // Numerology 0 (15KHz)
48 {11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273}, // Numerology 1 (30KHz)
49 {0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135} // Numerology 2 (60KHz)
52 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
53 static uint16_t nNumRbsPerSymF2[2][4] =
55 // 50Mhz 100MHz 200MHz 400MHz
56 {66, 132, 264, 0}, // Numerology 2 (60KHz)
57 {32, 66, 132, 264} // Numerology 3 (120KHz)
60 // 38.211 - Table 4.2.1
61 static uint16_t nSubCarrierSpacing[5] =
70 // TTI interval in us (slot duration)
71 static uint16_t nTtiInterval[4] =
80 // F1 Tables 38.101-1 Table F.5.3. Window length for normal CP
81 static uint16_t nCpSizeF1[3][13][2] =
83 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
84 {{40, 36}, {80, 72}, {120, 108}, {160, 144}, {160, 144}, {240, 216}, {320, 288}, {320, 288}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}}, // Numerology 0 (15KHz)
85 {{22, 18}, {44, 36}, {66, 54}, {88, 72}, {88, 72}, {132, 108}, {176, 144}, {176, 144}, {264, 216}, {264, 216}, {352, 288}, {352, 288}, {352, 288}}, // Numerology 1 (30KHz)
86 { {0, 0}, {26, 18}, {39, 27}, {52, 36}, {52, 36}, {78, 54}, {104, 72}, {104, 72}, {156, 108}, {156, 108}, {208, 144}, {208, 144}, {208, 144}}, // Numerology 2 (60KHz)
89 // F2 Tables 38.101-2 Table F.5.3. Window length for normal CP
90 static int16_t nCpSizeF2[2][4][2] =
92 // 50Mhz 100MHz 200MHz 400MHz
93 { {0, 0}, {104, 72}, {208, 144}, {416, 288}}, // Numerology 2 (60KHz)
94 {{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
99 static uint32_t xran_fs_max_slot_num[XRAN_PORTS_NUM] = {8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000};
100 static uint32_t xran_fs_max_slot_num_SFN[XRAN_PORTS_NUM] = {20480,20480,20480,20480,20480,20480,20480,20480}; /* max slot number counted as SFN is 0-1023 */
101 static uint16_t xran_fs_num_slot_tdd_loop[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{ XRAN_NUM_OF_SLOT_IN_TDD_LOOP }};
102 static uint16_t xran_fs_num_dl_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{{0}}};
103 static uint16_t xran_fs_num_ul_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{{0}}};
104 static uint8_t xran_fs_slot_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{{XRAN_SLOT_TYPE_INVALID}}};
105 static uint8_t xran_fs_slot_symb_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{{XRAN_SLOT_TYPE_INVALID}}}};
106 static float xran_fs_ul_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{0.0}};
107 static float xran_fs_dl_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {{0.0}};
109 extern uint16_t xran_max_frame;
111 uint32_t xran_fs_get_tti_interval(uint8_t nMu)
115 return nTtiInterval[nMu];
119 printf("ERROR: %s Mu[%d] is not valid, setting to 0\n",__FUNCTION__, nMu);
120 return nTtiInterval[0];
124 uint32_t xran_fs_get_scs(uint8_t nMu)
128 return nSubCarrierSpacing[nMu];
132 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
138 //-------------------------------------------------------------------------------------------
139 /** @ingroup group_nr5g_source_phy_common
141 * @param[in] nNumerology - Numerology determine sub carrier spacing, Value: 0->4 0: 15khz, 1: 30khz, 2: 60khz 3: 120khz, 4: 240khz
142 * @param[in] nBandwidth - Carrier bandwidth for in MHz. Value: 5->400
143 * @param[in] nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
145 * @return Number of RBs in cell
148 * Returns number of RBs based on 38.101-1 and 38.101-2 for the cell
151 //-------------------------------------------------------------------------------------------
152 uint16_t xran_fs_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
157 if (nAbsFrePointA <= 6000000)
159 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
164 case XRAN_BW_5_0_MHZ:
165 numRBs = nNumRbsPerSymF1[nNumerology][0];
168 case XRAN_BW_10_0_MHZ:
169 numRBs = nNumRbsPerSymF1[nNumerology][1];
172 case XRAN_BW_15_0_MHZ:
173 numRBs = nNumRbsPerSymF1[nNumerology][2];
176 case XRAN_BW_20_0_MHZ:
177 numRBs = nNumRbsPerSymF1[nNumerology][3];
180 case XRAN_BW_25_0_MHZ:
181 numRBs = nNumRbsPerSymF1[nNumerology][4];
184 case XRAN_BW_30_0_MHZ:
185 numRBs = nNumRbsPerSymF1[nNumerology][5];
188 case XRAN_BW_40_0_MHZ:
189 numRBs = nNumRbsPerSymF1[nNumerology][6];
192 case XRAN_BW_50_0_MHZ:
193 numRBs = nNumRbsPerSymF1[nNumerology][7];
196 case XRAN_BW_60_0_MHZ:
197 numRBs = nNumRbsPerSymF1[nNumerology][8];
200 case XRAN_BW_70_0_MHZ:
201 numRBs = nNumRbsPerSymF1[nNumerology][9];
204 case XRAN_BW_80_0_MHZ:
205 numRBs = nNumRbsPerSymF1[nNumerology][10];
208 case XRAN_BW_90_0_MHZ:
209 numRBs = nNumRbsPerSymF1[nNumerology][11];
212 case XRAN_BW_100_0_MHZ:
213 numRBs = nNumRbsPerSymF1[nNumerology][12];
224 if ((nNumerology >= 2) && (nNumerology <= 3))
226 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
229 case XRAN_BW_50_0_MHZ:
230 numRBs = nNumRbsPerSymF2[nNumerology-2][0];
233 case XRAN_BW_100_0_MHZ:
234 numRBs = nNumRbsPerSymF2[nNumerology-2][1];
237 case XRAN_BW_200_0_MHZ:
238 numRBs = nNumRbsPerSymF2[nNumerology-2][2];
241 case XRAN_BW_400_0_MHZ:
242 numRBs = nNumRbsPerSymF2[nNumerology-2][3];
255 printf("ERROR: %s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA);
259 printf("%s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA, numRBs);
265 //-------------------------------------------------------------------------------------------
266 /** @ingroup phy_cal_nrarfcn
268 * @param[in] center frequency
273 * This calculates NR-ARFCN value according to center frequency
276 //-------------------------------------------------------------------------------------------
277 uint32_t xran_fs_cal_nrarfcn(uint32_t nCenterFreq)
279 uint32_t nDeltaFglobal,nFoffs,nNoffs;
280 uint32_t nNRARFCN = 0;
282 if(nCenterFreq > 0 && nCenterFreq < 3000*1000)
288 else if(nCenterFreq >= 3000*1000 && nCenterFreq < 24250*1000)
294 else if(nCenterFreq >= 24250*1000 && nCenterFreq <= 100000*1000)
302 printf("@@@@ incorrect center frerquency %d\n",nCenterFreq);
306 nNRARFCN = ((nCenterFreq - nFoffs)/nDeltaFglobal) + nNoffs;
308 printf("%s: nCenterFreq[%d] nDeltaFglobal[%d] nFoffs[%d] nNoffs[%d] nNRARFCN[%d]\n", __FUNCTION__, nCenterFreq, nDeltaFglobal, nFoffs, nNoffs, nNRARFCN);
312 uint32_t xran_fs_slot_limit_init(uint32_t PortId, int32_t tti_interval_us)
314 xran_fs_max_slot_num[PortId] = (1000/tti_interval_us)*1000;
315 xran_fs_max_slot_num_SFN[PortId] = (1000/tti_interval_us)*(xran_max_frame+1)*10;
316 return xran_fs_max_slot_num[PortId];
319 uint32_t xran_fs_get_max_slot(uint32_t PortId)
321 return xran_fs_max_slot_num[PortId];
324 uint32_t xran_fs_get_max_slot_SFN(uint32_t PortId)
326 return xran_fs_max_slot_num_SFN[PortId];
329 int32_t xran_fs_slot_limit(uint32_t PortId, int32_t nSfIdx)
332 nSfIdx += xran_fs_max_slot_num[PortId];
335 while (nSfIdx >= xran_fs_max_slot_num[PortId]) {
336 nSfIdx -= xran_fs_max_slot_num[PortId];
342 void xran_fs_clear_slot_type(uint32_t PortId, uint32_t nPhyInstanceId)
344 xran_fs_ul_rate[PortId][nPhyInstanceId] = 0.0;
345 xran_fs_dl_rate[PortId][nPhyInstanceId] = 0.0;
346 xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] = 1;
349 int32_t xran_fs_set_slot_type(uint32_t PortId, uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig)
351 uint32_t nSlotNum, nSymNum, nVal, i, j;
352 uint32_t numDlSym, numUlSym, numGuardSym;
353 uint32_t numDlSlots = 0, numUlSlots = 0, numSpDlSlots = 0, numSpUlSlots = 0, numSpSlots = 0;
355 char sSlotPattern[XRAN_SLOT_TYPE_LAST][10] = {"IN\0", "DL\0", "UL\0", "SP\0", "FD\0"};
358 // nPhyInstanceId Carrier ID
359 // nFrameDuplexType 0 = FDD 1 = TDD
360 // nTddPeriod Tdd Periodicity
361 // psSlotConfig[80] Slot Config Structure for nTddPeriod Slots
363 xran_fs_ul_rate[PortId][nPhyInstanceId] = 0.0;
364 xran_fs_dl_rate[PortId][nPhyInstanceId] = 0.0;
365 xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] = nTddPeriod;
367 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
369 xran_fs_slot_type[PortId][nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID;
370 xran_fs_num_dl_sym_sp[PortId][nPhyInstanceId][i] = 0;
371 xran_fs_num_ul_sym_sp[PortId][nPhyInstanceId][i] = 0;
374 if (nFrameDuplexType == XRAN_FDD)
376 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
378 xran_fs_slot_type[PortId][nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD;
379 for(j = 0; j < XRAN_NUM_OF_SYMBOL_PER_SLOT; j++)
380 xran_fs_slot_symb_type[PortId][nPhyInstanceId][i][j] = XRAN_SYMBOL_TYPE_FDD;
382 xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] = 1;
383 xran_fs_dl_rate[PortId][nPhyInstanceId] = 1.0;
384 xran_fs_ul_rate[PortId][nPhyInstanceId] = 1.0;
388 for (nSlotNum = 0; nSlotNum < nTddPeriod; nSlotNum++)
393 for (nSymNum = 0; nSymNum < XRAN_NUM_OF_SYMBOL_PER_SLOT; nSymNum++)
395 switch(psSlotConfig[nSlotNum].nSymbolType[nSymNum])
397 case XRAN_SYMBOL_TYPE_DL:
399 xran_fs_slot_symb_type[PortId][nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_DL;
401 case XRAN_SYMBOL_TYPE_GUARD:
402 xran_fs_slot_symb_type[PortId][nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_GUARD;
406 xran_fs_slot_symb_type[PortId][nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_UL;
412 print_dbg("nSlotNum[%d] : numDlSym[%d] numGuardSym[%d] numUlSym[%d] ", nSlotNum, numDlSym, numGuardSym, numUlSym);
414 if ((numUlSym == 0) && (numGuardSym == 0))
416 xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL;
418 print_dbg("XRAN_SLOT_TYPE_DL\n");
420 else if ((numDlSym == 0) && (numGuardSym == 0))
422 xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL;
424 print_dbg("XRAN_SLOT_TYPE_UL\n");
428 xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP;
430 print_dbg("XRAN_SLOT_TYPE_SP\n");
435 xran_fs_num_dl_sym_sp[PortId][nPhyInstanceId][nSlotNum] = numDlSym;
440 xran_fs_num_ul_sym_sp[PortId][nPhyInstanceId][nSlotNum] = numUlSym;
443 print_dbg(" numDlSlots[%d] numUlSlots[%d] numSpSlots[%d] numSpDlSlots[%d] numSpUlSlots[%d]\n", numDlSlots, numUlSlots, numSpSlots, numSpDlSlots, numSpUlSlots);
446 xran_fs_dl_rate[PortId][nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod;
447 xran_fs_ul_rate[PortId][nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod;
450 print_dbg("%s: nPhyInstanceId[%d] nFrameDuplexType[%d], nTddPeriod[%d]\n",
451 __FUNCTION__, nPhyInstanceId, nFrameDuplexType, nTddPeriod);
453 print_dbg("DLRate[%f] ULRate[%f]\n", xran_fs_dl_rate[PortId][nPhyInstanceId], xran_fs_ul_rate[PortId][nPhyInstanceId]);
455 nVal = (xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] < 10) ? xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] : 10;
457 print_dbg("SlotPattern:\n");
459 for (nSlotNum = 0; nSlotNum < nVal; nSlotNum++)
461 print_dbg("%d ", nSlotNum);
465 print_dbg(" %3d ", 0);
466 for (nSlotNum = 0, i = 0; nSlotNum < xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId]; nSlotNum++)
468 print_dbg("%s ", sSlotPattern[xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum]]);
470 if ((i == 10) && ((nSlotNum+1) < xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId]))
473 print_dbg(" %3d ", nSlotNum);
482 int32_t xran_fs_get_slot_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx, int32_t nType)
484 int32_t nSfIdxMod, nSfType, ret = 0;
486 nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1);
487 nSfType = xran_fs_slot_type[PortId][nCellIdx][nSfIdxMod];
489 if (nSfType == nType)
493 else if (nSfType == XRAN_SLOT_TYPE_SP)
495 if ((nType == XRAN_SLOT_TYPE_DL) && xran_fs_num_dl_sym_sp[PortId][nCellIdx][nSfIdxMod])
500 if ((nType == XRAN_SLOT_TYPE_UL) && xran_fs_num_ul_sym_sp[PortId][nCellIdx][nSfIdxMod])
505 else if (nSfType == XRAN_SLOT_TYPE_FDD)
513 int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx)
517 nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1);
519 return xran_fs_slot_symb_type[PortId][nCellIdx][nSfIdxMod][nSymbIdx];