/******************************************************************************
*
-* Copyright (c) 2019 Intel.
+* Copyright (c) 2020 Intel.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
{
enum xran_pkt_dir direction = XRAN_DIR_DL;
uint16_t section_id = 7;
+ uint16_t num_sections = 1;
enum xran_input_byte_order iq_buf_byte_order = XRAN_CPU_LE_BYTE_ORDER;
uint8_t frame_id = 99;
uint8_t subframe_id = 9;
uint8_t seq_id =0;
uint32_t do_copy = 0;
uint8_t compMeth = 0;
+ enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC;
uint8_t iqWidth = 16;
int32_t prep_bytes;
prep_bytes = prepare_symbol_ex(direction,
section_id,
test_buffer,
- (struct rb_map *)iq_offset,
+ (uint8_t *)iq_offset,
compMeth,
iqWidth,
iq_buf_byte_order,
CC_ID,
RU_Port_ID,
seq_id,
- do_copy);
+ do_copy,
+ staticEn,
+ num_sections,
+ 0);
ASSERT_EQ(prep_bytes, 3168);
sizeof (struct xran_ecpri_hdr) +
sizeof(struct radio_app_common_hdr));
- ASSERT_EQ (ecpri_hdr->cmnhdr.ecpri_mesg_type, ECPRI_IQ_DATA);
- payl_size = rte_be_to_cpu_16(ecpri_hdr->cmnhdr.ecpri_payl_size);
+ ASSERT_EQ (ecpri_hdr->cmnhdr.bits.ecpri_mesg_type, ECPRI_IQ_DATA);
+ payl_size = rte_be_to_cpu_16(ecpri_hdr->cmnhdr.bits.ecpri_payl_size);
ASSERT_EQ (payl_size, 3180);
- ASSERT_EQ(app_hdr->data_direction, direction);
+ ASSERT_EQ(app_hdr->data_feature.data_direction, direction);
ASSERT_EQ(app_hdr->frame_id, frame_id);
res_sect.fields.all_bits = rte_be_to_cpu_32(section_hdr->fields.all_bits);
{
/* UL direction */
void *iq_samp_buf;
- struct ecpri_seq_id seq;
+ union ecpri_seq_id seq;
int num_bytes = 0;
uint8_t CC_ID = 0;
&rb,
§_id,
0,
+ XRAN_COMP_HDR_TYPE_DYNAMIC,
&compMeth,
&iqWidth);