* INTC Contribution to the O-RAN F Release for O-DU Low

[o-du/phy.git] / fhi_lib / app / usecase / cat_b / mu1_100mhz / 1 / config_file_o_ru.dat

diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat
index d149f4e..35378b1 100644 (file)
--- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat
+++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat
@@ -110,11 +110,14 @@ antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin  #CC3
 antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin  #CC3
 antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin  #CC3
 
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
 prachConfigIndex=189
 
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3           # scheduled SRS slot within TDD period
+srsNdmOffset=3      # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4  # TX duration for NDM SRTS U-Plane (numberof of symbols)
 
 antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
 antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
@@ -179,6 +182,9 @@ PrbElemUl5=180,36,0,14,6,1,1,9,1
 PrbElemUl6=216,36,0,14,7,1,1,9,1
 PrbElemUl7=252,21,0,14,8,1,1,9,1
 
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
 ###########################################################
 
 ## control of IQ byte order