1 /******************************************************************************
3 * Copyright (c) 2021 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
23 #include <linux/types.h>
24 #include <linux/module.h>
25 #include <linux/device.h>
26 #include <linux/ioctl.h>
27 #include <linux/cdev.h>
28 #include <linux/wait.h>
29 #include <linux/sched.h>
30 #define MODNAME (KBUILD_MODNAME)
31 #else /* __KERNEL__ */
32 #include <sys/ioctl.h>
34 #include <semaphore.h>
35 #include <rte_common.h>
36 #include <rte_atomic.h>
37 #include <rte_memzone.h>
43 #define WLS_PRINT(format, args...) printk(format, ##args)
44 #define WLS_ERROR(format, args...) printk(KERN_ERR "wls err: " format,##args)
47 #define WLS_DEBUG(format, args...) \
50 printk(KERN_INFO "wls debug: " format,##args); \
53 #define WLS_DEBUG(format, args...) do { } while(0)
56 /******************************************************************************
57 * Module error codes *
58 ******************************************************************************/
59 #define WLS_RC_MDMA_ID_ERROR (-1)
60 #define WLS_RC_MDMA_TASK_ERROR (-2)
61 #define WLS_RC_ALLOC_DELAY_MEM_ERROR (-3)
62 #define WLS_RC_ALLOC_BAR_MEM_ERROR (-4)
63 #define WLS_RC_ALLOC_TAR_MEM_ERROR (-5)
64 #define WLS_RC_PARAM_SIZE_ERROR (-6)
65 #define WLS_RC_WLS_HEAP_ALLOC_ERROR (-7)
66 #define WLS_RC_IRQ_ALLOC_ERROR (-8)
67 #define WLS_RC_DMA_ALLOC_ERROR (-9)
68 #define WLS_RC_TRANSACTION_ERROR (-10)
69 #define WLS_RC_PHY_CTX_ERROR (-11)
70 #define WLS_RC_KERNEL_HEAP_ALLOC_ERROR (-12)
71 #define WLS_RC_CONFIGURATION_ERROR (-13)
72 #define WLS_RC_THREAD_CREATION_ERROR (-14)
74 #define WLS_IOC_MAGIC 'W'
75 #define WLS_IOC_OPEN _IOWR(WLS_IOC_MAGIC, WLS_IOC_OPEN_NO, uint64_t)
76 #define WLS_IOC_CLOSE _IOWR(WLS_IOC_MAGIC, WLS_IOC_CLOSE_NO, uint64_t)
77 #define WLS_IOC_PUT _IOWR(WLS_IOC_MAGIC, WLS_IOC_PUT_NO, uint64_t)
78 #define WLS_IOC_EVENT _IOWR(WLS_IOC_MAGIC, WLS_IOC_EVENT_NO, uint64_t)
79 #define WLS_IOC_WAIT _IOWR(WLS_IOC_MAGIC, WLS_IOC_WAIT_NO, uint64_t)
80 #define WLS_IOC_WAKE_UP _IOWR(WLS_IOC_MAGIC, WLS_IOC_WAKE_UP_NO, uint64_t)
81 #define WLS_IOC_CONNECT _IOWR(WLS_IOC_MAGIC, WLS_IOC_CONNECT_NO, uint64_t)
82 #define WLS_IOC_FILL _IOWR(WLS_IOC_MAGIC, WLS_IOC_FILL_NO, uint64_t)
103 #define WLS_RUP512B(x) (((x)+511)&(~511))
104 #define WLS_RUP256B(x) (((x)+255)&(~255))
105 #define WLS_RUP128B(x) (((x)+127)&(~127))
106 #define WLS_RUP64B(x) (((x)+63)&(~63))
107 #define WLS_RUP32B(x) (((x)+31)&(~31))
108 #define WLS_RUP16B(x) (((x)+15)&(~15))
109 #define WLS_RUP8B(x) (((x)+7)&(~7))
110 #define WLS_RUP4B(x) (((x)+3)&(~3))
111 #define WLS_RUP2B(x) (((x)+1)&(~1))
113 #define WLS_US_CLIENTS_MAX 4
115 #define CACHE_LINE_SIZE 64 /**< Cache line size. */
116 #define CACHE_LINE_MASK (CACHE_LINE_SIZE-1) /**< Cache line mask. */
118 #define CACHE_LINE_ROUNDUP(size) \
119 (CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE))
121 #define DMA_ALIGNMENT_SIZE 256L
123 // To make DMA we make sure that block starts on 256 bytes boundary
124 #define DMA_ALIGNMENT_ROUNDUP(size) \
125 (DMA_ALIGNMENT_SIZE * ((size + DMA_ALIGNMENT_SIZE - 1) / DMA_ALIGNMENT_SIZE))
127 /**< Return the first cache-aligned value greater or equal to size. */
130 * Force alignment to cache line.
132 #define __wls_cache_aligned __attribute__((__aligned__(CACHE_LINE_SIZE)))
134 #define WLS_HUGE_DEF_PAGE_SIZE 0x40000000LL
135 #define WLS_IS_ONE_HUGE_PAGE(ptr, size, hp_size) ((((unsigned long long)ptr & (~(hp_size - 1)))\
136 == (((unsigned long long)ptr + size - 1) & (~(hp_size - 1)))) ? 1 : 0)
138 typedef struct hugepage_tabl_s
144 #define DMA_MAP_MAX_BLOCK_SIZE 64*1024
145 #define MAX_N_HUGE_PAGES 32
146 #define UL_FREE_BLOCK_QUEUE_SIZE 1200
148 #define WLS_GET_QUEUE_N_ELEMENTS 1024
149 #define WLS_PUT_QUEUE_N_ELEMENTS 1024
151 #define WLS_DEV_SHM_NAME_LEN RTE_MEMZONE_NAMESIZE
153 #define FIFO_LEN 1024
155 typedef struct wls_wait_req_s {
156 uint64_t wls_us_kernel_va;
163 typedef struct wls_sema_priv_s
166 rte_atomic16_t is_irq;
167 wls_wait_req_t drv_block[FIFO_LEN];
168 volatile unsigned int drv_block_put;
169 volatile unsigned int drv_block_get;
172 typedef struct wls_us_priv_s
174 wls_sema_priv_t sema;
180 typedef struct wls_us_ctx_s
183 void * wls_us_user_space_va;
184 uint64_t padding_wls_us_user_space_va;
187 uint64_t wls_us_kernel_va;
191 uint32_t wls_us_ctx_size;
192 uint32_t HugePageSize;
196 uint64_t padding_alloc_buffer;
199 hugepage_tabl_t hugepageTbl [MAX_N_HUGE_PAGES];
201 FASTQUEUE ul_free_block_pq;
202 uint64_t ul_free_block_storage[UL_FREE_BLOCK_QUEUE_SIZE * sizeof(uint64_t)];
204 WLS_MSG_QUEUE get_queue;
205 WLS_MSG_HANDLE get_storage[WLS_GET_QUEUE_N_ELEMENTS];
207 WLS_MSG_QUEUE put_queue;
208 WLS_MSG_HANDLE put_storage[WLS_PUT_QUEUE_N_ELEMENTS];
210 uint64_t freePtrList[UL_FREE_BLOCK_QUEUE_SIZE * sizeof(uint64_t)];
211 uint32_t freeListIndex;
214 // dst userspace context address (kernel va)
215 uint64_t dst_kernel_va;
216 // dst userspace context address (local user sapce va)
218 volatile uint64_t dst_user_va;
219 // dst userspace context address (local user sapce va)
220 volatile uint64_t dst_pa;
223 wls_us_priv_t wls_us_private;
226 char wls_dev_name[WLS_DEV_SHM_NAME_LEN];
227 char wls_shm_name[WLS_DEV_SHM_NAME_LEN];
232 typedef struct wls_fill_req_s {
233 uint64_t wls_us_kernel_va;
239 typedef struct wls_connect_req_s {
240 uint64_t wls_us_kernel_va;
243 typedef struct wls_drv_ctx_s
246 uint32_t us_ctx_cout;
247 wls_us_ctx_t p_wls_us_ctx[WLS_US_CLIENTS_MAX];
248 wls_us_ctx_t p_wls_us_pa_ctx[WLS_US_CLIENTS_MAX];
249 uint32_t nWlsClients;
250 uint32_t nMacBufferSize;
251 uint32_t nPhyBufferSize;
252 pthread_mutex_t mng_mutex;
255 typedef struct wls_open_req_s {
261 typedef struct wls_close_req_s {
267 typedef enum wls_events_num_s {
268 WLS_EVENT_IA_READY = 0,
274 typedef struct wls_event_req_s {
275 uint64_t wls_us_kernel_va;
276 uint64_t event_to_wls;
277 uint64_t event_param;
280 typedef struct wls_put_req_s {
281 uint64_t wls_us_kernel_va;
284 typedef struct wls_wake_up_req_s {
285 uint64_t wls_us_kernel_va;
291 static inline uint64_t wls_rdtsc(void)
301 asm volatile("rdtsc" :
307 #endif /* __WLS_H__*/