1 /******************************************************************************
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3 * Copyright (c) 2019 Intel.
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5 * Licensed under the Apache License, Version 2.0 (the "License");
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6 * you may not use this file except in compliance with the License.
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7 * You may obtain a copy of the License at
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9 * http://www.apache.org/licenses/LICENSE-2.0
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11 * Unless required by applicable law or agreed to in writing, software
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12 * distributed under the License is distributed on an "AS IS" BASIS,
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13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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14 * See the License for the specific language governing permissions and
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15 * limitations under the License.
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17 *******************************************************************************/
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20 #ifndef XRAN_LIB_WRAP_HPP
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21 #define XRAN_LIB_WRAP_HPP
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23 #include <exception>
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32 #include "common.hpp"
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33 #include "xran_fh_o_du.h"
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34 #include "xran_common.h"
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35 #include "xran_frame_struct.h"
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38 #define XRAN_UT_CFG_FILENAME "conf.json"
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40 #define XRAN_UT_KEY_GLOBALCFG "GLOBAL"
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41 #define XRAN_UT_KEY_GLOBALCFG_IO "io_cfg"
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42 #define XRAN_UT_KEY_GLOBALCFG_EAXCID "eAxCId_cfg"
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43 #define XRAN_UT_KEY_GLOBALCFG_PRACH "prach_cfg"
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44 #define XRAN_UT_KEY_GLOBALCFG_RU "ru_cfg"
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45 #define XRAN_UT_KEY_GLOBALCFG_SLOT "slotcfg_"
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47 #define MAX_NUM_OF_XRAN_CTX (2)
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49 #define SW_FPGA_TOTAL_BUFFER_LEN (4*1024*1024*1024)
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50 #define SW_FPGA_SEGMENT_BUFFER_LEN (1*1024*1024*1024)
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51 #define SW_FPGA_FH_TOTAL_BUFFER_LEN (1*1024*1024*1024)
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52 #define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192)
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54 #define MAX_ANT_CARRIER_SUPPORTED (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR)
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58 extern uint32_t xran_lib_ota_tti;
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59 extern uint32_t xran_lib_ota_sym;
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60 extern uint32_t xran_lib_ota_sym_idx;
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62 void sym_ota_cb(struct rte_timer *tim, void *arg);
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63 void tti_ota_cb(struct rte_timer *tim, void *arg);
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72 XRANFTHTX_PRB_MAP_OUT,
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73 XRANFTHTX_SEC_DESC_OUT,
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75 XRANFTHRX_PRB_MAP_IN,
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76 XRANFTHTX_SEC_DESC_IN,
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78 MAX_SW_XRAN_INTERFACE_NUM
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79 } SWXRANInterfaceTypeEnum;
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83 PHY_BW_5MHZ = 5, PHY_BW_10MHZ = 10, PHY_BW_15MHZ = 15,
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84 PHY_BW_20MHZ = 20, PHY_BW_25MHZ = 25, PHY_BW_30MHZ = 30,
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85 PHY_BW_40MHZ = 40, PHY_BW_50MHZ = 50, PHY_BW_60MHZ = 60,
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86 PHY_BW_70MHZ = 70, PHY_BW_80MHZ = 80, PHY_BW_90MHZ = 90,
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87 PHY_BW_100MHZ = 100, PHY_BW_200MHZ = 200, PHY_BW_400MHZ = 400
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90 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
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91 const uint16_t nNumRbsPerSymF1[3][13] =
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93 // 5MHz 10MHz 15MHz 20MHz 25MHz 30MHz 40MHz 50MHz 60MHz 70MHz 80MHz 90MHz 100MHz
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94 { 25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0 }, // Numerology 0 (15KHz)
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95 { 11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273 }, // Numerology 1 (30KHz)
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96 { 0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135 } // Numerology 2 (60KHz)
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99 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
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100 const uint16_t nNumRbsPerSymF2[2][4] =
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102 // 50MHz 100MHz 200MHz 400MHz
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103 { 66, 132, 264, 0 }, // Numerology 2 (60KHz)
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104 { 32, 66, 132, 264 } // Numerology 3 (120KHz)
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109 char argv[25] = "unittest";
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111 std::string m_dpdk_dev_up, m_dpdk_dev_cp, m_dpdk_bbdev;
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113 void *m_xranhandle;
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115 uint8_t m_du_mac[6] = { 0x00,0x11, 0x22, 0x33, 0x44, 0x66 };
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116 uint8_t m_ru_mac[6] = { 0x00,0x11, 0x22, 0x33, 0x44, 0x55 };
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118 uint32_t m_nSlots = 10;
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120 struct xran_fh_config m_xranConf;
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121 struct xran_fh_init m_xranInit;
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123 struct xran_timer_ctx {
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124 uint32_t tti_to_process;
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125 } m_timer_ctx[MAX_NUM_OF_XRAN_CTX];
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128 BbuIoBufCtrlStruct m_sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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129 BbuIoBufCtrlStruct m_sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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130 BbuIoBufCtrlStruct m_sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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131 BbuIoBufCtrlStruct m_sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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132 BbuIoBufCtrlStruct m_sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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134 /* buffers lists */
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135 struct xran_flat_buffer m_sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
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136 struct xran_flat_buffer m_sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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137 struct xran_flat_buffer m_sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
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138 struct xran_flat_buffer m_sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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139 struct xran_flat_buffer m_sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
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141 void *m_nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector
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142 uint32_t m_nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool
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144 uint32_t m_nSW_ToFpga_FTH_TxBufferLen;
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145 uint32_t m_nFpgaToSW_FTH_RxBufferLen;
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147 int32_t m_nSectorIndex[XRAN_MAX_SECTOR_NR];
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149 int iq_bfw_buffer_size_dl = 0;
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150 int iq_bfw_buffer_size_ul = 0;
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152 /* beamforming weights for UL (O-DU) */
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153 int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
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154 int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
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155 int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
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157 /* beamforming weights for UL (O-DU) */
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158 int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
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159 int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
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160 int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
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166 template<typename T>
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167 T get_globalcfg(const std::string &type, const std::string ¶meter_name)
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169 return m_global_cfg[XRAN_UT_KEY_GLOBALCFG][type][parameter_name];
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172 template<typename T>
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173 std::vector<T> get_globalcfg_array(const std::string &type, const std::string ¶meter_name)
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175 auto array_size = m_global_cfg[XRAN_UT_KEY_GLOBALCFG][type][parameter_name].size();
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177 std::vector<T> result(array_size);
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179 for(unsigned number = 0; number < array_size; number++)
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180 result.at(number) = m_global_cfg[XRAN_UT_KEY_GLOBALCFG][type][parameter_name][number];
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185 uint16_t get_eaxcid_mask(int numbit, int shift)
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187 uint16_t result = 0;
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189 for(int i=0; i < numbit; i++) {
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190 result = result << 1; result +=1;
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192 return (result << shift);
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197 xran_status_t status;
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198 int32_t i, j, k, z;
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199 SWXRANInterfaceTypeEnum eInterfaceType;
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207 std::cout << "XRAN front haul xran_mm_init" << std::endl;
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208 status = xran_mm_init(m_xranhandle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);
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209 if(status != XRAN_STATUS_SUCCESS) {
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210 std::cout << "Failed at XRAN front haul xran_mm_init" << std::endl;
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214 /* initialize maximum instances to have flexibility for the tests */
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215 int nInstanceNum = XRAN_MAX_SECTOR_NR;
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216 /* initialize maximum supported CC to have flexibility on the test */
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217 int32_t nSectorNum = 6;//XRAN_MAX_SECTOR_NR;
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219 for(k = 0; k < XRAN_PORTS_NUM; k++) {
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220 status = xran_sector_get_instances(m_xranhandle, nInstanceNum, &m_nInstanceHandle[k][0]);
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221 if(status != XRAN_STATUS_SUCCESS) {
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222 std::cout << "get sector instance failed " << k << " for XRAN nInstanceNum " << nInstanceNum << std::endl;
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225 for (i = 0; i < nInstanceNum; i++)
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226 std::cout << __func__ << " [" << k << "]: CC " << i << " handle " << m_nInstanceHandle[0][i] << std::endl;
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228 std::cout << "Sucess xran_mm_init" << std::endl;
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231 for(i = 0; i<nSectorNum; i++) {
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232 eInterfaceType = XRANFTHTX_OUT;
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233 status = xran_bm_init(m_nInstanceHandle[0][i],
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234 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
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235 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
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236 m_nSW_ToFpga_FTH_TxBufferLen);
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237 if(status != XRAN_STATUS_SUCCESS) {
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238 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
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241 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
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242 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
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243 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0;
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244 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
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245 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
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246 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
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247 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
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248 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulTxBuffers[j][i][z][0];
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250 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {
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251 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol
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252 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
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253 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
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254 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
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255 if(status != XRAN_STATUS_SUCCESS) {
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256 std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;
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259 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
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260 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
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263 u32dptr = (uint32_t*)(ptr);
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264 uint8_t *ptr_temp = (uint8_t *)ptr;
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265 memset(u32dptr, 0x0, m_nSW_ToFpga_FTH_TxBufferLen);
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272 eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
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273 status = xran_bm_init(m_nInstanceHandle[0][i],
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274 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
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275 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
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276 if(XRAN_STATUS_SUCCESS != status) {
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277 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
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280 eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
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281 status = xran_bm_init(m_nInstanceHandle[0][i],
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282 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
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283 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
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284 sizeof(struct xran_prb_map));
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285 if(status != XRAN_STATUS_SUCCESS) {
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286 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
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289 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
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290 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
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291 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
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292 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
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293 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
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294 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
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295 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
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296 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulTxPrbMapBuffers[j][i][z];
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298 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
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299 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
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300 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
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301 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
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302 if(status != XRAN_STATUS_SUCCESS) {
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303 std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;
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306 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
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307 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
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311 struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
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312 //memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map));
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313 for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SYM; elm_id++){
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314 struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
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315 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
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316 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT], &sd_ptr, &sd_mb);
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317 if(XRAN_STATUS_SUCCESS != status){
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318 std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;
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321 pPrbElem->p_sec_desc[k] = (struct xran_section_desc *)sd_ptr;
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328 for(i = 0; i<nSectorNum; i++) {
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329 eInterfaceType = XRANFTHRX_IN;
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330 status = xran_bm_init(m_nInstanceHandle[0][i],
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331 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
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332 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
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333 m_nSW_ToFpga_FTH_TxBufferLen); /* ????, actual alloc size is m_nFpgaToSW_FTH_RxBUfferLen */
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334 if(status != XRAN_STATUS_SUCCESS) {
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335 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
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339 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
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340 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
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341 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0;
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342 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
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343 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
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344 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
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345 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
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346 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulRxBuffers[j][i][z][0];
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347 for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {
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348 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nFpgaToSW_FTH_RxBufferLen;
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349 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
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350 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
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351 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],&ptr, &mb);
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352 if(status != XRAN_STATUS_SUCCESS) {
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353 std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;
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356 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
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357 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb;
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359 u32dptr = (uint32_t*)(ptr);
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360 uint8_t *ptr_temp = (uint8_t *)ptr;
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361 memset(u32dptr, 0x0, m_nFpgaToSW_FTH_RxBufferLen);
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367 eInterfaceType = XRANFTHTX_SEC_DESC_IN;
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368 status = xran_bm_init(m_nInstanceHandle[0][i],
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369 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
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370 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
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371 if(XRAN_STATUS_SUCCESS != status) {
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372 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
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375 eInterfaceType = XRANFTHRX_PRB_MAP_IN;
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376 status = xran_bm_init(m_nInstanceHandle[0][i],
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377 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
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378 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
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379 sizeof(struct xran_prb_map));
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380 if(status != XRAN_STATUS_SUCCESS) {
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381 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
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385 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
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386 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
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387 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
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388 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
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389 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
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390 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
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391 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
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392 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulRxPrbMapBuffers[j][i][z];
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394 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
\r
395 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
\r
396 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
\r
397 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i],m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
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398 if(status != XRAN_STATUS_SUCCESS) {
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399 std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer , status " << status << std::endl;
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402 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
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403 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
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407 struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
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408 //memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map));
\r
409 for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SYM; elm_id++){
\r
410 struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
\r
411 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
\r
412 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN], &sd_ptr, &sd_mb);
\r
413 if(XRAN_STATUS_SUCCESS != status){
\r
414 std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;
\r
417 pPrbElem->p_sec_desc[k] = (struct xran_section_desc *)sd_ptr;
\r
424 for(i = 0; i<nSectorNum; i++) {
\r
425 eInterfaceType = XRANFTHRACH_IN;
\r
426 status = xran_bm_init(m_nInstanceHandle[0][i],
\r
427 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
\r
428 XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,
\r
429 FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
\r
430 if(status != XRAN_STATUS_SUCCESS) {
\r
431 std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;
\r
434 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {
\r
435 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
\r
436 m_sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
\r
437 m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
438 m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
439 m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
440 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR;
\r
441 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFHPrachRxBuffers[j][i][z][0];
\r
442 for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {
\r
443 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN;
\r
444 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
\r
445 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
\r
446 status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
\r
447 if(status != XRAN_STATUS_SUCCESS) {
\r
448 std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;
\r
451 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
\r
452 m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
\r
454 u32dptr = (uint32_t*)(ptr);
\r
455 memset(u32dptr, 0x0, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
\r
470 std::string tmpstr;
\r
471 unsigned int tmp_mac[6];
\r
473 m_global_cfg = read_json_from_file(XRAN_UT_CFG_FILENAME);
\r
475 memset(&m_xranInit, 0, sizeof(xran_fh_init));
\r
477 m_xranInit.io_cfg.id = 0;
\r
479 /* DPDK configuration */
\r
480 m_dpdk_dev_up = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdk_dev_up");
\r
481 m_dpdk_dev_cp = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdk_dev_cp");
\r
482 m_xranInit.io_cfg.dpdk_dev[XRAN_UP_VF] = (m_dpdk_dev_up == "") ? NULL : (char *)&m_dpdk_dev_up;
\r
483 m_xranInit.io_cfg.dpdk_dev[XRAN_CP_VF] = (m_dpdk_dev_cp == "") ? NULL : (char *)&m_dpdk_dev_cp;
\r
485 m_xranInit.io_cfg.core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "core");
\r
486 m_xranInit.io_cfg.system_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "system_core");
\r
487 m_xranInit.io_cfg.pkt_proc_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "pkt_proc_core");
\r
488 m_xranInit.io_cfg.pkt_aux_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "pkt_aux_core");
\r
489 m_xranInit.io_cfg.timing_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "timing_core");
\r
491 std::string bbdev_mode = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "bbdev_mode");
\r
492 if(bbdev_mode == "sw")
\r
493 m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_MODE_HW_OFF;
\r
494 else if(bbdev_mode == "hw")
\r
495 m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_MODE_HW_ON;
\r
496 else if(bbdev_mode == "none")
\r
497 m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
\r
499 std::cout << "Invalid BBDev mode [" << bbdev_mode << "], bbdev won't be used." << std::endl;
\r
500 m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
\r
503 m_xranInit.dpdkBasebandFecMode = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkBasebandFecMode");
\r
505 m_dpdk_bbdev = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkBasebandDevice");
\r
506 m_xranInit.dpdkBasebandDevice = (m_dpdk_bbdev == "") ? NULL : (char *)&m_dpdk_bbdev;
\r
508 /* Network configurations */
\r
509 m_xranInit.mtu = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "mtu");
\r
511 std::string du_mac_str = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "o_du_macaddr");
\r
512 std::string ru_mac_str = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "o_ru_macaddr");
\r
513 /* using temp variables to resolve KW issue */
\r
514 std::sscanf(du_mac_str.c_str(), "%02x:%02x:%02x:%02x:%02x:%02x",
\r
515 &tmp_mac[0], &tmp_mac[1], &tmp_mac[2],
\r
516 &tmp_mac[3], &tmp_mac[4], &tmp_mac[5]);
\r
518 m_du_mac[i] = (uint8_t)tmp_mac[i];
\r
519 std::sscanf(du_mac_str.c_str(), "%02x:%02x:%02x:%02x:%02x:%02x",
\r
520 &tmp_mac[0], &tmp_mac[1], &tmp_mac[2],
\r
521 &tmp_mac[3], &tmp_mac[4], &tmp_mac[5]);
\r
523 m_ru_mac[i] = (uint8_t)tmp_mac[i];
\r
524 m_xranInit.p_o_du_addr = (int8_t *)m_du_mac;
\r
525 m_xranInit.p_o_ru_addr = (int8_t *)m_ru_mac;
\r
526 m_xranInit.cp_vlan_tag = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "cp_vlan_tag");
\r
527 m_xranInit.up_vlan_tag = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "up_vlan_tag");
\r
529 /* eAxCID configurations */
\r
530 int bitnum_cuport = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_cuPortId");
\r
531 int bitnum_bandsec = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_bandSectorId");
\r
532 int bitnum_ccid = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_ccId");
\r
533 int bitnum_ruport = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_ruPortId");
\r
535 m_xranInit.eAxCId_conf.bit_cuPortId = bitnum_bandsec + bitnum_ccid + bitnum_ruport;
\r
536 m_xranInit.eAxCId_conf.bit_bandSectorId = bitnum_ccid + bitnum_ruport;
\r
537 m_xranInit.eAxCId_conf.bit_ccId = bitnum_ruport;
\r
538 m_xranInit.eAxCId_conf.bit_ruPortId = 0;
\r
539 m_xranInit.eAxCId_conf.mask_cuPortId = get_eaxcid_mask(bitnum_cuport, m_xranInit.eAxCId_conf.bit_cuPortId);
\r
540 m_xranInit.eAxCId_conf.mask_bandSectorId = get_eaxcid_mask(bitnum_bandsec, m_xranInit.eAxCId_conf.bit_bandSectorId);
\r
541 m_xranInit.eAxCId_conf.mask_ccId = get_eaxcid_mask(bitnum_ccid, m_xranInit.eAxCId_conf.bit_ccId);
\r
542 m_xranInit.eAxCId_conf.mask_ruPortId = get_eaxcid_mask(bitnum_ruport, m_xranInit.eAxCId_conf.bit_ruPortId);
\r
544 m_xranInit.totalBfWeights = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "totalBfWeights");
\r
546 m_xranInit.Tadv_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Tadv_cp_dl");
\r
547 m_xranInit.T2a_min_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_dl");
\r
548 m_xranInit.T2a_max_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_dl");
\r
549 m_xranInit.T2a_min_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_ul");
\r
550 m_xranInit.T2a_max_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_ul");
\r
551 m_xranInit.T2a_min_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_up");
\r
552 m_xranInit.T2a_max_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_up");
\r
553 m_xranInit.Ta3_min = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_min");
\r
554 m_xranInit.Ta3_max = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_max");
\r
555 m_xranInit.T1a_min_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_dl");
\r
556 m_xranInit.T1a_max_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_dl");
\r
557 m_xranInit.T1a_min_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_ul");
\r
558 m_xranInit.T1a_max_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_ul");
\r
559 m_xranInit.T1a_min_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_up");
\r
560 m_xranInit.T1a_max_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_up");
\r
561 m_xranInit.Ta4_min = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_min");
\r
562 m_xranInit.Ta4_max = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_max");
\r
564 m_xranInit.enableCP = 1;
\r
565 m_xranInit.prachEnable = 1;
\r
566 m_xranInit.debugStop = 0;
\r
567 m_xranInit.debugStopCount = 0;
\r
568 m_xranInit.DynamicSectionEna= 0;
\r
570 m_xranInit.filePrefix = "wls";
\r
572 m_bSub6 = get_globalcfg<bool>(XRAN_UT_KEY_GLOBALCFG_RU, "sub6");
\r
574 memset(&m_xranConf, 0, sizeof(struct xran_fh_config));
\r
575 tmpstr = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_RU, "duplex");
\r
576 if(tmpstr == "FDD") {
\r
577 m_xranConf.frame_conf.nFrameDuplexType = 0;
\r
579 else if(tmpstr == "TDD") {
\r
580 m_xranConf.frame_conf.nFrameDuplexType = 1;
\r
582 std::string slotcfg_key = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_RU, "slot_config");
\r
584 int numcfg = get_globalcfg<int>(slotcfg_key, "period");
\r
585 m_xranConf.frame_conf.nTddPeriod = numcfg;
\r
587 for(int i=0; i< numcfg; i++) {
\r
588 std::stringstream slotcfgname;
\r
589 slotcfgname << "slot" << i;
\r
590 std::vector<int> slotcfg = get_globalcfg_array<int>(slotcfg_key, slotcfgname.str());
\r
591 for(int j=0; j < slotcfg.size(); j++) {
\r
592 m_xranConf.frame_conf.sSlotConfig[i].nSymbolType[j] = slotcfg[j];
\r
594 m_xranConf.frame_conf.sSlotConfig[i].reserved[0] = 0;
\r
595 m_xranConf.frame_conf.sSlotConfig[i].reserved[1] = 0;
\r
599 std::cout << "*** Invalid Duplex type [" << tmpstr << "] !!!" << std::endl;
\r
600 std::cout << "****** Set it to FDD... " << std::endl;
\r
601 m_xranConf.frame_conf.nFrameDuplexType = 0;
\r
604 m_xranConf.frame_conf.nNumerology = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "mu");
\r
605 if(m_xranConf.frame_conf.nNumerology > 3) {
\r
606 std::cout << "*** Invalid Numerology [" << m_xranConf.frame_conf.nNumerology << "] !!!" << std::endl;
\r
607 m_xranConf.frame_conf.nNumerology = 0;
\r
608 std::cout << "****** Set it to " << m_xranConf.frame_conf.nNumerology << "..." << std::endl;
\r
611 m_xranConf.nCC = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "num_cc");
\r
612 if(m_xranConf.nCC > XRAN_MAX_SECTOR_NR) {
\r
613 std::cout << "*** Exceeds maximum number of carriers supported [" << m_xranConf.nCC << "] !!!" << std::endl;
\r
614 m_xranConf.nCC = XRAN_MAX_SECTOR_NR;
\r
615 std::cout << "****** Adjusted to " << m_xranConf.nCC << "..." << std::endl;
\r
617 m_xranConf.neAxc = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "num_eaxc");
\r
618 if(m_xranConf.neAxc > XRAN_MAX_ANTENNA_NR) {
\r
619 std::cout << "*** Exceeds maximum number of antenna supported [" << m_xranConf.neAxc << "] !!!" << std::endl;
\r
620 m_xranConf.neAxc = XRAN_MAX_ANTENNA_NR;
\r
621 std::cout << "****** Adjusted to " << m_xranConf.neAxc << "..." << std::endl;
\r
624 m_bSub6 = get_globalcfg<bool>(XRAN_UT_KEY_GLOBALCFG_RU, "sub6");
\r
625 temp = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "chbw_dl");
\r
626 m_xranConf.nDLRBs = get_num_rbs(get_numerology(), temp, m_bSub6);
\r
627 temp = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "chbw_ul");
\r
628 m_xranConf.nULRBs = get_num_rbs(get_numerology(), temp, m_bSub6);
\r
630 m_xranConf.nAntElmTRx = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "ant_elm_trx");
\r
631 m_xranConf.nDLFftSize = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size");
\r
632 m_xranConf.nULFftSize = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size");
\r
634 m_xranConf.prach_conf.nPrachConfIdx = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "config_id");
\r
635 m_xranConf.prach_conf.nPrachSubcSpacing = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "scs");
\r
636 m_xranConf.prach_conf.nPrachFreqStart = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "freq_start");
\r
637 m_xranConf.prach_conf.nPrachFreqOffset = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "freq_offset");
\r
638 m_xranConf.prach_conf.nPrachFilterIdx = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "filter_id");
\r
639 m_xranConf.prach_conf.nPrachZeroCorrConf= 0;
\r
640 m_xranConf.prach_conf.nPrachRestrictSet = 0;
\r
641 m_xranConf.prach_conf.nPrachRootSeqIdx = 0;
\r
643 tmpstr = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_RU, "category");
\r
645 m_xranConf.ru_conf.xranCat = XRAN_CATEGORY_A;
\r
646 else if(tmpstr == "B")
\r
647 m_xranConf.ru_conf.xranCat = XRAN_CATEGORY_B;
\r
649 std::cout << "*** Invalid RU Category [" << tmpstr << "] !!!" << std::endl;
\r
650 std::cout << "****** Set it to Category A... " << std::endl;
\r
651 m_xranConf.ru_conf.xranCat = XRAN_CATEGORY_A;
\r
654 m_xranConf.ru_conf.iqWidth = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "iq_width");
\r
655 m_xranConf.ru_conf.compMeth = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "comp_meth");
\r
657 temp = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size");
\r
658 m_xranConf.ru_conf.fftSize = 0;
\r
660 ++m_xranConf.ru_conf.fftSize;
\r
662 m_xranConf.ru_conf.byteOrder = XRAN_NE_BE_BYTE_ORDER;
\r
663 m_xranConf.ru_conf.iqOrder = XRAN_I_Q_ORDER;
\r
665 m_xranConf.log_level = 0;
\r
667 m_xranConf.bbdev_enc = nullptr;
\r
668 m_xranConf.bbdev_dec = nullptr;
\r
669 m_xranConf.ttiCb = nullptr;
\r
670 m_xranConf.ttiCbParam = nullptr;
\r
682 printf("O-DU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
\r
683 m_xranInit.p_o_du_addr[0],
\r
684 m_xranInit.p_o_du_addr[1],
\r
685 m_xranInit.p_o_du_addr[2],
\r
686 m_xranInit.p_o_du_addr[3],
\r
687 m_xranInit.p_o_du_addr[4],
\r
688 m_xranInit.p_o_du_addr[5]);
\r
690 printf("O-RU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
\r
691 m_xranInit.p_o_ru_addr[0],
\r
692 m_xranInit.p_o_ru_addr[1],
\r
693 m_xranInit.p_o_ru_addr[2],
\r
694 m_xranInit.p_o_ru_addr[3],
\r
695 m_xranInit.p_o_ru_addr[4],
\r
696 m_xranInit.p_o_ru_addr[5]);
\r
698 printf("eAxCID - %d:%d:%d:%d (%04x, %04x, %04x, %04x)\n",
\r
699 m_xranInit.eAxCId_conf.bit_cuPortId,
\r
700 m_xranInit.eAxCId_conf.bit_bandSectorId,
\r
701 m_xranInit.eAxCId_conf.bit_ccId,
\r
702 m_xranInit.eAxCId_conf.bit_ruPortId,
\r
703 m_xranInit.eAxCId_conf.mask_cuPortId,
\r
704 m_xranInit.eAxCId_conf.mask_bandSectorId,
\r
705 m_xranInit.eAxCId_conf.mask_ccId,
\r
706 m_xranInit.eAxCId_conf.mask_ruPortId);
\r
708 printf("Total BF Weights : %d\n", m_xranInit.totalBfWeights);
\r
710 xran_init(0, NULL, &m_xranInit, &argv[0], &m_xranhandle);
\r
712 for(i = 0; i < XRAN_MAX_SECTOR_NR; i++)
\r
713 m_nSectorIndex[i] = i;
\r
715 /* set to maximum length to support multiple cases */
\r
716 m_nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/
\r
717 m_nSW_ToFpga_FTH_TxBufferLen = 13168; /* 273*12*4 + 64*/
\r
719 if(init_memory() < 0) {
\r
720 std::cout << "Fatal Error on Initialization !!!" << std::endl;
\r
721 std::cout << "INIT FAILED" << std::endl;
\r
725 std::cout << "INIT DONE" << std::endl;
\r
732 xran_close(m_xranhandle);
\r
733 m_xranhandle = nullptr;
\r
734 std::cout << "CLOSE DONE" << std::endl;
\r
737 std::cout << "ALREADY CLOSED" << std::endl;
\r
740 int Init(struct xran_fh_config *pCfg = nullptr)
\r
742 xran_status_t status;
\r
743 int32_t nSectorNum;
\r
744 int32_t i, j, k, z;
\r
750 SWXRANInterfaceTypeEnum eInterfaceType;
\r
751 int32_t cc_id, ant_id, sym_id, tti;
\r
754 struct xran_prb_map *pRbMap = NULL;
\r
757 /* Update member variables */
\r
759 memcpy(&m_xranConf, pCfg, sizeof(struct xran_fh_config));
\r
761 /* Init timer context */
\r
762 xran_lib_ota_tti = 0;
\r
763 xran_lib_ota_sym = 0;
\r
764 xran_lib_ota_sym_idx = 0;
\r
765 for(i=0; i < MAX_NUM_OF_XRAN_CTX; i++)
\r
766 m_timer_ctx[i].tti_to_process = i;
\r
768 nSectorNum = get_num_cc();
\r
770 /* Cat B RU support */
\r
771 if(get_rucategory() == XRAN_CATEGORY_B) {
\r
772 /* 10 * [14*32*273*2*2] = 4892160 bytes */
\r
773 iq_bfw_buffer_size_dl = (m_nSlots * N_SYM_PER_SLOT * get_num_antelmtrx() * get_num_dlrbs() * 4L);
\r
774 iq_bfw_buffer_size_ul = (m_nSlots * N_SYM_PER_SLOT * get_num_antelmtrx() * get_num_ulrbs() * 4L);
\r
776 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(get_num_cc() * get_num_eaxc()); i++) {
\r
777 p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl);
\r
778 tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl;
\r
779 if(p_tx_dl_bfw_buffer[i] == NULL)
\r
782 memset(p_tx_dl_bfw_buffer[i], 'D', iq_bfw_buffer_size_dl);
\r
783 tx_dl_bfw_buffer_position[i] = 0;
\r
785 p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_ul);
\r
786 tx_ul_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_ul;
\r
787 if(p_tx_ul_bfw_buffer[i] == NULL)
\r
790 memset(p_tx_ul_bfw_buffer[i], 'U', iq_bfw_buffer_size_ul);
\r
791 tx_ul_bfw_buffer_position[i] = 0;
\r
796 for(cc_id = 0; cc_id <nSectorNum; cc_id++) {
\r
797 for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) {
\r
798 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++) {
\r
799 flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
\r
802 pRbMap = (struct xran_prb_map *)m_sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
\r
804 pRbMap->dir = XRAN_DIR_DL;
\r
805 pRbMap->xran_port = 0;
\r
806 pRbMap->band_id = 0;
\r
807 pRbMap->cc_id = cc_id;
\r
808 pRbMap->ru_port_id = ant_id;
\r
809 pRbMap->tti_id = tti;
\r
810 pRbMap->start_sym_id = 0;
\r
812 pRbMap->nPrbElm = 1;
\r
813 pRbMap->prbMap[0].nRBStart = 0;
\r
814 pRbMap->prbMap[0].nRBSize = get_num_dlrbs();
\r
815 pRbMap->prbMap[0].nStartSymb = 0;
\r
816 pRbMap->prbMap[0].numSymb = 14;
\r
817 pRbMap->prbMap[0].nBeamIndex = 0;
\r
818 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
\r
820 if(get_rucategory() == XRAN_CATEGORY_A) {
\r
821 pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_ID_BASED;
\r
822 pRbMap->prbMap[0].bf_weight_update = 0;
\r
823 //pRbMap->prbMap[0].bf_attribute.weight[];
\r
824 //pRbMap->prbMap[0].bf_precoding.weight[];
\r
826 else if(get_rucategory() == XRAN_CATEGORY_B) {
\r
829 char *dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
\r
830 struct xran_prb_elm* p_prbMap = NULL;
\r
833 pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;
\r
834 pRbMap->prbMap[0].bf_weight_update = 1;
\r
836 num_antelm = get_num_antelmtrx();
\r
838 /* populate beam weights to C-plane for each elm */
\r
839 pRbMap->bf_weight.nAntElmTRx = num_antelm;
\r
840 for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
\r
841 p_prbMap = &pRbMap->prbMap[idxElm];
\r
842 for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++) {
\r
843 /* copy BF W IQs for 1 PRB of */
\r
844 rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4);
\r
848 } /* else if(get_rucategory() == XRAN_CATEGORY_B) */
\r
851 std::cout << "DL pRbMap ==NULL" << std::endl;
\r
855 pRbMap = (struct xran_prb_map *)m_sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
\r
857 pRbMap->dir = XRAN_DIR_UL;
\r
858 pRbMap->xran_port = 0;
\r
859 pRbMap->band_id = 0;
\r
860 pRbMap->cc_id = cc_id;
\r
861 pRbMap->ru_port_id = ant_id;
\r
862 pRbMap->tti_id = tti;
\r
863 pRbMap->start_sym_id = 0;
\r
865 pRbMap->nPrbElm = 1;
\r
866 pRbMap->prbMap[0].nRBStart = 0;
\r
867 pRbMap->prbMap[0].nRBSize = get_num_ulrbs();
\r
868 pRbMap->prbMap[0].nStartSymb = 0;
\r
869 pRbMap->prbMap[0].numSymb = 14;
\r
870 pRbMap->prbMap[0].nBeamIndex = 0;
\r
871 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
\r
873 if(get_rucategory() == XRAN_CATEGORY_A) {
\r
874 pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_ID_BASED;
\r
875 pRbMap->prbMap[0].bf_weight_update = 0;
\r
876 //pRbMap->prbMap[0].bf_attribute.weight[];
\r
877 //pRbMap->prbMap[0].bf_precoding.weight[];
\r
879 else if(get_rucategory() == XRAN_CATEGORY_B) {
\r
882 char *ul_bfw_pos = ((char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId];
\r
883 struct xran_prb_elm* p_prbMap = NULL;
\r
886 pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;
\r
887 pRbMap->prbMap[0].bf_weight_update = 1;
\r
889 num_antelm = get_num_antelmtrx();
\r
891 /* populate beam weights to C-plane for each elm */
\r
892 pRbMap->bf_weight.nAntElmTRx = num_antelm;
\r
893 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
\r
894 p_prbMap = &pRbMap->prbMap[idxElm];
\r
895 for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++){
\r
896 /* copy BF W IQs for 1 PRB of */
\r
897 rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (ul_bfw_pos + (iPrb*num_antelm)*4), num_antelm*4);
\r
901 } /* else if(get_rucategory() == XRAN_CATEGORY_B) */
\r
905 std::cout << "UL: pRbMap ==NULL" << std::endl;
\r
918 if(get_rucategory() == XRAN_CATEGORY_B) {
\r
919 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(get_num_cc() * get_num_eaxc()); i++) {
\r
920 if(p_tx_dl_bfw_buffer[i]) {
\r
921 free(p_tx_dl_bfw_buffer[i]);
\r
922 p_tx_dl_bfw_buffer[i] == NULL;
\r
925 if(p_tx_ul_bfw_buffer[i]) {
\r
926 free(p_tx_ul_bfw_buffer[i]);
\r
927 p_tx_ul_bfw_buffer[i] == NULL;
\r
936 void Open(xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up,
\r
937 void *fh_rx_callback, void *fh_rx_prach_callback)
\r
939 struct xran_fh_config *pXranConf;
\r
940 int32_t nSectorNum;
\r
942 struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
\r
943 struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
\r
944 struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
\r
945 struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
\r
946 struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
\r
949 xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
\r
950 xran_reg_physide_cb(xranHandle, physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);
\r
951 xran_reg_physide_cb(xranHandle, physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX);
\r
953 nSectorNum = get_num_cc();
\r
955 for(i=0; i<nSectorNum; i++) {
\r
956 for(j=0; j<XRAN_N_FE_BUF_LEN; j++) {
\r
957 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {
\r
958 pFthTxBuffer[i][z][j] = &(m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
\r
959 pFthTxPrbMapBuffer[i][z][j] = &(m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
\r
960 pFthRxBuffer[i][z][j] = &(m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
\r
961 pFthRxPrbMapBuffer[i][z][j] = &(m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
\r
962 pFthRxRachBuffer[i][z][j] = &(m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
\r
967 if(m_nInstanceHandle[0] != NULL) {
\r
968 for(i = 0; i<nSectorNum; i++) {
\r
969 xran_5g_fronthault_config(m_nInstanceHandle[0][i],
\r
970 pFthTxBuffer[i], pFthTxPrbMapBuffer[i],
\r
971 pFthRxBuffer[i], pFthRxPrbMapBuffer[i],
\r
972 (void (*)(void *, xran_status_t))fh_rx_callback, &pFthRxBuffer[i][0]);
\r
974 xran_5g_prach_req(m_nInstanceHandle[0][i], pFthRxRachBuffer[i],
\r
975 (void (*)(void *, xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i][0]);
\r
979 xran_register_cb_mbuf2ring(send_cp, send_up);
\r
981 xran_open(m_xranhandle, &m_xranConf);
\r
987 xran_close(m_xranhandle);
\r
993 return(xran_start(m_xranhandle));
\r
1001 return(xran_stop(m_xranhandle));
\r
1006 /* emulation of timer */
\r
1009 tti_ota_cb(nullptr, get_timer_ctx());
\r
1012 void update_symbol_index()
\r
1014 xran_lib_ota_sym_idx++;
\r
1015 if((xran_lib_ota_sym_idx % N_SYM_PER_SLOT) == 0) {
\r
1019 xran_lib_ota_sym++;
\r
1020 if(xran_lib_ota_sym >= N_SYM_PER_SLOT)
\r
1021 xran_lib_ota_sym = 0;
\r
1024 int apply_cpenable(bool flag)
\r
1026 struct xran_device_ctx *pCtx = xran_dev_get_ctx();
\r
1031 if(pCtx == nullptr)
\r
1034 if(flag == true) {
\r
1035 m_xranInit.enableCP = 1;
\r
1036 pCtx->enableCP = 1;
\r
1039 m_xranInit.enableCP = 0;
\r
1040 pCtx->enableCP = 0;
\r
1047 int get_slot_config(const std::string &cfgname, struct xran_frame_config *pCfg)
\r
1050 std::vector<int> slotcfg;
\r
1052 numcfg = get_globalcfg<int>(cfgname, "period");
\r
1053 pCfg->nTddPeriod = numcfg;
\r
1054 for(i=0; i < numcfg; i++) {
\r
1055 std::stringstream slotcfgname;
\r
1057 slotcfgname << "slot" << i;
\r
1058 std::vector<int> slotcfg = get_globalcfg_array<int>(cfgname, slotcfgname.str());
\r
1060 for(j=0; j < slotcfg.size(); j++)
\r
1061 pCfg->sSlotConfig[i].nSymbolType[j] = slotcfg[j];
\r
1062 pCfg->sSlotConfig[i].reserved[0] = 0; pCfg->sSlotConfig[i].reserved[1] = 0;
\r
1068 int get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, bool nSub6)
\r
1070 if(nNumerology > 3)
\r
1074 if (nNumerology < 3) {
\r
1075 /* F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB */
\r
1076 switch(nBandwidth) {
\r
1077 case PHY_BW_5MHZ: return(nNumRbsPerSymF1[nNumerology][0]);
\r
1078 case PHY_BW_10MHZ: return(nNumRbsPerSymF1[nNumerology][1]);
\r
1079 case PHY_BW_15MHZ: return(nNumRbsPerSymF1[nNumerology][2]);
\r
1080 case PHY_BW_20MHZ: return(nNumRbsPerSymF1[nNumerology][3]);
\r
1081 case PHY_BW_25MHZ: return(nNumRbsPerSymF1[nNumerology][4]);
\r
1082 case PHY_BW_30MHZ: return(nNumRbsPerSymF1[nNumerology][5]);
\r
1083 case PHY_BW_40MHZ: return(nNumRbsPerSymF1[nNumerology][6]);
\r
1084 case PHY_BW_50MHZ: return(nNumRbsPerSymF1[nNumerology][7]);
\r
1085 case PHY_BW_60MHZ: return(nNumRbsPerSymF1[nNumerology][8]);
\r
1086 case PHY_BW_70MHZ: return(nNumRbsPerSymF1[nNumerology][9]);
\r
1087 case PHY_BW_80MHZ: return(nNumRbsPerSymF1[nNumerology][10]);
\r
1088 case PHY_BW_90MHZ: return(nNumRbsPerSymF1[nNumerology][11]);
\r
1089 case PHY_BW_100MHZ: return(nNumRbsPerSymF1[nNumerology][12]);
\r
1093 else { /* if(nSub6) */
\r
1094 if((nNumerology >= 2) && (nNumerology <= 3)) {
\r
1096 /* F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB */
\r
1097 switch(nBandwidth) {
\r
1098 case PHY_BW_50MHZ: return(nNumRbsPerSymF2[nNumerology][0]); break;
\r
1099 case PHY_BW_100MHZ: return(nNumRbsPerSymF2[nNumerology][1]); break;
\r
1100 case PHY_BW_200MHZ: return(nNumRbsPerSymF2[nNumerology][2]); break;
\r
1101 case PHY_BW_400MHZ: return(nNumRbsPerSymF2[nNumerology][3]); break;
\r
1109 void *get_xranhandle() { return(m_xranhandle); }
\r
1110 void *get_timer_ctx() { return((void *)&m_timer_ctx[0]); }
\r
1112 int get_symbol_index() { return (xran_lib_ota_sym); }
\r
1114 bool is_running() { return((xran_get_if_state() == XRAN_RUNNING)?true:false); }
\r
1116 enum xran_category get_rucategory() { return(m_xranConf.ru_conf.xranCat); }
\r
1118 int get_numerology() { return(m_xranConf.frame_conf.nNumerology); }
\r
1119 int get_duplextype() { return(m_xranConf.frame_conf.nFrameDuplexType); }
\r
1120 int get_num_cc() { return(m_xranConf.nCC); }
\r
1121 int get_num_eaxc() { return(m_xranConf.neAxc); }
\r
1122 int get_num_dlrbs() { return(m_xranConf.nDLRBs); }
\r
1123 int get_num_ulrbs() { return(m_xranConf.nULRBs); }
\r
1124 int get_num_antelmtrx() { return(m_xranConf.nAntElmTRx); }
\r
1126 bool is_cpenable() { return(m_xranInit.enableCP); };
\r
1127 bool is_prachenable() { return(m_xranInit.prachEnable); };
\r
1128 bool is_dynamicsection() { return(m_xranInit.DynamicSectionEna?true:false); }
\r
1130 void get_cfg_prach(struct xran_prach_config *pCfg)
\r
1133 memcpy(pCfg, &m_xranConf.prach_conf, sizeof(struct xran_prach_config));
\r
1136 void get_cfg_frame(struct xran_frame_config *pCfg)
\r
1139 memcpy(pCfg, &m_xranConf.frame_conf, sizeof(struct xran_frame_config));
\r
1142 void get_cfg_ru(struct xran_ru_config *pCfg)
\r
1145 memcpy(pCfg, &m_xranConf.ru_conf, sizeof(struct xran_ru_config));
\r
1148 void get_cfg_fh(struct xran_fh_config *pCfg)
\r
1151 memcpy(pCfg, &m_xranConf, sizeof(struct xran_fh_config));
\r
1157 /* external declaration for the instance */
\r
1158 extern xranLibWraper *xranlib;
\r
1161 #endif //XRAN_LIB_WRAP_HPP
\r