1 /******************************************************************************
3 * Copyright (c) 2020 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * @brief This module provides implementation of BBU tasks for sample app
23 * @author Intel Corporation
28 /*******************************************************************************
29 * Include public/global header files
30 *******************************************************************************/
37 #include <immintrin.h>
40 #include "app_bbu_pool.h"
41 #include "app_io_fh_xran.h"
42 #include "xran_compression.h"
43 #include "xran_cp_api.h"
44 #include "xran_fh_o_du.h"
45 #include "xran_mlog_task_id.h"
47 extern RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM];
48 static SampleSplitStruct gsUlCfgAxCTaskSplit[MAX_PHY_INSTANCES][MAX_NUM_OF_SF_5G_CTX][MAX_TEST_SPLIT_NUM];
50 void app_bbu_pool_pre_task_ul_cfg(uint32_t nSubframe, uint16_t nCellIdx, TaskPreGen *pPara)
52 int32_t nSplitGroup = 0;
54 uint32_t nSfIdx = get_dl_sf_idx(nSubframe, nCellIdx);
55 uint32_t nCtxNum = get_dl_sf_ctx(nSfIdx, nCellIdx);
56 SampleSplitStruct *pTaskSplitPara;
57 int32_t nGroupNum = 0;
58 int32_t nSymbStart = 0, nSymbPerSplit = 0;
59 int32_t nTotalLayers = 0, nLayerStart = 0, nLayerPerSplit = 0;
60 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
61 struct xran_fh_config* pXranConf = NULL;
62 // struct xran_io_shared_ctrl *psIoCtrl = NULL;
63 uint32_t nRuCcidx = 0;
64 int32_t xran_port = 0;
67 if(psXranIoIf == NULL)
68 rte_panic("psXranIoIf == NULL");
70 if(nCellIdx >= MAX_PHY_INSTANCES)
71 rte_panic("nCellIdx >= MAX_PHY_INSTANCES");
73 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
76 printf("incorrect xran_port\n");
77 return /*EBBUPOOL_CORRECT*/;
80 // psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
81 pXranConf = &app_io_xran_fh_config[xran_port];
83 rte_panic("pXranConf");
85 if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_A) {
86 neAxc = pXranConf->neAxc;
88 } else if (pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B) {
89 neAxc = pXranConf->neAxcUl;
96 /* all symb per eAxC */
98 // nTotalSymb = XRAN_NUM_OF_SYMBOL_PER_SLOT;
99 nSymbPerSplit = XRAN_NUM_OF_SYMBOL_PER_SLOT;
101 nLayerPerSplit = nTotalLayers/nSplitGroup;
103 pPara->nTaskNum = nSplitGroup;
104 for (iTask = 0; iTask < (nSplitGroup-1) && iTask < (MAX_TEST_SPLIT_NUM-1); iTask ++)
106 pTaskSplitPara = &(gsUlCfgAxCTaskSplit[nCellIdx][nCtxNum][iTask]);
107 pTaskSplitPara->nSymbStart = nSymbStart;
108 pTaskSplitPara->nSymbNum = nSymbPerSplit;
109 pTaskSplitPara->eSplitType = LAYER_SPLIT;
110 pTaskSplitPara->nSplitIndex = iTask;
111 pTaskSplitPara->nGroupStart = 0;
112 pTaskSplitPara->nGroupNum = nGroupNum;
113 pTaskSplitPara->nLayerStart = nLayerStart;
114 pTaskSplitPara->nLayerNum = nLayerPerSplit;
115 pPara->pTaskExePara[iTask] = pTaskSplitPara;
116 //nSymbStart += nSymbPerSplit;
117 nLayerStart += nLayerPerSplit;
120 pTaskSplitPara = &(gsUlCfgAxCTaskSplit[nCellIdx][nCtxNum][iTask]);
121 pTaskSplitPara->nSymbStart = nSymbStart;
122 pTaskSplitPara->nSymbNum = nSymbPerSplit;
123 pTaskSplitPara->eSplitType = LAYER_SPLIT;
124 pTaskSplitPara->nSplitIndex = iTask;
125 pTaskSplitPara->nGroupStart = 0;
126 pTaskSplitPara->nGroupNum = nGroupNum;
127 pTaskSplitPara->nLayerStart = nLayerStart;
128 pTaskSplitPara->nLayerNum = nTotalLayers - nLayerStart;
129 pPara->pTaskExePara[iTask] = pTaskSplitPara;
134 /*! \brief Task function for UL configuration in PHY.
135 \param [in] pCookies Task input parameter.
136 \return BBU pool state
138 int32_t app_bbu_pool_task_ul_config(void * pCookies)
140 EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
141 uint16_t nCellIdx = pEventCtrl->nCellIdx;
142 uint32_t nSfIdx = get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
143 uint32_t nCtxNum = get_ul_sf_ctx(nSfIdx, nCellIdx);
144 uint64_t mlog_start = MLogTick();// nTtiStartTime = gTtiStartTime;
145 uint32_t mlogVariablesCnt, mlogVariables[50];
146 uint32_t nRuCcidx = 0;
147 int32_t xran_port = 0;
148 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
149 struct xran_fh_config* pXranConf = NULL;
150 // uint32_t neAxc = 0;
151 xran_status_t status;
152 struct xran_io_shared_ctrl *psIoCtrl = NULL;
153 int32_t cc_id, ant_id, sym_id, tti;
155 struct o_xu_buffers * p_iq = NULL;
156 int32_t nSymbMask = 0b11111111111111;
157 RuntimeConfig *p_o_xu_cfg = NULL;
158 SampleSplitStruct *pTaskPara = (SampleSplitStruct*)pEventCtrl->pTaskPara;
159 uint16_t nLayerStart = 0, nLayer = 0;//, iSplit =0;
161 if(psXranIoIf == NULL)
162 rte_panic("psXranIoIf == NULL");
164 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
167 printf("incorrect xran_port\n");
168 return EBBUPOOL_CORRECT;
170 psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
172 rte_panic("psIoCtrl");
174 pXranConf = &app_io_xran_fh_config[xran_port];
175 if(pXranConf == NULL)
176 rte_panic("pXranConf");
179 if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_A)
180 neAxc = pXranConf->neAxc;
181 else if (pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B)
182 neAxc = pXranConf->neAxcUl;
186 mlogVariablesCnt = 0;
187 mlogVariables[mlogVariablesCnt++] = 0xCCEECCEE;
188 mlogVariables[mlogVariablesCnt++] = pEventCtrl->nSlotIdx;
189 mlogVariables[mlogVariablesCnt++] = 0;
190 mlogVariables[mlogVariablesCnt++] = nCellIdx;
191 mlogVariables[mlogVariablesCnt++] = nSfIdx;
192 mlogVariables[mlogVariablesCnt++] = nCtxNum;
193 mlogVariables[mlogVariablesCnt++] = xran_port;
194 mlogVariables[mlogVariablesCnt++] = nRuCcidx;
196 p_o_xu_cfg = p_startupConfiguration[xran_port];
197 if(p_o_xu_cfg == NULL)
198 rte_panic("p_o_xu_cfg");
200 if(LAYER_SPLIT == pTaskPara->eSplitType) {
201 // iSplit = pTaskPara->nSplitIndex;
202 nLayerStart = pTaskPara->nLayerStart;
203 nLayer = pTaskPara->nLayerNum;
204 //printf("\nsf %d nSymbStart %d nSymb %d iSplit %d", nSfIdx, nSymbStart, nSymb, iSplit);
206 rte_panic("LAYER_SPLIT == pTaskPara->eSplitType");
209 if(p_o_xu_cfg->p_buff) {
210 p_iq = p_o_xu_cfg->p_buff;
212 rte_panic("Error p_o_xu_cfg->p_buff\n");
215 for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
216 if (cc_id >= XRAN_MAX_SECTOR_NR)
218 rte_panic("cell id %d exceeding max number", cc_id);
220 for(ant_id = nLayerStart; ant_id < (nLayerStart + nLayer); ant_id++) {
221 if(p_o_xu_cfg->appMode == APP_O_DU) {
222 flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
224 flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
226 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
227 if(((1 << sym_id) & nSymbMask)) {
228 if ((status = app_io_xran_iq_content_init_cp_rx(p_o_xu_cfg->appMode, pXranConf,
229 psXranIoIf, psIoCtrl, p_iq,
230 cc_id, ant_id, sym_id, tti, flowId)) != 0) {
231 rte_panic("app_io_xran_iq_content_init_cp_rx");
238 xran_prepare_cp_ul_slot(xran_port, nSfIdx, nRuCcidx, /*psXranIoIf->num_cc_per_port[xran_port]*/ 1, nSymbMask, nLayerStart,
239 nLayer, 0, XRAN_NUM_OF_SYMBOL_PER_SLOT);
241 if (mlogVariablesCnt)
242 MLogAddVariables((uint32_t)mlogVariablesCnt, (uint32_t *)mlogVariables, mlog_start);
244 //unlock the next task
245 next_event_unlock(pCookies);
246 MLogTask(PCID_GNB_UL_CFG_CC0+nCellIdx, mlog_start, MLogTick());
248 return EBBUPOOL_CORRECT;
252 app_io_xran_ul_decomp_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
253 uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
255 xran_status_t status;
256 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
257 int32_t xran_port = 0;
258 uint32_t nRuCcidx = 0;
259 struct o_xu_buffers * p_iq = NULL;
260 RuntimeConfig *p_o_xu_cfg = NULL;
262 struct xran_fh_config *pXranConf = NULL;
263 int32_t cc_id, ant_id, sym_id, tti;
264 struct xran_io_shared_ctrl *psIoCtrl = NULL;
265 uint32_t xran_max_antenna_nr;
266 // uint32_t xran_max_ant_array_elm_nr;
267 // uint32_t xran_max_antenna_nr_prach;
269 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
272 printf("incorrect xran_port\n");
276 psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
278 if(psIoCtrl == NULL) {
279 printf("psIoCtrl == NULL\n");
283 p_o_xu_cfg = p_startupConfiguration[xran_port];
284 if(p_o_xu_cfg == NULL) {
285 printf("p_o_xu_cfg == NULL\n");
289 if(p_o_xu_cfg->p_buff) {
290 p_iq = p_o_xu_cfg->p_buff;
292 rte_panic("Error p_o_xu_cfg->p_buff\n");
295 pXranConf = &app_io_xran_fh_config[xran_port];
297 xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
298 // xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
299 // xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
302 for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
303 for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < xran_max_antenna_nr; ant_id++) {
304 if(p_o_xu_cfg->appMode == APP_O_DU) {
305 flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id;
307 flowId = p_o_xu_cfg->numAxc * cc_id + ant_id;
309 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
310 if(((1 << sym_id) & nSymMask)) {
311 if ((status = app_io_xran_iq_content_get_up_rx(p_o_xu_cfg->appMode, pXranConf,
312 psXranIoIf, psIoCtrl, p_iq,
313 cc_id, ant_id, sym_id, tti, flowId)) != 0) {
314 rte_panic("app_io_xran_iq_content_get_up_rx");
325 app_io_xran_prach_decomp_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
326 uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
328 xran_status_t status;
329 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
330 int32_t xran_port = 0;
331 uint32_t nRuCcidx = 0;
332 struct o_xu_buffers * p_iq = NULL;
333 RuntimeConfig *p_o_xu_cfg = NULL;
335 struct xran_fh_config *pXranConf = NULL;
336 int32_t cc_id, ant_id, sym_id, tti;
337 struct xran_io_shared_ctrl *psIoCtrl = NULL;
338 uint32_t xran_max_antenna_nr;
339 // uint32_t xran_max_ant_array_elm_nr;
340 uint32_t xran_max_antenna_nr_prach;
342 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
345 printf("incorrect xran_port\n");
349 psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
351 if(psIoCtrl == NULL) {
352 printf("psIoCtrl == NULL\n");
356 p_o_xu_cfg = p_startupConfiguration[xran_port];
357 if(p_o_xu_cfg == NULL) {
358 printf("p_o_xu_cfg == NULL\n");
362 if(p_o_xu_cfg->p_buff) {
363 p_iq = p_o_xu_cfg->p_buff;
365 rte_panic("Error p_o_xu_cfg->p_buff\n");
368 pXranConf = &app_io_xran_fh_config[xran_port];
370 xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
371 // xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
372 xran_max_antenna_nr_prach = RTE_MIN(xran_max_antenna_nr, XRAN_MAX_PRACH_ANT_NUM);
375 for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
376 for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < xran_max_antenna_nr_prach; ant_id++) {
377 flowId = xran_max_antenna_nr_prach * cc_id + ant_id;
379 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
380 if(((1 << sym_id) & nSymMask)) {
381 if ((status = app_io_xran_iq_content_get_up_prach(p_o_xu_cfg->appMode, pXranConf,
382 psXranIoIf, psIoCtrl, p_iq,
383 cc_id, ant_id, sym_id, tti, flowId)) != 0) {
384 rte_panic("app_io_xran_iq_content_get_up_prach");
396 app_io_xran_srs_decomp_func(uint16_t nCellIdx, uint32_t nSfIdx, uint32_t nSymMask,
397 uint32_t nAntStart, uint32_t nAntNum, uint32_t nSymStart, uint32_t nSymNum)
399 xran_status_t status;
400 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
401 int32_t xran_port = 0;
402 uint32_t nRuCcidx = 0;
403 struct o_xu_buffers * p_iq = NULL;
404 RuntimeConfig *p_o_xu_cfg = NULL;
406 struct xran_fh_config *pXranConf = NULL;
407 int32_t cc_id, ant_id, sym_id, tti;
408 struct xran_io_shared_ctrl *psIoCtrl = NULL;
409 uint32_t xran_max_antenna_nr;
410 uint32_t xran_max_ant_array_elm_nr;
412 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nCellIdx, &nRuCcidx);
415 printf("incorrect xran_port\n");
419 psIoCtrl = app_io_xran_if_ctrl_get(xran_port);
421 if(psIoCtrl == NULL) {
422 printf("psIoCtrl == NULL\n");
426 p_o_xu_cfg = p_startupConfiguration[xran_port];
427 if(p_o_xu_cfg == NULL) {
428 printf("p_o_xu_cfg == NULL\n");
432 if(p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs){
433 if(p_o_xu_cfg->p_buff) {
434 p_iq = p_o_xu_cfg->p_buff;
436 rte_panic("Error p_o_xu_cfg->p_buff\n");
439 pXranConf = &app_io_xran_fh_config[xran_port];
441 xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc);
442 xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr);
445 for(cc_id = nRuCcidx; cc_id < psXranIoIf->num_cc_per_port[xran_port]; cc_id++) {
446 for(ant_id = nAntStart; ant_id < (nAntStart + nAntNum) && ant_id < xran_max_ant_array_elm_nr; ant_id++) {
447 flowId = pXranConf->nAntElmTRx*cc_id + ant_id;
448 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
449 if(((1 << sym_id) & nSymMask)) {
450 if ((status = app_io_xran_iq_content_get_up_srs(p_o_xu_cfg->appMode, pXranConf,
451 psXranIoIf, psIoCtrl, p_iq,
452 cc_id, ant_id, sym_id, tti, flowId)) != 0) {
453 rte_panic("app_io_xran_iq_content_get_up_srs");
465 app_bbu_pool_task_symX_wakeup(void *pCookies, uint32_t nSym)
467 EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
468 uint16_t nCellIdx = pEventCtrl->nCellIdx;
469 uint32_t nSfIdx = pEventCtrl->nSlotIdx;/*get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);*/
471 uint32_t nSymbMask = 0;
472 uint32_t nSymStart = 0;
473 // uint32_t nSymNum = 0;
475 uint32_t Nrx_antennas;
476 uint16_t nOranCellIdx;
478 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
480 int32_t xran_port = 0;
481 uint32_t nRuCcidx = 0;
482 struct xran_fh_config *pXranConf = NULL;
484 nOranCellIdx = nCellIdx;
485 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
487 printf("incorrect xran_port\n");
491 pXranConf = &app_io_xran_fh_config[xran_port];
492 Nrx_antennas = pXranConf->neAxcUl;
494 if(Nrx_antennas == 0)
495 rte_panic("[p %d cell %d] Nrx_antennas == 0\n", xran_port, nCellIdx);
498 // nSymNum = XRAN_NUM_OF_SYMBOL_PER_SLOT;
502 case 2: /* [0,1,2] */
505 case 6: /* [3,4,5,6] */
508 case 11: /* [7,8,9,10,11] */
511 case 13: /* [12,13] */
515 rte_panic("nSym %d\n", nSym);
519 if (nSym == 13) /* w/a to run copy to IQ buffer as single short */
521 nSymbMask = 0b11111111111111;
522 app_io_xran_ul_decomp_func(nCellIdx, nSfIdx, nSymbMask, 0, Nrx_antennas, nSymStart, XRAN_NUM_OF_SYMBOL_PER_SLOT);
525 return EBBUPOOL_CORRECT;
529 app_bbu_pool_task_sym2_wakeup(void *pCookies)
532 // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
533 // uint16_t nCellIdx = pEventCtrl->nCellIdx;
534 uint64_t mlog_start = MLogTick();
536 ret = app_bbu_pool_task_symX_wakeup(pCookies, 2);
538 //unlock the next task
539 next_event_unlock(pCookies);
540 MLogTask(PID_GNB_SYM2_WAKEUP, mlog_start, MLogTick());
546 app_bbu_pool_task_sym6_wakeup(void *pCookies)
549 // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
550 uint64_t mlog_start = MLogTick();
552 ret = app_bbu_pool_task_symX_wakeup(pCookies, 6);
554 //unlock the next task
555 next_event_unlock(pCookies);
556 MLogTask(PID_GNB_SYM6_WAKEUP, mlog_start, MLogTick());
561 app_bbu_pool_task_sym11_wakeup(void *pCookies)
564 // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
565 uint64_t mlog_start = MLogTick();
567 ret = app_bbu_pool_task_symX_wakeup(pCookies, 11);
569 //unlock the next task
570 next_event_unlock(pCookies);
571 MLogTask(PID_GNB_SYM11_WAKEUP, mlog_start, MLogTick());
576 app_bbu_pool_task_sym13_wakeup(void *pCookies)
579 // EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
580 uint64_t mlog_start = MLogTick();
582 ret = app_bbu_pool_task_symX_wakeup(pCookies, 13);
584 //unlock the next task
585 next_event_unlock(pCookies);
586 MLogTask(PID_GNB_SYM13_WAKEUP, mlog_start, MLogTick());
591 app_bbu_pool_task_prach_wakeup(void *pCookies)
593 EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
594 uint16_t nCellIdx = pEventCtrl->nCellIdx;
595 uint32_t nSfIdx = pEventCtrl->nSlotIdx;// get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
597 uint32_t nSymbMask = 0;
598 uint32_t nSymStart = 0;
599 // uint32_t nSymNum = 0;
601 uint32_t Nrx_antennas;
602 uint16_t nOranCellIdx;
604 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
606 int32_t xran_port = 0;
607 uint32_t nRuCcidx = 0;
608 struct xran_fh_config *pXranConf = NULL;
609 uint64_t mlog_start = MLogTick();
610 nOranCellIdx = nCellIdx;
611 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
613 printf("incorrect xran_port\n");
617 pXranConf = &app_io_xran_fh_config[xran_port];
618 Nrx_antennas = RTE_MIN(pXranConf->neAxcUl, XRAN_MAX_PRACH_ANT_NUM);
620 if(Nrx_antennas == 0)
621 rte_panic("Nrx_antennas == 0\n");
624 // nSymNum = XRAN_NUM_OF_SYMBOL_PER_SLOT;
625 nSymbMask = 0b11111111111111;
627 app_io_xran_prach_decomp_func(nCellIdx, nSfIdx, nSymbMask, 0, Nrx_antennas, nSymStart, XRAN_NUM_OF_SYMBOL_PER_SLOT);
629 //unlock the next task
630 next_event_unlock(pCookies);
631 MLogTask(PID_GNB_PRACH_WAKEUP, mlog_start, MLogTick());
632 return EBBUPOOL_CORRECT;
636 app_bbu_pool_task_srs_wakeup(void *pCookies)
639 EventCtrlStruct *pEventCtrl = (EventCtrlStruct *)pCookies;
640 uint16_t nCellIdx = pEventCtrl->nCellIdx;
641 uint32_t nSfIdx = pEventCtrl->nSlotIdx;// get_ul_sf_idx(pEventCtrl->nSlotIdx, nCellIdx);
643 uint32_t nSymbMask = 0;
644 uint32_t nSymStart = 0;
645 // uint32_t nSymNum = 0;
647 uint32_t Nrx_antennas;
648 uint16_t nOranCellIdx;
650 struct bbu_xran_io_if *psXranIoIf = app_io_xran_if_get();
652 int32_t xran_port = 0;
653 uint32_t nRuCcidx = 0;
654 struct xran_fh_config *pXranConf = NULL;
655 uint64_t mlog_start = MLogTick();
656 nOranCellIdx = nCellIdx;
657 xran_port = app_io_xran_map_cellid_to_port(psXranIoIf, nOranCellIdx, &nRuCcidx);
659 printf("incorrect xran_port\n");
663 pXranConf = &app_io_xran_fh_config[xran_port];
664 Nrx_antennas = pXranConf->nAntElmTRx;
667 // nSymNum = XRAN_NUM_OF_SYMBOL_PER_SLOT;
668 nSymbMask = 0b11111111111111;
670 ret = app_io_xran_srs_decomp_func(nCellIdx, nSfIdx, nSymbMask, 0, Nrx_antennas, nSymStart, XRAN_NUM_OF_SYMBOL_PER_SLOT);
671 //unlock the next task
672 next_event_unlock(pCookies);
673 MLogTask(PID_GNB_SRS_WAKEUP, mlog_start, MLogTick());