[Task-ID: ODUHIGH-455] Changes to support new L1 20.11

Signed-off-by: barveankit <anbarve@radisys.com>
Change-Id: I6058cf6966e75f31aa568ba5030c16d2723515eb
Signed-off-by: lal.harshita <Harshita.Lal@radisys.com>

diff --git a/build/odu/makefile b/build/odu/makefile
index 03284ec..ac5db97 100644 (file)
--- a/build/odu/makefile
+++ b/build/odu/makefile
@@ -111,35 +111,16 @@ export I_OPTS
 # Add to the linker options the platform specific components
 L_OPTS+=-lnsl -lrt -lm -lpthread -lsctp 
 ifeq ($(PHY), INTEL_L1)
-       L_OPTS+=-L/root/intel/phy/wls_lib/lib -lwls                         \
-        -lhugetlbfs -lnuma -ldl -L/root/intel/dpdk-19.11/x86_64-native-linuxapp-gcc/lib             \
-        -ldpdk -lrte_gso -lrte_pmd_atlantic -lrte_pmd_iavf -lrte_pmd_tap -lrte_acl                  \
-        -lrte_hash -lrte_pmd_avp -lrte_pmd_ice -lrte_pmd_thunderx_nicvf -lrte_bbdev                 \
-        -lrte_ip_frag -lrte_pmd_axgbe -lrte_pmd_ifc -lrte_pmd_vdev_netvsc -lrte_bitratestats        \
-        -lrte_ipsec -lrte_pmd_bbdev_fpga_lte_fec -lrte_pmd_ixgbe -lrte_pmd_vhost                    \
-        -lrte_bpf -lrte_jobstats -lrte_pmd_bbdev_null -lrte_pmd_kni -lrte_pmd_virtio                \
-        -lrte_bus_dpaa -lrte_kni -lrte_pmd_bbdev_turbo_sw -lrte_pmd_lio -lrte_pmd_virtio_crypto     \
-        -lrte_bus_fslmc -lrte_kvargs -lrte_pmd_bnxt -lrte_pmd_memif -lrte_pmd_vmxnet3_uio           \
-        -lrte_bus_ifpga -lrte_latencystats -lrte_pmd_bond -lrte_pmd_netvsc -lrte_port               \
-        -lrte_bus_pci -lrte_lpm -lrte_pmd_caam_jr -lrte_pmd_nfp -lrte_power -lrte_bus_vdev          \
-        -lrte_mbuf -lrte_pmd_crypto_scheduler -lrte_pmd_nitrox -lrte_rawdev -lrte_bus_vmbus         \
-        -lrte_member -lrte_pmd_cxgbe -lrte_pmd_null -lrte_rawdev_dpaa2_cmdif -lrte_cfgfile          \
-        -lrte_mempool -lrte_pmd_dpaa -lrte_pmd_null_crypto -lrte_rawdev_dpaa2_qdma                  \
-        -lrte_cmdline -lrte_mempool_bucket -lrte_pmd_dpaa2 -lrte_pmd_octeontx -lrte_rawdev_ioat     \
-        -lrte_common_cpt -lrte_mempool_dpaa -lrte_pmd_dpaa2_event -lrte_pmd_octeontx2               \
-        -lrte_rawdev_ntb -lrte_common_dpaax -lrte_mempool_dpaa2 -lrte_pmd_dpaa2_sec                 \
-        -lrte_pmd_octeontx2_crypto -lrte_rawdev_octeontx2_dma -lrte_common_octeontx                 \
-        -lrte_mempool_octeontx -lrte_pmd_dpaa_event -lrte_pmd_octeontx2_event -lrte_rawdev_skeleton \
-        -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_pmd_dpaa_sec -lrte_pmd_octeontx_crypto \
-        -lrte_rcu -lrte_compressdev -lrte_mempool_ring -lrte_pmd_dsw_event -lrte_pmd_octeontx_ssovf \
-        -lrte_reorder -lrte_cryptodev -lrte_mempool_stack -lrte_pmd_e1000 -lrte_pmd_octeontx_zip    \
-        -lrte_rib -lrte_distributor -lrte_meter -lrte_pmd_ena -lrte_pmd_opdl_event -lrte_ring       \
-        -lrte_eal -lrte_metrics -lrte_pmd_enetc -lrte_pmd_qat -lrte_sched -lrte_efd -lrte_net       \
-        -lrte_pmd_enic -lrte_pmd_qede -lrte_security -lrte_ethdev -lrte_pci -lrte_pmd_failsafe      \
-        -lrte_pmd_ring -lrte_stack -lrte_eventdev -lrte_pdump -lrte_pmd_fm10k -lrte_pmd_sfc_efx     \
-        -lrte_table -lrte_fib -lrte_pipeline -lrte_pmd_hinic -lrte_pmd_skeleton_event -lrte_timer   \
-        -lrte_flow_classify -lrte_pmd_af_packet -lrte_pmd_hns3 -lrte_pmd_softnic -lrte_vhost        \
-        -lrte_gro -lrte_pmd_ark -lrte_pmd_i40e -lrte_pmd_sw_event
+       L_OPTS+=-L/root/Intel-L1-20.11.1/phy/wls_lib/ -lwls                         \
+        -lhugetlbfs -lnuma -ldl -L/root/Intel-L1-20.11.1/dpdk-20.11.1/build/lib                        \
+        -lrte_gso -lrte_acl -lrte_hash -lrte_bbdev -lrte_ip_frag -lrte_bitratestats -lrte_ipsec        \
+        -lrte_bpf -lrte_jobstats -lrte_telemetry -lrte_kni -lrte_kvargs -lrte_latencystats -lrte_port  \
+        -lrte_lpm -lrte_power -lrte_mbuf -lrte_rawdev -lrte_member -lrte_cfgfile -lrte_mempool         \
+                 -lrte_cmdline -lrte_rcu -lrte_compressdev -lrte_reorder -lrte_cryptodev -lrte_rib              \
+                 -lrte_distributor -lrte_meter  -lrte_ring -lrte_eal -lrte_metrics -lrte_sched -lrte_efd        \
+                 -lrte_net -lrte_security -lrte_ethdev -lrte_pci -lrte_stack -lrte_eventdev -lrte_pdump         \
+                 -lrte_table -lrte_fib -lrte_pipeline -lrte_timer -lrte_flow_classify -lrte_vhost               \
+        -lrte_gro
 endif
 
 ifeq ($(O1_ENABLE),YES)

diff --git a/container-tag.yaml b/container-tag.yaml
index 11f2e4f..d99778a 100644 (file)
--- a/container-tag.yaml
+++ b/container-tag.yaml
@@ -1,4 +1,4 @@
 # The Jenkins job requires a tag to build the Docker image.
 # Global-JJB script assumes this file is in the repo root.
 ---
-tag: 6.0.1
+tag: 6.0.2

diff --git a/docs/release-notes.rst b/docs/release-notes.rst
index 3e9039a..5d78a47 100644 (file)
--- a/docs/release-notes.rst
+++ b/docs/release-notes.rst
@@ -181,8 +181,9 @@ F release
 |                                      |                                      |   
 +--------------------------------------+--------------------------------------+
 | **Repo/commit-ID**                   |o-du/l2/                              |
-|                                      |I2eeed74163fe985e6421ea563c5170f8cf81 |
-|                                      |7e6d                                  |
+|                                      |I6058cf6966e75f31aa568ba5030c16d2723  |
+|                                      |515eb                                 |
+|                                      |                                      |
 +--------------------------------------+--------------------------------------+
 | **Release designation**              | F release                            |
 |                                      |                                      |   

diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 620f396..19437b9 100644 (file)
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -66,17 +66,17 @@ II. Execution - Using Docker Images
 The call flow between O-DU High and CU Stub can be achieved by executing docker containers.
 
 - Pull the last built docker images:
-    -  docker pull nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2:6.0.1
-    -  docker pull nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2-cu-stub:6.0.1
+    -  docker pull nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2:6.0.2
+    -  docker pull nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2-cu-stub:6.0.2
 
 - Run CU Stub docker:
     - docker run -it --privileged --net=host --entrypoint bash
-      nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2-cu-stub:6.0.1   
+      nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2-cu-stub:6.0.2
     - ./cu_stub
 
 - Run ODU docker:
     - docker run -it --privileged --net=host --entrypoint bash
-      nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2:6.0.1   
+      nexus3.o-ran-sc.org:10004/o-ran-sc/o-du-l2:6.0.2
     - ./odu
 
 

diff --git a/releases/container-release-o-du-l2 b/releases/container-release-o-du-l2
index 019fcbd..c195a82 100644 (file)
--- a/releases/container-release-o-du-l2
+++ b/releases/container-release-o-du-l2
@@ -1,11 +1,11 @@
 ---
 
 distribution_type: container
-container_release_tag: 6.0.1
+container_release_tag: 6.0.2
 container_pull_registry: nexus.o-ran-sc.org:10004
 container_push_registry: nexus.o-ran-sc.org:10002
 project: o-du-l2 
-ref: eda4b205c3734bde66da2ec74427220890479920
+ref: 16d167817574850a75f64df4579e896d3ab2af47
 containers:
 - name: o-du-l2
-version: 6.0.1
+version: 6.0.2

diff --git a/releases/container-release-o-du-l2-cu-stub b/releases/container-release-o-du-l2-cu-stub
index 263da0c..9335cda 100644 (file)
--- a/releases/container-release-o-du-l2-cu-stub
+++ b/releases/container-release-o-du-l2-cu-stub
@@ -1,11 +1,11 @@
 ---
 
 distribution_type: container
-container_release_tag: 6.0.1
+container_release_tag: 6.0.2
 container_pull_registry: nexus.o-ran-sc.org:10004
 container_push_registry: nexus.o-ran-sc.org:10002
 project: o-du-l2 
-ref: eda4b205c3734bde66da2ec74427220890479920
+ref: 16d167817574850a75f64df4579e896d3ab2af47
 containers:
 - name: o-du-l2-cu-stub
-version: 6.0.1
+version: 6.0.2

diff --git a/src/5gnrmac/lwr_mac_ex_ms.c b/src/5gnrmac/lwr_mac_ex_ms.c
index abf31e3..387351b 100644 (file)
--- a/src/5gnrmac/lwr_mac_ex_ms.c
+++ b/src/5gnrmac/lwr_mac_ex_ms.c
@@ -23,7 +23,7 @@
 #include "lwr_mac_fsm.h"\r
 #include "lwr_mac_phy.h"\r
 #ifdef INTEL_FAPI\r
-#include "fapi.h"\r
+#include "nr5g_fapi_internal.h"\r
 #include "fapi_vendor_extension.h"\r
 #endif\r
 #ifndef INTEL_WLS_MEM\r

diff --git a/src/5gnrmac/lwr_mac_fsm.c b/src/5gnrmac/lwr_mac_fsm.c
index eea67e8..e3d256f 100644 (file)
--- a/src/5gnrmac/lwr_mac_fsm.c
+++ b/src/5gnrmac/lwr_mac_fsm.c
@@ -27,7 +27,7 @@
 #include "mac.h"
 #include "lwr_mac.h"
 #ifdef INTEL_FAPI
-#include "fapi.h"
+#include "nr5g_fapi_internal.h"
 #include "fapi_vendor_extension.h"
 #endif
 #ifdef INTEL_WLS_MEM
@@ -3396,7 +3396,7 @@ uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, MacCel
 
 #ifdef INTEL_WLS_MEM
    mtGetWlsHdl(&wlsHdlr);
-   pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, sib1Payload);
+   pduDesc[pduIndex].tlvs[0].value = (uint8_t *)(WLS_VA2PA(wlsHdlr, sib1Payload));
 #else
    pduDesc[pduIndex].tlvs[0].value = sib1Payload;
 #endif
@@ -3458,7 +3458,7 @@ uint8_t fillPageTxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, DlPage
 
 #ifdef INTEL_WLS_MEM
    mtGetWlsHdl(&wlsHdlr);
-   pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, pagePayload);
+   pduDesc[pduIndex].tlvs[0].value = (uint8_t *)(WLS_VA2PA(wlsHdlr, pagePayload));
 #else
    pduDesc[pduIndex].tlvs[0].value = pagePayload;
 #endif
@@ -3518,7 +3518,7 @@ uint8_t fillRarTxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, RarInfo
 
 #ifdef INTEL_WLS_MEM
    mtGetWlsHdl(&wlsHdlr);
-   pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, rarPayload);
+   pduDesc[pduIndex].tlvs[0].value = (uint8_t *)(WLS_VA2PA(wlsHdlr, rarPayload));
 #else
    pduDesc[pduIndex].tlvs[0].value = rarPayload;
 #endif
@@ -3577,7 +3577,7 @@ uint8_t fillDlMsgTxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, DlMsg
 
 #ifdef INTEL_WLS_MEM
    mtGetWlsHdl(&wlsHdlr);
-   pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, dlMsgPayload);
+   pduDesc[pduIndex].tlvs[0].value = (uint8_t *)(WLS_VA2PA(wlsHdlr, dlMsgPayload));
 #else
    pduDesc[pduIndex].tlvs[0].value = dlMsgPayload;
 #endif

diff --git a/src/5gnrmac/lwr_mac_handle_phy.c b/src/5gnrmac/lwr_mac_handle_phy.c
index 9e00914..bce5ed4 100644 (file)
--- a/src/5gnrmac/lwr_mac_handle_phy.c
+++ b/src/5gnrmac/lwr_mac_handle_phy.c
@@ -20,7 +20,7 @@
 #include "common_def.h"
 #include "lrg.h"
 #ifdef INTEL_FAPI
-#include "fapi.h"
+#include "nr5g_fapi_internal.h"
 #include "fapi_vendor_extension.h"
 #endif
 

diff --git a/src/5gnrmac/lwr_mac_phy.c b/src/5gnrmac/lwr_mac_phy.c
index 15a6cb5..23571ae 100644 (file)
--- a/src/5gnrmac/lwr_mac_phy.c
+++ b/src/5gnrmac/lwr_mac_phy.c
@@ -31,7 +31,7 @@
 #include "lwr_mac_utils.h"
 #include "lwr_mac.h"
 #ifdef INTEL_FAPI
-#include "fapi.h"
+#include "nr5g_fapi_internal.h"
 #include "fapi_vendor_extension.h"
 #endif
 #ifdef INTEL_WLS_MEM

diff --git a/src/5gnrmac/lwr_mac_phy.h b/src/5gnrmac/lwr_mac_phy.h
index 456d8c5..516fa17 100644 (file)
--- a/src/5gnrmac/lwr_mac_phy.h
+++ b/src/5gnrmac/lwr_mac_phy.h
@@ -63,6 +63,7 @@ typedef struct wlsBlockToFree
 
 CmLListCp wlsBlockToFreeList[WLS_MEM_FREE_PRD];
 
+void addWlsBlockToFree(void *msg, uint32_t msgLen, uint8_t idx);
 void freeWlsBlockList(uint8_t idx);
 void LwrMacEnqueueWlsBlock();
 void LwrMacRecvPhyMsg();

diff --git a/src/5gnrmac/mac_slot_ind.c b/src/5gnrmac/mac_slot_ind.c
index fc32cc1..2492f2a 100644 (file)
--- a/src/5gnrmac/mac_slot_ind.c
+++ b/src/5gnrmac/mac_slot_ind.c
@@ -29,6 +29,7 @@
 #include "lwr_mac_fsm.h"
 #include "mac_utils.h"
 #include "mac_harq_dl.h"
+#include "lwr_mac_phy.h"
 
 /* function pointers for packing slot ind from mac to sch */
 MacSchSlotIndFunc macSchSlotIndOpts[] =

diff --git a/src/5gnrmac/mac_ue_mgr.c b/src/5gnrmac/mac_ue_mgr.c
index c6634bf..cbabb28 100644 (file)
--- a/src/5gnrmac/mac_ue_mgr.c
+++ b/src/5gnrmac/mac_ue_mgr.c
@@ -2779,7 +2779,7 @@ uint8_t MacProcSchUeDeleteRsp(Pst *pst, SchUeDeleteRsp *schUeDelRsp)
                   }
                   memset(&macCb.macCell[cellIdx]->ueCb[ueId -1], 0, sizeof(MacUeCb));
                   macCb.macCell[cellIdx]->numActvUe--;
-                  result = SUCCESS;
+                  result = DEL_SUCCESSFUL;
                   ret = ROK;
                }
                else
@@ -2870,7 +2870,7 @@ uint8_t MacProcUeDeleteReq(Pst *pst, MacUeDelete *ueDelete)
 {
    uint8_t ret = ROK;
    uint8_t cellIdx=0;
-   UeDeleteStatus result=SUCCESS;
+   UeDeleteStatus result=DEL_SUCCESSFUL;
    MacUeCb  *ueCb = NULLP;
    MacCellCb *cellCb = NULLP;
 
@@ -2904,7 +2904,7 @@ uint8_t MacProcUeDeleteReq(Pst *pst, MacUeDelete *ueDelete)
          result = CELLID_INVALID;
       }
 
-      if(result != SUCCESS)
+      if(result != DEL_SUCCESSFUL)
       {
          MacSendUeDeleteRsp(ueDelete->cellId, ueDelete->crnti, result);
          MAC_FREE_SHRABL_BUF(pst->region, pst->pool, ueDelete, sizeof(MacUeDelete));

diff --git a/src/cm/du_app_mac_inf.h b/src/cm/du_app_mac_inf.h
index 6221e5b..b0e13be 100644 (file)
--- a/src/cm/du_app_mac_inf.h
+++ b/src/cm/du_app_mac_inf.h
@@ -105,7 +105,7 @@ typedef enum
 
 typedef enum
 {
-   SUCCESS,
+   DEL_SUCCESSFUL,
    CELLID_INVALID,
    UEID_INVALID
 }UeDeleteStatus;

diff --git a/src/du_app/du_f1ap_msg_hdl.c b/src/du_app/du_f1ap_msg_hdl.c
index 789e342..d99b9bf 100644 (file)
--- a/src/du_app/du_f1ap_msg_hdl.c
+++ b/src/du_app/du_f1ap_msg_hdl.c
@@ -13031,7 +13031,7 @@ uint8_t procF1UeContextSetupReq(F1AP_PDU_t *f1apMsg)
                GET_CELL_IDX(nrCellId, cellIdx);
                if(!duCb.actvCellLst[cellIdx])
                {
-                  DU_LOG("\nERROR  -->  F1AP : Cell Id [%d] not found", nrCellId);
+                  DU_LOG("\nERROR  -->  F1AP : Cell Id [%lu] not found", nrCellId);
                   ret = RFAILED;
                }
                break;
@@ -13086,7 +13086,7 @@ uint8_t procF1UeContextSetupReq(F1AP_PDU_t *f1apMsg)
                      gnbDuUeF1apId = ueIdx +1;
                   else
                   {
-                     DU_LOG("\nERROR  -->  F1AP : No free UE IDX found in UE bit map of cell Id [%d]", nrCellId);
+                     DU_LOG("\nERROR  -->  F1AP : No free UE IDX found in UE bit map of cell Id [%lu]", nrCellId);
                      ret = RFAILED;
                      break;
                   }
@@ -14752,7 +14752,7 @@ uint8_t duProcGnbDuCfgUpdAckMsg(uint8_t transId)
                            if(ret == RFAILED)
                            {
                               DU_LOG("\nERROR  --> DU_APP : duProcGnbDuCfgUpdAckMsg(): Failed to send cell delete\
-                              request for cellId[%d]", cellId);
+                              request for cellId[%lu]", cellId);
                            }
                         }
                         else
@@ -14773,7 +14773,7 @@ uint8_t duProcGnbDuCfgUpdAckMsg(uint8_t transId)
                               if(ret == RFAILED)
                               {
                                  DU_LOG("\nERROR  --> DU_APP : duProcGnbDuCfgUpdAckMsg(): Failed to build and send UE delete\
-                                 request for cellId[%d]", cellId);
+                                 request for cellId[%lu]", cellId);
                               }
                               ueIdx++;
                               totalActiveUe--;
@@ -14782,7 +14782,7 @@ uint8_t duProcGnbDuCfgUpdAckMsg(uint8_t transId)
                      }
                      else
                      {
-                        DU_LOG("\nERROR  --> DU_APP : duProcGnbDuCfgUpdAckMsg(): CellId [%d] not found", cellId);
+                        DU_LOG("\nERROR  --> DU_APP : duProcGnbDuCfgUpdAckMsg(): CellId [%lu] not found", cellId);
                         ret = RFAILED;
                      }
                      break;
@@ -16600,7 +16600,7 @@ uint8_t procPagingMsg(F1AP_PDU_t *f1apMsg)
                                  bitStringToInt(&pagingCellItem->nRCGI.nRCellIdentity, &cellId);
                                  if(processPagingMsg(cellId, tmpPagingParam) != ROK)
                                  {
-                                    DU_LOG("\nERROR  --> DU APP : Paging Processing Failed at CellId:%d",cellId);
+                                    DU_LOG("\nERROR  --> DU APP : Paging Processing Failed at CellId:%lu",cellId);
                                     continue;
                                  }
                               }

diff --git a/src/du_app/du_ue_mgr.c b/src/du_app/du_ue_mgr.c
index c2f7f86..71e8709 100644 (file)
--- a/src/du_app/du_ue_mgr.c
+++ b/src/du_app/du_ue_mgr.c
@@ -3255,7 +3255,7 @@ uint8_t DuProcMacUeDeleteRsp(Pst *pst, MacUeDeleteRsp *deleteRsp)
    
    if(deleteRsp)
    {
-      if(deleteRsp->result == SUCCESS)
+      if(deleteRsp->result == DEL_SUCCESSFUL)
       {
          DU_LOG("\nINFO   -->  DU APP : MAC UE Delete Response : SUCCESS [UE IDX : %d]", deleteRsp->ueId);
          GET_CELL_IDX(deleteRsp->cellId, cellIdx);

diff --git a/src/intel_fapi/fapi_vendor_extension.h b/src/intel_fapi/fapi_vendor_extension.h
index ba16e57..aa0069b 100644 (file)
--- a/src/intel_fapi/fapi_vendor_extension.h
+++ b/src/intel_fapi/fapi_vendor_extension.h
@@ -23,6 +23,10 @@
 extern "C" {
 #endif
 
+#include <stdint.h>
+
+#include "fapi_interface.h"
+
 #define FAPI_VENDOR_MESSAGE                                 0x10
 #define FAPI_VENDOR_EXT_SHUTDOWN_REQUEST                    0x11
 #define FAPI_VENDOR_EXT_SHUTDOWN_RESPONSE                   0x12
@@ -31,14 +35,27 @@ extern "C" {
 #define FAPI_VENDOR_EXT_DL_IQ_SAMPLES                       0x13
 #define FAPI_VENDOR_EXT_UL_IQ_SAMPLES                       0x14
 #define FAPI_VENDOR_EXT_START_RESPONSE                      0x15
+#define FAPI_VENDOR_EXT_ADD_REMOVE_CORE                     0x16
 #endif
 
+#define FAPI_VENDOR_EXT_P7_IND                              0x17
+
 /* ----- WLS Operation --- */
 #define FAPI_VENDOR_MSG_HEADER_IND                          0x1A
 
 // PDSCH Payload
 #define FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ                   0x1B
 
+#define MAX_SNR_COUNT                                       (255)
+#define FAPI_VENDOR_MAX_RXRU_NUM                            16
+#define FAPI_VENDOR_MAX_TXRU_NUM                            4
+#define FAPI_VENDOR_MAX_SRS_PORT_PER_UE                     2
+#define FAPI_VENDOR_MAX_NUM_ANT                             64
+
+enum {
+    USE_VENDOR_EPREXSSB = 1
+};
+
 // Linked list header present at the top of all messages
     typedef struct _fapi_api_queue_elem {
         struct _fapi_api_queue_elem *p_next;
@@ -57,9 +74,13 @@ extern "C" {
 #define FAPI_MAX_IQ_SAMPLE_FILE_SIZE                        576
 #define FAPI_MAX_IQ_SAMPLE_DL_PORTS                          16
 #define FAPI_MAX_IQ_SAMPLE_UL_PORTS                           2
-#define FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS                   8
+#define FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS                  16
 #define FAPI_MAX_IQ_SAMPLE_UL_ANTENNA                        64
 #define FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE                     4096
+
+#define FAPI_MAX_NUM_SET_CORE_MASK ( 4 )
+#define FAPI_MAX_MASK_OPTIONS      ( 4 )
+#define FAPI_NUM_SPLIT_OPTIONS     ( 22 )
 #endif
 
     typedef struct {
@@ -68,7 +89,14 @@ extern "C" {
         uint8_t group_hop_flag;
         uint8_t sequence_hop_flag;
         // uint8_t                     nDMRS_type_A_pos;
-        uint8_t pad[3];
+        uint8_t prach_nr_of_rx_ru;
+        uint8_t nr_of_dl_ports;
+        uint8_t nr_of_ul_ports;
+        uint16_t urllc_capable;
+        uint16_t urllc_mini_slot_mask;
+        uint8_t ssb_subc_spacing;
+        uint8_t use_vendor_EpreXSSB;  // values: USE_VENDOR_EPREXSSB - use; else don't use
+        uint8_t pad[2];
     } fapi_config_req_vendor_msg_t;
 
     typedef struct {
@@ -86,11 +114,135 @@ extern "C" {
         uint16_t slot;
     } fapi_stop_req_vendor_msg_t;
 
+// P7 vendor extensions
+    typedef struct {
+        uint8_t nr_of_antenna_ports;
+        uint8_t nr_of_rx_ru;
+        uint8_t pad[2];
+        uint8_t rx_ru_idx[FAPI_VENDOR_MAX_RXRU_NUM];
+        // open for extension for new fields from ULSCHPDUStruct
+    } fapi_vendor_ul_pusch_pdu_t;
+
+    typedef struct {
+        uint8_t nr_of_rx_ru;
+        uint8_t pad[1];
+        uint16_t group_id;
+        uint8_t rx_ru_idx[FAPI_VENDOR_MAX_RXRU_NUM];
+        // open for extension for new fields from ULCCHUCIPDUStruct
+    } fapi_vendor_ul_pucch_pdu_t;
+
+    typedef struct {
+        uint8_t nr_of_rx_ru;
+        uint8_t pad[3];
+        uint8_t rx_ru_idx[FAPI_VENDOR_MAX_RXRU_NUM];
+        // open for extension for new fields from SRSPDUStruct
+    } fapi_vendor_ul_srs_pdu_t;
+
+    typedef struct {
+        uint16_t pdu_type;
+        uint16_t pad;
+        union {
+            fapi_vendor_ul_pusch_pdu_t pusch_pdu;
+            fapi_vendor_ul_pucch_pdu_t pucch_pdu;
+            fapi_vendor_ul_srs_pdu_t srs_pdu;
+            // open for extension for prach vendor type (as in fapi_ul_tti_req_pdu_t)
+        } pdu;
+    } fapi_vendor_ul_tti_req_pdu_t;
+
+    typedef struct {
+        fapi_vendor_ul_tti_req_pdu_t ul_pdus[FAPI_MAX_NUMBER_UL_PDUS_PER_TTI];
+        uint8_t num_ul_pdu;
+        uint8_t pad[3];
+        uint32_t sym;
+        // open for extension for new fields from PULConfigRequestStruct
+    } fapi_vendor_ul_tti_req_t;
+
+    typedef struct {
+        uint16_t epre_ratio_of_pdcch_to_ssb;
+        uint16_t epre_ratio_of_dmrs_to_ssb;
+        // open for extension for new fields from DCIPDUStruct
+    } fapi_vendor_dl_dci_t;
+
+    typedef struct {
+        uint16_t num_dl_dci;
+        uint8_t pad[2];
+        fapi_vendor_dl_dci_t dl_dci[FAPI_MAX_NUMBER_DL_DCI];
+    } fapi_vendor_dl_pdcch_pdu_t;
+
+   typedef struct {
+        uint16_t epre_ratio_of_pdsch_to_ssb;
+        uint16_t epre_ratio_of_dmrs_to_ssb;
+        uint8_t nr_of_antenna_ports;
+        uint8_t pad[3];
+        uint8_t tx_ru_idx[FAPI_VENDOR_MAX_TXRU_NUM];
+        // open for extension for new fields from DLSCHPDUStruct
+    } fapi_vendor_dl_pdsch_pdu_t;
+
+    typedef struct {
+        uint16_t epre_ratio_to_ssb;
+        uint8_t pad[2];
+    } fapi_vendor_csi_rs_pdu_t;
+
+    typedef struct {
+        uint16_t pdu_type;
+        uint16_t pdu_size;
+        union {
+            fapi_vendor_dl_pdcch_pdu_t pdcch_pdu;
+            fapi_vendor_dl_pdsch_pdu_t pdsch_pdu;
+            fapi_vendor_csi_rs_pdu_t csi_rs_pdu;
+            // open for extension for ssb vendor types (as in fapi_dl_tti_req_pdu_t)
+        } pdu;
+    } fapi_vendor_dl_tti_req_pdu_t;
+
+    typedef struct {
+        uint32_t sym;
+        uint16_t lte_crs_carrier_freq_dl;
+        uint8_t lte_crs_present;
+        uint8_t lte_crs_carrier_bandwidth_dl;
+        uint8_t lte_crs_nr_of_crs_ports;
+        uint8_t lte_crs_v_shift;
+        uint8_t pdcch_precoder_en;
+        uint8_t ssb_precoder_en;
+        uint8_t num_pdus;
+        uint8_t pad[3];
+        fapi_vendor_dl_tti_req_pdu_t pdus[FAPI_MAX_PDUS_PER_SLOT];
+        // open for extension for new fields from DLConfigRequestStruct
+    } fapi_vendor_dl_tti_req_t;
+
+    typedef struct {
+        uint16_t pdu_type;
+        uint16_t pdu_size;
+        fapi_vendor_dl_pdcch_pdu_t pdcch_pdu_config;
+    } fapi_vendor_dci_pdu_t;
+
+    typedef struct {
+        uint32_t sym;
+        uint8_t num_pdus;
+        uint8_t pad[3];
+        fapi_vendor_dci_pdu_t pdus[FAPI_MAX_NUMBER_UCI_PDUS_PER_SLOT];
+        // open for extension for new fields from ULDCIRequestStruct
+    } fapi_vendor_ul_dci_req_t;
+
+    typedef struct {
+        uint32_t sym;
+        // open for extension for new fields from TXRequestStruct
+    } fapi_vendor_tx_data_req_t;
+
+    typedef struct {
+        fapi_vendor_dl_tti_req_t dl_tti_req;
+        fapi_vendor_ul_tti_req_t ul_tti_req;
+        fapi_vendor_ul_dci_req_t ul_dci_req;
+        fapi_vendor_tx_data_req_t tx_data_req;
+    } fapi_vendor_p7_msg_t;
+
+// P7 vendor extensions end
+
     typedef struct {
         fapi_msg_t header;
         fapi_config_req_vendor_msg_t config_req_vendor;
         fapi_start_req_vendor_msg_t start_req_vendor;
         fapi_stop_req_vendor_msg_t stop_req_vendor;
+        fapi_vendor_p7_msg_t p7_req_vendor;
     } fapi_vendor_msg_t;
 
     typedef struct {
@@ -107,6 +259,58 @@ extern "C" {
         uint32_t nStatus;
     } fapi_vendor_ext_shutdown_res_t;
 
+    typedef struct {
+        int16_t nSNR[MAX_SNR_COUNT];
+        int16_t pad;
+    } fapi_vendor_ext_snr_t;
+
+    typedef struct {
+        uint8_t nr_of_port;
+        uint8_t nr_of_rx_ant;
+        uint16_t nr_of_rbs;
+        uint8_t is_chan_est_pres;
+        uint8_t pad[3];
+        int16_t *p_srs_chan_est[FAPI_VENDOR_MAX_SRS_PORT_PER_UE]
+            [FAPI_VENDOR_MAX_NUM_ANT];
+    } fapi_vendor_ext_srs_pdu_t;
+
+    typedef struct {
+        uint8_t num_pdus;
+        uint8_t pad[3];
+        fapi_vendor_ext_srs_pdu_t srs_pdus[FAPI_MAX_NUMBER_SRS_PDUS_PER_SLOT];
+    } fapi_vendor_ext_srs_ind_t;
+
+    typedef struct {
+        uint32_t carrier_idx;
+        uint32_t sym;
+    } fapi_vendor_ext_slot_ind_t;
+
+    typedef struct {
+        uint32_t carrier_idx;
+        uint32_t sym;
+    } fapi_vendor_ext_rx_data_ind_t;
+
+    typedef struct {
+        uint32_t carrier_idx;
+        uint32_t sym;
+    } fapi_vendor_ext_crc_ind_t;
+
+    typedef struct {
+        uint32_t carrier_idx;
+        uint32_t sym;
+    } fapi_vendor_ext_uci_ind_t;
+
+    typedef struct {
+        fapi_msg_t header;
+        fapi_vendor_ext_snr_t crc_snr;
+        fapi_vendor_ext_snr_t uci_snr;
+        fapi_vendor_ext_srs_ind_t srs_ind;
+        fapi_vendor_ext_slot_ind_t slot_ind;
+        fapi_vendor_ext_rx_data_ind_t rx_data_ind;        
+        fapi_vendor_ext_crc_ind_t crc_ind;
+        fapi_vendor_ext_uci_ind_t uci_ind;
+    } fapi_vendor_p7_ind_msg_t;
+
 #ifdef DEBUG_MODE
     typedef struct {
         uint32_t carrNum;
@@ -119,6 +323,8 @@ extern "C" {
         uint32_t startSymNum;
         char filename_in_ul_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
             [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+        char filename_in_ul_iq_compressed[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
+            [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
         char filename_in_prach_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
             [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
         char filename_in_srs_iq[FAPI_MAX_IQ_SAMPLE_UL_ANTENNA]
@@ -128,6 +334,19 @@ extern "C" {
             [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
         char filename_out_ul_beam[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS]
             [FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+        char filename_out_dl_iq_compressed[FAPI_MAX_IQ_SAMPLE_FILE_SIZE];
+
+        /* DL Compression add */
+        uint16_t nDLCompressionIdx;
+        uint16_t nDLCompiqWidth;
+        uint16_t nDLCompScaleFactor;
+        uint16_t nDLCompreMask;
+
+        /*nULDecompressionIdx, determine the UL Decompression method, Value:0->4*/
+        /*0:NONE,  1:BLKFLOAT,  2:BLKSCALE,  3:ULAW,  4:MODULATION*/
+        uint16_t nULDecompressionIdx;
+        uint16_t nULDecompiqWidth;
+
         uint8_t buffer[FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE];
     } fapi_vendor_ext_iq_samples_info_t;
 
@@ -147,6 +366,17 @@ extern "C" {
     typedef struct {
         fapi_msg_t header;
     } fapi_vendor_ext_start_response_t;
+
+    typedef struct {
+        uint32_t eOption;
+        uint64_t nCoreMask[FAPI_MAX_MASK_OPTIONS][FAPI_MAX_NUM_SET_CORE_MASK];
+        uint32_t nMacOptions[FAPI_NUM_SPLIT_OPTIONS];
+    } fapi_vendor_ext_add_remove_core_info_t;
+
+    typedef struct {
+        fapi_msg_t header;
+        fapi_vendor_ext_add_remove_core_info_t add_remove_core_info;
+    } fapi_vendor_ext_add_remove_core_msg_t;
 #endif
 
 #if defined(__cplusplus)

diff --git a/src/intel_fapi/nr5g_fapi_common_types.h b/src/intel_fapi/nr5g_fapi_common_types.h
new file mode 100644 (file)
index 0000000..f993c36
--- /dev/null
+++ b/src/intel_fapi/nr5g_fapi_common_types.h
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+#ifndef _NR5G_FAPI_COMMON_TYPES_H_
+#define _NR5G_FAPI_COMMON_TYPES_H_
+
+#ifndef TRUE
+/** TRUE = 1 */
+#define TRUE 1
+#endif                          /* #ifndef TRUE */
+
+#ifndef FALSE
+/** FALSE = 0 */
+#define FALSE 0
+#endif                          /* #ifndef FALSE */
+
+#ifndef SUCCESS
+/** SUCCESS = 0 */
+#define SUCCESS     0
+#endif                          /* #ifndef SUCCESS */
+
+#ifndef FAILURE
+/** FAILURE = 1 */
+#define FAILURE     1
+#endif                          /* #ifndef FAILURE */
+
+#define RUP512B(x) (((x)+511)&(~511))
+#define RUP256B(x) (((x)+255)&(~255))
+#define RUP128B(x) (((x)+127)&(~127))
+#define RUP64B(x) (((x)+63)&(~63))
+#define RUP32B(x) (((x)+31)&(~31))
+#define RUP16B(x) (((x)+15)&(~15))
+#define RUP8B(x)  (((x)+7)&(~7))
+#define RUP4B(x)  (((x)+3)&(~3))
+#define RUP2B(x)  (((x)+1)&(~1))
+
+//#define UNUSED(x) (void)(x)
+
+#endif                          // _NR5G_FAPI_COMMON_TYPES_H_

diff --git a/src/intel_fapi/fapi.h b/src/intel_fapi/nr5g_fapi_internal.h
similarity index 71%
rename from src/intel_fapi/fapi.h
rename to src/intel_fapi/nr5g_fapi_internal.h
index 6ab2abb..a1d72c2 100644 (file)
--- a/src/intel_fapi/fapi.h
+++ b/src/intel_fapi/nr5g_fapi_internal.h
@@ -1,796 +1,649 @@
-/******************************************************************************\r
-*   Copyright 2017 Cisco Systems, Inc.\r
-*   Copyright (c) 2019 Intel.\r
-*\r
-*   Licensed under the Apache License, Version 2.0 (the "License");\r
-*   you may not use this file except in compliance with the License.\r
-*   You may obtain a copy of the License at\r
-*\r
-*       http://www.apache.org/licenses/LICENSE-2.0\r
-*\r
-*   Unless required by applicable law or agreed to in writing, software\r
-*   distributed under the License is distributed on an "AS IS" BASIS,\r
-*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-*   See the License for the specific language governing permissions and\r
-*   limitations under the License.\r
-*\r
-*******************************************************************************/\r
-// This file has been modified by Intel in order to support 5G FAPI:PHY API Specification\r
-// Document 222.10.01 dated June 2019\r
-// Changes made by luis.farias@intel.com\r
-/**\r
- * @file\r
- * This file consist of FAPI configuration APIs macros, structure typedefs and\r
- * prototypes.\r
- *\r
- **/\r
-\r
-#ifndef _FAPI_H_\r
-#define _FAPI_H_\r
-\r
-#include <stdint.h>\r
-\r
-#include "fapi_interface.h"\r
-//#include "fapi_vendor_common_defs.h"\r
-\r
-#define RELEASE_15                                  0x0001\r
-\r
-// Datatypes typedefs - end\r
-\r
-typedef enum {\r
-    FAPI_SUCCESS = 0,\r
-    FAPI_FAILURE\r
-} fapiStatus_t;\r
-// Updated per 5G FAPI\r
-\r
-\r
-\r
-// Updated per 5G FAPI    \r
-typedef enum {\r
-    FAPI_UL_TTI_REQ_PRACH_PDU_TYPE = 0,\r
-    FAPI_UL_TTI_REQ_PUSCH_PDU_TYPE,\r
-    FAPI_UL_TTI_REQ_PUCCH_PDU_TYPE,\r
-    FAPI_UL_TTI_REQ_SRS_PDU_TYPE\r
-}fapiULTtiReqPduType_e;\r
-// Updated per 5G FAPI\r
-typedef enum {\r
-    FAPI_UCI_IND_ON_PUSCH_PDU_TYPE = 0,\r
-    FAPI_UCI_IND_ON_PUCCH_FMT_0_1_PDU_TYPE,\r
-    FAPI_UCI_IND_ON_PUCCH_FMT_2_3_4_PDU_TYPE\r
-}fapiUciIndPdu_Type_e;\r
-    \r
-// CRC\r
-enum {\r
-    FAPI_CRC_CORRECT = 0,\r
-    FAPI_CRC_ERROR = 1\r
-};\r
-\r
-//------------------------------------------------------------------------------\r
-// Fapi Infra Declarations\r
-//------------------------------------------------------------------------------\r
-// Release/Features support\r
-typedef enum {\r
-    FAPI_NOT_SUPPORTED = 0,\r
-    FAPI_SUPPORTED,\r
-} fapiSupport_t;\r
-\r
-// FAPI States\r
-/**\r
- * FAPI state is maintained per fapi instance. If FAPI messages are received in\r
- * wrong state an ERROR.indication message will be sent by FAPI.\r
- */\r
-typedef enum fapiStates\r
-{\r
-    FAPI_STATE_IDLE = 0,\r
-    FAPI_STATE_CONFIGURED,\r
-    FAPI_STATE_RUNNING\r
-} fapiStates_t;\r
-\r
-// Information of optional and mandatory status for a TLV\r
-typedef enum {\r
-    FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,\r
-    FAPI_IDLE_STATE_ONLY_MANDATORY,\r
-    FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,\r
-    FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,\r
-    FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,\r
-    FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL\r
-} fapiTlvStatus_t;\r
-\r
-// PARAMETERS INFORMATION\r
-\r
-#define FAPI_NORMAL_CYCLIC_PREFIX_MASK              0x01\r
-#define FAPI_EXTENDED_CYCLIC_PREFIX_MASK            0x02\r
-\r
-// In 5G FAPI FrameDuplexType as part of Cell Configuration\r
-typedef enum\r
-{\r
-    TDD_DUPLEX = 0,\r
-    FDD_DUPLEX\r
-} modes;     //Defined now\r
-\r
-// Subcarrier spacing information\r
-#define FAPI_15KHZ_MASK                             0x01\r
-#define FAPI_30KHZ_MASK                             0x02\r
-#define FAPI_60KHZ_MASK                             0x04\r
-#define FAPI_120KHZ_MASK                            0x08\r
-\r
-// Bandwitdth information\r
-#define FAPI_5MHZ_BW_MASK                           0x0001\r
-#define FAPI_10MHZ_BW_MASK                          0x0002\r
-#define FAPI_15MHZ_BW_MASK                          0x0004\r
-#define FAPI_20MHZ_BW_MASK                          0x0010\r
-#define FAPI_40MHZ_BW_MASK                          0x0020\r
-#define FAPI_50MHZ_BW_MASK                          0x0040\r
-#define FAPI_60MHZ_BW_MASK                          0x0080\r
-#define FAPI_70MHZ_BW_MASK                          0x0100\r
-#define FAPI_80MHZ_BW_MASK                          0x0200\r
-#define FAPI_90MHZ_BW_MASK                          0x0400\r
-#define FAPI_100MHZ_BW_MASK                         0x0800\r
-#define FAPI_200MHZ_BW_MASK                         0x1000\r
-#define FAPI_400MHZ_BW_MASK                         0x2000\r
-\r
-\r
-// PDCCH Information\r
-#define FAPI_CCE_MAPPING_INTERLEAVED_MASK           0x01\r
-#define FAPI_CCE_MAPPING_NONINTERLVD_MASK           0x02\r
-// Upper Bound for PDCCH Channels per Slot\r
-#define FAPI_MAX_PDCCHS_PER_SLOT_MASK               0xff\r
-\r
-// PUCCH Information\r
-#define FAPI_FORMAT_0_MASK                          0x01\r
-#define FAPI_FORMAT_1_MASK                          0x02\r
-#define FAPI_FORMAT_2_MASK                          0x04\r
-#define FAPI_FORMAT_3_MASK                          0x08\r
-#define FAPI_FORMAT_4_MASK                          0x10\r
-// Upper Bound for PUCCH Channels per Slot\r
-#define FAPI_MAX_PUCCHS_PER_SLOT_MASK               0xff\r
-\r
-// PDSCH Information\r
-#define FAPI_PDSCH_MAPPING_TYPE_A_MASK              0x01\r
-#define FAPI_PDSCH_MAPPING_TYPE_B_MASK              0x02\r
-#define FAPI_PDSCH_ALLOC_TYPE_0_MASK                0x01\r
-#define FAPI_PDSCH_ALLOC_TYPE_1_MASK                0x02\r
-#define FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK    0x01\r
-#define FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK       0x02\r
-#define FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK          0x01\r
-#define FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK          0x02\r
-#define FAPI_PDSCH_DMRS_MAX_LENGTH_1                0\r
-#define FAPI_PDSCH_DMRS_MAX_LENGTH_2                1\r
-#define FAPI_DMRS_ADDITIONAL_POS_0_MASK             0x01\r
-#define FAPI_DMRS_ADDITIONAL_POS_1_MASK             0x02\r
-#define FAPI_DMRS_ADDITIONAL_POS_2_MASK             0x04\r
-#define FAPI_DMRS_ADDITIONAL_POS_3_MASK             0x08\r
-//Upper Limit for PDSCHS TBs per Slot\r
-#define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK           0xff\r
-#define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH            2\r
-\r
-typedef enum modulationOrder {\r
-    FAPI_QPSK                                       = 0,\r
-    FAPI_16QAM,\r
-    FAPI_64QAM,\r
-    FAPI_256QAM\r
-} fapiModOrder_t;\r
-\r
-#define FAPI_MAX_MUMIMO_USERS_MASK                  0xff\r
-\r
-\r
-// PUSCH Parameters\r
-\r
-#define FAPI_PUSCH_MAPPING_TYPE_A_MASK              0x01\r
-#define FAPI_PUSCH_MAPPING_TYPE_B_MASK              0x02\r
-#define FAPI_PUSCH_ALLOC_TYPE_0_MASK                0x01\r
-#define FAPI_PUSCH_ALLOC_TYPE_1_MASK                0x02\r
-#define FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK    0x01\r
-#define FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK       0x02\r
-#define FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK          0x01\r
-#define FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK          0x02\r
-#define FAPI_PUSCH_DMRS_MAX_LENGTH_1                0\r
-#define FAPI_PUSCH_DMRS_MAX_LENGTH_2                1\r
-// Upper limit for PUSCHMAXPTRSPORTS\r
-#define FAPI_PUSCH_MAX_PTRS_PORTS_UB                2\r
-//Upper Limit for PDSCHS TBs per Slot\r
-#define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK           0xff\r
-\r
-typedef enum aggregationFactor\r
-{\r
-    FAPI_PUSCH_AGG_FACTOR_1                         = 0,\r
-    FAPI_PUSCH_AGG_FACTOR_2,\r
-    FAPI_PUSCH_AGG_FACTOR_4,\r
-    FAPI_PUSCH_AGG_FACTOR_8\r
-} fapiPuschAggFactor_t;\r
-\r
-// PRACH Parameters\r
-#define FAPI_PRACH_LF_FORMAT_0_MASK                 0x01\r
-#define FAPI_PRACH_LF_FORMAT_1_MASK                 0x02\r
-#define FAPI_PRACH_LF_FORMAT_2_MASK                 0x04\r
-#define FAPI_PRACH_LF_FORMAT_3_MASK                 0x08\r
-\r
-#define FAPI_PRACH_SF_FORMAT_A1_MASK                0x01\r
-#define FAPI_PRACH_SF_FORMAT_A2_MASK                0x02\r
-#define FAPI_PRACH_SF_FORMAT_A3_MASK                0x04\r
-#define FAPI_PRACH_SF_FORMAT_B1_MASK                0x08\r
-#define FAPI_PRACH_SF_FORMAT_B2_MASK                0x10\r
-#define FAPI_PRACH_SF_FORMAT_B3_MASK                0x20\r
-#define FAPI_PRACH_SF_FORMAT_B4_MASK                0x40\r
-#define FAPI_PRACH_SF_FORMAT_C0_MASK                0x80\r
-#define FAPI_PRACH_SF_FORMAT_C2_MASK                0x100\r
-\r
-typedef enum {\r
-    FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_1               = 0,\r
-    FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_2,\r
-    FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_4,\r
-    FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_8\r
-}  fapi_prachMaxFdOccasionsPerSlot_t;      \r
-\r
-// Measurement Parameters\r
-#define FAPI_RSSI_REPORT_IN_DBM_MASK                0x01\r
-#define FAPI_RSSI_REPORT_IN_DBFS_MASK               0x02\r
-\r
-// CONFIGURATION INFORMATION\r
-// CARRIER CONFIGURATION\r
-// BANDWIDTH\r
-#define FAPI_BANDWIDTH_5_MHZ                        5\r
-#define FAPI_BANDWIDTH_10_MHZ                       10\r
-#define FAPI_BANDWIDTH_15_MHZ                       15\r
-#define FAPI_BANDWIDTH_20_MHZ                       20\r
-#define FAPI_BANDWIDTH_25_MHZ                       25\r
-#define FAPI_BANDWIDTH_30_MHZ                       30\r
-#define FAPI_BANDWIDTH_40_MHZ                       40\r
-#define FAPI_BANDWIDTH_50_MHZ                       50\r
-#define FAPI_BANDWIDTH_60_MHZ                       60\r
-#define FAPI_BANDWIDTH_70_MHZ                       70\r
-#define FAPI_BANDWIDTH_80_MHZ                       80\r
-#define FAPI_BANDWIDTH_90_MHZ                       90\r
-#define FAPI_BANDWIDTH_100_MHZ                      100\r
-#define FAPI_BANDWIDTH_200_MHZ                      200\r
-#define FAPI_BANDWIDTH_400_MHZ                      400\r
-\r
-// Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1\r
-// Lower Bound KHz\r
-#define FAPI_MIN_FREQUENCY_PT_A                     450000\r
-// Upper Bound KHz\r
-#define FAPI_MAX_FREQUENCY_PT_A                     52600000\r
-// dlk0, ulk0 per 38.211 Section 5.3.1\r
-// Upper Bound\r
-#define FAPI_K0_MAX                                 23699\r
-// dlGridSize, ulGridSize per 38.211 Section 4.4.2\r
-// Upper Bound\r
-#define FAPI_GRIDSIZE_MAX                           275\r
-// Number of Transmit Antennas\r
-// Define upper mask based on variable type\r
-#define FAPI_NUM_ANT_MASK                           0xffff\r
-\r
-// CELL CONFIGURATION\r
-// Physical Cell ID from 38.211 Section 7.4.2.1\r
-// Upper Bound\r
-#define FAPI_MAX_CELL_ID                            1007\r
-\r
-// SSB CONFIGURATION\r
-// SSB POWER RANGE in dBm\r
-#define FAPI_SS_PBCH_LOWEST_POWER                   -60\r
-#define FAPI_SS_PBCH_MAX_POWER                      50\r
-// BCH PAYLOAD  for 5G the MAC always generates the BCH Payload\r
-#define FAPI_BCH_PAYLOAD_GEN_BY_MAC                 0\r
-#define FAPI_BCH_PAYLOAD_WITH_PHY_GEN_TIMING        1\r
-#define FAPI_BCH_PAYLOAD_ENTIRELY_GEN_BY_PHY        2\r
-// ScsCommon\r
-#define FAPI_SCSCOMMON_MASK                         0x03\r
-\r
-// PRACH CONFIGURATION\r
-#define FAPI_PRACH_LONG_SEQUENCE                    0\r
-#define FAPI_PRACH_SHORT_SEQUENCE                   1\r
-#define FAPI_PRACH_SUBC_SPACING_MAX                 4\r
-// Restricted Set Configuration\r
-#define FAPI_PRACH_RESTRICTED_SET_UNRESTRICTED      0\r
-#define FAPI_PRACH_RESTRICTED_SET_TYPE_A            1\r
-#define FAPI_PRACH_RESTRICTED_SET_TYPE_B            2    \r
-// Root Sequence Index\r
-// Upper Bound\r
-#define FAPI_PRACH_ROOT_SEQ_INDEX_MAX               837         \r
-// k1\r
-// Upper Bound\r
-#define FAPI_K1_UPPER_BOUND                         272\r
-// PRACH Zero Corr Configuration\r
-// Upper Bound\r
-#define FAPI_PRACHZEROCORRCONF_MASK                 0x0f\r
-// Number of Unused Root Sequences Mask\r
-#define FAPI_UNUSEDROOTSEQUENCES_MASK               0x0f\r
-// SSBPERRACH\r
-typedef enum \r
-{\r
-    FAPI_SSB_PER_RACH_1_OVER_8                      = 0,\r
-    FAPI_SSB_PER_RACH_1_OVER_4,\r
-    FAPI_SSB_PER_RACH_1_OVER_2,\r
-    FAPI_SSB_PER_RACH_1,\r
-    FAPI_SSB_PER_RACH_2,\r
-    FAPI_SSB_PER_RACH_4,\r
-    FAPI_SSB_PER_RACH_8,\r
-    FAPI_SSB_PER_RACH_16\r
-} fapiSsbPerRach_t;     \r
-\r
-// SSB Table\r
-// Ssb Offset Point A max\r
-#define FAPI_SSB_OFFSET_POINTA_MAX                  2199\r
-// betaPSS  i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1\r
-#define FAPI_BETAPSS_0_DB                           0\r
-#define FAPI_BETAPSS_3_DB                           1\r
-// SSB Period in ms\r
-#define FAPI_SSB_PERIOD_5_MS                        0\r
-#define FAPI_SSB_PERIOD_10_MS                       1\r
-#define FAPI_SSB_PERIOD_20_MS                       2\r
-#define FAPI_SSB_PERIOD_40_MS                       3\r
-#define FAPI_SSB_PERIOD_80_MS                       4\r
-#define FAPI_SSB_PERIOD_160_MS                      5\r
-\r
-// Ssb Subcarrier Offset    per 38.211 Section 7.4.3.1\r
-// SsbSubcarrierOffset mask\r
-#define FAPI_SSB_SUBCARRIER_OFFSET_MASK             0x1f\r
-// MIB PAYLOAD MASK\r
-#define MIB_PAYLOAD_MASK                            0xfff0\r
-// BEAM ID MASK\r
-#define FAPI_BEAM_ID_MASK                           0x3f\r
-\r
-// TDD Table\r
-// TDD Period\r
-#define FAPI_TDD_PERIOD_0_P_5_MS                        0\r
-#define FAPI_TDD_PERIOD_0_P_625_MS                      1\r
-#define FAPI_TDD_PERIOD_1_MS                            2\r
-#define FAPI_TDD_PERIOD_1_P_25_MS                       3\r
-#define FAPI_TDD_PERIOD_2_MS                            4\r
-#define FAPI_TDD_PERIOD_2_P_5_MS                        5\r
-#define FAPI_TDD_PERIOD_5_MS                            6\r
-#define FAPI_TDD_PERIOD_10_MS                           7\r
-\r
-// Slot Configuration\r
-#define FAPI_DL_SLOT                                    0\r
-#define FAPI_UL_SLOT                                    1\r
-#define FAPI_GUARD_SLOT                                 2\r
-\r
-// Measurement configuration\r
-#define FAPI_NO_RSSI_REPORTING                          0\r
-#define FAPI_RSSI_REPORTED_IN_DBM                       1\r
-#define FAPI_RSSI_REPORTED_IN_DBFS                      2\r
-\r
-// Error Indication\r
-#define FAPI_SFN_MASK                                   0x03ff\r
-\r
-// Status and Error Codes for either .response or ERROR.indication\r
-// Updated per 5g FAPI Table 3-31\r
-/*\r
-typedef enum {\r
-    MSG_OK = 0,\r
-    MSG_INVALID_STATE,\r
-    MSG_INVALID_CONFIG,\r
-    SFN_OUT_OF_SYNC,\r
-    MSG_SLOT_ERR,\r
-    MSG_BCH_MISSING,\r
-    MSG_INVALID_SFN,\r
-    MSG_UL_DCI_ERR, \r
-    MSG_TX_ERR\r
- }fapiStatusAndErrorCodes_e;\r
-*/\r
- // Digital Beam Table (DBT) PDU\r
- // Number of Digital Beam Mask\r
- // Number of TX RUS Mask\r
- // Beam Index Mask\r
- // Digital Beam Index weights Real and Imaginary Mask\r
- \r
- // Precoding Matrix (PM) PDU\r
- // Precoding Matrix ID Mask\r
- // Number of Layers Mask\r
- // Number of Antenna Ports at the precoder output Mask\r
- // Precoder Weights Real and Imaginary Mask\r
- #define FAPI_U16_MASK                                  0xffff\r
- \r
- // Slot Indication\r
- \r
- #define FAPI_SLOT_MAX_VALUE                            319\r
- \r
- // DL_TTI.request\r
- // nPDUS mask\r
- // nGroup mask\r
- #define FAPI_U8_MASK                                   0xff\r
- \r
- typedef enum {\r
-    FAPI_DL_TTI_REQ_PDCCH_PDU_TYPE = 0,\r
-    FAPI_DL_TTI_REQ_PDSCH_PDU_TYPE,\r
-    FAPI_DL_TTI_REQ_CSI_RS_PDU_TYPE,\r
-    FAPI_DL_TTI_REQ_SSB_PDU_TYPE\r
-}fapiDlTtiReqPduType_e; \r
-\r
-// nUe\r
-// Define Maximum number of Ues per Group\r
-#define FAPI_MAX_NUMBER_OF_UES_PER_GROUP                12\r
-\r
-// PDCCH PDU\r
-#define FAPI_BWPSIZE_MAX                                275\r
-#define FAPI_BWPSIZE_START_MAX                          274\r
-#define FAPI_SUBCARRIER_SPACING_MAX                     4\r
-#define FAPI_CYCLIC_PREFIX_NORMAL                       0\r
-#define FAPI_CYCLIC_PREFIX_EXTENDED                     1\r
-#define FAPI_MAX_SYMBOL_START_INDEX                     13\r
-\r
-#define FAPI_CORESET_DURATION_1_SYMBOL                  1\r
-#define FAPI_CORESET_DURATION_2_SYMBOLS                 2\r
-#define FAPI_CORESET_DURATION_3_SYMBOLS                 3\r
-\r
-#define FAPI_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED       0\r
-#define FAPI_CCE_REG_MAPPING_TYPE_INTERLEAVED           1\r
-#define FAPI_REG_BUNDLE_SIZE_2                          2\r
-#define FAPI_REG_BUNDLE_SIZE_3                          3\r
-#define FAPI_REG_BUNDLE_SIZE_6                          6\r
-\r
-#define FAPI_INTERLEAVER_SIZE_2                         2\r
-#define FAPI_INTERLEAVER_SIZE_3                         3\r
-#define FAPI_INTERLEAVER_SIZE_6                         6\r
-\r
-#define FAPI_CORESET_TYPE_0_CONF_BY_PBCH_OR_SIB1        0\r
-#define FAPI_CORESET_TYPE_1                             1\r
-\r
-#define FAPI_PREC_GRANULARITY_SAME_AS_REG_BUNDLE        0\r
-#define FAPI_PREC_GRANULARITY_ALL_CONTIG_RBS            1\r
-\r
-#define FAPI_CCE_INDEX_MAX                              135\r
-#define FAPI_PDCCH_AGG_LEVEL_1                          1\r
-#define FAPI_PDCCH_AGG_LEVEL_2                          2\r
-#define FAPI_PDCCH_AGG_LEVEL_4                          4\r
-#define FAPI_PDCCH_AGG_LEVEL_8                          8\r
-#define FAPI_PDCCH_AGG_LEVEL_16                         16\r
-\r
-#define FAPI_BETA_PDCCH_1_0_MAX                         17\r
-\r
-#define FAPI_POWER_CTRL_OFF_SS_MINUS_3_DB               0\r
-#define FAPI_POWER_CTRL_OFF_SS_0_DB                     1\r
-#define FAPI_POWER_CTRL_OFF_SS_3_DB                     2\r
-#define FAPI_POWER_CTRL_OFF_SS_6_DB                     3\r
-\r
-#define FAPI_MAX_NUMBER_OF_CODEWORDS                    2\r
-\r
-#define FAPI_MAX_MCS_INDEX                              31\r
-#define FAPI_MCS_INDEX_MASK                             0x1f\r
-\r
-#define FAPI_MCS_TABLE_NOT_QAM_256                      0\r
-#define FAPI_MCS_TABLE_QAM_256                          1\r
-#define FAPI_MCS_TABLE_QAM_64_LOW_SE                    2\r
-\r
-#define FAPI_REDUNDANCY_INDEX_MASK                      0x03\r
-#define FAPI_MAX_DL_LAYERS                              8\r
-\r
-#define FAPI_TRANSMISSION_SCHEME_1                      1\r
-\r
-#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A           0\r
-#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC   1\r
-\r
-#define FAPI_DL_DMRS_SYMB_POS_MASK                      0x3fff\r
-\r
-#define FAPI_MAX_DMRS_CDM_GRPS_WO_DATA                  3\r
-\r
-#define FAPI_DMRS_PORTS_MASK                            0x0fff\r
-\r
-#define FAPI_RES_ALLOC_TYPE_0                           0\r
-#define FAPI_RES_ALLOC_TYPE_1                           1\r
-\r
-#define FAPI_VRB_TO_PRB_MAP_NON_INTERLVD                0\r
-#define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_2          1\r
-#define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_4          2\r
-\r
-#define FAPI_MAX_START_SYMBOL_INDEX                     13\r
-#define FAPI_MAX_NR_OF_SYMBOLS                          14\r
-#define FAPI_PTRS_PORT_INDEX_MASK                       0x3f\r
-#define FAPI_PTRS_TIME_DENSITY_1                        0\r
-#define FAPI_PTRS_TIME_DENSITY_2                        1\r
-#define FAPI_PTRS_TIME_DENSITY_4                        2\r
-#define FAPI_PTRS_FREQ_DENSITY_2                        0\r
-#define FAPI_PTRS_FREQ_DENSITY_4                        1\r
-#define FAPI_PTRS_RE_OFFSET_MASK                        0x03\r
-#define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK                 0x03\r
-// PDSCH Power Control Offset\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB                 0\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB                 1\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_6_DB                 2\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_5_DB                 3\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_4_DB                 4\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_3_DB                 5\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_2_DB                 6\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_1_DB                 7\r
-#define FAPI_PWR_CTRL_OFFSET_0_DB                       8\r
-#define FAPI_PWR_CTRL_OFFSET_1_DB                       9\r
-#define FAPI_PWR_CTRL_OFFSET_2_DB                       10\r
-#define FAPI_PWR_CTRL_OFFSET_3_DB                       11\r
-#define FAPI_PWR_CTRL_OFFSET_4_DB                       12\r
-#define FAPI_PWR_CTRL_OFFSET_5_DB                       13\r
-#define FAPI_PWR_CTRL_OFFSET_6_DB                       14\r
-#define FAPI_PWR_CTRL_OFFSET_7_DB                       15\r
-#define FAPI_PWR_CTRL_OFFSET_8_DB                       16\r
-#define FAPI_PWR_CTRL_OFFSET_9_DB                       17\r
-#define FAPI_PWR_CTRL_OFFSET_10_DB                      18\r
-#define FAPI_PWR_CTRL_OFFSET_11_DB                      19\r
-#define FAPI_PWR_CTRL_OFFSET_12_DB                      20\r
-#define FAPI_PWR_CTRL_OFFSET_13_DB                      21\r
-#define FAPI_PWR_CTRL_OFFSET_14_DB                      22\r
-#define FAPI_PWR_CTRL_OFFSET_15_DB                      23\r
-// Power Control Offset SS\r
-#define FAPI_PWR_CTRL_OFFSET_SS_MINUS_3_DB              0\r
-#define FAPI_PWR_CTRL_OFFSET_SS_0_DB                    1\r
-#define FAPI_PWR_CTRL_OFFSET_SS_3_DB                    2\r
-#define FAPI_PWR_CTRL_OFFSET_SS_6_DB                    3\r
-// CSI Type\r
-#define FAPI_CSI_TRS                                    0\r
-#define FAPI_CSI_NON_ZERO_POWER                         1\r
-#define FAPI_CSI_ZERO_POWER                             2\r
-// Row entry into CSI Resource Location Table\r
-#define FAPI_CSIRLT_ROW_MAX_VALUE                       18\r
-#define FAPI_CSI_FREQ_DOMAIN_MASK                       0x0fff\r
-#define FAPI_CSI_SYMB_L1_MIN                            2\r
-#define FAPI_CSI_SYMB_L1_MAX                            12\r
-// CDM Type\r
-#define FAPI_CDM_TYPE_NO_CDM                            0\r
-#define FAPI_CDM_TYPE_FD_CDM                            1\r
-#define FAPI_CDM_TYPE_CDM4_FD2_TD2                      2\r
-#define FAPI_CDM_TYPE_CDM8_FD2_TD4                      3\r
-// Frequency Density\r
-#define FAPI_FD_DOT5_EVEN_RB                            0\r
-#define FAPI_FD_DOT5_ODD_RB                             1\r
-#define FAPI_FD_ONE                                     2\r
-#define FAPI_FD_THREE                                   3\r
-\r
-// SSB\r
-#define FAPI_SSB_BLOCK_INDEX_MASK                       0x3f\r
-#define FAPI_SSB_SC_OFFSET_MASK                         0x1f\r
-\r
-// UL TTI REQUEST\r
-#define FAPI_MAX_NUM_UE_GROUPS_INCLUDED                 8\r
-#define FAPI__MAX_NUM_UE_IN_GROUP                       6\r
-// PRACH PDU\r
-#define FAPI_MAX_NUM_PRACH_OCAS                         7\r
-// PRACH FORMAT\r
-#define FAPI_PRACH_FORMAT_A1                            0\r
-#define FAPI_PRACH_FORMAT_A2                            1\r
-#define FAPI_PRACH_FORMAT_A3                            2\r
-#define FAPI_PRACH_FORMAT_B1                            3\r
-#define FAPI_PRACH_FORMAT_B2                            4\r
-#define FAPI_PRACH_FORMAT_B3                            5\r
-#define FAPI_PRACH_FORMAT_B4                            6\r
-#define FAPI_PRACH_FORMAT_C0                            7\r
-#define FAPI_PRACH_FORMAT_C2                            8\r
-\r
-#define FAPI_MAX_PRACH_FD_OCCASION_INDEX                7\r
-#define FAPI_MAX_ZC_ZONE_CONFIG_NUMBER                  419\r
-\r
-// PUSCH PDU\r
-#define FAPI_PUSCH_BIT_DATA_PRESENT_MASK                0x0001\r
-#define FAPI_PUSCH_UCI_DATA_PRESENT_MASK                0x0002\r
-#define FAPI_PUSCH_PTRS_INCLUDED_FR2_MASK               0x0004\r
-#define FAPI_PUSCH_DFTS_OFDM_TX_MASK                    0x0008\r
-\r
-#define FAPI_MAX_QAM_MOD_ORDER                          8\r
-#define FAPI_MCS_INDEX_MASK                             0x1f\r
-\r
-#define FAPI_MCS_TABLE_NOT_QAM256                       0\r
-#define FAPI_MCS_TABLE_QAM256                           1\r
-#define FAPI_MCS_TABLE_QAM64_LOWSE                      2\r
-#define FAPI_MCS_TABLE_NOT_QAM256_W_XFRM_PRECOD         3\r
-#define FAPI_MCS_TABLE_QAM64_LOWSE_W_XFRM_PRECOD        4\r
-#define FAPI_PUSCH_MAX_NUM_LAYERS                       4\r
-// DMRS\r
-#define FAPI_UL_DMRS_SYMB_POS_MASK                      0x3fff\r
-#define FAPI_UL_DMRS_CONFIG_TYPE_1                      0\r
-#define FAPI_UL_DMRS_CONFIG_TYPE_2                      1\r
-#define FAPI_MAX_DMRS_CDM_GRPS_NO_DATA                  3\r
-#define FAPI_UL_DMRS_PORTS_MASK                         0x07ff\r
-#define FAPI_UL_TX_DIRECT_CURR_LOCATION_MAX             3299\r
-#define FAPI_UL_TX_DIRECT_CURR_LOC_OUTSIDE_CARRIER      3300\r
-#define FAPI_UL_TX_DIRECT_CURR_LOC_UNDETERMINED         3301\r
-// PUSCH DATA\r
-#define FAPI_RV_INDEX_MASK                              0x03\r
-#define FAPI_HARQ_PROCESS_ID_MASK                       0x0f\r
-// PUSCH UCI INFO\r
-#define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_SMALL_BLOCK_MAX    11\r
-#define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_POLAR_MAX          1706\r
-// ALPHA SCALING\r
-#define FAPI_ALPHA_SCALE_0_5                            0\r
-#define FAPI_ALPHA_SCALE_0_65                           1\r
-#define FAPI_ALPHA_SCALE_0_8                            2\r
-#define FAPI_ALPHA_SCALE_1_0                            3\r
-// BETA OFFSET HARQ ACK\r
-#define FAPI_BETA_OFFSET_HARQ_ACK_MAX                   15\r
-#define FAPI_BETA_OFFSET_CSIX_MAX                       18\r
-\r
-// PUSCH PTRS INFORMATION 38.212 Section 7.3.1.1.2\r
-#define FAPI_MAX_NUMBER_PTRS_PORT_INDEX                 11  // 0..11\r
-// UL PTRS POWER 5G FAPI Table 3-49\r
-#define FAPI_UL_PTRS_PWR_0_DB                           0\r
-#define FAPI_UL_PTRS_PWR_3_DB                           1\r
-#define FAPI_UL_PTRS_PWR_4_77_DB                        2\r
-#define FAPI_UL_PTRS_PWR_6_DB                           3\r
-// DFTSOFDM INFO 5g FAPI Table 3-50\r
-#define FAPI_MAX_LOW_PAPR_GROUP_NUMBER                  29  // 0..29\r
-#define FAPI_MAX_LOW_PAPR_SEQ_NUMBER                    87  // 3*LOW_PAPR_GRP_NUM\r
-#define FAPI_MAX_UL PTRS_SAMP_DENSITY                   8\r
-#define FAPI_MAX_UL_PTRS_TD_XFRM_PRECOD                 4\r
-\r
-// PUCCH PDU Table 3-51\r
-#define FAPI_MAX_PUCCH_FORMAT_TYPE                      4\r
-#define FAPI_MULTI_SLOT_TX_IND_NO_MULTI_SLOT            0\r
-#define FAPI_MULTI_SLOT_TX_IND_TX_START                 1\r
-#define FAPI_MULTI_SLOT_TX_IND_TX_CONT                  2\r
-#define FAPI_MULTI_SLOT_TX_IND_TX_END                   3\r
-#define FAPI_MAX_NUM_PRB_FOR_A_PUCCH                    16\r
-#define FAPI_MAX_PUCCH_DUR_F0_AND_F2                    2\r
-#define FAPI_MIN_PUCCH_DUR_F1_F3_F4                     4\r
-#define FAPI_MAX_PUCCH_DUR_F1_F3_F4                     14\r
-#define FAPI_MAX_INIT_CYCLIC_SHIFT_F0_F1_F3_F4          11\r
-#define FAPI_MAX_OCC_INDEX_F1                           6\r
-#define FAPI_MAX_PRE_DFT_OCC_IDX_F4                     3\r
-#define FAPI_MAX_PRE_DFT_OCC_LEN_F4                     4\r
-#define FAPI_MAX_DMRS_CYC_SHIFT_F4                      9\r
-#define FAPI_BIT_LEN_HARQ_PL_ZERO                       0\r
-#define FAPI_BIT_LEN_HARQ_PL_F0_F1_2_BITS               1\r
-#define FAPI_BIT_LEN_HARQ_PL_F2_F3_F4_1706_BITS         2\r
-#define FAPI_BIT_LEN_CSI_PX_PL_NO_CSI                   0\r
-#define FAPI_BIT_LEN_CSI_PX_PL_1706_BITS                1\r
-\r
-// SRS PDU\r
-#define FAPI_1_SRS_ANT_PORT                             0\r
-#define FAPI_2_SRS_ANT_PORTS                            1\r
-#define FAPI_4_SRS_ANT_PORTS                            2\r
-#define FAPI_SRS_NO_REPETITIONS                         0\r
-#define FAPI_SRS_2_REPETITIONS                          2\r
-#define FAPI_SRS_4_REPETITIONS                          4\r
-#define FAPI_SRS_CONFIG_INDEX_MASK                      0x3f\r
-#define FAPI_SRS_BW_INDEX_MASK                          0x03\r
-#define FAPI_TX_COMB_SIZE_2                             0\r
-#define FAPI_TX_COMB_SIZE_4                             1\r
-#define FAPI_MAX_SRS_FREQ_POSITION                      67\r
-#define FAPI_MAX_SRS_FD_SHIFT                           268\r
-#define FAPI_SRS_FREQ_HOPPING_MASK                      0x03\r
-#define FAPI_SRS_NO_HOPPING                             0\r
-#define FAPI_SRS_GRP_OR_SEQ_HOPPING                     1\r
-#define FAPI_SRS_SEQ_HOPPING                            2\r
-#define FAPI_SRS_RES_ALLOC_APERIODIC                    0\r
-#define FAPI_SRS_RES_ALLOC_SEMI_PERSISTENT              1\r
-#define FAPI_SRS_RES_ALLOC_PERIODIC                     2\r
-#define FAPI_MAX_LSOT_OFFSET_VALUE                      2559\r
-\r
-// RX_DATA Indication\r
-#define FAPI_UL_CQI_INVALID                             255\r
-#define FAPI_TIMING_ADVANCE_INVALID                     0xffff\r
-#define FAPI_MAX_TIMING_ADVANCE                         63\r
-#define FAPI_MAX_RSSI                                   1280\r
-\r
-\r
-// RACH Indication\r
-#define FAPI_RACH_FREQ_INDEX_MAX                        7\r
-#define FAPI_RACH_DETECTED_PREAMBLES_MASK               0x3f\r
-#define FAPI_RACH_TIMING_ADVANCE_MAX                    3846\r
-#define FAPI_RACH_PREAMBLE_POWER_INVALID                0xffffffff\r
-#define FAPI_RACH_PREAMBLE_TIMING_ADVANCE_INVALID       0xffff\r
-#define FAPI_RACH_PREAMBLE_POWER_MAX                    170000\r
-\r
-// SR, HARQ, and CSI Part 1/2 PDUs Table 3-66\r
-#define FAPI_SR_MASK                                    0x01\r
-#define FAPI_HARQ_MASK                                  0x02\r
-#define FAPI_CSI_PART1                                  0x04\r
-#define FAPI_CSI_PART2                                  0x08\r
-#define FAPI_PUCCH_FORMAT2                              0\r
-#define FAPI_PUCCH_FORMAT3                              1\r
-#define FAPI_PUCCH_FORMAT4                              2\r
-#define FAPI_PUCCH_FORMAT_MASK                          0x03\r
-\r
-// SR PDU For Format 0 or 1 Table 3-67\r
-#define FAPI_SR_CONFIDENCE_LEVEL_GOOD                   0\r
-#define FAPI_SR_CONFIDENCE_LEVEL_BAD                    1\r
-#define FAPI_SR_CONFIDENCE_LEVEL_INVALID                0xff\r
-\r
-// HARQ PDU for Format 0 or 1 Table 3-68\r
-#define FAPI_HARQ_VALUE_PASS                            0\r
-#define FAPI_HARQ_VALUE_FAIL                            1\r
-#define FAPI_HARQ_VALUE_NOT_PRESENT                     2\r
-\r
-// SR PDU for Format 2,3 or 4 Table 3-69\r
-#define FAPI_SR_PAYLOAD_MAX                             1\r
-\r
-// HARQ PDU for Format 2,3 or 4 Table 3-70\r
-#define FAPI_HARQ_CRC_PASS                              0\r
-#define FAPI_HARQ_CRC_FAIL                              1\r
-#define FAPI_HARQ_CRC_NOT_PRESENT                       2\r
-#define FAPI_HARQ_PAYLOAD_MAX                           214\r
-\r
-\r
-// CSI Part 1 PDU Table 3-71 and 3-72\r
-#define FAPI_CSI_PARTX_CRC_PASS                         0\r
-#define FAPI_CSI_PARTX_CRC_FAIL                         1\r
-#define FAPI_CSI_PARTX_CRC_NOT_PRESENT                  2\r
-#define FAPI_CSI_PARTX_PAYLOAD_MAX                      214\r
-\r
-#if 0\r
-//------------------------------------------------------------------------------\r
-// FAPI callback functions to be implemented by the user\r
-//------------------------------------------------------------------------------\r
-/**\r
- *  fapi callback structure is passed as part of ``fapi_create``. FAPI will call\r
- *  these functions in response to any received request message.\r
- *\r
- *  *Note: vendor specific callbacks are only valid in TIMER_MODE. Must be set\r
- *  to NULL in RADIO mode.*\r
- */\r
-typedef struct {\r
-    void  (*fapi_param_response)   (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiParamResp_t    resp);\r
-    void  (*fapi_config_response)  (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiConfigResp_t   resp);\r
-    void  (*fapi_stop_ind)         (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiStopInd_t      resp);\r
-    void  (*fapi_error_ind)        (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiErrorInd_t     ind);\r
-    void  (*fapi_subframe_ind)     (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiSubframeInd_t  ind);\r
-    void  (*fapi_harq_ind)         (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiHarqInd_t      ind);\r
-    void  (*fapi_crc_ind)          (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiCrcInd_t       ind);\r
-    void  (*fapi_rx_ulsch_ind)     (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiRxUlschInd_t   ind);\r
-    void  (*fapi_rx_cqi_ind)       (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiRxCqiInd_t     ind);\r
-    void  (*fapi_rx_sr_ind)        (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiRxSrInd_t      ind);\r
-    void  (*fapi_rach_ind)         (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiRachInd_t      ind);\r
-    void  (*fapi_srs_ind)          (fapiInstanceHdl_t  fapiHdl,\r
-                                        pfapiSrsInd_t       ind);\r
-//------------------------------------------------------------------------------\r
-// Vendor Specific Callbacks\r
-//------------------------------------------------------------------------------\r
-    void  (*fapi_rip_measurement)       (fapiInstanceHdl_t  fapiHdl,\r
-                                            pfapiMeasReport_t   pMeasReport);\r
-    void  (*fapi_start_phy_shutdown)    (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-    void  (*fapi_shutdown_resp)         (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-    void  (*fapi_start_cnf)             (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-    void  (*fapi_ul_iq_samples)         (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-    void  (*fapi_dl_iq_samples)         (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-    void  (*fapi_ul_copy_results_ind)   (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-\r
-    void  (*fapi_endof_phy2mac_processing)    (fapiInstanceHdl_t  fapiHdl,\r
-                                            void           *pMsgInd);\r
-} fapiCb_t, *pfapiCb_t;\r
-\r
-//------------------------------------------------------------------------------\r
-\r
-fapiStatus_t      fapi_init(pfapiInitConfig_t pinitConfig);\r
-fapiStatus_t      fapi_destroy(void);\r
-fapiInstanceHdl_t fapi_create(pfapiCb_t callbacks,\r
-                      pfapiCreateConfig_t pCreateConfig);\r
-fapiStatus_t      fapi_delete(fapiInstanceHdl_t fapiHdl);\r
-\r
-//------------------------------------------------------------------------------\r
-// Fapi P5 Messages\r
-//------------------------------------------------------------------------------\r
-fapiStatus_t    fapi_param_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiParamReq_t req);\r
-fapiStatus_t    fapi_config_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiConfigReq_t req);\r
-fapiStatus_t    fapi_start_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiStartReq_t req);\r
-fapiStatus_t    fapi_stop_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiStopReq_t req);\r
-//------------------------------------------------------------------------------\r
-// Fapi P7 Messages\r
-//------------------------------------------------------------------------------\r
-fapiStatus_t    fapi_dl_config_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiDlConfigReq_t req);\r
-fapiStatus_t    fapi_ul_config_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiUlConfigReq_t req);\r
-fapiStatus_t    fapi_hi_dci0_request(fapiInstanceHdl_t fapiHdl,\r
-                      pfapiHiDci0Req_t req);\r
-fapiStatus_t    fapi_tx_request(fapiInstanceHdl_t fapiHdl, pfapiTxReq_t\r
-                      req);\r
-#endif\r
-#endif //_FAPI_H_\r
-\r
+/******************************************************************************
+*   Copyright (c) 2019 Intel.
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*******************************************************************************/
+/**
+ * @file
+ * This file consist of FAPI configuration APIs macros, structure typedefs and
+ * prototypes.
+ *
+ **/
+
+#ifndef _NR5G_FAPI_INTELNAL_H_
+#define _NR5G_FAPI_INTELNAL_H_
+
+#include "fapi_interface.h"
+#include "nr5g_fapi_common_types.h"
+
+#define  MAX_UL_SLOT_INFO_COUNT                      20 //Maximum no of Slots for which UL_TTI.request info has to
+#define  MAX_UL_SYMBOL_INFO_COUNT                    FAPI_MAX_NR_OF_SYMBOLS
+//Maximum no of symbols which may be configured with separate UL_TTI.request (URLLC)
+#define  FAPI_MAX_NUM_PUSCH_PDU                     255 //as per Table 3-44
+#define  FAPI_MAX_NUM_PUCCH_PDU                     255 //as per Table 3-44
+#define  FAPI_MAX_NUM_SRS_PDU                       255 //as per Table 3-73
+#define  FAPI_MAX_NUM_RACH_PDU                      255 //as per Table 3-74
+#define  FAPI_MAX_PHY_INSTANCES                      24
+#define  FAPI_MAX_SLOT_INFO_URLLC                     2
+
+// CONFIGURATION INFORMATION CARRIER CONFIGURATION BANDWIDTH
+#define FAPI_BANDWIDTH_5_MHZ                          5
+#define FAPI_BANDWIDTH_10_MHZ                        10
+#define FAPI_BANDWIDTH_15_MHZ                        15
+#define FAPI_BANDWIDTH_20_MHZ                        20
+#define FAPI_BANDWIDTH_25_MHZ                        25
+#define FAPI_BANDWIDTH_30_MHZ                        30
+#define FAPI_BANDWIDTH_40_MHZ                        40
+#define FAPI_BANDWIDTH_50_MHZ                        50
+#define FAPI_BANDWIDTH_60_MHZ                        60
+#define FAPI_BANDWIDTH_70_MHZ                        70
+#define FAPI_BANDWIDTH_80_MHZ                        80
+#define FAPI_BANDWIDTH_90_MHZ                        90
+#define FAPI_BANDWIDTH_100_MHZ                      100
+#define FAPI_BANDWIDTH_200_MHZ                      200
+#define FAPI_BANDWIDTH_400_MHZ                      400
+
+#define FAPI_SUBCARRIER_SPACING_15                  0
+#define FAPI_SUBCARRIER_SPACING_30                  1
+#define FAPI_SUBCARRIER_SPACING_60                  2
+#define FAPI_SUBCARRIER_SPACING_120                 3
+
+#define FAPI_FFT_SIZE_512                          512
+#define FAPI_FFT_SIZE_1024                         1024
+#define FAPI_FFT_SIZE_2048                         2048
+#define FAPI_FFT_SIZE_4096                         4096
+
+#define FAPI_MAX_DL_LAYERS                              MAX_NUM_DL_LAYERS
+#define FAPI_MAX_UL_LAYERS                              4
+// FAPI Supports MAX 12; Mapping to Intel Phys capabilities
+#define FAPI_MAX_DMRS_PORTS                             MAX_DL_PER_UE_DMRS_PORT_NUM
+// FAPI Supports MAX 12; Mapping to Intel Phys capabilities
+#define FAPI_MAX_PTRS_PORTS                             MAX_DL_PER_UE_PTRS_PORT_NUM
+
+// FAPI States
+/**
+ * FAPI state is maintained per fapi instance. If FAPI messages are received in
+ * wrong state an ERROR.indication message will be sent by FAPI.
+ */
+typedef enum _fapi_states {
+    FAPI_STATE_IDLE = 0,
+    FAPI_STATE_CONFIGURED,
+    FAPI_STATE_RUNNING
+} fapi_states_t;
+
+typedef enum {
+    FAPI_PUCCH_FORMAT_TYPE_0 = 0,
+    FAPI_PUCCH_FORMAT_TYPE_1,
+    FAPI_PUCCH_FORMAT_TYPE_2,
+    FAPI_PUCCH_FORMAT_TYPE_3,
+    FAPI_PUCCH_FORMAT_TYPE_4,
+} nr5g_fapi_uci_format_t;
+
+typedef struct {
+    uint8_t group_id;
+    uint16_t initial_cyclic_shift;
+    uint8_t nr_of_symbols;
+    uint8_t start_symbol_index;
+    uint8_t time_domain_occ_idx;
+} nr5g_fapi_pucch_resources_t;
+
+
+typedef enum {
+    MEM_STAT_CONFIG_REQ = 0,
+    MEM_STAT_START_REQ,
+    MEM_STAT_STOP_REQ,
+    MEM_STAT_SHUTDOWN_REQ,
+    MEM_STAT_DL_CONFIG_REQ,
+    MEM_STAT_UL_CONFIG_REQ,
+    MEM_STAT_UL_DCI_REQ,
+    MEM_STAT_TX_REQ,
+    MEM_STAT_DL_IQ_SAMPLES,
+    MEM_STAT_UL_IQ_SAMPLES,
+    MEM_STAT_DEFAULT,
+} _mem_stats_for_dl;
+
+//Unused definitions
+#define RELEASE_15 0x0001
+
+#define FAPI_NORMAL_CYCLIC_PREFIX_MASK              0x01
+#define FAPI_EXTENDED_CYCLIC_PREFIX_MASK            0x02
+
+// PDCCH Information
+#define FAPI_CCE_MAPPING_INTERLEAVED_MASK           0x01
+#define FAPI_CCE_MAPPING_NONINTERLVD_MASK           0x02
+// Upper Bound for PDCCH Channels per Slot
+#define FAPI_MAX_PDCCHS_PER_SLOT_MASK               0xff
+
+// PUCCH Information
+#define FAPI_FORMAT_0_MASK                          0x01
+#define FAPI_FORMAT_1_MASK                          0x02
+#define FAPI_FORMAT_2_MASK                          0x04
+#define FAPI_FORMAT_3_MASK                          0x08
+#define FAPI_FORMAT_4_MASK                          0x10
+// Upper Bound for PUCCH Channels per Slot
+#define FAPI_MAX_PUCCHS_PER_SLOT_MASK               0xff
+
+// PDSCH Information
+#define FAPI_PDSCH_MAPPING_TYPE_A_MASK              0x01
+#define FAPI_PDSCH_MAPPING_TYPE_B_MASK              0x02
+#define FAPI_PDSCH_ALLOC_TYPE_0_MASK                0x01
+#define FAPI_PDSCH_ALLOC_TYPE_1_MASK                0x02
+#define FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK    0x01
+#define FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK       0x02
+#define FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK          0x01
+#define FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK          0x02
+#define FAPI_PDSCH_DMRS_MAX_LENGTH_1                0
+#define FAPI_PDSCH_DMRS_MAX_LENGTH_2                1
+#define FAPI_DMRS_ADDITIONAL_POS_0_MASK             0x01
+#define FAPI_DMRS_ADDITIONAL_POS_1_MASK             0x02
+#define FAPI_DMRS_ADDITIONAL_POS_2_MASK             0x04
+#define FAPI_DMRS_ADDITIONAL_POS_3_MASK             0x08
+// Upper Limit for PDSCHS TBs per Slot
+#define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK           0xff
+#define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH            2
+
+// Subcarrier spacing information
+#define FAPI_15KHZ_MASK                             0x01
+#define FAPI_30KHZ_MASK                             0x02
+#define FAPI_60KHZ_MASK                             0x04
+#define FAPI_120KHZ_MASK                            0x08
+
+// Bandwitdth information
+#define FAPI_5MHZ_BW_MASK                           0x0001
+#define FAPI_10MHZ_BW_MASK                          0x0002
+#define FAPI_15MHZ_BW_MASK                          0x0004
+#define FAPI_20MHZ_BW_MASK                          0x0010
+#define FAPI_40MHZ_BW_MASK                          0x0020
+#define FAPI_50MHZ_BW_MASK                          0x0040
+#define FAPI_60MHZ_BW_MASK                          0x0080
+#define FAPI_70MHZ_BW_MASK                          0x0100
+#define FAPI_80MHZ_BW_MASK                          0x0200
+#define FAPI_90MHZ_BW_MASK                          0x0400
+#define FAPI_100MHZ_BW_MASK                         0x0800
+#define FAPI_200MHZ_BW_MASK                         0x1000
+#define FAPI_400MHZ_BW_MASK                         0x2000
+
+#define FAPI_MAX_MUMIMO_USERS_MASK                  0xff
+
+// PUSCH Parameters
+#define FAPI_PUSCH_MAPPING_TYPE_A_MASK              0x01
+#define FAPI_PUSCH_MAPPING_TYPE_B_MASK              0x02
+#define FAPI_PUSCH_ALLOC_TYPE_0_MASK                0x01
+#define FAPI_PUSCH_ALLOC_TYPE_1_MASK                0x02
+#define FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK    0x01
+#define FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK       0x02
+#define FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK          0x01
+#define FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK          0x02
+#define FAPI_PUSCH_DMRS_MAX_LENGTH_1                0
+#define FAPI_PUSCH_DMRS_MAX_LENGTH_2                1
+// Upper limit for PUSCHMAXPTRSPORTS
+#define FAPI_PUSCH_MAX_PTRS_PORTS_UB                2
+//Upper Limit for PDSCHS TBs per Slot
+#define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK           0xff
+
+// PRACH Parameters
+#define FAPI_PRACH_LF_FORMAT_0_MASK                 0x01
+#define FAPI_PRACH_LF_FORMAT_1_MASK                 0x02
+#define FAPI_PRACH_LF_FORMAT_2_MASK                 0x04
+#define FAPI_PRACH_LF_FORMAT_3_MASK                 0x08
+
+#define FAPI_PRACH_SF_FORMAT_A1_MASK                0x01
+#define FAPI_PRACH_SF_FORMAT_A2_MASK                0x02
+#define FAPI_PRACH_SF_FORMAT_A3_MASK                0x04
+#define FAPI_PRACH_SF_FORMAT_B1_MASK                0x08
+#define FAPI_PRACH_SF_FORMAT_B2_MASK                0x10
+#define FAPI_PRACH_SF_FORMAT_B3_MASK                0x20
+#define FAPI_PRACH_SF_FORMAT_B4_MASK                0x40
+#define FAPI_PRACH_SF_FORMAT_C0_MASK                0x80
+#define FAPI_PRACH_SF_FORMAT_C2_MASK                0x100
+
+// Measurement Parameters
+#define FAPI_RSSI_REPORT_IN_DBM_MASK                0x01
+#define FAPI_RSSI_REPORT_IN_DBFS_MASK               0x02
+
+// Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1
+// Lower Bound KHz
+#define FAPI_MIN_FREQUENCY_PT_A                     450000
+// Upper Bound KHz
+#define FAPI_MAX_FREQUENCY_PT_A                     52600000
+// dlk0, ulk0 per 38.211 Section 5.3.1
+// Upper Bound
+#define FAPI_K0_MAX                                 23699
+// dlGridSize, ulGridSize per 38.211 Section 4.4.2
+// Upper Bound
+#define FAPI_GRIDSIZE_MAX                           275
+// Number of Transmit Antennas
+// Define upper mask based on variable type
+#define FAPI_NUM_ANT_MASK                           0xffff
+// CELL CONFIGURATION
+// Physical Cell ID from 38.211 Section 7.4.2.1
+// Upper Bound
+#define FAPI_MAX_CELL_ID                            1007
+// SSB CONFIGURATION
+// SSB POWER RANGE in dBm
+#define FAPI_SS_PBCH_LOWEST_POWER                   -60
+#define FAPI_SS_PBCH_MAX_POWER                      50
+// BCH PAYLOAD  for 5G the MAC always generates the BCH Payload
+#define FAPI_BCH_PAYLOAD_GEN_BY_MAC                 0
+#define FAPI_BCH_PAYLOAD_WITH_PHY_GEN_TIMING        1
+#define FAPI_BCH_PAYLOAD_ENTIRELY_GEN_BY_PHY        2
+// ScsCommon
+#define FAPI_SCSCOMMON_MASK                         0x03
+// PRACH CONFIGURATION
+#define FAPI_PRACH_LONG_SEQUENCE                    0
+#define FAPI_PRACH_SHORT_SEQUENCE                   1
+#define FAPI_PRACH_SUBC_SPACING_MAX                 4
+// Restricted Set Configuration
+#define FAPI_PRACH_RESTRICTED_SET_UNRESTRICTED      0
+#define FAPI_PRACH_RESTRICTED_SET_TYPE_A            1
+#define FAPI_PRACH_RESTRICTED_SET_TYPE_B            2
+// Root Sequence Index
+// Upper Bound
+#define FAPI_PRACH_ROOT_SEQ_INDEX_MAX               837
+// k1
+// Upper Bound
+#define FAPI_K1_UPPER_BOUND                         272
+// PRACH Zero Corr Configuration
+// Upper Bound
+#define FAPI_PRACHZEROCORRCONF_MASK                 0x0f
+// Number of Unused Root Sequences Mask
+#define FAPI_UNUSEDROOTSEQUENCES_MASK               0x0f
+// SSB
+#define FAPI_SSB_SUB6_THRESHOLD                  6000000
+// Ssb Offset Point A max
+#define FAPI_SSB_OFFSET_POINTA_MAX                  2199
+// betaPSS  i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1
+#define FAPI_BETAPSS_0_DB                           0
+#define FAPI_BETAPSS_3_DB                           1
+// SSB Period in ms
+#define FAPI_SSB_PERIOD_5_MS                        0
+#define FAPI_SSB_PERIOD_10_MS                       1
+#define FAPI_SSB_PERIOD_20_MS                       2
+#define FAPI_SSB_PERIOD_40_MS                       3
+#define FAPI_SSB_PERIOD_80_MS                       4
+#define FAPI_SSB_PERIOD_160_MS                      5
+// Ssb Subcarrier Offset    per 38.211 Section 7.4.3.1
+// SsbSubcarrierOffset mask
+#define FAPI_SSB_SUBCARRIER_OFFSET_MASK             0x1f
+// MIB PAYLOAD MASK
+#define MIB_PAYLOAD_MASK                            0xfff0
+// BEAM ID MASK
+#define FAPI_BEAM_ID_MASK                           0x3f
+// TDD Table
+// TDD Period
+#define FAPI_TDD_PERIOD_0_P_5_MS                        0
+#define FAPI_TDD_PERIOD_0_P_625_MS                      1
+#define FAPI_TDD_PERIOD_1_MS                            2
+#define FAPI_TDD_PERIOD_1_P_25_MS                       3
+#define FAPI_TDD_PERIOD_2_MS                            4
+#define FAPI_TDD_PERIOD_2_P_5_MS                        5
+#define FAPI_TDD_PERIOD_5_MS                            6
+#define FAPI_TDD_PERIOD_10_MS                           7
+// Slot Configuration
+#define FAPI_DL_SLOT                                    0
+#define FAPI_UL_SLOT                                    1
+#define FAPI_GUARD_SLOT                                 2
+// Measurement configuration
+#define FAPI_NO_RSSI_REPORTING                          0
+#define FAPI_RSSI_REPORTED_IN_DBM                       1
+#define FAPI_RSSI_REPORTED_IN_DBFS                      2
+// Error Indication
+#define FAPI_SFN_MASK                                   0x03ff
+ // Slot Indication
+#define FAPI_SLOT_MAX_VALUE                            159
+
+#define FAPI_U16_MASK                                  0xffff
+#define FAPI_U8_MASK                                   0xff
+// Define Maximum number of Ues per Group
+#define FAPI_MAX_NUMBER_OF_UES_PER_GROUP                12
+
+// PDCCH PDU
+#define FAPI_BWPSIZE_MAX                                275
+#define FAPI_BWPSIZE_START_MAX                          274
+#define FAPI_SUBCARRIER_SPACING_MAX                     4
+#define FAPI_CYCLIC_PREFIX_NORMAL                       0
+#define FAPI_CYCLIC_PREFIX_EXTENDED                     1
+#define FAPI_MAX_SYMBOL_START_INDEX                     13
+
+#define FAPI_CORESET_DURATION_1_SYMBOL                  1
+#define FAPI_CORESET_DURATION_2_SYMBOLS                 2
+#define FAPI_CORESET_DURATION_3_SYMBOLS                 3
+
+#define FAPI_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED       0
+#define FAPI_CCE_REG_MAPPING_TYPE_INTERLEAVED           1
+#define FAPI_REG_BUNDLE_SIZE_2                          2
+#define FAPI_REG_BUNDLE_SIZE_3                          3
+#define FAPI_REG_BUNDLE_SIZE_6                          6
+
+#define FAPI_INTERLEAVER_SIZE_2                         2
+#define FAPI_INTERLEAVER_SIZE_3                         3
+#define FAPI_INTERLEAVER_SIZE_6                         6
+
+#define FAPI_CORESET_TYPE_0_CONF_BY_PBCH_OR_SIB1        0
+#define FAPI_CORESET_TYPE_1                             1
+
+#define FAPI_PREC_GRANULARITY_SAME_AS_REG_BUNDLE        0
+#define FAPI_PREC_GRANULARITY_ALL_CONTIG_RBS            1
+
+#define FAPI_CCE_INDEX_MAX                              135
+#define FAPI_PDCCH_AGG_LEVEL_1                          1
+#define FAPI_PDCCH_AGG_LEVEL_2                          2
+#define FAPI_PDCCH_AGG_LEVEL_4                          4
+#define FAPI_PDCCH_AGG_LEVEL_8                          8
+#define FAPI_PDCCH_AGG_LEVEL_16                         16
+
+#define FAPI_BETA_PDCCH_1_0_MAX                         17
+
+#define FAPI_POWER_CTRL_OFF_SS_MINUS_3_DB               0
+#define FAPI_POWER_CTRL_OFF_SS_0_DB                     1
+#define FAPI_POWER_CTRL_OFF_SS_3_DB                     2
+#define FAPI_POWER_CTRL_OFF_SS_6_DB                     3
+
+#define FAPI_MAX_NUMBER_OF_CODEWORDS                    2
+
+#define FAPI_MAX_MCS_INDEX                              31
+#define FAPI_MCS_INDEX_MASK                             0x1f
+
+#define FAPI_MCS_TABLE_NOT_QAM_256                      0
+#define FAPI_MCS_TABLE_QAM_256                          1
+#define FAPI_MCS_TABLE_QAM_64_LOW_SE                    2
+
+#define FAPI_REDUNDANCY_INDEX_MASK                      0x03
+
+#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A           0
+#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC   1
+
+#define FAPI_DL_DMRS_SYMB_POS_MASK                      0x3fff
+
+#define FAPI_MAX_DMRS_CDM_GRPS_WO_DATA                  3
+
+#define FAPI_DMRS_PORTS_MASK                            0x0fff
+
+#define FAPI_RES_ALLOC_TYPE_0                           0
+#define FAPI_RES_ALLOC_TYPE_1                           1
+
+#define FAPI_VRB_TO_PRB_MAP_NON_INTERLVD                0
+#define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_2          1
+#define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_4          2
+
+#define FAPI_MAX_START_SYMBOL_INDEX                     13
+#define FAPI_MAX_NR_OF_SYMBOLS                          14
+#define FAPI_PTRS_PORT_INDEX_MASK                       0x3f
+#define FAPI_PTRS_TIME_DENSITY_1                        0
+#define FAPI_PTRS_TIME_DENSITY_2                        1
+#define FAPI_PTRS_TIME_DENSITY_4                        2
+#define FAPI_PTRS_FREQ_DENSITY_2                        0
+#define FAPI_PTRS_FREQ_DENSITY_4                        1
+#define FAPI_PTRS_RE_OFFSET_MASK                        0x03
+#define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK                 0x03
+
+// PDSCH Power Control Offset
+#define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB                 0
+#define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB                 1
+#define FAPI_PWR_CTRL_OFFSET_MINUS_6_DB                 2
+#define FAPI_PWR_CTRL_OFFSET_MINUS_5_DB                 3
+#define FAPI_PWR_CTRL_OFFSET_MINUS_4_DB                 4
+#define FAPI_PWR_CTRL_OFFSET_MINUS_3_DB                 5
+#define FAPI_PWR_CTRL_OFFSET_MINUS_2_DB                 6
+#define FAPI_PWR_CTRL_OFFSET_MINUS_1_DB                 7
+#define FAPI_PWR_CTRL_OFFSET_0_DB                       8
+#define FAPI_PWR_CTRL_OFFSET_1_DB                       9
+#define FAPI_PWR_CTRL_OFFSET_2_DB                       10
+#define FAPI_PWR_CTRL_OFFSET_3_DB                       11
+#define FAPI_PWR_CTRL_OFFSET_4_DB                       12
+#define FAPI_PWR_CTRL_OFFSET_5_DB                       13
+#define FAPI_PWR_CTRL_OFFSET_6_DB                       14
+#define FAPI_PWR_CTRL_OFFSET_7_DB                       15
+#define FAPI_PWR_CTRL_OFFSET_8_DB                       16
+#define FAPI_PWR_CTRL_OFFSET_9_DB                       17
+#define FAPI_PWR_CTRL_OFFSET_10_DB                      18
+#define FAPI_PWR_CTRL_OFFSET_11_DB                      19
+#define FAPI_PWR_CTRL_OFFSET_12_DB                      20
+#define FAPI_PWR_CTRL_OFFSET_13_DB                      21
+#define FAPI_PWR_CTRL_OFFSET_14_DB                      22
+#define FAPI_PWR_CTRL_OFFSET_15_DB                      23
+// Power Control Offset SS
+#define FAPI_PWR_CTRL_OFFSET_SS_MINUS_3_DB              0
+#define FAPI_PWR_CTRL_OFFSET_SS_0_DB                    1
+#define FAPI_PWR_CTRL_OFFSET_SS_3_DB                    2
+#define FAPI_PWR_CTRL_OFFSET_SS_6_DB                    3
+// CSI Type
+#define FAPI_CSI_TRS                                    0
+#define FAPI_CSI_NON_ZERO_POWER                         1
+#define FAPI_CSI_ZERO_POWER                             2
+// Row entry into CSI Resource Location Table
+#define FAPI_CSIRLT_ROW_MAX_VALUE                       18
+#define FAPI_CSI_FREQ_DOMAIN_MASK                       0x0fff
+#define FAPI_CSI_SYMB_L1_MIN                            2
+#define FAPI_CSI_SYMB_L1_MAX                            12
+// CDM Type
+#define FAPI_CDM_TYPE_NO_CDM                            0
+#define FAPI_CDM_TYPE_FD_CDM                            1
+#define FAPI_CDM_TYPE_CDM4_FD2_TD2                      2
+#define FAPI_CDM_TYPE_CDM8_FD2_TD4                      3
+// Frequency Density
+#define FAPI_FD_DOT5_EVEN_RB                            0
+#define FAPI_FD_DOT5_ODD_RB                             1
+#define FAPI_FD_ONE                                     2
+#define FAPI_FD_THREE                                   3
+
+// SSB
+#define FAPI_SSB_BLOCK_INDEX_MASK                       0x3f
+#define FAPI_SSB_SC_OFFSET_MASK                         0x1f
+
+// UL TTI REQUEST
+#define FAPI_MAX_NUM_UE_GROUPS_INCLUDED                 8
+#define FAPI__MAX_NUM_UE_IN_GROUP                       6
+// PRACH PDU
+#define FAPI_MAX_NUM_PRACH_OCAS                         7
+// PRACH FORMAT
+#define FAPI_PRACH_FORMAT_A1                            0
+#define FAPI_PRACH_FORMAT_A2                            1
+#define FAPI_PRACH_FORMAT_A3                            2
+#define FAPI_PRACH_FORMAT_B1                            3
+#define FAPI_PRACH_FORMAT_B2                            4
+#define FAPI_PRACH_FORMAT_B3                            5
+#define FAPI_PRACH_FORMAT_B4                            6
+#define FAPI_PRACH_FORMAT_C0                            7
+#define FAPI_PRACH_FORMAT_C2                            8
+
+#define FAPI_MAX_PRACH_FD_OCCASION_INDEX                7
+#define FAPI_MAX_ZC_ZONE_CONFIG_NUMBER                  419
+
+// PUSCH PDU
+#define FAPI_PUSCH_BIT_DATA_PRESENT_MASK                0x0001
+#define FAPI_PUSCH_UCI_DATA_PRESENT_MASK                0x0002
+#define FAPI_PUSCH_PTRS_INCLUDED_FR2_MASK               0x0004
+#define FAPI_PUSCH_DFTS_OFDM_TX_MASK                    0x0008
+
+#define FAPI_MAX_QAM_MOD_ORDER                          8
+#define FAPI_MCS_INDEX_MASK                             0x1f
+
+#define FAPI_MCS_TABLE_NOT_QAM256                       0
+#define FAPI_MCS_TABLE_QAM256                           1
+#define FAPI_MCS_TABLE_QAM64_LOWSE                      2
+#define FAPI_MCS_TABLE_NOT_QAM256_W_XFRM_PRECOD         3
+#define FAPI_MCS_TABLE_QAM64_LOWSE_W_XFRM_PRECOD        4
+#define FAPI_PUSCH_MAX_NUM_LAYERS                       4
+// DMRS
+#define FAPI_UL_DMRS_SYMB_POS_MASK                      0x3fff
+#define FAPI_UL_DMRS_CONFIG_TYPE_1                      0
+#define FAPI_UL_DMRS_CONFIG_TYPE_2                      1
+#define FAPI_MAX_DMRS_CDM_GRPS_NO_DATA                  3
+#define FAPI_UL_DMRS_PORTS_MASK                         0x07ff
+#define FAPI_UL_TX_DIRECT_CURR_LOCATION_MAX             3299
+#define FAPI_UL_TX_DIRECT_CURR_LOC_OUTSIDE_CARRIER      3300
+#define FAPI_UL_TX_DIRECT_CURR_LOC_UNDETERMINED         3301
+// PUSCH DATA
+#define FAPI_RV_INDEX_MASK                              0x03
+#define FAPI_HARQ_PROCESS_ID_MASK                       0x0f
+// PUSCH UCI INFO
+#define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_SMALL_BLOCK_MAX    11
+#define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_POLAR_MAX          1706
+// ALPHA SCALING
+#define FAPI_ALPHA_SCALE_0_5                            0
+#define FAPI_ALPHA_SCALE_0_65                           1
+#define FAPI_ALPHA_SCALE_0_8                            2
+#define FAPI_ALPHA_SCALE_1_0                            3
+// BETA OFFSET HARQ ACK
+#define FAPI_BETA_OFFSET_HARQ_ACK_MAX                   15
+#define FAPI_BETA_OFFSET_CSIX_MAX                       18
+
+// PUSCH PTRS INFORMATION 38.212 Section 7.3.1.1.2
+#define FAPI_MAX_NUMBER_PTRS_PORT_INDEX                 11  // 0..11
+// UL PTRS POWER 5G FAPI Table 3-49
+#define FAPI_UL_PTRS_PWR_0_DB                           0
+#define FAPI_UL_PTRS_PWR_3_DB                           1
+#define FAPI_UL_PTRS_PWR_4_77_DB                        2
+#define FAPI_UL_PTRS_PWR_6_DB                           3
+// DFTSOFDM INFO 5g FAPI Table 3-50
+#define FAPI_MAX_LOW_PAPR_GROUP_NUMBER                  29  // 0..29
+#define FAPI_MAX_LOW_PAPR_SEQ_NUMBER                    87  // 3*LOW_PAPR_GRP_NUM
+#define FAPI_MAX_UL PTRS_SAMP_DENSITY                   8
+#define FAPI_MAX_UL_PTRS_TD_XFRM_PRECOD                 4
+
+// PUCCH PDU Table 3-51
+#define FAPI_MAX_PUCCH_FORMAT_TYPE                      4
+#define FAPI_MULTI_SLOT_TX_IND_NO_MULTI_SLOT            0
+#define FAPI_MULTI_SLOT_TX_IND_TX_START                 1
+#define FAPI_MULTI_SLOT_TX_IND_TX_CONT                  2
+#define FAPI_MULTI_SLOT_TX_IND_TX_END                   3
+#define FAPI_MAX_NUM_PRB_FOR_A_PUCCH                    16
+#define FAPI_MAX_PUCCH_DUR_F0_AND_F2                    2
+#define FAPI_MIN_PUCCH_DUR_F1_F3_F4                     4
+#define FAPI_MAX_PUCCH_DUR_F1_F3_F4                     14
+#define FAPI_MAX_INIT_CYCLIC_SHIFT_F0_F1_F3_F4          11
+#define FAPI_MAX_OCC_INDEX_F1                           6
+#define FAPI_MAX_PRE_DFT_OCC_IDX_F4                     3
+#define FAPI_MAX_PRE_DFT_OCC_LEN_F4                     4
+#define FAPI_MAX_DMRS_CYC_SHIFT_F4                      9
+#define FAPI_BIT_LEN_HARQ_PL_ZERO                       0
+#define FAPI_BIT_LEN_HARQ_PL_F0_F1_2_BITS               1
+#define FAPI_BIT_LEN_HARQ_PL_F2_F3_F4_1706_BITS         2
+#define FAPI_BIT_LEN_CSI_PX_PL_NO_CSI                   0
+#define FAPI_BIT_LEN_CSI_PX_PL_1706_BITS                1
+
+// SRS PDU
+#define FAPI_1_SRS_ANT_PORT                             0
+#define FAPI_2_SRS_ANT_PORTS                            1
+#define FAPI_4_SRS_ANT_PORTS                            2
+#define FAPI_SRS_NO_REPETITIONS                         0
+#define FAPI_SRS_2_REPETITIONS                          2
+#define FAPI_SRS_4_REPETITIONS                          4
+#define FAPI_SRS_CONFIG_INDEX_MASK                      0x3f
+#define FAPI_SRS_BW_INDEX_MASK                          0x03
+#define FAPI_TX_COMB_SIZE_2                             0
+#define FAPI_TX_COMB_SIZE_4                             1
+#define FAPI_MAX_SRS_FREQ_POSITION                      67
+#define FAPI_MAX_SRS_FD_SHIFT                           268
+#define FAPI_SRS_FREQ_HOPPING_MASK                      0x03
+#define FAPI_SRS_NO_HOPPING                             0
+#define FAPI_SRS_GRP_OR_SEQ_HOPPING                     1
+#define FAPI_SRS_SEQ_HOPPING                            2
+#define FAPI_SRS_RES_ALLOC_APERIODIC                    0
+#define FAPI_SRS_RES_ALLOC_SEMI_PERSISTENT              1
+#define FAPI_SRS_RES_ALLOC_PERIODIC                     2
+#define FAPI_MAX_LSOT_OFFSET_VALUE                      2559
+
+// RX_DATA Indication
+#define FAPI_UL_CQI_INVALID                             255
+#define FAPI_TIMING_ADVANCE_INVALID                     0xffff
+#define FAPI_MAX_TIMING_ADVANCE                         63
+#define FAPI_MAX_RSSI                                   1280
+
+// RACH Indication
+#define FAPI_RACH_FREQ_INDEX_MAX                        7
+#define FAPI_RACH_DETECTED_PREAMBLES_MASK               0x3f
+#define FAPI_RACH_TIMING_ADVANCE_MAX                    3846
+#define FAPI_RACH_PREAMBLE_POWER_INVALID                0xffffffff
+#define FAPI_RACH_PREAMBLE_TIMING_ADVANCE_INVALID       0xffff
+#define FAPI_RACH_PREAMBLE_POWER_MAX                    170000
+
+// SR, HARQ, and CSI Part 1/2 PDUs Table 3-66
+#define FAPI_SR_MASK                                    0x01
+#define FAPI_HARQ_MASK                                  0x02
+#define FAPI_CSI_PART1                                  0x04
+#define FAPI_CSI_PART2                                  0x08
+#define FAPI_PUCCH_FORMAT2                              0
+#define FAPI_PUCCH_FORMAT3                              1
+#define FAPI_PUCCH_FORMAT4                              2
+#define FAPI_PUCCH_FORMAT_MASK                          0x03
+
+// SR PDU For Format 0 or 1 Table 3-67
+#define FAPI_SR_CONFIDENCE_LEVEL_GOOD                   0
+#define FAPI_SR_CONFIDENCE_LEVEL_BAD                    1
+#define FAPI_SR_CONFIDENCE_LEVEL_INVALID                0xff
+
+// HARQ PDU for Format 0 or 1 Table 3-68
+#define FAPI_HARQ_VALUE_PASS                            0
+#define FAPI_HARQ_VALUE_FAIL                            1
+#define FAPI_HARQ_VALUE_NOT_PRESENT                     2
+
+// SR PDU for Format 2,3 or 4 Table 3-69
+#define FAPI_SR_PAYLOAD_MAX                             1
+
+// HARQ PDU for Format 2,3 or 4 Table 3-70
+#define FAPI_HARQ_CRC_PASS                              0
+#define FAPI_HARQ_CRC_FAIL                              1
+#define FAPI_HARQ_CRC_NOT_PRESENT                       2
+#define FAPI_HARQ_PAYLOAD_MAX                           214
+
+// CSI Part 1 PDU Table 3-71 and 3-72
+#define FAPI_CSI_PARTX_CRC_PASS                         0
+#define FAPI_CSI_PARTX_CRC_FAIL                         1
+#define FAPI_CSI_PARTX_CRC_NOT_PRESENT                  2
+#define FAPI_CSI_PARTX_PAYLOAD_MAX                      214
+
+// CRC
+enum {
+    FAPI_CRC_CORRECT = 0,
+    FAPI_CRC_ERROR = 1
+};
+
+// Release/Features support
+typedef enum {
+    FAPI_NOT_SUPPORTED = 0,
+    FAPI_SUPPORTED,
+} fapiSupport_t;
+
+// Information of optional and mandatory status for a TLV
+typedef enum {
+    FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,
+    FAPI_IDLE_STATE_ONLY_MANDATORY,
+    FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,
+    FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,
+    FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,
+    FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL
+} fapiTlvStatus_t;
+
+typedef enum modulationOrder {
+    FAPI_QPSK = 0,
+    FAPI_16QAM,
+    FAPI_64QAM,
+    FAPI_256QAM
+} fapiModOrder_t;
+
+// SSBPERRACH
+typedef enum {
+    FAPI_SSB_PER_RACH_1_OVER_8 = 0,
+    FAPI_SSB_PER_RACH_1_OVER_4,
+    FAPI_SSB_PER_RACH_1_OVER_2,
+    FAPI_SSB_PER_RACH_1,
+    FAPI_SSB_PER_RACH_2,
+    FAPI_SSB_PER_RACH_4,
+    FAPI_SSB_PER_RACH_8,
+    FAPI_SSB_PER_RACH_16
+} fapiSsbPerRach_t;
+
+#endif                          //_NR5G_FAPI_INTELNAL_H_

diff --git a/src/mt/mt_ss.c b/src/mt/mt_ss.c
index dc3c0b3..03e7a28 100644 (file)
--- a/src/mt/mt_ss.c
+++ b/src/mt/mt_ss.c
@@ -181,7 +181,8 @@ S16 rgBatchProc ARGS((
 char            my_buffer2[4096 * 4] = { 0 };
 char            my_buffer[4096] = { 0 };
 int             my_buffer_idx = 0;
-
+uint64_t        nWlsMacMemorySize = 0;
+uint64_t        nWlsPhyMemorySize = 0;
 
 
 #define sigsegv_print(x, ...)    my_buffer_idx += sprintf(&my_buffer[my_buffer_idx], x "\n", ##__VA_ARGS__)
@@ -891,7 +892,7 @@ S16 smWrReadWlsConfigParams (Void);
 static int SOpenWlsIntf()
 {
    uint8_t i;
-   void *hdl;
+   void *hdl = NULLP;
 #define WLS_DEVICE_NAME "wls0"
 
    char *my_argv[] = {"gnodeb", "-c3", "--proc-type=auto", "--file-prefix", WLS_DEVICE_NAME, "--iova-mode=pa"};
@@ -913,7 +914,16 @@ static int SOpenWlsIntf()
    hdl = WLS_Open(WLS_DEVICE_NAME, 1);
 #endif
 #else
+#ifdef INTEL_L1_V19_10
    hdl = WLS_Open(WLS_DEVICE_NAME, WLS_MASTER_CLIENT, WLS_MEM_SIZE);
+#elif INTEL_L1
+   hdl = WLS_Open(WLS_DEVICE_NAME, WLS_MASTER_CLIENT, &nWlsMacMemorySize, &nWlsPhyMemorySize);
+
+   if(hdl == NULL)
+   {
+      printf("\nERROR: WLS_Open > DEVICE_NAME mismatch. WLS Device Name should be same as 'wls_dev_name' parameter in 'phycfg_xran.xml' file");
+   }
+#endif
 #endif
 
    osCp.wls.intf = hdl;
@@ -1584,6 +1594,8 @@ static S16 SAllocateWlsDynMem()
    osCp.wls.allocAddr = WLS_Alloc(osCp.wls.intf,
 #ifdef INTEL_L1_V19_10
         WLS_MEMORY_SIZE);
+#elif INTEL_L1
+    nWlsMacMemorySize+nWlsPhyMemorySize);   
 #else
    (reqdMemSz + (4 * 1024 * 1024)));
 #endif

diff --git a/src/phy_stub/phy_stub_ex_ms.c b/src/phy_stub/phy_stub_ex_ms.c
index 387326c..e8fdd67 100644 (file)
--- a/src/phy_stub/phy_stub_ex_ms.c
+++ b/src/phy_stub/phy_stub_ex_ms.c
@@ -19,7 +19,7 @@
 #include "common_def.h"
 #include "phy_stub_utils.h"
 #ifdef INTEL_FAPI
-#include "fapi.h"
+#include "nr5g_fapi_internal.h"
 #include "fapi_vendor_extension.h"
 #endif
 #include "phy_stub.h"

diff --git a/src/phy_stub/phy_stub_msg_hdl.c b/src/phy_stub/phy_stub_msg_hdl.c
index 5e462f4..1b1694d 100644 (file)
--- a/src/phy_stub/phy_stub_msg_hdl.c
+++ b/src/phy_stub/phy_stub_msg_hdl.c
@@ -27,7 +27,7 @@
 #include "lwr_mac_fsm.h"
 #include "lwr_mac_phy.h"
 #ifdef INTEL_FAPI
-#include "fapi.h"
+#include "nr5g_fapi_internal.h"
 #include "fapi_vendor_extension.h"
 #endif
 #include "lwr_mac_upr_inf.h"

diff --git a/src/phy_stub/phy_stub_thread_hdl.c b/src/phy_stub/phy_stub_thread_hdl.c
index 99b33aa..d1d3664 100644 (file)
--- a/src/phy_stub/phy_stub_thread_hdl.c
+++ b/src/phy_stub/phy_stub_thread_hdl.c
@@ -21,7 +21,7 @@
 #include "common_def.h"
 #include "phy_stub_utils.h"
 #ifdef INTEL_FAPI
-#include "fapi.h"
+#include "nr5g_fapi_internal.h"
 #include "fapi_vendor_extension.h"
 #endif
 #include "phy_stub.h"