1 /******************************************************************************
\r
2 * Copyright 2017 Cisco Systems, Inc.
\r
3 * Copyright (c) 2019 Intel.
\r
5 * Licensed under the Apache License, Version 2.0 (the "License");
\r
6 * you may not use this file except in compliance with the License.
\r
7 * You may obtain a copy of the License at
\r
9 * http://www.apache.org/licenses/LICENSE-2.0
\r
11 * Unless required by applicable law or agreed to in writing, software
\r
12 * distributed under the License is distributed on an "AS IS" BASIS,
\r
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
\r
14 * See the License for the specific language governing permissions and
\r
15 * limitations under the License.
\r
17 *******************************************************************************/
\r
18 // This file has been modified by Intel in order to support 5G FAPI:PHY API Specification
\r
19 // Document 222.10.01 dated June 2019
\r
20 // Changes made by luis.farias@intel.com
\r
23 * This file consist of FAPI configuration APIs macros, structure typedefs and
\r
33 #include "fapi_interface.h"
\r
34 //#include "fapi_vendor_common_defs.h"
\r
36 #define RELEASE_15 0x0001
\r
38 // Datatypes typedefs - end
\r
44 // Updated per 5G FAPI
\r
48 // Updated per 5G FAPI
\r
50 FAPI_UL_TTI_REQ_PRACH_PDU_TYPE = 0,
\r
51 FAPI_UL_TTI_REQ_PUSCH_PDU_TYPE,
\r
52 FAPI_UL_TTI_REQ_PUCCH_PDU_TYPE,
\r
53 FAPI_UL_TTI_REQ_SRS_PDU_TYPE
\r
54 }fapiULTtiReqPduType_e;
\r
55 // Updated per 5G FAPI
\r
57 FAPI_UCI_IND_ON_PUSCH_PDU_TYPE = 0,
\r
58 FAPI_UCI_IND_ON_PUCCH_FMT_0_1_PDU_TYPE,
\r
59 FAPI_UCI_IND_ON_PUCCH_FMT_2_3_4_PDU_TYPE
\r
60 }fapiUciIndPdu_Type_e;
\r
64 FAPI_CRC_CORRECT = 0,
\r
68 //------------------------------------------------------------------------------
\r
69 // Fapi Infra Declarations
\r
70 //------------------------------------------------------------------------------
\r
71 // Release/Features support
\r
73 FAPI_NOT_SUPPORTED = 0,
\r
79 * FAPI state is maintained per fapi instance. If FAPI messages are received in
\r
80 * wrong state an ERROR.indication message will be sent by FAPI.
\r
82 typedef enum fapiStates
\r
84 FAPI_STATE_IDLE = 0,
\r
85 FAPI_STATE_CONFIGURED,
\r
89 // Information of optional and mandatory status for a TLV
\r
91 FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,
\r
92 FAPI_IDLE_STATE_ONLY_MANDATORY,
\r
93 FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,
\r
94 FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,
\r
95 FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,
\r
96 FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL
\r
99 // PARAMETERS INFORMATION
\r
101 #define FAPI_NORMAL_CYCLIC_PREFIX_MASK 0x01
\r
102 #define FAPI_EXTENDED_CYCLIC_PREFIX_MASK 0x02
\r
104 // In 5G FAPI FrameDuplexType as part of Cell Configuration
\r
109 } modes; //Defined now
\r
111 // Subcarrier spacing information
\r
112 #define FAPI_15KHZ_MASK 0x01
\r
113 #define FAPI_30KHZ_MASK 0x02
\r
114 #define FAPI_60KHZ_MASK 0x04
\r
115 #define FAPI_120KHZ_MASK 0x08
\r
117 // Bandwitdth information
\r
118 #define FAPI_5MHZ_BW_MASK 0x0001
\r
119 #define FAPI_10MHZ_BW_MASK 0x0002
\r
120 #define FAPI_15MHZ_BW_MASK 0x0004
\r
121 #define FAPI_20MHZ_BW_MASK 0x0010
\r
122 #define FAPI_40MHZ_BW_MASK 0x0020
\r
123 #define FAPI_50MHZ_BW_MASK 0x0040
\r
124 #define FAPI_60MHZ_BW_MASK 0x0080
\r
125 #define FAPI_70MHZ_BW_MASK 0x0100
\r
126 #define FAPI_80MHZ_BW_MASK 0x0200
\r
127 #define FAPI_90MHZ_BW_MASK 0x0400
\r
128 #define FAPI_100MHZ_BW_MASK 0x0800
\r
129 #define FAPI_200MHZ_BW_MASK 0x1000
\r
130 #define FAPI_400MHZ_BW_MASK 0x2000
\r
133 // PDCCH Information
\r
134 #define FAPI_CCE_MAPPING_INTERLEAVED_MASK 0x01
\r
135 #define FAPI_CCE_MAPPING_NONINTERLVD_MASK 0x02
\r
136 // Upper Bound for PDCCH Channels per Slot
\r
137 #define FAPI_MAX_PDCCHS_PER_SLOT_MASK 0xff
\r
139 // PUCCH Information
\r
140 #define FAPI_FORMAT_0_MASK 0x01
\r
141 #define FAPI_FORMAT_1_MASK 0x02
\r
142 #define FAPI_FORMAT_2_MASK 0x04
\r
143 #define FAPI_FORMAT_3_MASK 0x08
\r
144 #define FAPI_FORMAT_4_MASK 0x10
\r
145 // Upper Bound for PUCCH Channels per Slot
\r
146 #define FAPI_MAX_PUCCHS_PER_SLOT_MASK 0xff
\r
148 // PDSCH Information
\r
149 #define FAPI_PDSCH_MAPPING_TYPE_A_MASK 0x01
\r
150 #define FAPI_PDSCH_MAPPING_TYPE_B_MASK 0x02
\r
151 #define FAPI_PDSCH_ALLOC_TYPE_0_MASK 0x01
\r
152 #define FAPI_PDSCH_ALLOC_TYPE_1_MASK 0x02
\r
153 #define FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01
\r
154 #define FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02
\r
155 #define FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK 0x01
\r
156 #define FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK 0x02
\r
157 #define FAPI_PDSCH_DMRS_MAX_LENGTH_1 0
\r
158 #define FAPI_PDSCH_DMRS_MAX_LENGTH_2 1
\r
159 #define FAPI_DMRS_ADDITIONAL_POS_0_MASK 0x01
\r
160 #define FAPI_DMRS_ADDITIONAL_POS_1_MASK 0x02
\r
161 #define FAPI_DMRS_ADDITIONAL_POS_2_MASK 0x04
\r
162 #define FAPI_DMRS_ADDITIONAL_POS_3_MASK 0x08
\r
163 //Upper Limit for PDSCHS TBs per Slot
\r
164 #define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK 0xff
\r
165 #define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH 2
\r
167 typedef enum modulationOrder {
\r
174 #define FAPI_MAX_MUMIMO_USERS_MASK 0xff
\r
177 // PUSCH Parameters
\r
179 #define FAPI_PUSCH_MAPPING_TYPE_A_MASK 0x01
\r
180 #define FAPI_PUSCH_MAPPING_TYPE_B_MASK 0x02
\r
181 #define FAPI_PUSCH_ALLOC_TYPE_0_MASK 0x01
\r
182 #define FAPI_PUSCH_ALLOC_TYPE_1_MASK 0x02
\r
183 #define FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01
\r
184 #define FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02
\r
185 #define FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK 0x01
\r
186 #define FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK 0x02
\r
187 #define FAPI_PUSCH_DMRS_MAX_LENGTH_1 0
\r
188 #define FAPI_PUSCH_DMRS_MAX_LENGTH_2 1
\r
189 // Upper limit for PUSCHMAXPTRSPORTS
\r
190 #define FAPI_PUSCH_MAX_PTRS_PORTS_UB 2
\r
191 //Upper Limit for PDSCHS TBs per Slot
\r
192 #define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK 0xff
\r
194 typedef enum aggregationFactor
\r
196 FAPI_PUSCH_AGG_FACTOR_1 = 0,
\r
197 FAPI_PUSCH_AGG_FACTOR_2,
\r
198 FAPI_PUSCH_AGG_FACTOR_4,
\r
199 FAPI_PUSCH_AGG_FACTOR_8
\r
200 } fapiPuschAggFactor_t;
\r
202 // PRACH Parameters
\r
203 #define FAPI_PRACH_LF_FORMAT_0_MASK 0x01
\r
204 #define FAPI_PRACH_LF_FORMAT_1_MASK 0x02
\r
205 #define FAPI_PRACH_LF_FORMAT_2_MASK 0x04
\r
206 #define FAPI_PRACH_LF_FORMAT_3_MASK 0x08
\r
208 #define FAPI_PRACH_SF_FORMAT_A1_MASK 0x01
\r
209 #define FAPI_PRACH_SF_FORMAT_A2_MASK 0x02
\r
210 #define FAPI_PRACH_SF_FORMAT_A3_MASK 0x04
\r
211 #define FAPI_PRACH_SF_FORMAT_B1_MASK 0x08
\r
212 #define FAPI_PRACH_SF_FORMAT_B2_MASK 0x10
\r
213 #define FAPI_PRACH_SF_FORMAT_B3_MASK 0x20
\r
214 #define FAPI_PRACH_SF_FORMAT_B4_MASK 0x40
\r
215 #define FAPI_PRACH_SF_FORMAT_C0_MASK 0x80
\r
216 #define FAPI_PRACH_SF_FORMAT_C2_MASK 0x100
\r
219 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_1 = 0,
\r
220 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_2,
\r
221 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_4,
\r
222 FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_8
\r
223 } fapi_prachMaxFdOccasionsPerSlot_t;
\r
225 // Measurement Parameters
\r
226 #define FAPI_RSSI_REPORT_IN_DBM_MASK 0x01
\r
227 #define FAPI_RSSI_REPORT_IN_DBFS_MASK 0x02
\r
229 // CONFIGURATION INFORMATION
\r
230 // CARRIER CONFIGURATION
\r
232 #define FAPI_BANDWIDTH_5_MHZ 5
\r
233 #define FAPI_BANDWIDTH_10_MHZ 10
\r
234 #define FAPI_BANDWIDTH_15_MHZ 15
\r
235 #define FAPI_BANDWIDTH_20_MHZ 20
\r
236 #define FAPI_BANDWIDTH_25_MHZ 25
\r
237 #define FAPI_BANDWIDTH_30_MHZ 30
\r
238 #define FAPI_BANDWIDTH_40_MHZ 40
\r
239 #define FAPI_BANDWIDTH_50_MHZ 50
\r
240 #define FAPI_BANDWIDTH_60_MHZ 60
\r
241 #define FAPI_BANDWIDTH_70_MHZ 70
\r
242 #define FAPI_BANDWIDTH_80_MHZ 80
\r
243 #define FAPI_BANDWIDTH_90_MHZ 90
\r
244 #define FAPI_BANDWIDTH_100_MHZ 100
\r
245 #define FAPI_BANDWIDTH_200_MHZ 200
\r
246 #define FAPI_BANDWIDTH_400_MHZ 400
\r
248 // Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1
\r
250 #define FAPI_MIN_FREQUENCY_PT_A 450000
\r
252 #define FAPI_MAX_FREQUENCY_PT_A 52600000
\r
253 // dlk0, ulk0 per 38.211 Section 5.3.1
\r
255 #define FAPI_K0_MAX 23699
\r
256 // dlGridSize, ulGridSize per 38.211 Section 4.4.2
\r
258 #define FAPI_GRIDSIZE_MAX 275
\r
259 // Number of Transmit Antennas
\r
260 // Define upper mask based on variable type
\r
261 #define FAPI_NUM_ANT_MASK 0xffff
\r
263 // CELL CONFIGURATION
\r
264 // Physical Cell ID from 38.211 Section 7.4.2.1
\r
266 #define FAPI_MAX_CELL_ID 1007
\r
268 // SSB CONFIGURATION
\r
269 // SSB POWER RANGE in dBm
\r
270 #define FAPI_SS_PBCH_LOWEST_POWER -60
\r
271 #define FAPI_SS_PBCH_MAX_POWER 50
\r
272 // BCH PAYLOAD for 5G the MAC always generates the BCH Payload
\r
273 #define FAPI_BCH_PAYLOAD_GEN_BY_MAC 0
\r
274 #define FAPI_BCH_PAYLOAD_WITH_PHY_GEN_TIMING 1
\r
275 #define FAPI_BCH_PAYLOAD_ENTIRELY_GEN_BY_PHY 2
\r
277 #define FAPI_SCSCOMMON_MASK 0x03
\r
279 // PRACH CONFIGURATION
\r
280 #define FAPI_PRACH_LONG_SEQUENCE 0
\r
281 #define FAPI_PRACH_SHORT_SEQUENCE 1
\r
282 #define FAPI_PRACH_SUBC_SPACING_MAX 4
\r
283 // Restricted Set Configuration
\r
284 #define FAPI_PRACH_RESTRICTED_SET_UNRESTRICTED 0
\r
285 #define FAPI_PRACH_RESTRICTED_SET_TYPE_A 1
\r
286 #define FAPI_PRACH_RESTRICTED_SET_TYPE_B 2
\r
287 // Root Sequence Index
\r
289 #define FAPI_PRACH_ROOT_SEQ_INDEX_MAX 837
\r
292 #define FAPI_K1_UPPER_BOUND 272
\r
293 // PRACH Zero Corr Configuration
\r
295 #define FAPI_PRACHZEROCORRCONF_MASK 0x0f
\r
296 // Number of Unused Root Sequences Mask
\r
297 #define FAPI_UNUSEDROOTSEQUENCES_MASK 0x0f
\r
301 FAPI_SSB_PER_RACH_1_OVER_8 = 0,
\r
302 FAPI_SSB_PER_RACH_1_OVER_4,
\r
303 FAPI_SSB_PER_RACH_1_OVER_2,
\r
304 FAPI_SSB_PER_RACH_1,
\r
305 FAPI_SSB_PER_RACH_2,
\r
306 FAPI_SSB_PER_RACH_4,
\r
307 FAPI_SSB_PER_RACH_8,
\r
308 FAPI_SSB_PER_RACH_16
\r
309 } fapiSsbPerRach_t;
\r
312 // Ssb Offset Point A max
\r
313 #define FAPI_SSB_OFFSET_POINTA_MAX 2199
\r
314 // betaPSS i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1
\r
315 #define FAPI_BETAPSS_0_DB 0
\r
316 #define FAPI_BETAPSS_3_DB 1
\r
317 // SSB Period in ms
\r
318 #define FAPI_SSB_PERIOD_5_MS 0
\r
319 #define FAPI_SSB_PERIOD_10_MS 1
\r
320 #define FAPI_SSB_PERIOD_20_MS 2
\r
321 #define FAPI_SSB_PERIOD_40_MS 3
\r
322 #define FAPI_SSB_PERIOD_80_MS 4
\r
323 #define FAPI_SSB_PERIOD_160_MS 5
\r
325 // Ssb Subcarrier Offset per 38.211 Section 7.4.3.1
\r
326 // SsbSubcarrierOffset mask
\r
327 #define FAPI_SSB_SUBCARRIER_OFFSET_MASK 0x1f
\r
328 // MIB PAYLOAD MASK
\r
329 #define MIB_PAYLOAD_MASK 0xfff0
\r
331 #define FAPI_BEAM_ID_MASK 0x3f
\r
335 #define FAPI_TDD_PERIOD_0_P_5_MS 0
\r
336 #define FAPI_TDD_PERIOD_0_P_625_MS 1
\r
337 #define FAPI_TDD_PERIOD_1_MS 2
\r
338 #define FAPI_TDD_PERIOD_1_P_25_MS 3
\r
339 #define FAPI_TDD_PERIOD_2_MS 4
\r
340 #define FAPI_TDD_PERIOD_2_P_5_MS 5
\r
341 #define FAPI_TDD_PERIOD_5_MS 6
\r
342 #define FAPI_TDD_PERIOD_10_MS 7
\r
344 // Slot Configuration
\r
345 #define FAPI_DL_SLOT 0
\r
346 #define FAPI_UL_SLOT 1
\r
347 #define FAPI_GUARD_SLOT 2
\r
349 // Measurement configuration
\r
350 #define FAPI_NO_RSSI_REPORTING 0
\r
351 #define FAPI_RSSI_REPORTED_IN_DBM 1
\r
352 #define FAPI_RSSI_REPORTED_IN_DBFS 2
\r
354 // Error Indication
\r
355 #define FAPI_SFN_MASK 0x03ff
\r
357 // Status and Error Codes for either .response or ERROR.indication
\r
358 // Updated per 5g FAPI Table 3-31
\r
363 MSG_INVALID_CONFIG,
\r
370 }fapiStatusAndErrorCodes_e;
\r
372 // Digital Beam Table (DBT) PDU
\r
373 // Number of Digital Beam Mask
\r
374 // Number of TX RUS Mask
\r
376 // Digital Beam Index weights Real and Imaginary Mask
\r
378 // Precoding Matrix (PM) PDU
\r
379 // Precoding Matrix ID Mask
\r
380 // Number of Layers Mask
\r
381 // Number of Antenna Ports at the precoder output Mask
\r
382 // Precoder Weights Real and Imaginary Mask
\r
383 #define FAPI_U16_MASK 0xffff
\r
387 #define FAPI_SLOT_MAX_VALUE 319
\r
392 #define FAPI_U8_MASK 0xff
\r
395 FAPI_DL_TTI_REQ_PDCCH_PDU_TYPE = 0,
\r
396 FAPI_DL_TTI_REQ_PDSCH_PDU_TYPE,
\r
397 FAPI_DL_TTI_REQ_CSI_RS_PDU_TYPE,
\r
398 FAPI_DL_TTI_REQ_SSB_PDU_TYPE
\r
399 }fapiDlTtiReqPduType_e;
\r
402 // Define Maximum number of Ues per Group
\r
403 #define FAPI_MAX_NUMBER_OF_UES_PER_GROUP 12
\r
406 #define FAPI_BWPSIZE_MAX 275
\r
407 #define FAPI_BWPSIZE_START_MAX 274
\r
408 #define FAPI_SUBCARRIER_SPACING_MAX 4
\r
409 #define FAPI_CYCLIC_PREFIX_NORMAL 0
\r
410 #define FAPI_CYCLIC_PREFIX_EXTENDED 1
\r
411 #define FAPI_MAX_SYMBOL_START_INDEX 13
\r
413 #define FAPI_CORESET_DURATION_1_SYMBOL 1
\r
414 #define FAPI_CORESET_DURATION_2_SYMBOLS 2
\r
415 #define FAPI_CORESET_DURATION_3_SYMBOLS 3
\r
417 #define FAPI_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0
\r
418 #define FAPI_CCE_REG_MAPPING_TYPE_INTERLEAVED 1
\r
419 #define FAPI_REG_BUNDLE_SIZE_2 2
\r
420 #define FAPI_REG_BUNDLE_SIZE_3 3
\r
421 #define FAPI_REG_BUNDLE_SIZE_6 6
\r
423 #define FAPI_INTERLEAVER_SIZE_2 2
\r
424 #define FAPI_INTERLEAVER_SIZE_3 3
\r
425 #define FAPI_INTERLEAVER_SIZE_6 6
\r
427 #define FAPI_CORESET_TYPE_0_CONF_BY_PBCH_OR_SIB1 0
\r
428 #define FAPI_CORESET_TYPE_1 1
\r
430 #define FAPI_PREC_GRANULARITY_SAME_AS_REG_BUNDLE 0
\r
431 #define FAPI_PREC_GRANULARITY_ALL_CONTIG_RBS 1
\r
433 #define FAPI_CCE_INDEX_MAX 135
\r
434 #define FAPI_PDCCH_AGG_LEVEL_1 1
\r
435 #define FAPI_PDCCH_AGG_LEVEL_2 2
\r
436 #define FAPI_PDCCH_AGG_LEVEL_4 4
\r
437 #define FAPI_PDCCH_AGG_LEVEL_8 8
\r
438 #define FAPI_PDCCH_AGG_LEVEL_16 16
\r
440 #define FAPI_BETA_PDCCH_1_0_MAX 17
\r
442 #define FAPI_POWER_CTRL_OFF_SS_MINUS_3_DB 0
\r
443 #define FAPI_POWER_CTRL_OFF_SS_0_DB 1
\r
444 #define FAPI_POWER_CTRL_OFF_SS_3_DB 2
\r
445 #define FAPI_POWER_CTRL_OFF_SS_6_DB 3
\r
447 #define FAPI_MAX_NUMBER_OF_CODEWORDS 2
\r
449 #define FAPI_MAX_MCS_INDEX 31
\r
450 #define FAPI_MCS_INDEX_MASK 0x1f
\r
452 #define FAPI_MCS_TABLE_NOT_QAM_256 0
\r
453 #define FAPI_MCS_TABLE_QAM_256 1
\r
454 #define FAPI_MCS_TABLE_QAM_64_LOW_SE 2
\r
456 #define FAPI_REDUNDANCY_INDEX_MASK 0x03
\r
457 #define FAPI_MAX_DL_LAYERS 8
\r
459 #define FAPI_TRANSMISSION_SCHEME_1 1
\r
461 #define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A 0
\r
462 #define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC 1
\r
464 #define FAPI_DL_DMRS_SYMB_POS_MASK 0x3fff
\r
466 #define FAPI_MAX_DMRS_CDM_GRPS_WO_DATA 3
\r
468 #define FAPI_DMRS_PORTS_MASK 0x0fff
\r
470 #define FAPI_RES_ALLOC_TYPE_0 0
\r
471 #define FAPI_RES_ALLOC_TYPE_1 1
\r
473 #define FAPI_VRB_TO_PRB_MAP_NON_INTERLVD 0
\r
474 #define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_2 1
\r
475 #define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_4 2
\r
477 #define FAPI_MAX_START_SYMBOL_INDEX 13
\r
478 #define FAPI_MAX_NR_OF_SYMBOLS 14
\r
479 #define FAPI_PTRS_PORT_INDEX_MASK 0x3f
\r
480 #define FAPI_PTRS_TIME_DENSITY_1 0
\r
481 #define FAPI_PTRS_TIME_DENSITY_2 1
\r
482 #define FAPI_PTRS_TIME_DENSITY_4 2
\r
483 #define FAPI_PTRS_FREQ_DENSITY_2 0
\r
484 #define FAPI_PTRS_FREQ_DENSITY_4 1
\r
485 #define FAPI_PTRS_RE_OFFSET_MASK 0x03
\r
486 #define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK 0x03
\r
487 // PDSCH Power Control Offset
\r
488 #define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB 0
\r
489 #define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB 1
\r
490 #define FAPI_PWR_CTRL_OFFSET_MINUS_6_DB 2
\r
491 #define FAPI_PWR_CTRL_OFFSET_MINUS_5_DB 3
\r
492 #define FAPI_PWR_CTRL_OFFSET_MINUS_4_DB 4
\r
493 #define FAPI_PWR_CTRL_OFFSET_MINUS_3_DB 5
\r
494 #define FAPI_PWR_CTRL_OFFSET_MINUS_2_DB 6
\r
495 #define FAPI_PWR_CTRL_OFFSET_MINUS_1_DB 7
\r
496 #define FAPI_PWR_CTRL_OFFSET_0_DB 8
\r
497 #define FAPI_PWR_CTRL_OFFSET_1_DB 9
\r
498 #define FAPI_PWR_CTRL_OFFSET_2_DB 10
\r
499 #define FAPI_PWR_CTRL_OFFSET_3_DB 11
\r
500 #define FAPI_PWR_CTRL_OFFSET_4_DB 12
\r
501 #define FAPI_PWR_CTRL_OFFSET_5_DB 13
\r
502 #define FAPI_PWR_CTRL_OFFSET_6_DB 14
\r
503 #define FAPI_PWR_CTRL_OFFSET_7_DB 15
\r
504 #define FAPI_PWR_CTRL_OFFSET_8_DB 16
\r
505 #define FAPI_PWR_CTRL_OFFSET_9_DB 17
\r
506 #define FAPI_PWR_CTRL_OFFSET_10_DB 18
\r
507 #define FAPI_PWR_CTRL_OFFSET_11_DB 19
\r
508 #define FAPI_PWR_CTRL_OFFSET_12_DB 20
\r
509 #define FAPI_PWR_CTRL_OFFSET_13_DB 21
\r
510 #define FAPI_PWR_CTRL_OFFSET_14_DB 22
\r
511 #define FAPI_PWR_CTRL_OFFSET_15_DB 23
\r
512 // Power Control Offset SS
\r
513 #define FAPI_PWR_CTRL_OFFSET_SS_MINUS_3_DB 0
\r
514 #define FAPI_PWR_CTRL_OFFSET_SS_0_DB 1
\r
515 #define FAPI_PWR_CTRL_OFFSET_SS_3_DB 2
\r
516 #define FAPI_PWR_CTRL_OFFSET_SS_6_DB 3
\r
518 #define FAPI_CSI_TRS 0
\r
519 #define FAPI_CSI_NON_ZERO_POWER 1
\r
520 #define FAPI_CSI_ZERO_POWER 2
\r
521 // Row entry into CSI Resource Location Table
\r
522 #define FAPI_CSIRLT_ROW_MAX_VALUE 18
\r
523 #define FAPI_CSI_FREQ_DOMAIN_MASK 0x0fff
\r
524 #define FAPI_CSI_SYMB_L1_MIN 2
\r
525 #define FAPI_CSI_SYMB_L1_MAX 12
\r
527 #define FAPI_CDM_TYPE_NO_CDM 0
\r
528 #define FAPI_CDM_TYPE_FD_CDM 1
\r
529 #define FAPI_CDM_TYPE_CDM4_FD2_TD2 2
\r
530 #define FAPI_CDM_TYPE_CDM8_FD2_TD4 3
\r
531 // Frequency Density
\r
532 #define FAPI_FD_DOT5_EVEN_RB 0
\r
533 #define FAPI_FD_DOT5_ODD_RB 1
\r
534 #define FAPI_FD_ONE 2
\r
535 #define FAPI_FD_THREE 3
\r
538 #define FAPI_SSB_BLOCK_INDEX_MASK 0x3f
\r
539 #define FAPI_SSB_SC_OFFSET_MASK 0x1f
\r
542 #define FAPI_MAX_NUM_UE_GROUPS_INCLUDED 8
\r
543 #define FAPI__MAX_NUM_UE_IN_GROUP 6
\r
545 #define FAPI_MAX_NUM_PRACH_OCAS 7
\r
547 #define FAPI_PRACH_FORMAT_A1 0
\r
548 #define FAPI_PRACH_FORMAT_A2 1
\r
549 #define FAPI_PRACH_FORMAT_A3 2
\r
550 #define FAPI_PRACH_FORMAT_B1 3
\r
551 #define FAPI_PRACH_FORMAT_B2 4
\r
552 #define FAPI_PRACH_FORMAT_B3 5
\r
553 #define FAPI_PRACH_FORMAT_B4 6
\r
554 #define FAPI_PRACH_FORMAT_C0 7
\r
555 #define FAPI_PRACH_FORMAT_C2 8
\r
557 #define FAPI_MAX_PRACH_FD_OCCASION_INDEX 7
\r
558 #define FAPI_MAX_ZC_ZONE_CONFIG_NUMBER 419
\r
561 #define FAPI_PUSCH_BIT_DATA_PRESENT_MASK 0x0001
\r
562 #define FAPI_PUSCH_UCI_DATA_PRESENT_MASK 0x0002
\r
563 #define FAPI_PUSCH_PTRS_INCLUDED_FR2_MASK 0x0004
\r
564 #define FAPI_PUSCH_DFTS_OFDM_TX_MASK 0x0008
\r
566 #define FAPI_MAX_QAM_MOD_ORDER 8
\r
567 #define FAPI_MCS_INDEX_MASK 0x1f
\r
569 #define FAPI_MCS_TABLE_NOT_QAM256 0
\r
570 #define FAPI_MCS_TABLE_QAM256 1
\r
571 #define FAPI_MCS_TABLE_QAM64_LOWSE 2
\r
572 #define FAPI_MCS_TABLE_NOT_QAM256_W_XFRM_PRECOD 3
\r
573 #define FAPI_MCS_TABLE_QAM64_LOWSE_W_XFRM_PRECOD 4
\r
574 #define FAPI_PUSCH_MAX_NUM_LAYERS 4
\r
576 #define FAPI_UL_DMRS_SYMB_POS_MASK 0x3fff
\r
577 #define FAPI_UL_DMRS_CONFIG_TYPE_1 0
\r
578 #define FAPI_UL_DMRS_CONFIG_TYPE_2 1
\r
579 #define FAPI_MAX_DMRS_CDM_GRPS_NO_DATA 3
\r
580 #define FAPI_UL_DMRS_PORTS_MASK 0x07ff
\r
581 #define FAPI_UL_TX_DIRECT_CURR_LOCATION_MAX 3299
\r
582 #define FAPI_UL_TX_DIRECT_CURR_LOC_OUTSIDE_CARRIER 3300
\r
583 #define FAPI_UL_TX_DIRECT_CURR_LOC_UNDETERMINED 3301
\r
585 #define FAPI_RV_INDEX_MASK 0x03
\r
586 #define FAPI_HARQ_PROCESS_ID_MASK 0x0f
\r
588 #define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_SMALL_BLOCK_MAX 11
\r
589 #define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_POLAR_MAX 1706
\r
591 #define FAPI_ALPHA_SCALE_0_5 0
\r
592 #define FAPI_ALPHA_SCALE_0_65 1
\r
593 #define FAPI_ALPHA_SCALE_0_8 2
\r
594 #define FAPI_ALPHA_SCALE_1_0 3
\r
595 // BETA OFFSET HARQ ACK
\r
596 #define FAPI_BETA_OFFSET_HARQ_ACK_MAX 15
\r
597 #define FAPI_BETA_OFFSET_CSIX_MAX 18
\r
599 // PUSCH PTRS INFORMATION 38.212 Section 7.3.1.1.2
\r
600 #define FAPI_MAX_NUMBER_PTRS_PORT_INDEX 11 // 0..11
\r
601 // UL PTRS POWER 5G FAPI Table 3-49
\r
602 #define FAPI_UL_PTRS_PWR_0_DB 0
\r
603 #define FAPI_UL_PTRS_PWR_3_DB 1
\r
604 #define FAPI_UL_PTRS_PWR_4_77_DB 2
\r
605 #define FAPI_UL_PTRS_PWR_6_DB 3
\r
606 // DFTSOFDM INFO 5g FAPI Table 3-50
\r
607 #define FAPI_MAX_LOW_PAPR_GROUP_NUMBER 29 // 0..29
\r
608 #define FAPI_MAX_LOW_PAPR_SEQ_NUMBER 87 // 3*LOW_PAPR_GRP_NUM
\r
609 #define FAPI_MAX_UL PTRS_SAMP_DENSITY 8
\r
610 #define FAPI_MAX_UL_PTRS_TD_XFRM_PRECOD 4
\r
612 // PUCCH PDU Table 3-51
\r
613 #define FAPI_MAX_PUCCH_FORMAT_TYPE 4
\r
614 #define FAPI_MULTI_SLOT_TX_IND_NO_MULTI_SLOT 0
\r
615 #define FAPI_MULTI_SLOT_TX_IND_TX_START 1
\r
616 #define FAPI_MULTI_SLOT_TX_IND_TX_CONT 2
\r
617 #define FAPI_MULTI_SLOT_TX_IND_TX_END 3
\r
618 #define FAPI_MAX_NUM_PRB_FOR_A_PUCCH 16
\r
619 #define FAPI_MAX_PUCCH_DUR_F0_AND_F2 2
\r
620 #define FAPI_MIN_PUCCH_DUR_F1_F3_F4 4
\r
621 #define FAPI_MAX_PUCCH_DUR_F1_F3_F4 14
\r
622 #define FAPI_MAX_INIT_CYCLIC_SHIFT_F0_F1_F3_F4 11
\r
623 #define FAPI_MAX_OCC_INDEX_F1 6
\r
624 #define FAPI_MAX_PRE_DFT_OCC_IDX_F4 3
\r
625 #define FAPI_MAX_PRE_DFT_OCC_LEN_F4 4
\r
626 #define FAPI_MAX_DMRS_CYC_SHIFT_F4 9
\r
627 #define FAPI_BIT_LEN_HARQ_PL_ZERO 0
\r
628 #define FAPI_BIT_LEN_HARQ_PL_F0_F1_2_BITS 1
\r
629 #define FAPI_BIT_LEN_HARQ_PL_F2_F3_F4_1706_BITS 2
\r
630 #define FAPI_BIT_LEN_CSI_PX_PL_NO_CSI 0
\r
631 #define FAPI_BIT_LEN_CSI_PX_PL_1706_BITS 1
\r
634 #define FAPI_1_SRS_ANT_PORT 0
\r
635 #define FAPI_2_SRS_ANT_PORTS 1
\r
636 #define FAPI_4_SRS_ANT_PORTS 2
\r
637 #define FAPI_SRS_NO_REPETITIONS 0
\r
638 #define FAPI_SRS_2_REPETITIONS 2
\r
639 #define FAPI_SRS_4_REPETITIONS 4
\r
640 #define FAPI_SRS_CONFIG_INDEX_MASK 0x3f
\r
641 #define FAPI_SRS_BW_INDEX_MASK 0x03
\r
642 #define FAPI_TX_COMB_SIZE_2 0
\r
643 #define FAPI_TX_COMB_SIZE_4 1
\r
644 #define FAPI_MAX_SRS_FREQ_POSITION 67
\r
645 #define FAPI_MAX_SRS_FD_SHIFT 268
\r
646 #define FAPI_SRS_FREQ_HOPPING_MASK 0x03
\r
647 #define FAPI_SRS_NO_HOPPING 0
\r
648 #define FAPI_SRS_GRP_OR_SEQ_HOPPING 1
\r
649 #define FAPI_SRS_SEQ_HOPPING 2
\r
650 #define FAPI_SRS_RES_ALLOC_APERIODIC 0
\r
651 #define FAPI_SRS_RES_ALLOC_SEMI_PERSISTENT 1
\r
652 #define FAPI_SRS_RES_ALLOC_PERIODIC 2
\r
653 #define FAPI_MAX_LSOT_OFFSET_VALUE 2559
\r
655 // RX_DATA Indication
\r
656 #define FAPI_UL_CQI_INVALID 255
\r
657 #define FAPI_TIMING_ADVANCE_INVALID 0xffff
\r
658 #define FAPI_MAX_TIMING_ADVANCE 63
\r
659 #define FAPI_MAX_RSSI 1280
\r
663 #define FAPI_RACH_FREQ_INDEX_MAX 7
\r
664 #define FAPI_RACH_DETECTED_PREAMBLES_MASK 0x3f
\r
665 #define FAPI_RACH_TIMING_ADVANCE_MAX 3846
\r
666 #define FAPI_RACH_PREAMBLE_POWER_INVALID 0xffffffff
\r
667 #define FAPI_RACH_PREAMBLE_TIMING_ADVANCE_INVALID 0xffff
\r
668 #define FAPI_RACH_PREAMBLE_POWER_MAX 170000
\r
670 // SR, HARQ, and CSI Part 1/2 PDUs Table 3-66
\r
671 #define FAPI_SR_MASK 0x01
\r
672 #define FAPI_HARQ_MASK 0x02
\r
673 #define FAPI_CSI_PART1 0x04
\r
674 #define FAPI_CSI_PART2 0x08
\r
675 #define FAPI_PUCCH_FORMAT2 0
\r
676 #define FAPI_PUCCH_FORMAT3 1
\r
677 #define FAPI_PUCCH_FORMAT4 2
\r
678 #define FAPI_PUCCH_FORMAT_MASK 0x03
\r
680 // SR PDU For Format 0 or 1 Table 3-67
\r
681 #define FAPI_SR_CONFIDENCE_LEVEL_GOOD 0
\r
682 #define FAPI_SR_CONFIDENCE_LEVEL_BAD 1
\r
683 #define FAPI_SR_CONFIDENCE_LEVEL_INVALID 0xff
\r
685 // HARQ PDU for Format 0 or 1 Table 3-68
\r
686 #define FAPI_HARQ_VALUE_PASS 0
\r
687 #define FAPI_HARQ_VALUE_FAIL 1
\r
688 #define FAPI_HARQ_VALUE_NOT_PRESENT 2
\r
690 // SR PDU for Format 2,3 or 4 Table 3-69
\r
691 #define FAPI_SR_PAYLOAD_MAX 1
\r
693 // HARQ PDU for Format 2,3 or 4 Table 3-70
\r
694 #define FAPI_HARQ_CRC_PASS 0
\r
695 #define FAPI_HARQ_CRC_FAIL 1
\r
696 #define FAPI_HARQ_CRC_NOT_PRESENT 2
\r
697 #define FAPI_HARQ_PAYLOAD_MAX 214
\r
700 // CSI Part 1 PDU Table 3-71 and 3-72
\r
701 #define FAPI_CSI_PARTX_CRC_PASS 0
\r
702 #define FAPI_CSI_PARTX_CRC_FAIL 1
\r
703 #define FAPI_CSI_PARTX_CRC_NOT_PRESENT 2
\r
704 #define FAPI_CSI_PARTX_PAYLOAD_MAX 214
\r
707 //------------------------------------------------------------------------------
\r
708 // FAPI callback functions to be implemented by the user
\r
709 //------------------------------------------------------------------------------
\r
711 * fapi callback structure is passed as part of ``fapi_create``. FAPI will call
\r
712 * these functions in response to any received request message.
\r
714 * *Note: vendor specific callbacks are only valid in TIMER_MODE. Must be set
\r
715 * to NULL in RADIO mode.*
\r
718 void (*fapi_param_response) (fapiInstanceHdl_t fapiHdl,
\r
719 pfapiParamResp_t resp);
\r
720 void (*fapi_config_response) (fapiInstanceHdl_t fapiHdl,
\r
721 pfapiConfigResp_t resp);
\r
722 void (*fapi_stop_ind) (fapiInstanceHdl_t fapiHdl,
\r
723 pfapiStopInd_t resp);
\r
724 void (*fapi_error_ind) (fapiInstanceHdl_t fapiHdl,
\r
725 pfapiErrorInd_t ind);
\r
726 void (*fapi_subframe_ind) (fapiInstanceHdl_t fapiHdl,
\r
727 pfapiSubframeInd_t ind);
\r
728 void (*fapi_harq_ind) (fapiInstanceHdl_t fapiHdl,
\r
729 pfapiHarqInd_t ind);
\r
730 void (*fapi_crc_ind) (fapiInstanceHdl_t fapiHdl,
\r
731 pfapiCrcInd_t ind);
\r
732 void (*fapi_rx_ulsch_ind) (fapiInstanceHdl_t fapiHdl,
\r
733 pfapiRxUlschInd_t ind);
\r
734 void (*fapi_rx_cqi_ind) (fapiInstanceHdl_t fapiHdl,
\r
735 pfapiRxCqiInd_t ind);
\r
736 void (*fapi_rx_sr_ind) (fapiInstanceHdl_t fapiHdl,
\r
737 pfapiRxSrInd_t ind);
\r
738 void (*fapi_rach_ind) (fapiInstanceHdl_t fapiHdl,
\r
739 pfapiRachInd_t ind);
\r
740 void (*fapi_srs_ind) (fapiInstanceHdl_t fapiHdl,
\r
741 pfapiSrsInd_t ind);
\r
742 //------------------------------------------------------------------------------
\r
743 // Vendor Specific Callbacks
\r
744 //------------------------------------------------------------------------------
\r
745 void (*fapi_rip_measurement) (fapiInstanceHdl_t fapiHdl,
\r
746 pfapiMeasReport_t pMeasReport);
\r
747 void (*fapi_start_phy_shutdown) (fapiInstanceHdl_t fapiHdl,
\r
749 void (*fapi_shutdown_resp) (fapiInstanceHdl_t fapiHdl,
\r
751 void (*fapi_start_cnf) (fapiInstanceHdl_t fapiHdl,
\r
753 void (*fapi_ul_iq_samples) (fapiInstanceHdl_t fapiHdl,
\r
755 void (*fapi_dl_iq_samples) (fapiInstanceHdl_t fapiHdl,
\r
757 void (*fapi_ul_copy_results_ind) (fapiInstanceHdl_t fapiHdl,
\r
760 void (*fapi_endof_phy2mac_processing) (fapiInstanceHdl_t fapiHdl,
\r
762 } fapiCb_t, *pfapiCb_t;
\r
764 //------------------------------------------------------------------------------
\r
766 fapiStatus_t fapi_init(pfapiInitConfig_t pinitConfig);
\r
767 fapiStatus_t fapi_destroy(void);
\r
768 fapiInstanceHdl_t fapi_create(pfapiCb_t callbacks,
\r
769 pfapiCreateConfig_t pCreateConfig);
\r
770 fapiStatus_t fapi_delete(fapiInstanceHdl_t fapiHdl);
\r
772 //------------------------------------------------------------------------------
\r
773 // Fapi P5 Messages
\r
774 //------------------------------------------------------------------------------
\r
775 fapiStatus_t fapi_param_request(fapiInstanceHdl_t fapiHdl,
\r
776 pfapiParamReq_t req);
\r
777 fapiStatus_t fapi_config_request(fapiInstanceHdl_t fapiHdl,
\r
778 pfapiConfigReq_t req);
\r
779 fapiStatus_t fapi_start_request(fapiInstanceHdl_t fapiHdl,
\r
780 pfapiStartReq_t req);
\r
781 fapiStatus_t fapi_stop_request(fapiInstanceHdl_t fapiHdl,
\r
782 pfapiStopReq_t req);
\r
783 //------------------------------------------------------------------------------
\r
784 // Fapi P7 Messages
\r
785 //------------------------------------------------------------------------------
\r
786 fapiStatus_t fapi_dl_config_request(fapiInstanceHdl_t fapiHdl,
\r
787 pfapiDlConfigReq_t req);
\r
788 fapiStatus_t fapi_ul_config_request(fapiInstanceHdl_t fapiHdl,
\r
789 pfapiUlConfigReq_t req);
\r
790 fapiStatus_t fapi_hi_dci0_request(fapiInstanceHdl_t fapiHdl,
\r
791 pfapiHiDci0Req_t req);
\r
792 fapiStatus_t fapi_tx_request(fapiInstanceHdl_t fapiHdl, pfapiTxReq_t
\r
Code Review / o-du / l2.git / blob