1 /******************************************************************************
3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
21 #include <sys/syscall.h>
37 #include "xran_mlog_lnx.h"
39 #include "xran_fh_o_du.h"
40 #include "xran_compression.h"
41 #include "xran_cp_api.h"
42 #include "xran_sync_api.h"
43 #include "xran_mlog_task_id.h"
45 #define MAX_BBU_POOL_CORE_MASK (4)
48 #define SW_FPGA_TOTAL_BUFFER_LEN 4*1024*1024*1024
49 #define SW_FPGA_SEGMENT_BUFFER_LEN 1*1024*1024*1024
50 #define SW_FPGA_FH_TOTAL_BUFFER_LEN 1*1024*1024*1024
51 #define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192)
53 #define NSEC_PER_SEC 1000000000
55 #define MAX_PKT_BURST (448+4) // 4x14x8
56 #define N_MAX_BUFFER_SEGMENT MAX_PKT_BURST
58 #define MAIN_PRIORITY 98
59 #define NUM_OF_SUBFRAME_PER_FRAME (10)
63 uint64_t tick_per_usec;
64 static volatile uint64_t timer_last_irq_tick = 0;
65 static uint64_t tsc_resolution_hz = 0;
67 RuntimeConfig startupConfiguration = {0};
70 uint32_t nFpgaToSW_FTH_RxBufferLen;
71 uint32_t nFpgaToSW_PRACH_RxBufferLen;
72 uint32_t nSW_ToFpga_FTH_TxBufferLen;
74 static struct xran_fh_init xranInit;
75 void * xranHandle = NULL;
77 struct xran_fh_config xranConf;
78 struct xran_fh_config *pXranConf = NULL;
82 uint32_t phaseFlag :1;
84 uint32_t SULFreShift :1;
89 typedef struct XranLibConfig
91 uint32_t nDriverCoreId;
92 uint32_t nTimingAdvance;
94 uint32_t nFhBufIntFlag;
96 uint32_t nNrOfSlotInSf;
97 uint32_t nNrofSfInFrame;
98 void * pFthInstanceHandles;
102 XRANFTHTX_PRB_MAP_OUT,
103 XRANFTHTX_SEC_DESC_OUT,
105 XRANFTHRX_PRB_MAP_IN,
106 XRANFTHTX_SEC_DESC_IN,
109 MAX_SW_XRAN_INTERFACE_NUM
110 }SWXRANInterfaceTypeEnum;
113 * manage one cell's all Ethernet frames for one DL or UL LTE subframe
116 /* -1-this subframe is not used in current frame format
117 0-this subframe can be transmitted, i.e., data is ready
118 1-this subframe is waiting transmission, i.e., data is not ready
119 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1,
122 int32_t bValid ; // when UL rx, it is subframe index.
124 int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE
125 // -1 means that DL packet to be transmitted is not ready in BS
126 int32_t nSegTransferred; // number of data segments has been transmitted or received
127 struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool
128 struct xran_buffer_list sBufferList;
129 } BbuIoBufCtrlStruct;
134 uint8_t nDriverCoreId;
137 struct rte_mempool *bbuio_buf_pool;
140 BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
141 BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
142 BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
143 BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
144 BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
147 BbuIoBufCtrlStruct sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
150 struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
151 struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
152 struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
153 struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
154 struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
156 /* Cat B SRS buffers */
157 struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
159 void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector
160 uint32_t nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool
161 uint16_t nInstanceNum;
163 uint64_t nTscTiming[XRAN_N_FE_BUF_LEN]; // records the TSC when a timing packet is received.
166 static BbuXranIoIfStruct gsXranIoIf;
167 static XranLibConfigStruct *gpXranLibConfig = NULL;
169 extern long rx_counter;
170 extern long tx_counter;
171 extern long tx_bytes_counter;
172 extern long rx_bytes_counter;
173 extern long tx_bytes_per_sec;
174 extern long rx_bytes_per_sec;
175 long old_rx_counter = 0;
176 long old_tx_counter = 0;
180 #define CPU_HZ tick_per_usec //us
182 /* Application User space functions */
183 void xran_fh_rx_callback(void *pCallbackTag, int32_t status);
184 void xran_fh_rx_prach_callback(void *pCallbackTag, int32_t status);
186 static BbuXranIoIfStruct *xran_get_ctx(void)
191 static void print_menu()
193 puts("+---------------------------------------+");
194 puts("| Press 1 to start 5G NR XRAN traffic |");
195 puts("| Press 2 reserved for future use |");
196 puts("| Press 3 to quit |");
197 puts("+---------------------------------------+");
200 static int32_t get_xran_sfidx(uint8_t nNrOfSlotInSf)
204 uint32_t nSubframeIdx;
208 uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
209 nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf
210 + nSubframeIdx*nNrOfSlotInSf
213 printf("\nxranTime is %d, return is %d, radio frame is %d, subframe is %d slot is %d tsc is %llu us",
225 void xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
227 uint64_t t1 = MLogTick();
228 uint32_t mlogVar[10];
229 uint32_t mlogVarCnt = 0;
230 uint8_t Numerlogy = xranConf.frame_conf.nNumerology;
231 uint8_t nNrOfSlotInSf = 1<<Numerlogy;
232 int32_t sfIdx = get_xran_sfidx(nNrOfSlotInSf);
234 mlogVar[mlogVarCnt++] = 0xCCCCCCCC;
235 mlogVar[mlogVarCnt++] = status >> 16; /* tti */
236 mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */
237 mlogVar[mlogVarCnt++] = (uint32_t)sfIdx;
238 MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
241 MLogTask(PID_GNB_SYM_CB, t1, MLogTick());
245 void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
247 uint64_t t1 = MLogTick();
248 uint32_t mlogVar[10];
249 uint32_t mlogVarCnt = 0;
251 mlogVar[mlogVarCnt++] = 0xDDDDDDDD;
252 mlogVar[mlogVarCnt++] = status >> 16; /* tti */
253 mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */
254 MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
257 MLogTask(PID_GNB_PRACH_CB, t1, MLogTick());
260 void xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status)
262 uint64_t t1 = MLogTick();
263 uint32_t mlogVar[10];
264 uint32_t mlogVarCnt = 0;
266 mlogVar[mlogVarCnt++] = 0xCCCCCCCC;
267 mlogVar[mlogVarCnt++] = status >> 16; /* tti */
268 mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */
269 MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
272 MLogTask(PID_GNB_SRS_CB, t1, MLogTick());
276 //-------------------------------------------------------------------------------------------
277 /** @ingroup group_nbiot_source_auxlib_timer
284 * This function reads the rtdsc clock and returns the current value in there.
287 //-------------------------------------------------------------------------------------------
288 unsigned long timer_get_ticks(void)
293 unsigned long tsc_64;
301 __asm volatile("rdtsc" :
305 ret = ((unsigned long)tsc.tsc_64);
309 //-------------------------------------------------------------------------------------------
310 /** @ingroup group_lte_source_auxlib_timer
314 * @return 0 if SUCCESS
317 * This function gets the clock speed of the core and figures out number of ticks per usec.
318 * It is used by l1app and testmac applications to initialize the mlog utility
321 //-------------------------------------------------------------------------------------------
322 int timer_set_tsc_freq_from_clock(void)
324 #define NS_PER_SEC 1E9
325 struct timespec sleeptime = {.tv_nsec = 5E8 }; /* 1/2 second */
326 struct timespec t_start, t_end;
327 uint64_t tsc_resolution_hz = 0;
329 if (clock_gettime(CLOCK_MONOTONIC_RAW, &t_start) == 0)
331 unsigned long ns, end, start = timer_get_ticks();
332 nanosleep(&sleeptime,NULL);
333 clock_gettime(CLOCK_MONOTONIC_RAW, &t_end);
334 end = timer_get_ticks();
335 ns = ((t_end.tv_sec - t_start.tv_sec) * NS_PER_SEC);
336 ns += (t_end.tv_nsec - t_start.tv_nsec);
338 double secs = (double)ns/NS_PER_SEC;
339 tsc_resolution_hz = (unsigned long)((end - start)/secs);
341 tick_per_usec = (tsc_resolution_hz / 1000000);
342 printf("System clock (rdtsc) resolution %lu [Hz]\n", tsc_resolution_hz);
343 printf("Ticks per us %lu\n", tick_per_usec);
350 int physide_dl_tti_call_back(void * param)
352 uint64_t t1 = MLogTick();
354 MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
358 int physide_ul_half_slot_call_back(void * param)
360 uint64_t t1 = MLogTick();
362 MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
366 int physide_ul_full_slot_call_back(void * param)
368 uint64_t t1 = MLogTick();
370 MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
374 int32_t init_xran(void)
376 BbuXranIoIfStruct *psBbuIo = xran_get_ctx();
377 xran_status_t status;
378 int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
388 SWXRANInterfaceTypeEnum eInterfaceType;
390 XranLibConfigStruct *ptrLibConfig;
392 struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
393 struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
394 struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
395 struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
396 struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
397 struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
399 for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
401 nSectorIndex[nSectorNum] = nSectorNum;
404 nSectorNum = numCCPorts;
405 printf ("XRAN front haul xran_mm_init \n");
406 status = xran_mm_init (xranHandle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);
407 if (status != XRAN_STATUS_SUCCESS)
409 printf ("Failed at XRAN front haul xran_mm_init \n");
413 psBbuIo->nInstanceNum = numCCPorts;
415 for (k = 0; k < XRAN_PORTS_NUM; k++) {
416 status = xran_sector_get_instances (xranHandle, psBbuIo->nInstanceNum,&psBbuIo->nInstanceHandle[k][0]);
417 if (status != XRAN_STATUS_SUCCESS)
419 printf ("get sector instance failed %d for XRAN nInstanceNum %d\n",k, psBbuIo->nInstanceNum);
422 for (i = 0; i < psBbuIo->nInstanceNum; i++){
423 printf("%s [%d]: CC %d handle %p\n", __FUNCTION__, k, i, psBbuIo->nInstanceHandle[0][i]);
427 printf("Sucess xran_mm_init \n");
428 gpXranLibConfig = (XranLibConfigStruct*)malloc(sizeof(XranLibConfigStruct));
429 ptrLibConfig = gpXranLibConfig;
433 ptrLibConfig->nDriverCoreId = psBbuIo->nDriverCoreId;
434 ptrLibConfig->pFecInstanceHandles = &(psBbuIo->nInstanceHandle[FPGA_FEC][0]);
435 ptrLibConfig->pFthInstanceHandles = &(psBbuIo->nInstanceHandle[FPGA_FRONTHAUL][0]);
436 ptrLibConfig->nTimingAdvance = psFPGAInitPara->nTimeAdvance;
437 ptrLibConfig->nFhConfig = psFPGAInitPara->nEthPorts;
438 ptrLibConfig->nFhBufIntFlag = 0; //need init fronthaul buffer, then set to 1.
439 ptrLibConfig->nNrofSfInFrame = NUM_OF_SUBFRAME_PER_FRAME;
440 ptrLibConfig->nNrOfSlotInSf = pConfigParams->nNumOfSlotPerSubframe;
441 if (pConfigParams->nNumerology < 3)
443 ptrLibConfig->nSectorNum = psFPGAInitPara->nSecNum;
449 printf ("could not allocate ptrLibConfig in init_xran\n");
453 printf("nSectorNum %d\n", nSectorNum);
456 for(i = 0; i<nSectorNum; i++)
458 eInterfaceType = XRANFTHTX_OUT;
459 printf("nSectorIndex[%d] = %d\n",i, nSectorIndex[i]);
460 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
461 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
462 if(XRAN_STATUS_SUCCESS != status) {
463 rte_panic("Failed at xran_bm_init , status %d\n", status);
465 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
467 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
468 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0;
469 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
470 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
471 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
472 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
473 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulTxBuffers[j][i][z][0];
475 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
477 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol
478 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
479 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
480 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
481 if(XRAN_STATUS_SUCCESS != status){
482 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
484 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
485 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
488 u32dptr = (uint32_t*)(ptr);
489 uint8_t *ptr_temp = (uint8_t *)ptr;
490 memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen);
491 // ptr_temp[0] = j; // TTI
492 // ptr_temp[1] = i; // Sec
493 // ptr_temp[2] = z; // Ant
494 // ptr_temp[3] = k; // sym
501 eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
502 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
503 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
504 if(XRAN_STATUS_SUCCESS != status) {
505 rte_panic("Failed at xran_bm_init , status %d\n", status);
508 eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
509 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
510 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
511 if(XRAN_STATUS_SUCCESS != status) {
512 rte_panic("Failed at xran_bm_init , status %d\n", status);
515 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
517 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
518 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
519 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
520 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
521 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
522 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
523 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulTxPrbMapBuffers[j][i][z];
526 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
527 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
528 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
529 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
530 if(XRAN_STATUS_SUCCESS != status) {
531 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
533 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
534 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
540 struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
541 if (startupConfiguration.appMode == APP_O_DU)
542 memcpy(ptr, &startupConfiguration.PrbMapDl, sizeof(struct xran_prb_map));
544 memcpy(ptr, &startupConfiguration.PrbMapUl, sizeof(struct xran_prb_map));
546 for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
547 struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
548 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
549 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT],&sd_ptr, &sd_mb);
550 if(XRAN_STATUS_SUCCESS != status){
551 rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status);
553 pPrbElem->p_sec_desc[k] = sd_ptr;
562 for(i = 0; i<nSectorNum; i++)
564 eInterfaceType = XRANFTHRX_IN;
565 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
566 if(XRAN_STATUS_SUCCESS != status)
568 printf("Failed at xran_bm_init, status %d\n", status);
569 iAssert(status == XRAN_STATUS_SUCCESS);
572 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
574 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
575 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0;
576 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
577 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
578 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
579 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
580 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulRxBuffers[j][i][z][0];
581 for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
583 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nFpgaToSW_FTH_RxBufferLen; // 1 symbols 3200bytes
584 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
585 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
586 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
587 if(XRAN_STATUS_SUCCESS != status) {
588 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
590 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
591 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb;
593 u32dptr = (uint32_t*)(ptr);
594 uint8_t *ptr_temp = (uint8_t *)ptr;
595 memset(u32dptr, 0x0, nFpgaToSW_FTH_RxBufferLen);
596 // ptr_temp[0] = j; // TTI
597 // ptr_temp[1] = i; // Sec
598 // ptr_temp[2] = z; // Ant
599 // ptr_temp[3] = k; // sym
606 eInterfaceType = XRANFTHTX_SEC_DESC_IN;
607 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
608 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
609 if(XRAN_STATUS_SUCCESS != status) {
610 rte_panic("Failed at xran_bm_init , status %d\n", status);
612 eInterfaceType = XRANFTHRX_PRB_MAP_IN;
613 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
614 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
615 if(XRAN_STATUS_SUCCESS != status) {
616 rte_panic("Failed at xran_bm_init, status %d\n", status);
619 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
620 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
621 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
622 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
623 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
624 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
625 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
626 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulRxPrbMapBuffers[j][i][z];
628 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
629 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
630 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
631 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
632 if(XRAN_STATUS_SUCCESS != status) {
633 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
635 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
636 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
641 struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
643 if (startupConfiguration.appMode == APP_O_DU)
644 memcpy(ptr, &startupConfiguration.PrbMapUl, sizeof(struct xran_prb_map));
646 memcpy(ptr, &startupConfiguration.PrbMapDl, sizeof(struct xran_prb_map));
648 for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
649 struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
650 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
651 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN],&sd_ptr, &sd_mb);
652 if(XRAN_STATUS_SUCCESS != status){
653 rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status);
655 pPrbElem->p_sec_desc[k] = sd_ptr;
665 // add prach rx buffer
666 for(i = 0; i<nSectorNum; i++)
668 eInterfaceType = XRANFTHRACH_IN;
669 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
670 if(XRAN_STATUS_SUCCESS != status) {
671 rte_panic("Failed at xran_bm_init, status %d\n", status);
673 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
675 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
676 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
677 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
678 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
679 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
680 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR; // ant number.
681 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHPrachRxBuffers[j][i][z][0];
682 for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
684 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN;
685 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
686 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
687 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
688 if(XRAN_STATUS_SUCCESS != status) {
689 rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status);
691 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
692 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
694 u32dptr = (uint32_t*)(ptr);
695 memset(u32dptr, 0x0, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
702 /* add SRS rx buffer */
703 for(i = 0; i<nSectorNum; i++)
705 eInterfaceType = XRANSRS_IN;
706 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
707 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANT_ARRAY_ELM_NR*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
709 if(XRAN_STATUS_SUCCESS != status) {
710 rte_panic("Failed at xran_bm_init, status %d\n", status);
712 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
714 for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
715 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0;
716 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
717 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
718 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
719 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANT_ARRAY_ELM_NR; /* ant number */
720 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHSrsRxBuffers[j][i][z][0];
721 for(k = 0; k < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; k++)
723 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen;
724 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
725 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
726 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
727 if(XRAN_STATUS_SUCCESS != status) {
728 rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status);
730 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
731 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
733 u32dptr = (uint32_t*)(ptr);
734 memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen);
742 for(i=0; i<nSectorNum; i++)
744 for(j=0; j<XRAN_N_FE_BUF_LEN; j++)
746 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
747 pFthTxBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
748 pFthTxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
749 pFthRxBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
750 pFthRxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
751 pFthRxRachBuffer[i][z][j] = &(psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
754 for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
755 pFthRxSrsBuffer[i][z][j] = &(psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList);
760 if(NULL != psBbuIo->nInstanceHandle[0])
762 /* add pusch callback */
763 for (i = 0; i<nSectorNum; i++)
765 xran_5g_fronthault_config (psBbuIo->nInstanceHandle[0][i],
767 pFthTxPrbMapBuffer[i],
769 pFthRxPrbMapBuffer[i],
770 xran_fh_rx_callback, &pFthRxBuffer[i][0]);
773 /* add prach callback here */
774 for (i = 0; i<nSectorNum; i++)
776 xran_5g_prach_req(psBbuIo->nInstanceHandle[0][i], pFthRxRachBuffer[i],
777 xran_fh_rx_prach_callback,&pFthRxRachBuffer[i][0]);
780 /* add SRS callback here */
781 for (i = 0; i<nSectorNum; i++) {
782 xran_5g_srs_req(psBbuIo->nInstanceHandle[0][i], pFthRxSrsBuffer[i],
783 xran_fh_rx_srs_callback,&pFthRxSrsBuffer[i][0]);
786 ptrLibConfig->nFhBufIntFlag = 1;
792 int init_xran_iq_content(void)
794 BbuXranIoIfStruct *psBbuIo = xran_get_ctx();
795 xran_status_t status;
796 int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
798 int32_t cc_id, ant_id, sym_id, tti;
801 uint8_t frame_id = 0;
802 uint8_t subframe_id = 0;
812 struct xran_prb_map *pRbMap = NULL;
814 for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
816 nSectorIndex[nSectorNum] = nSectorNum;
818 nSectorNum = numCCPorts;
819 printf ("init_xran_iq_content\n");
822 for(cc_id = 0; cc_id <nSectorNum; cc_id++)
824 for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) {
825 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
826 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
828 flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
829 if(p_tx_play_buffer[flowId]){
831 pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
833 if (xranInit.DynamicSectionEna == 0){
834 pRbMap->dir = XRAN_DIR_DL;
835 pRbMap->xran_port = 0;
837 pRbMap->cc_id = cc_id;
838 pRbMap->ru_port_id = ant_id;
839 pRbMap->tti_id = tti;
840 pRbMap->start_sym_id = 0;
842 pRbMap->prbMap[0].nStartSymb = 0;
843 pRbMap->prbMap[0].numSymb = 14;
844 pRbMap->prbMap[0].nRBStart = 0;
845 pRbMap->prbMap[0].nRBSize = pXranConf->nDLRBs;
846 pRbMap->prbMap[0].nBeamIndex = 0;
847 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
848 pRbMap->prbMap[0].iqWidth = 16;
849 } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
850 && startupConfiguration.appMode == APP_O_DU
851 && sym_id == 0){ /* BF Ws are per slot */
853 char* dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
854 struct xran_prb_elm* p_pRbMapElm = NULL;
855 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
856 p_pRbMapElm = &pRbMap->prbMap[idxElm];
857 p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx;
858 if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update){
859 int16_t ext_len = 9600;
860 int16_t ext_sec_total = 0;
861 int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
866 ext_buf += (RTE_PKTMBUF_HEADROOM +
867 sizeof (struct xran_ecpri_hdr) +
868 sizeof(struct xran_cp_radioapp_section1));
870 ext_len -= (RTE_PKTMBUF_HEADROOM +
871 sizeof (struct xran_ecpri_hdr) +
872 sizeof(struct xran_cp_radioapp_section1));
873 ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
875 (int16_t *) (dl_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4),
876 p_pRbMapElm->nRBSize,
877 pXranConf->nAntElmTRx,
878 p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
879 if(ext_sec_total > 0){
880 p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
881 p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
883 rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
886 rte_panic("xran_malloc return NULL\n");
892 printf("DL pRbMap ==NULL\n");
896 pos = ((char*)p_tx_play_buffer[flowId]) + tx_play_buffer_position[flowId];
897 ptr = psBbuIo->sFrontHaulTxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
901 u8dptr = (uint8_t*)ptr;
902 int16_t payload_len = 0;
904 uint8_t *dst = (uint8_t *)u8dptr;
905 uint8_t *src = (uint8_t *)pos;
906 struct xran_prb_elm* p_prbMapElm = &pRbMap->prbMap[idxElm];
907 dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod);
908 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
909 struct xran_section_desc *p_sec_desc = NULL;
910 p_prbMapElm = &pRbMap->prbMap[idxElm];
911 p_sec_desc = p_prbMapElm->p_sec_desc[sym_id];
913 if(p_sec_desc == NULL){
914 printf ("p_sec_desc == NULL\n");
917 src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L);
919 if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) {
920 payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
921 rte_memcpy(dst, src, payload_len);
923 } else if (p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT) {
924 struct xranlib_compress_request bfp_com_req;
925 struct xranlib_compress_response bfp_com_rsp;
927 memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request));
928 memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
930 bfp_com_req.data_in = (int16_t*)src;
931 bfp_com_req.numRBs = p_prbMapElm->nRBSize;
932 bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
933 bfp_com_req.compMethod = p_prbMapElm->compMethod;
934 bfp_com_req.iqWidth = p_prbMapElm->iqWidth;
936 bfp_com_rsp.data_out = (int8_t*)dst;
939 if(xranlib_compress_avx512(&bfp_com_req, &bfp_com_rsp) < 0){
940 printf ("compression failed [%d]\n",
941 p_prbMapElm->compMethod);
944 payload_len = bfp_com_rsp.len;
947 printf ("p_prbMapElm->compMethod == %d is not supported\n",
948 p_prbMapElm->compMethod);
952 /* update RB map for given element */
953 p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr);
954 p_sec_desc->iq_buffer_len = payload_len;
956 /* add headroom for ORAN headers between IQs for chunk of RBs*/
958 dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod);
962 printf("ptr ==NULL\n");
967 pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
969 if (xranInit.DynamicSectionEna == 0){
970 pRbMap->dir = XRAN_DIR_UL;
971 pRbMap->xran_port = 0;
973 pRbMap->cc_id = cc_id;
974 pRbMap->ru_port_id = ant_id;
975 pRbMap->tti_id = tti;
976 pRbMap->start_sym_id = 0;
978 pRbMap->prbMap[0].nRBStart = 0;
979 pRbMap->prbMap[0].nRBSize = pXranConf->nULRBs;
980 pRbMap->prbMap[0].nStartSymb = 0;
981 pRbMap->prbMap[0].numSymb = 14;
982 pRbMap->prbMap[0].p_sec_desc[sym_id]->iq_buffer_offset = 0;
983 pRbMap->prbMap[0].p_sec_desc[sym_id]->iq_buffer_len = pXranConf->nULRBs *4L;
984 pRbMap->prbMap[0].nBeamIndex = 0;
985 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
986 } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
987 && startupConfiguration.appMode == APP_O_DU
990 char * ul_bfw_pos = ((char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId];
991 struct xran_prb_elm* p_pRbMapElm = NULL;
993 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
994 p_pRbMapElm = &pRbMap->prbMap[idxElm];
995 p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx;
996 if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update){
997 int16_t ext_len = 9600;
998 int16_t ext_sec_total = 0;
999 int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
1001 int16_t *ptr = NULL;
1004 ext_buf += (RTE_PKTMBUF_HEADROOM +
1005 sizeof (struct xran_ecpri_hdr) +
1006 sizeof(struct xran_cp_radioapp_section1));
1008 ext_len -= (RTE_PKTMBUF_HEADROOM +
1009 sizeof (struct xran_ecpri_hdr) +
1010 sizeof(struct xran_cp_radioapp_section1));
1011 ptr = (int16_t*)(ul_bfw_pos +(p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4);
1012 ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
1014 (int16_t *) (ul_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4),
1015 p_pRbMapElm->nRBSize,
1016 pXranConf->nAntElmTRx,
1017 p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
1018 if(ext_sec_total > 0){
1019 p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
1020 p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
1022 rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
1025 rte_panic("xran_malloc return NULL\n");
1031 printf("DL pRbMap ==NULL\n");
1035 tx_play_buffer_position[flowId] += pXranConf->nDLRBs*N_SC_PER_PRB*4;
1037 if(tx_play_buffer_position[flowId] >= tx_play_buffer_size[flowId])
1038 tx_play_buffer_position[flowId] = 0;
1040 if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
1041 && startupConfiguration.appMode == APP_O_DU
1043 tx_dl_bfw_buffer_position[flowId] += (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4;
1044 if(tx_dl_bfw_buffer_position[flowId] >= tx_dl_bfw_buffer_size[flowId])
1045 tx_dl_bfw_buffer_position[flowId] = 0;
1047 tx_ul_bfw_buffer_position[flowId] += (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4;
1048 if(tx_ul_bfw_buffer_position[flowId] >= tx_ul_bfw_buffer_size[flowId])
1049 tx_ul_bfw_buffer_position[flowId] = 0;
1052 //printf("flowId %d\n", flowId);
1057 /* prach TX for RU only */
1058 if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
1059 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
1060 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
1061 flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
1063 if(p_tx_prach_play_buffer[flowId]){
1064 pos = ((char*)p_tx_prach_play_buffer[flowId]);
1066 ptr = psBbuIo->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
1069 u32dptr = (uint32_t*)(ptr);
1070 /* duplicate full PRACH (repetition * occassions ) in every symbol */
1071 memset(u32dptr,0 , PRACH_PLAYBACK_BUFFER_BYTES);
1072 rte_memcpy(u32dptr, pos, RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, tx_prach_play_buffer_size[flowId]));
1075 printf("ptr ==NULL\n");
1078 //printf("flowId %d\n", flowId);
1084 /* SRS TX for RU only */
1085 if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
1086 for(ant_id = 0; ant_id < XRAN_MAX_ANT_ARRAY_ELM_NR; ant_id++){
1087 for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) {
1088 flowId = XRAN_MAX_ANT_ARRAY_ELM_NR*cc_id + ant_id;
1090 if(p_tx_srs_play_buffer[flowId]){
1091 pos = ((char*)p_tx_srs_play_buffer[flowId]) + tx_srs_play_buffer_position[flowId];
1092 ptr = psBbuIo->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
1094 if(startupConfiguration.srsSymMask & (1 << sym_id) ){
1096 u32dptr = (uint32_t*)(ptr);
1097 memset(u32dptr,0 , pXranConf->nULRBs*N_SC_PER_PRB*4);
1098 rte_memcpy(u32dptr, pos, pXranConf->nULRBs*N_SC_PER_PRB*4);
1101 printf("ptr ==NULL\n");
1105 tx_srs_play_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
1107 if(tx_srs_play_buffer_position[flowId] >= tx_srs_play_buffer_size[flowId])
1108 tx_srs_play_buffer_position[flowId] = 0;
1110 //printf("flowId %d\n", flowId);
1121 void stop_xran(void)
1123 xran_status_t status = 0;
1124 SWXRANInterfaceTypeEnum eInterfaceType;
1126 free(gpXranLibConfig);
1127 gpXranLibConfig = NULL;
1129 status += xran_mm_destroy(xranHandle)*2;
1131 if(XRAN_STATUS_SUCCESS != status)
1133 printf("Failed at xran_mm_destroy, status %d\n",status);
1134 iAssert(status == XRAN_STATUS_SUCCESS);
1138 int get_xran_iq_content(void)
1140 BbuXranIoIfStruct *psBbuIo = xran_get_ctx();
1141 xran_status_t status;
1142 int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
1144 int32_t cc_id, ant_id, sym_id, tti;
1147 uint8_t frame_id = 0;
1148 uint8_t subframe_id = 0;
1149 uint8_t slot_id = 0;
1159 for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
1161 nSectorIndex[nSectorNum] = nSectorNum;
1163 nSectorNum = numCCPorts;
1164 printf ("get_xran_iq_content\n");
1167 for(cc_id = 0; cc_id <nSectorNum; cc_id++)
1169 for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti++) {
1170 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
1172 struct xran_prb_map *pRbMap = NULL;
1173 struct xran_prb_elm *pRbElm = NULL;
1174 struct xran_section_desc *p_sec_desc = NULL;
1175 pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
1178 flowId = XRAN_MAX_ANTENNA_NR * cc_id + ant_id;
1179 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
1180 pRbElm = &pRbMap->prbMap[0];
1181 if(pRbMap->nPrbElm == 1){
1182 if(p_rx_log_buffer[flowId]) {
1183 pos = ((char*)p_rx_log_buffer[flowId]) + rx_log_buffer_position[flowId];
1184 ptr = psBbuIo->sFrontHaulRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
1186 u32dptr = (uint32_t*)(ptr);
1187 char* my_ptr =(char *)ptr;
1188 rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L);
1190 printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id);
1194 for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
1195 pRbElm = &pRbMap->prbMap[idxElm];
1196 p_sec_desc = pRbElm->p_sec_desc[sym_id];
1197 if(p_rx_log_buffer[flowId] && p_sec_desc){
1198 if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){
1199 pos = ((char*)p_rx_log_buffer[flowId]) + rx_log_buffer_position[flowId];
1200 ptr = p_sec_desc->pData;
1202 int32_t payload_len = 0;
1203 u32dptr = (uint32_t*)(ptr);
1204 if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){
1205 struct xranlib_decompress_request bfp_decom_req;
1206 struct xranlib_decompress_response bfp_decom_rsp;
1208 memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
1209 memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
1211 bfp_decom_req.data_in = (int8_t *)u32dptr;
1212 bfp_decom_req.numRBs = pRbElm->nRBSize;
1213 bfp_decom_req.len = (3* pRbElm->iqWidth + 1)*pRbElm->nRBSize;
1214 bfp_decom_req.compMethod = pRbElm->compMethod;
1215 bfp_decom_req.iqWidth = pRbElm->iqWidth;
1217 bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
1218 bfp_decom_rsp.len = 0;
1220 if(xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp) < 0){
1221 printf ("compression failed [%d]\n",
1222 pRbElm->compMethod);
1225 payload_len = bfp_decom_rsp.len;
1228 rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4);
1235 rx_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
1237 if(rx_log_buffer_position[flowId] >= rx_log_buffer_size[flowId])
1238 rx_log_buffer_position[flowId] = 0;
1241 /* prach RX for O-DU only */
1242 if(startupConfiguration.appMode == APP_O_DU) {
1243 flowId = XRAN_MAX_ANTENNA_NR * cc_id + ant_id;
1244 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++){
1245 if(p_prach_log_buffer[flowId]){
1246 /* (0-79 slots) 10ms of IQs */
1247 pos = ((char*)p_prach_log_buffer[flowId]) + prach_log_buffer_position[flowId];
1248 ptr = psBbuIo->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; //8192 144
1250 u32dptr = (uint32_t*)(ptr);
1251 rte_memcpy(pos, u32dptr, PRACH_PLAYBACK_BUFFER_BYTES);
1253 printf("ptr ==NULL\n");
1255 prach_log_buffer_position[flowId] += PRACH_PLAYBACK_BUFFER_BYTES;
1257 if(prach_log_buffer_position[flowId] >= prach_log_buffer_size[flowId])
1258 prach_log_buffer_position[flowId] = 0;
1260 //printf("flowId %d\n", flowId);
1266 /* SRS RX for O-DU only */
1267 if(startupConfiguration.appMode == APP_O_DU) {
1268 for(ant_id = 0; ant_id < XRAN_MAX_ANT_ARRAY_ELM_NR; ant_id++){
1269 flowId = XRAN_MAX_ANT_ARRAY_ELM_NR*cc_id + ant_id;
1270 for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++){
1271 if(p_srs_log_buffer[flowId]){
1272 pos = ((char*)p_srs_log_buffer[flowId]) + srs_log_buffer_position[flowId];
1273 ptr = psBbuIo->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
1275 u32dptr = (uint32_t*)(ptr);
1276 rte_memcpy(pos, u32dptr, pXranConf->nULRBs*N_SC_PER_PRB*4);
1278 printf("ptr ==NULL\n");
1280 srs_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
1282 if(srs_log_buffer_position[flowId] >= srs_log_buffer_size[flowId])
1283 srs_log_buffer_position[flowId] = 0;
1285 //printf("flowId %d\n", flowId);
1296 void version_print(void)
1298 char sysversion[100];
1299 char *compilation_date = __DATE__;
1300 char *compilation_time = __TIME__;
1305 snprintf(sysversion, 99, "Version: %s", VERSIONX);
1306 nLen = strlen(sysversion);
1309 printf("===========================================================================================================\n");
1310 printf("SAMPLE-APP VERSION\n");
1311 printf("===========================================================================================================\n");
1313 printf("%s\n", sysversion);
1314 printf("build-date: %s\n", compilation_date);
1315 printf("build-time: %s\n", compilation_time);
1318 int main(int argc, char *argv[])
1324 char prefix_name[256];
1325 uint32_t nCenterFreq;
1327 struct stat st = {0};
1328 uint32_t filenameLength = strlen(argv[1]);
1329 char *pCheckName1 = NULL, *pCheckName2 = NULL;
1330 enum xran_if_state xran_curr_if_state = XRAN_INIT;
1332 uint64_t nMask = (uint64_t)1;
1333 uint16_t nCoreUsage[4*64+1];
1334 uint16_t nCoreId[4*64];
1336 uint64_t nTotalTime;
1343 errx(2, "Need two argument - the PCI address of the network port");
1344 if (filenameLength >= 256)
1346 printf("Config file name input is too long, exiting!\n");
1353 len = strlen(argv[1]) + 1;
1354 if (len > (sizeof(filename) - 10))
1355 len = (sizeof(filename) - 10);
1356 strncpy(filename, argv[1], (sizeof(filename) - 10));
1357 filename[len] = '\0';
1359 if (xran_is_synchronized() != 0)
1360 printf("Machine is not synchronized using PTP!\n");
1362 printf("Machine is synchronized using PTP!\n");
1364 memset(&startupConfiguration, 0, sizeof(RuntimeConfig));
1366 if (parseConfigFile(filename, (RuntimeConfig*)&startupConfiguration) != 0) {
1367 printf("Configuration file error.\n");
1371 if(startupConfiguration.ant_file[0] == NULL){
1372 printf("it looks like test vector for antennas were not provided\n");
1376 if (startupConfiguration.numCC > XRAN_MAX_SECTOR_NR) {
1377 printf("Number of cells %d exceeds max number supported %d!\n", startupConfiguration.numCC, XRAN_MAX_SECTOR_NR);
1378 startupConfiguration.numCC = XRAN_MAX_SECTOR_NR;
1381 if (startupConfiguration.antElmTRx > XRAN_MAX_ANT_ARRAY_ELM_NR) {
1382 printf("Number of Antenna elements %d exceeds max number supported %d!\n", startupConfiguration.antElmTRx, XRAN_MAX_ANT_ARRAY_ELM_NR);
1383 startupConfiguration.antElmTRx = XRAN_MAX_ANT_ARRAY_ELM_NR;
1386 numCCPorts = startupConfiguration.numCC;
1387 num_eAxc = startupConfiguration.numAxc;
1389 printf("numCCPorts %d num_eAxc%d\n", numCCPorts, num_eAxc);
1391 if (startupConfiguration.mu_number <= 1){
1392 nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/
1393 nFpgaToSW_PRACH_RxBufferLen = 8192;
1394 nSW_ToFpga_FTH_TxBufferLen = 13168 + /* 273*12*4 + 64* + ETH AND ORAN HDRs */
1395 XRAN_MAX_SECTIONS_PER_SYM* (RTE_PKTMBUF_HEADROOM + sizeof(struct ether_hdr) +
1396 sizeof(struct xran_ecpri_hdr) +
1397 sizeof(struct radio_app_common_hdr) +
1398 sizeof(struct data_section_hdr));
1399 } else if (startupConfiguration.mu_number == 3){
1400 nFpgaToSW_FTH_RxBufferLen = 3328;
1401 nFpgaToSW_PRACH_RxBufferLen = 8192;
1402 nSW_ToFpga_FTH_TxBufferLen = 3328 +
1403 XRAN_MAX_SECTIONS_PER_SYM * (RTE_PKTMBUF_HEADROOM + sizeof(struct ether_hdr) +
1404 sizeof(struct xran_ecpri_hdr) +
1405 sizeof(struct radio_app_common_hdr) +
1406 sizeof(struct data_section_hdr));
1408 printf("given numerology is not supported %d\n", startupConfiguration.mu_number);
1411 printf("nSW_ToFpga_FTH_TxBufferLen %d\n", nSW_ToFpga_FTH_TxBufferLen);
1413 memset(&xranInit, 0, sizeof(struct xran_fh_init));
1415 if(startupConfiguration.appMode == APP_O_DU) {
1416 printf("set O-DU\n");
1417 xranInit.io_cfg.id = 0;/* O-DU */
1418 xranInit.io_cfg.core = startupConfiguration.io_core;
1419 xranInit.io_cfg.system_core = startupConfiguration.system_core;
1420 xranInit.io_cfg.pkt_proc_core = startupConfiguration.pkt_proc_core;
1421 xranInit.io_cfg.pkt_aux_core = startupConfiguration.pkt_aux_core; /* do not start*/
1422 xranInit.io_cfg.timing_core = startupConfiguration.timing_core;
1424 printf("set O-RU\n");
1425 xranInit.io_cfg.id = 1; /* O-RU*/
1426 xranInit.io_cfg.core = startupConfiguration.io_core;
1427 xranInit.io_cfg.system_core = startupConfiguration.system_core;
1428 xranInit.io_cfg.pkt_proc_core = startupConfiguration.pkt_proc_core;
1429 xranInit.io_cfg.pkt_aux_core = startupConfiguration.pkt_aux_core; /* do not start*/
1430 xranInit.io_cfg.timing_core = startupConfiguration.timing_core;
1436 thread = pthread_self();
1438 CPU_SET(xranInit.io_cfg.system_core,&cpuset);
1439 pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset);
1441 handle_error_en(s, "pthread_setaffinity_np");
1444 xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
1446 if(startupConfiguration.xranCat == XRAN_CATEGORY_A){
1447 xranInit.eAxCId_conf.mask_cuPortId = 0xf000;
1448 xranInit.eAxCId_conf.mask_bandSectorId = 0x0f00;
1449 xranInit.eAxCId_conf.mask_ccId = 0x00f0;
1450 xranInit.eAxCId_conf.mask_ruPortId = 0x000f;
1451 xranInit.eAxCId_conf.bit_cuPortId = 12;
1452 xranInit.eAxCId_conf.bit_bandSectorId = 8;
1453 xranInit.eAxCId_conf.bit_ccId = 4;
1454 xranInit.eAxCId_conf.bit_ruPortId = 0;
1456 xranInit.eAxCId_conf.mask_cuPortId = 0xf000;
1457 xranInit.eAxCId_conf.mask_bandSectorId = 0x0c00;
1458 xranInit.eAxCId_conf.mask_ccId = 0x0300;
1459 xranInit.eAxCId_conf.mask_ruPortId = 0x00ff; /* more than [0-127] eAxC */
1460 xranInit.eAxCId_conf.bit_cuPortId = 12;
1461 xranInit.eAxCId_conf.bit_bandSectorId = 10;
1462 xranInit.eAxCId_conf.bit_ccId = 8;
1463 xranInit.eAxCId_conf.bit_ruPortId = 0;
1466 xranInit.io_cfg.dpdk_dev[XRAN_UP_VF] = argv[2];
1467 xranInit.io_cfg.dpdk_dev[XRAN_CP_VF] = argv[3];
1468 xranInit.mtu = startupConfiguration.mtu;
1470 xranInit.p_o_du_addr = (int8_t *)&startupConfiguration.o_du_addr;
1471 xranInit.p_o_ru_addr = (int8_t *)&startupConfiguration.o_ru_addr;
1473 snprintf(prefix_name, sizeof(prefix_name), "wls_%d",startupConfiguration.instance_id);
1474 xranInit.filePrefix = prefix_name;
1476 xranInit.totalBfWeights = startupConfiguration.totalBfWeights;
1478 xranInit.Tadv_cp_dl = startupConfiguration.Tadv_cp_dl;
1479 xranInit.T2a_min_cp_dl = startupConfiguration.T2a_min_cp_dl;
1480 xranInit.T2a_max_cp_dl = startupConfiguration.T2a_max_cp_dl;
1481 xranInit.T2a_min_cp_ul = startupConfiguration.T2a_min_cp_ul;
1482 xranInit.T2a_max_cp_ul = startupConfiguration.T2a_max_cp_ul;
1483 xranInit.T2a_min_up = startupConfiguration.T2a_min_up;
1484 xranInit.T2a_max_up = startupConfiguration.T2a_max_up;
1485 xranInit.Ta3_min = startupConfiguration.Ta3_min;
1486 xranInit.Ta3_max = startupConfiguration.Ta3_max;
1487 xranInit.T1a_min_cp_dl = startupConfiguration.T1a_min_cp_dl;
1488 xranInit.T1a_max_cp_dl = startupConfiguration.T1a_max_cp_dl;
1489 xranInit.T1a_min_cp_ul = startupConfiguration.T1a_min_cp_ul;
1490 xranInit.T1a_max_cp_ul = startupConfiguration.T1a_max_cp_ul;
1491 xranInit.T1a_min_up = startupConfiguration.T1a_min_up;
1492 xranInit.T1a_max_up = startupConfiguration.T1a_max_up;
1493 xranInit.Ta4_min = startupConfiguration.Ta4_min;
1494 xranInit.Ta4_max = startupConfiguration.Ta4_max;
1496 xranInit.enableCP = startupConfiguration.enableCP;
1497 xranInit.prachEnable = startupConfiguration.enablePrach;
1498 xranInit.srsEnable = startupConfiguration.enableSrs;
1499 xranInit.debugStop = startupConfiguration.debugStop;
1500 xranInit.debugStopCount = startupConfiguration.debugStopCount;
1501 xranInit.DynamicSectionEna = startupConfiguration.DynamicSectionEna;
1502 xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
1503 xranInit.GPS_Alpha = startupConfiguration.GPS_Alpha;
1504 xranInit.GPS_Beta = startupConfiguration.GPS_Beta;
1506 xranInit.cp_vlan_tag = startupConfiguration.cp_vlan_tag;
1507 xranInit.up_vlan_tag = startupConfiguration.up_vlan_tag;
1509 printf("IQ files size is %d slots\n", startupConfiguration.numSlots);
1511 iq_playback_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
1512 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
1515 iq_playback_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
1516 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
1520 /* 10 * [14*32*273*2*2] = 4892160 bytes */
1521 iq_bfw_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * startupConfiguration.antElmTRx *
1522 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
1525 /* 10 * [14*32*273*2*2] = 4892160 bytes */
1526 iq_bfw_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT *
1527 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
1530 /* 10 * [1*273*2*2] = 349440 bytes */
1531 iq_srs_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
1532 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
1535 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1536 p_tx_play_buffer[i] = (int16_t*)malloc(iq_playback_buffer_size_dl);
1537 tx_play_buffer_size[i] = (int32_t)iq_playback_buffer_size_dl;
1539 if (p_tx_play_buffer[i] == NULL)
1542 tx_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ant_file[i],
1543 "DL IFFT IN IQ Samples in binary format",
1544 (uint8_t*) p_tx_play_buffer[i],
1545 tx_play_buffer_size[i],
1547 tx_play_buffer_position[i] = 0;
1550 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
1551 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1553 p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl);
1554 tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl;
1556 if (p_tx_dl_bfw_buffer[i] == NULL)
1559 tx_dl_bfw_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.dl_bfw_file[i],
1560 "DL BF weights IQ Samples in binary format",
1561 (uint8_t*) p_tx_dl_bfw_buffer[i],
1562 tx_dl_bfw_buffer_size[i],
1564 tx_dl_bfw_buffer_position[i] = 0;
1568 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
1570 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1571 p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_ul);
1572 tx_ul_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_ul;
1574 if (p_tx_ul_bfw_buffer[i] == NULL)
1577 tx_ul_bfw_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ul_bfw_file[i],
1578 "UL BF weights IQ Samples in binary format",
1579 (uint8_t*) p_tx_ul_bfw_buffer[i],
1580 tx_ul_bfw_buffer_size[i],
1582 tx_ul_bfw_buffer_position[i] = 0;
1586 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
1587 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1588 p_tx_prach_play_buffer[i] = (int16_t*)malloc(PRACH_PLAYBACK_BUFFER_BYTES);
1589 tx_prach_play_buffer_size[i] = (int32_t)PRACH_PLAYBACK_BUFFER_BYTES;
1591 if (p_tx_prach_play_buffer[i] == NULL)
1594 memset(p_tx_prach_play_buffer[i], 0, PRACH_PLAYBACK_BUFFER_BYTES);
1596 tx_prach_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.prach_file[i],
1597 "PRACH IQ Samples in binary format",
1598 (uint8_t*) p_tx_prach_play_buffer[i],
1599 tx_prach_play_buffer_size[i],
1601 tx_prach_play_buffer_position[i] = 0;
1605 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
1607 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
1610 p_tx_srs_play_buffer[i] = (int16_t*)malloc(iq_srs_buffer_size_ul);
1611 tx_srs_play_buffer_size[i] = (int32_t)iq_srs_buffer_size_ul;
1613 if (p_tx_srs_play_buffer[i] == NULL)
1616 memset(p_tx_srs_play_buffer[i], 0, iq_srs_buffer_size_ul);
1617 tx_prach_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ul_srs_file[i],
1618 "SRS IQ Samples in binary format",
1619 (uint8_t*) p_tx_srs_play_buffer[i],
1620 tx_srs_play_buffer_size[i],
1623 tx_srs_play_buffer_position[i] = 0;
1628 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1630 p_rx_log_buffer[i] = (int16_t*)malloc(iq_playback_buffer_size_ul);
1631 rx_log_buffer_size[i] = (int32_t)iq_playback_buffer_size_ul;
1633 if (p_rx_log_buffer[i] == NULL)
1636 rx_log_buffer_position[i] = 0;
1638 memset(p_rx_log_buffer[i], 0, rx_log_buffer_size[i]);
1642 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1644 p_prach_log_buffer[i] = (int16_t*)malloc(startupConfiguration.numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES);
1645 prach_log_buffer_size[i] = (int32_t)startupConfiguration.numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES;
1647 if (p_prach_log_buffer[i] == NULL)
1650 memset(p_prach_log_buffer[i], 0, prach_log_buffer_size[i]);
1651 prach_log_buffer_position[i] = 0;
1655 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
1657 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
1660 p_srs_log_buffer[i] = (int16_t*)malloc(iq_srs_buffer_size_ul);
1661 srs_log_buffer_size[i] = (int32_t)iq_srs_buffer_size_ul;
1663 if (p_srs_log_buffer[i] == NULL)
1666 memset(p_srs_log_buffer[i], 0, iq_srs_buffer_size_ul);
1667 srs_log_buffer_position[i] = 0;
1671 if (stat("./logs", &st) == -1) {
1672 mkdir("./logs", 0777);
1675 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1677 snprintf(filename, sizeof(filename), "./logs/%s-play_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1678 sys_save_buf_to_file_txt(filename,
1679 "DL IFFT IN IQ Samples in human readable format",
1680 (uint8_t*) p_tx_play_buffer[i],
1681 tx_play_buffer_size[i],
1684 snprintf(filename, sizeof(filename),"./logs/%s-play_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1685 sys_save_buf_to_file(filename,
1686 "DL IFFT IN IQ Samples in binary format",
1687 (uint8_t*) p_tx_play_buffer[i],
1688 tx_play_buffer_size[i]/sizeof(short),
1692 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
1693 snprintf(filename, sizeof(filename),"./logs/%s-dl_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1694 sys_save_buf_to_file_txt(filename,
1695 "DL Beamformig weights IQ Samples in human readable format",
1696 (uint8_t*) p_tx_dl_bfw_buffer[i],
1697 tx_dl_bfw_buffer_size[i],
1700 snprintf(filename, sizeof(filename),"./logs/%s-dl_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1701 sys_save_buf_to_file(filename,
1702 "DL Beamformig weightsIQ Samples in binary format",
1703 (uint8_t*) p_tx_dl_bfw_buffer[i],
1704 tx_dl_bfw_buffer_size[i]/sizeof(short),
1708 snprintf(filename, sizeof(filename), "./logs/%s-ul_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1709 sys_save_buf_to_file_txt(filename,
1710 "UL Beamformig weights IQ Samples in human readable format",
1711 (uint8_t*) p_tx_ul_bfw_buffer[i],
1712 tx_ul_bfw_buffer_size[i],
1715 snprintf(filename, sizeof(filename),"./logs/%s-ul_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1716 sys_save_buf_to_file(filename,
1717 "UL Beamformig weightsIQ Samples in binary format",
1718 (uint8_t*) p_tx_ul_bfw_buffer[i],
1719 tx_ul_bfw_buffer_size[i]/sizeof(short),
1724 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
1725 snprintf(filename, sizeof(filename), "./logs/%s-play_prach_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1726 sys_save_buf_to_file_txt(filename,
1727 "PRACH IQ Samples in human readable format",
1728 (uint8_t*) p_tx_prach_play_buffer[i],
1729 tx_prach_play_buffer_size[i],
1732 snprintf(filename, sizeof(filename), "./logs/%s-play_prach_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1733 sys_save_buf_to_file(filename,
1734 "PRACH IQ Samples in binary format",
1735 (uint8_t*) p_tx_prach_play_buffer[i],
1736 tx_prach_play_buffer_size[i]/sizeof(short),
1741 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs && startupConfiguration.xranCat == XRAN_CATEGORY_B){
1743 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
1747 snprintf(filename, sizeof(filename), "./logs/%s-play_srs_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1748 sys_save_buf_to_file_txt(filename,
1749 "SRS IQ Samples in human readable format",
1750 (uint8_t*) p_tx_srs_play_buffer[i],
1751 tx_srs_play_buffer_size[i],
1754 snprintf(filename,sizeof(filename), "./logs/%s-play_srs_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
1755 sys_save_buf_to_file(filename,
1756 "SRS IQ Samples in binary format",
1757 (uint8_t*) p_tx_srs_play_buffer[i],
1758 tx_srs_play_buffer_size[i]/sizeof(short),
1763 if (startupConfiguration.iqswap == 1){
1764 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1765 printf("TX: Swap I and Q to match RU format: [%d]\n",i);
1769 signed short *ptr = (signed short *) p_tx_play_buffer[i];
1772 for (j = 0; j < (int32_t)(tx_play_buffer_size[i]/sizeof(short)) ; j = j + 2){
1774 ptr[j] = ptr[j + 1];
1778 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
1779 printf("DL BFW: Swap I and Q to match RU format: [%d]\n",i);
1783 signed short *ptr = (signed short *) p_tx_dl_bfw_buffer[i];
1786 for (j = 0; j < (int32_t)(tx_dl_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2){
1788 ptr[j] = ptr[j + 1];
1792 printf("UL BFW: Swap I and Q to match RU format: [%d]\n",i);
1796 signed short *ptr = (signed short *) p_tx_ul_bfw_buffer[i];
1799 for (j = 0; j < (int32_t)(tx_ul_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2){
1801 ptr[j] = ptr[j + 1];
1808 if (startupConfiguration.appMode == APP_O_RU){
1809 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1810 printf("PRACH: Swap I and Q to match RU format: [%d]\n",i);
1814 signed short *ptr = (signed short *) p_tx_prach_play_buffer[i];
1817 for (j = 0; j < (int32_t)(tx_prach_play_buffer_size[i]/sizeof(short)) ; j = j + 2){
1819 ptr[j] = ptr[j + 1];
1826 if (startupConfiguration.appMode == APP_O_RU){
1828 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
1830 printf("SRS: Swap I and Q to match RU format: [%d]\n",i);
1834 signed short *ptr = (signed short *) p_tx_srs_play_buffer[i];
1837 for (j = 0; j < (int32_t)(tx_srs_play_buffer_size[i]/sizeof(short)) ; j = j + 2){
1839 ptr[j] = ptr[j + 1];
1848 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1850 sprintf(filename, "./logs/swap_IQ_play_ant%d.txt", i);
1851 sys_save_buf_to_file_txt(filename,
1852 "DL IFFT IN IQ Samples in human readable format",
1853 (uint8_t*) p_tx_play_buffer[i],
1854 tx_play_buffer_size[i],
1858 if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0){
1859 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1860 printf("TX: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
1861 for (j = 0; j < tx_play_buffer_size[i]/sizeof(short); j++){
1862 p_tx_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_play_buffer[i][j]);
1865 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
1866 printf("DL BFW: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
1867 for (j = 0; j < tx_dl_bfw_buffer_size[i]/sizeof(short); j++){
1868 p_tx_dl_bfw_buffer[i][j] = rte_cpu_to_be_16(p_tx_dl_bfw_buffer[i][j]);
1870 printf("UL BFW: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
1871 for (j = 0; j < tx_ul_bfw_buffer_size[i]/sizeof(short); j++){
1872 p_tx_ul_bfw_buffer[i][j] = rte_cpu_to_be_16(p_tx_ul_bfw_buffer[i][j]);
1877 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
1878 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1879 printf("PRACH: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
1880 for (j = 0; j < tx_prach_play_buffer_size[i]/sizeof(short); j++){
1881 p_tx_prach_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_prach_play_buffer[i][j]);
1886 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
1888 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
1890 printf("SRS: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
1891 for (j = 0; j < tx_srs_play_buffer_size[i]/sizeof(short); j++){
1892 p_tx_srs_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_srs_play_buffer[i][j]);
1900 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
1902 sprintf(filename, "./logs/swap_be_play_ant%d.txt", i);
1903 sys_save_buf_to_file_txt(filename,
1904 "DL IFFT IN IQ Samples in human readable format",
1905 (uint8_t*) p_tx_play_buffer[i],
1906 tx_play_buffer_size[i],
1911 memset(&xranConf, 0, sizeof(struct xran_fh_config));
1912 pXranConf = &xranConf;
1914 pXranConf->nDLRBs = app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA);
1915 pXranConf->nULRBs = app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA);
1917 if(startupConfiguration.DynamicSectionEna == 0){
1918 struct xran_prb_map* pRbMap;
1920 pRbMap = &startupConfiguration.PrbMapDl;
1922 pRbMap->dir = XRAN_DIR_DL;
1923 pRbMap->xran_port = 0;
1924 pRbMap->band_id = 0;
1926 pRbMap->ru_port_id = 0;
1928 pRbMap->start_sym_id = 0;
1929 pRbMap->nPrbElm = 1;
1930 pRbMap->prbMap[0].nStartSymb = 0;
1931 pRbMap->prbMap[0].numSymb = 14;
1932 pRbMap->prbMap[0].nRBStart = 0;
1933 pRbMap->prbMap[0].nRBSize = pXranConf->nDLRBs;
1934 pRbMap->prbMap[0].nBeamIndex = 0;
1935 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
1936 pRbMap->prbMap[0].iqWidth = 16;
1938 pRbMap = &startupConfiguration.PrbMapUl;
1939 pRbMap->dir = XRAN_DIR_UL;
1940 pRbMap->xran_port = 0;
1941 pRbMap->band_id = 0;
1943 pRbMap->ru_port_id = 0;
1945 pRbMap->start_sym_id = 0;
1946 pRbMap->nPrbElm = 1;
1947 pRbMap->prbMap[0].nStartSymb = 0;
1948 pRbMap->prbMap[0].numSymb = 14;
1949 pRbMap->prbMap[0].nRBStart = 0;
1950 pRbMap->prbMap[0].nRBSize = pXranConf->nULRBs;
1951 pRbMap->prbMap[0].nBeamIndex = 0;
1952 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
1953 pRbMap->prbMap[0].iqWidth = 16;
1956 timer_set_tsc_freq_from_clock();
1957 xret = xran_init(argc, argv, &xranInit, argv[0], &xranHandle);
1958 if(xret != XRAN_STATUS_SUCCESS){
1959 printf("xran_init failed %d\n", xret);
1963 if(xranHandle == NULL)
1967 pXranConf->sector_id = 0;
1968 pXranConf->nCC = numCCPorts;
1969 pXranConf->neAxc = num_eAxc;
1970 pXranConf->neAxcUl = startupConfiguration.numUlAxc;
1971 pXranConf->nAntElmTRx = startupConfiguration.antElmTRx;
1973 pXranConf->frame_conf.nFrameDuplexType = startupConfiguration.nFrameDuplexType;
1974 pXranConf->frame_conf.nNumerology = startupConfiguration.mu_number;
1975 pXranConf->frame_conf.nTddPeriod = startupConfiguration.nTddPeriod;
1977 for (i = 0; i < startupConfiguration.nTddPeriod; i++){
1978 pXranConf->frame_conf.sSlotConfig[i] = startupConfiguration.sSlotConfig[i];
1981 pXranConf->prach_conf.nPrachSubcSpacing = startupConfiguration.mu_number;
1982 pXranConf->prach_conf.nPrachFreqStart = 0;
1983 pXranConf->prach_conf.nPrachFilterIdx = XRAN_FILTERINDEX_PRACH_ABC;
1984 pXranConf->prach_conf.nPrachConfIdx = startupConfiguration.prachConfigIndex;
1985 pXranConf->prach_conf.nPrachFreqOffset = -792;
1987 pXranConf->srs_conf.symbMask = startupConfiguration.srsSymMask;
1988 pXranConf->srs_conf.eAxC_offset = 2 * startupConfiguration.numAxc; /* PUSCH, PRACH, SRS */
1990 pXranConf->ru_conf.xranCat = startupConfiguration.xranCat;
1991 pXranConf->ru_conf.iqWidth = startupConfiguration.PrbMapDl.prbMap[0].iqWidth;
1993 if (startupConfiguration.compression == 0)
1994 pXranConf->ru_conf.compMeth = XRAN_COMPMETHOD_NONE;
1996 pXranConf->ru_conf.compMeth = XRAN_COMPMETHOD_BLKFLOAT;
1998 pXranConf->ru_conf.fftSize = 0;
1999 while (startupConfiguration.nULFftSize >>= 1)
2000 ++pXranConf->ru_conf.fftSize;
2002 pXranConf->ru_conf.byteOrder = (startupConfiguration.nebyteorderswap == 1) ? XRAN_NE_BE_BYTE_ORDER : XRAN_CPU_LE_BYTE_ORDER ;
2003 pXranConf->ru_conf.iqOrder = (startupConfiguration.iqswap == 1) ? XRAN_Q_I_ORDER : XRAN_I_Q_ORDER;
2005 printf("FFT Order %d\n", pXranConf->ru_conf.fftSize);
2007 nCenterFreq = startupConfiguration.nDLAbsFrePointA + (((pXranConf->nDLRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(startupConfiguration.mu_number));
2008 pXranConf->nDLCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq);
2009 printf("DL center freq %d DL NR-ARFCN %d\n", nCenterFreq, pXranConf->nDLCenterFreqARFCN);
2011 nCenterFreq = startupConfiguration.nULAbsFrePointA + (((pXranConf->nULRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(startupConfiguration.mu_number));
2012 pXranConf->nULCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq);
2013 printf("UL center freq %d UL NR-ARFCN %d\n", nCenterFreq, pXranConf->nULCenterFreqARFCN);
2015 pXranConf->bbdev_dec = NULL;
2016 pXranConf->bbdev_enc = NULL;
2018 pXranConf->log_level = 1;
2020 if(startupConfiguration.maxFrameId)
2021 pXranConf->ru_conf.xran_max_frame = startupConfiguration.maxFrameId;
2023 if(init_xran() != 0)
2026 xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
2027 xran_reg_physide_cb(xranHandle, physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);
2028 xran_reg_physide_cb(xranHandle, physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX);
2030 init_xran_iq_content();
2032 xret = xran_open(xranHandle, pXranConf);
2034 if(xret != XRAN_STATUS_SUCCESS){
2035 printf("xran_open failed %d\n", xret);
2039 snprintf(filename, sizeof(filename),"mlog-%s", startupConfiguration.appMode == 0 ? "o-du" : "o-ru");
2041 /* MLogOpen(0, 32, 0, 0xFFFFFFFF, filename);*/
2043 MLogOpen(256, 3, 20000, 0, filename);
2046 puts("----------------------------------------");
2047 printf("MLog Info: virt=0x%016lx size=%d\n", MLogGetFileLocation(), MLogGetFileSize());
2048 puts("----------------------------------------");
2051 uint64_t nActiveCoreMask[MAX_BBU_POOL_CORE_MASK] = {0};
2052 nActiveCoreMask[0] = 1 << xranInit.io_cfg.timing_core;
2053 uint32_t numCarriers = startupConfiguration.numCC;
2055 MLogAddTestCase(nActiveCoreMask, numCarriers);
2057 fcntl(0, F_SETFL, fcntl(0, F_GETFL) | O_NONBLOCK);
2059 state = APP_RUNNING;
2060 printf("Start XRAN traffic\n");
2061 xran_start(xranHandle);
2065 struct xran_common_counters x_counters;
2068 xran_curr_if_state = xran_get_if_state();
2069 if(xran_get_common_counters(xranHandle, &x_counters) == XRAN_STATUS_SUCCESS) {
2071 xran_get_time_stats(&nTotalTime, &nUsedTime, &nCoreUsed, 1);
2072 nUsedPercent = ((float)nUsedTime * 100.0) / (float)nTotalTime;
2074 printf("[%s][rx %ld pps %ld kbps %ld][tx %ld pps %ld kbps %ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld] IO Util: %5.2f %%\n",
2075 ((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"),
2077 rx_counter-old_rx_counter,
2078 rx_bytes_per_sec*8/1000L,
2080 tx_counter-old_tx_counter,
2081 tx_bytes_per_sec*8/1000L,
2082 x_counters.Rx_on_time,
2083 x_counters.Rx_early,
2085 x_counters.Rx_corrupt,
2086 x_counters.Rx_pkt_dupl,
2087 x_counters.Total_msgs_rcvd,
2090 if(rx_counter > old_rx_counter)
2091 old_rx_counter = rx_counter;
2092 if(tx_counter > old_tx_counter)
2093 old_tx_counter = tx_counter;
2095 if(rx_counter > 0 && tx_counter > 0)
2096 MLogSetMask(0xFFFFFFFF);
2098 printf("error xran_get_common_counters\n");
2101 if (xran_curr_if_state == XRAN_STOPPED){
2104 if (NULL == fgets(input, 10, stdin)) {
2108 const int sel_opt = atoi(input);
2111 xran_start(xranHandle);
2112 printf("Start XRAN traffic\n");
2117 xran_stop(xranHandle);
2118 printf("Stop XRAN traffic\n");
2119 state = APP_STOPPED;
2122 puts("Wrong option passed!");
2125 if (APP_STOPPED == state)
2129 get_xran_iq_content();
2131 puts("Closing l1 app... Ending all threads...");
2132 xran_close(xranHandle);
2136 puts("Dump IQs...");
2138 if (startupConfiguration.iqswap == 1){
2139 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
2140 printf("RX: Swap I and Q to match CPU format: [%d]\n",i);
2144 signed short *ptr = (signed short *) p_rx_log_buffer[i];
2147 for (j = 0; j < (int32_t)(rx_log_buffer_size[i]/sizeof(short)) ; j = j + 2){
2149 ptr[j] = ptr[j + 1];
2155 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
2157 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
2159 printf("SRS: Swap I and Q to match CPU format: [%d]\n",i);
2163 signed short *ptr = (signed short *) p_srs_log_buffer[i];
2166 for (j = 0; j < (int32_t)(srs_log_buffer_size[i]/sizeof(short)) ; j = j + 2){
2168 ptr[j] = ptr[j + 1];
2176 if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0) {
2178 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
2179 printf("RX: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i);
2180 for (j = 0; j < rx_log_buffer_size[i]/sizeof(short); j++){
2181 p_rx_log_buffer[i][j] = rte_be_to_cpu_16(p_rx_log_buffer[i][j]);
2185 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
2187 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
2189 printf("SRS: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i);
2190 for (j = 0; j < srs_log_buffer_size[i]/sizeof(short); j++){
2191 p_srs_log_buffer[i][j] = rte_be_to_cpu_16(p_srs_log_buffer[i][j]);
2197 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
2199 snprintf(filename, sizeof(filename), "./logs/%s-rx_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
2200 sys_save_buf_to_file_txt(filename,
2201 "UL FFT OUT IQ Samples in human readable format",
2202 (uint8_t*) p_rx_log_buffer[i],
2203 rx_log_buffer_size[i],
2206 snprintf(filename, sizeof(filename), "./logs/%s-rx_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
2207 sys_save_buf_to_file(filename,
2208 "UL FFT OUT IQ Samples in binary format",
2209 (uint8_t*) p_rx_log_buffer[i],
2210 rx_log_buffer_size[i]/sizeof(short),
2214 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
2216 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
2218 snprintf(filename, sizeof(filename), "./logs/%s-srs_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
2219 sys_save_buf_to_file_txt(filename,
2220 "SRS UL FFT OUT IQ Samples in human readable format",
2221 (uint8_t*) p_srs_log_buffer[i],
2222 srs_log_buffer_size[i],
2225 snprintf(filename, sizeof(filename), "./logs/%s-srs_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
2226 sys_save_buf_to_file(filename,
2227 "SRS UL FFT OUT IQ Samples in binary format",
2228 (uint8_t*) p_srs_log_buffer[i],
2229 srs_log_buffer_size[i]/sizeof(short),
2234 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enablePrach){
2235 if (startupConfiguration.iqswap == 1){
2236 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
2237 printf("PRACH: Swap I and Q to match CPU format: [%d]\n",i);
2241 signed short *ptr = (signed short *) p_prach_log_buffer[i];
2244 for (j = 0; j < (int32_t)(prach_log_buffer_size[i]/sizeof(short)) ; j = j + 2){
2246 ptr[j] = ptr[j + 1];
2254 if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0){
2255 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
2256 printf("PRACH: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i);
2257 for (j = 0; j < prach_log_buffer_size[i]/sizeof(short); j++){
2258 p_prach_log_buffer[i][j] = rte_be_to_cpu_16(p_prach_log_buffer[i][j]);
2264 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
2266 snprintf(filename, sizeof(filename), "./logs/%s-prach_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
2267 sys_save_buf_to_file_txt(filename,
2268 "PRACH FFT OUT IQ Samples in human readable format",
2269 (uint8_t*) p_prach_log_buffer[i],
2270 prach_log_buffer_size[i],
2273 snprintf(filename, sizeof(filename), "./logs/%s-prach_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
2274 sys_save_buf_to_file(filename,
2275 "PRACH FFT OUT IQ Samples in binary format",
2276 (uint8_t*) p_prach_log_buffer[i],
2277 prach_log_buffer_size[i]/sizeof(short),