--- /dev/null
+/******************************************************************************\r
+*\r
+* Copyright (c) 2019 Intel.\r
+*\r
+* Licensed under the Apache License, Version 2.0 (the "License");\r
+* you may not use this file except in compliance with the License.\r
+* You may obtain a copy of the License at\r
+*\r
+* http://www.apache.org/licenses/LICENSE-2.0\r
+*\r
+* Unless required by applicable law or agreed to in writing, software\r
+* distributed under the License is distributed on an "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+* See the License for the specific language governing permissions and\r
+* limitations under the License.\r
+*\r
+*******************************************************************************/\r
+\r
+\r
+#ifndef XRAN_LIB_WRAP_HPP\r
+#define XRAN_LIB_WRAP_HPP\r
+\r
+#include <exception>\r
+#include <random>\r
+#include <string>\r
+#include <utility>\r
+#include <vector>\r
+\r
+#include <malloc.h>\r
+#include <stdint.h>\r
+\r
+#include "common.hpp"\r
+#include "xran_fh_o_du.h"\r
+#include "xran_common.h"\r
+#include "xran_frame_struct.h"\r
+\r
+\r
+#define XRAN_UT_CFG_FILENAME "conf.json"\r
+\r
+#define XRAN_UT_KEY_GLOBALCFG "GLOBAL"\r
+#define XRAN_UT_KEY_GLOBALCFG_IO "io_cfg"\r
+#define XRAN_UT_KEY_GLOBALCFG_EAXCID "eAxCId_cfg"\r
+#define XRAN_UT_KEY_GLOBALCFG_PRACH "prach_cfg"\r
+#define XRAN_UT_KEY_GLOBALCFG_RU "ru_cfg"\r
+#define XRAN_UT_KEY_GLOBALCFG_SLOT "slotcfg_"\r
+\r
+#define MAX_NUM_OF_XRAN_CTX (2)\r
+\r
+#define SW_FPGA_TOTAL_BUFFER_LEN (4*1024*1024*1024)\r
+#define SW_FPGA_SEGMENT_BUFFER_LEN (1*1024*1024*1024)\r
+#define SW_FPGA_FH_TOTAL_BUFFER_LEN (1*1024*1024*1024)\r
+#define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192)\r
+\r
+#define MAX_ANT_CARRIER_SUPPORTED (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR)\r
+\r
+extern "C"\r
+{\r
+extern uint32_t xran_lib_ota_tti;\r
+extern uint32_t xran_lib_ota_sym;\r
+extern uint32_t xran_lib_ota_sym_idx;\r
+\r
+void sym_ota_cb(struct rte_timer *tim, void *arg);\r
+void tti_ota_cb(struct rte_timer *tim, void *arg);\r
+}\r
+\r
+class xranLibWraper\r
+{\r
+public:\r
+ typedef enum\r
+ {\r
+ XRANFTHTX_OUT = 0,\r
+ XRANFTHTX_PRB_MAP_OUT,\r
+ XRANFTHTX_SEC_DESC_OUT,\r
+ XRANFTHRX_IN,\r
+ XRANFTHRX_PRB_MAP_IN,\r
+ XRANFTHTX_SEC_DESC_IN,\r
+ XRANFTHRACH_IN,\r
+ MAX_SW_XRAN_INTERFACE_NUM\r
+ } SWXRANInterfaceTypeEnum;\r
+\r
+ enum nChBw\r
+ {\r
+ PHY_BW_5MHZ = 5, PHY_BW_10MHZ = 10, PHY_BW_15MHZ = 15,\r
+ PHY_BW_20MHZ = 20, PHY_BW_25MHZ = 25, PHY_BW_30MHZ = 30,\r
+ PHY_BW_40MHZ = 40, PHY_BW_50MHZ = 50, PHY_BW_60MHZ = 60,\r
+ PHY_BW_70MHZ = 70, PHY_BW_80MHZ = 80, PHY_BW_90MHZ = 90,\r
+ PHY_BW_100MHZ = 100, PHY_BW_200MHZ = 200, PHY_BW_400MHZ = 400\r
+ };\r
+\r
+ // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB\r
+ const uint16_t nNumRbsPerSymF1[3][13] =\r
+ {\r
+ // 5MHz 10MHz 15MHz 20MHz 25MHz 30MHz 40MHz 50MHz 60MHz 70MHz 80MHz 90MHz 100MHz\r
+ { 25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0 }, // Numerology 0 (15KHz)\r
+ { 11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273 }, // Numerology 1 (30KHz)\r
+ { 0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135 } // Numerology 2 (60KHz)\r
+ };\r
+\r
+ // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB\r
+ const uint16_t nNumRbsPerSymF2[2][4] =\r
+ {\r
+ // 50MHz 100MHz 200MHz 400MHz\r
+ { 66, 132, 264, 0 }, // Numerology 2 (60KHz)\r
+ { 32, 66, 132, 264 } // Numerology 3 (120KHz)\r
+ };\r
+\r
+\r
+protected:\r
+ char argv[25] = "unittest";\r
+\r
+ std::string m_dpdk_dev_up, m_dpdk_dev_cp, m_dpdk_bbdev;\r
+\r
+ void *m_xranhandle;\r
+\r
+ uint8_t m_du_mac[6] = { 0x00,0x11, 0x22, 0x33, 0x44, 0x66 };\r
+ uint8_t m_ru_mac[6] = { 0x00,0x11, 0x22, 0x33, 0x44, 0x55 };\r
+ bool m_bSub6;\r
+ uint32_t m_nSlots = 10;\r
+\r
+ struct xran_fh_config m_xranConf;\r
+ struct xran_fh_init m_xranInit;\r
+\r
+ struct xran_timer_ctx {\r
+ uint32_t tti_to_process;\r
+ } m_timer_ctx[MAX_NUM_OF_XRAN_CTX];\r
+\r
+ /* io struct */\r
+ BbuIoBufCtrlStruct m_sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+ BbuIoBufCtrlStruct m_sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+ BbuIoBufCtrlStruct m_sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+ BbuIoBufCtrlStruct m_sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+ BbuIoBufCtrlStruct m_sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ /* buffers lists */\r
+ struct xran_flat_buffer m_sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];\r
+ struct xran_flat_buffer m_sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+ struct xran_flat_buffer m_sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];\r
+ struct xran_flat_buffer m_sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+ struct xran_flat_buffer m_sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];\r
+\r
+ void *m_nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector\r
+ uint32_t m_nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool\r
+\r
+ uint32_t m_nSW_ToFpga_FTH_TxBufferLen;\r
+ uint32_t m_nFpgaToSW_FTH_RxBufferLen;\r
+\r
+ int32_t m_nSectorIndex[XRAN_MAX_SECTOR_NR];\r
+\r
+ int iq_bfw_buffer_size_dl = 0;\r
+ int iq_bfw_buffer_size_ul = 0;\r
+\r
+ /* beamforming weights for UL (O-DU) */\r
+ int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];\r
+ int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];\r
+ int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];\r
+\r
+ /* beamforming weights for UL (O-DU) */\r
+ int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];\r
+ int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];\r
+ int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];\r
+\r
+\r
+private:\r
+ json m_global_cfg;\r
+\r
+ template<typename T>\r
+ T get_globalcfg(const std::string &type, const std::string ¶meter_name)\r
+ {\r
+ return m_global_cfg[XRAN_UT_KEY_GLOBALCFG][type][parameter_name];\r
+ }\r
+\r
+ template<typename T>\r
+ std::vector<T> get_globalcfg_array(const std::string &type, const std::string ¶meter_name)\r
+ {\r
+ auto array_size = m_global_cfg[XRAN_UT_KEY_GLOBALCFG][type][parameter_name].size();\r
+\r
+ std::vector<T> result(array_size);\r
+\r
+ for(unsigned number = 0; number < array_size; number++)\r
+ result.at(number) = m_global_cfg[XRAN_UT_KEY_GLOBALCFG][type][parameter_name][number];\r
+\r
+ return result;\r
+ }\r
+\r
+ uint16_t get_eaxcid_mask(int numbit, int shift)\r
+ {\r
+ uint16_t result = 0;\r
+\r
+ for(int i=0; i < numbit; i++) {\r
+ result = result << 1; result +=1;\r
+ }\r
+ return (result << shift);\r
+ }\r
+\r
+ int init_memory()\r
+ {\r
+ xran_status_t status;\r
+ int32_t i, j, k, z;\r
+ SWXRANInterfaceTypeEnum eInterfaceType;\r
+ void *ptr;\r
+ void *mb;\r
+ uint32_t *u32dptr;\r
+ uint16_t *u16dptr;\r
+ uint8_t *u8dptr;\r
+\r
+\r
+ std::cout << "XRAN front haul xran_mm_init" << std::endl;\r
+ status = xran_mm_init(m_xranhandle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << "Failed at XRAN front haul xran_mm_init" << std::endl;\r
+ return (-1);\r
+ }\r
+\r
+ /* initialize maximum instances to have flexibility for the tests */\r
+ int nInstanceNum = XRAN_MAX_SECTOR_NR;\r
+ /* initialize maximum supported CC to have flexibility on the test */\r
+ int32_t nSectorNum = 6;//XRAN_MAX_SECTOR_NR;\r
+\r
+ for(k = 0; k < XRAN_PORTS_NUM; k++) {\r
+ status = xran_sector_get_instances(m_xranhandle, nInstanceNum, &m_nInstanceHandle[k][0]);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << "get sector instance failed " << k << " for XRAN nInstanceNum " << nInstanceNum << std::endl;\r
+ return (-1);\r
+ }\r
+ for (i = 0; i < nInstanceNum; i++)\r
+ std::cout << __func__ << " [" << k << "]: CC " << i << " handle " << m_nInstanceHandle[0][i] << std::endl;\r
+ }\r
+ std::cout << "Sucess xran_mm_init" << std::endl;\r
+\r
+ /* Init Memory */\r
+ for(i = 0; i<nSectorNum; i++) {\r
+ eInterfaceType = XRANFTHTX_OUT;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,\r
+ m_nSW_ToFpga_FTH_TxBufferLen);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {\r
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulTxBuffers[j][i][z][0];\r
+\r
+ for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;\r
+ m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;\r
+\r
+ if(ptr) {\r
+ u32dptr = (uint32_t*)(ptr);\r
+ uint8_t *ptr_temp = (uint8_t *)ptr;\r
+ memset(u32dptr, 0x0, m_nSW_ToFpga_FTH_TxBufferLen);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* C-plane DL */\r
+ eInterfaceType = XRANFTHTX_SEC_DESC_OUT;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));\r
+ if(XRAN_STATUS_SUCCESS != status) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ eInterfaceType = XRANFTHTX_PRB_MAP_OUT;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,\r
+ sizeof(struct xran_prb_map));\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {\r
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulTxPrbMapBuffers[j][i][z];\r
+\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;\r
+ m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;\r
+ void *sd_ptr;\r
+ void *sd_mb;\r
+ int elm_id;\r
+ struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;\r
+ //memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map));\r
+ for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SYM; elm_id++){\r
+ struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];\r
+ for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT], &sd_ptr, &sd_mb);\r
+ if(XRAN_STATUS_SUCCESS != status){\r
+ std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;\r
+ return (-1);\r
+ }\r
+ pPrbElem->p_sec_desc[k] = (struct xran_section_desc *)sd_ptr;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ for(i = 0; i<nSectorNum; i++) {\r
+ eInterfaceType = XRANFTHRX_IN;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,\r
+ m_nSW_ToFpga_FTH_TxBufferLen); /* ????, actual alloc size is m_nFpgaToSW_FTH_RxBUfferLen */\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+\r
+ for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {\r
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulRxBuffers[j][i][z][0];\r
+ for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nFpgaToSW_FTH_RxBufferLen;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],&ptr, &mb);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;\r
+ m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb;\r
+ if(ptr) {\r
+ u32dptr = (uint32_t*)(ptr);\r
+ uint8_t *ptr_temp = (uint8_t *)ptr;\r
+ memset(u32dptr, 0x0, m_nFpgaToSW_FTH_RxBufferLen);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ eInterfaceType = XRANFTHTX_SEC_DESC_IN;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));\r
+ if(XRAN_STATUS_SUCCESS != status) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ eInterfaceType = XRANFTHRX_PRB_MAP_IN;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,\r
+ sizeof(struct xran_prb_map));\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+\r
+ for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {\r
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulRxPrbMapBuffers[j][i][z];\r
+\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i],m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer , status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;\r
+ m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;\r
+ void *sd_ptr;\r
+ void *sd_mb;\r
+ int elm_id;\r
+ struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;\r
+ //memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map));\r
+ for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SYM; elm_id++){\r
+ struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];\r
+ for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN], &sd_ptr, &sd_mb);\r
+ if(XRAN_STATUS_SUCCESS != status){\r
+ std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;\r
+ return (-1);\r
+ }\r
+ pPrbElem->p_sec_desc[k] = (struct xran_section_desc *)sd_ptr;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ for(i = 0; i<nSectorNum; i++) {\r
+ eInterfaceType = XRANFTHRACH_IN;\r
+ status = xran_bm_init(m_nInstanceHandle[0][i],\r
+ &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],\r
+ XRAN_N_FE_BUF_LEN * XRAN_MAX_ANTENNA_NR * XRAN_NUM_OF_SYMBOL_PER_SLOT,\r
+ FPGA_TO_SW_PRACH_RX_BUFFER_LEN);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) {\r
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFHPrachRxBuffers[j][i][z][0];\r
+ for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) {\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;\r
+ status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);\r
+ if(status != XRAN_STATUS_SUCCESS) {\r
+ std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl;\r
+ return (-1);\r
+ }\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;\r
+ m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;\r
+ if(ptr) {\r
+ u32dptr = (uint32_t*)(ptr);\r
+ memset(u32dptr, 0x0, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return (0);\r
+ }\r
+\r
+\r
+public:\r
+ xranLibWraper()\r
+ {\r
+ int i, temp;\r
+ std::string tmpstr;\r
+ unsigned int tmp_mac[6];\r
+\r
+ m_global_cfg = read_json_from_file(XRAN_UT_CFG_FILENAME);\r
+\r
+ memset(&m_xranInit, 0, sizeof(xran_fh_init));\r
+\r
+ m_xranInit.io_cfg.id = 0;\r
+\r
+ /* DPDK configuration */\r
+ m_dpdk_dev_up = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdk_dev_up");\r
+ m_dpdk_dev_cp = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdk_dev_cp");\r
+ m_xranInit.io_cfg.dpdk_dev[XRAN_UP_VF] = (m_dpdk_dev_up == "") ? NULL : (char *)&m_dpdk_dev_up;\r
+ m_xranInit.io_cfg.dpdk_dev[XRAN_CP_VF] = (m_dpdk_dev_cp == "") ? NULL : (char *)&m_dpdk_dev_cp;\r
+\r
+ m_xranInit.io_cfg.core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "core");\r
+ m_xranInit.io_cfg.system_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "system_core");\r
+ m_xranInit.io_cfg.pkt_proc_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "pkt_proc_core");\r
+ m_xranInit.io_cfg.pkt_aux_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "pkt_aux_core");\r
+ m_xranInit.io_cfg.timing_core = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "timing_core");\r
+\r
+ std::string bbdev_mode = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "bbdev_mode");\r
+ if(bbdev_mode == "sw")\r
+ m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_MODE_HW_OFF;\r
+ else if(bbdev_mode == "hw")\r
+ m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_MODE_HW_ON;\r
+ else if(bbdev_mode == "none")\r
+ m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;\r
+ else {\r
+ std::cout << "Invalid BBDev mode [" << bbdev_mode << "], bbdev won't be used." << std::endl;\r
+ m_xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;\r
+ }\r
+\r
+ m_xranInit.dpdkBasebandFecMode = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkBasebandFecMode");\r
+\r
+ m_dpdk_bbdev = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkBasebandDevice");\r
+ m_xranInit.dpdkBasebandDevice = (m_dpdk_bbdev == "") ? NULL : (char *)&m_dpdk_bbdev;\r
+\r
+ /* Network configurations */\r
+ m_xranInit.mtu = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "mtu");\r
+\r
+ std::string du_mac_str = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "o_du_macaddr");\r
+ std::string ru_mac_str = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_IO, "o_ru_macaddr");\r
+ /* using temp variables to resolve KW issue */\r
+ std::sscanf(du_mac_str.c_str(), "%02x:%02x:%02x:%02x:%02x:%02x",\r
+ &tmp_mac[0], &tmp_mac[1], &tmp_mac[2],\r
+ &tmp_mac[3], &tmp_mac[4], &tmp_mac[5]);\r
+ for(i=0; i<6; i++)\r
+ m_du_mac[i] = (uint8_t)tmp_mac[i];\r
+ std::sscanf(du_mac_str.c_str(), "%02x:%02x:%02x:%02x:%02x:%02x",\r
+ &tmp_mac[0], &tmp_mac[1], &tmp_mac[2],\r
+ &tmp_mac[3], &tmp_mac[4], &tmp_mac[5]);\r
+ for(i=0; i<6; i++)\r
+ m_ru_mac[i] = (uint8_t)tmp_mac[i];\r
+ m_xranInit.p_o_du_addr = (int8_t *)m_du_mac;\r
+ m_xranInit.p_o_ru_addr = (int8_t *)m_ru_mac;\r
+ m_xranInit.cp_vlan_tag = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "cp_vlan_tag");\r
+ m_xranInit.up_vlan_tag = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_IO, "up_vlan_tag");\r
+\r
+ /* eAxCID configurations */\r
+ int bitnum_cuport = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_cuPortId");\r
+ int bitnum_bandsec = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_bandSectorId");\r
+ int bitnum_ccid = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_ccId");\r
+ int bitnum_ruport = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_ruPortId");\r
+\r
+ m_xranInit.eAxCId_conf.bit_cuPortId = bitnum_bandsec + bitnum_ccid + bitnum_ruport;\r
+ m_xranInit.eAxCId_conf.bit_bandSectorId = bitnum_ccid + bitnum_ruport;\r
+ m_xranInit.eAxCId_conf.bit_ccId = bitnum_ruport;\r
+ m_xranInit.eAxCId_conf.bit_ruPortId = 0;\r
+ m_xranInit.eAxCId_conf.mask_cuPortId = get_eaxcid_mask(bitnum_cuport, m_xranInit.eAxCId_conf.bit_cuPortId);\r
+ m_xranInit.eAxCId_conf.mask_bandSectorId = get_eaxcid_mask(bitnum_bandsec, m_xranInit.eAxCId_conf.bit_bandSectorId);\r
+ m_xranInit.eAxCId_conf.mask_ccId = get_eaxcid_mask(bitnum_ccid, m_xranInit.eAxCId_conf.bit_ccId);\r
+ m_xranInit.eAxCId_conf.mask_ruPortId = get_eaxcid_mask(bitnum_ruport, m_xranInit.eAxCId_conf.bit_ruPortId);\r
+\r
+ m_xranInit.totalBfWeights = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "totalBfWeights");\r
+\r
+ m_xranInit.Tadv_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Tadv_cp_dl");\r
+ m_xranInit.T2a_min_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_dl");\r
+ m_xranInit.T2a_max_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_dl");\r
+ m_xranInit.T2a_min_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_ul");\r
+ m_xranInit.T2a_max_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_ul");\r
+ m_xranInit.T2a_min_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_up");\r
+ m_xranInit.T2a_max_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_up");\r
+ m_xranInit.Ta3_min = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_min");\r
+ m_xranInit.Ta3_max = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_max");\r
+ m_xranInit.T1a_min_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_dl");\r
+ m_xranInit.T1a_max_cp_dl = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_dl");\r
+ m_xranInit.T1a_min_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_ul");\r
+ m_xranInit.T1a_max_cp_ul = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_ul");\r
+ m_xranInit.T1a_min_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_up");\r
+ m_xranInit.T1a_max_up = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_up");\r
+ m_xranInit.Ta4_min = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_min");\r
+ m_xranInit.Ta4_max = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_max");\r
+\r
+ m_xranInit.enableCP = 1;\r
+ m_xranInit.prachEnable = 1;\r
+ m_xranInit.debugStop = 0;\r
+ m_xranInit.debugStopCount = 0;\r
+ m_xranInit.DynamicSectionEna= 0;\r
+\r
+ m_xranInit.filePrefix = "wls";\r
+\r
+ m_bSub6 = get_globalcfg<bool>(XRAN_UT_KEY_GLOBALCFG_RU, "sub6");\r
+\r
+ memset(&m_xranConf, 0, sizeof(struct xran_fh_config));\r
+ tmpstr = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_RU, "duplex");\r
+ if(tmpstr == "FDD") {\r
+ m_xranConf.frame_conf.nFrameDuplexType = 0;\r
+ }\r
+ else if(tmpstr == "TDD") {\r
+ m_xranConf.frame_conf.nFrameDuplexType = 1;\r
+\r
+ std::string slotcfg_key = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_RU, "slot_config");\r
+\r
+ int numcfg = get_globalcfg<int>(slotcfg_key, "period");\r
+ m_xranConf.frame_conf.nTddPeriod = numcfg;\r
+\r
+ for(int i=0; i< numcfg; i++) {\r
+ std::stringstream slotcfgname;\r
+ slotcfgname << "slot" << i;\r
+ std::vector<int> slotcfg = get_globalcfg_array<int>(slotcfg_key, slotcfgname.str());\r
+ for(int j=0; j < slotcfg.size(); j++) {\r
+ m_xranConf.frame_conf.sSlotConfig[i].nSymbolType[j] = slotcfg[j];\r
+ }\r
+ m_xranConf.frame_conf.sSlotConfig[i].reserved[0] = 0;\r
+ m_xranConf.frame_conf.sSlotConfig[i].reserved[1] = 0;\r
+ }\r
+ }\r
+ else {\r
+ std::cout << "*** Invalid Duplex type [" << tmpstr << "] !!!" << std::endl;\r
+ std::cout << "****** Set it to FDD... " << std::endl;\r
+ m_xranConf.frame_conf.nFrameDuplexType = 0;\r
+ }\r
+\r
+ m_xranConf.frame_conf.nNumerology = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "mu");\r
+ if(m_xranConf.frame_conf.nNumerology > 3) {\r
+ std::cout << "*** Invalid Numerology [" << m_xranConf.frame_conf.nNumerology << "] !!!" << std::endl;\r
+ m_xranConf.frame_conf.nNumerology = 0;\r
+ std::cout << "****** Set it to " << m_xranConf.frame_conf.nNumerology << "..." << std::endl;\r
+ }\r
+\r
+ m_xranConf.nCC = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "num_cc");\r
+ if(m_xranConf.nCC > XRAN_MAX_SECTOR_NR) {\r
+ std::cout << "*** Exceeds maximum number of carriers supported [" << m_xranConf.nCC << "] !!!" << std::endl;\r
+ m_xranConf.nCC = XRAN_MAX_SECTOR_NR;\r
+ std::cout << "****** Adjusted to " << m_xranConf.nCC << "..." << std::endl;\r
+ }\r
+ m_xranConf.neAxc = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "num_eaxc");\r
+ if(m_xranConf.neAxc > XRAN_MAX_ANTENNA_NR) {\r
+ std::cout << "*** Exceeds maximum number of antenna supported [" << m_xranConf.neAxc << "] !!!" << std::endl;\r
+ m_xranConf.neAxc = XRAN_MAX_ANTENNA_NR;\r
+ std::cout << "****** Adjusted to " << m_xranConf.neAxc << "..." << std::endl;\r
+ }\r
+\r
+ m_bSub6 = get_globalcfg<bool>(XRAN_UT_KEY_GLOBALCFG_RU, "sub6");\r
+ temp = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "chbw_dl");\r
+ m_xranConf.nDLRBs = get_num_rbs(get_numerology(), temp, m_bSub6);\r
+ temp = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "chbw_ul");\r
+ m_xranConf.nULRBs = get_num_rbs(get_numerology(), temp, m_bSub6);\r
+\r
+ m_xranConf.nAntElmTRx = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "ant_elm_trx");\r
+ m_xranConf.nDLFftSize = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size");\r
+ m_xranConf.nULFftSize = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size");\r
+\r
+ m_xranConf.prach_conf.nPrachConfIdx = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "config_id");\r
+ m_xranConf.prach_conf.nPrachSubcSpacing = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "scs");\r
+ m_xranConf.prach_conf.nPrachFreqStart = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "freq_start");\r
+ m_xranConf.prach_conf.nPrachFreqOffset = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "freq_offset");\r
+ m_xranConf.prach_conf.nPrachFilterIdx = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_PRACH, "filter_id");\r
+ m_xranConf.prach_conf.nPrachZeroCorrConf= 0;\r
+ m_xranConf.prach_conf.nPrachRestrictSet = 0;\r
+ m_xranConf.prach_conf.nPrachRootSeqIdx = 0;\r
+\r
+ tmpstr = get_globalcfg<std::string>(XRAN_UT_KEY_GLOBALCFG_RU, "category");\r
+ if(tmpstr == "A")\r
+ m_xranConf.ru_conf.xranCat = XRAN_CATEGORY_A;\r
+ else if(tmpstr == "B")\r
+ m_xranConf.ru_conf.xranCat = XRAN_CATEGORY_B;\r
+ else {\r
+ std::cout << "*** Invalid RU Category [" << tmpstr << "] !!!" << std::endl;\r
+ std::cout << "****** Set it to Category A... " << std::endl;\r
+ m_xranConf.ru_conf.xranCat = XRAN_CATEGORY_A;\r
+ }\r
+\r
+ m_xranConf.ru_conf.iqWidth = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "iq_width");\r
+ m_xranConf.ru_conf.compMeth = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "comp_meth");\r
+\r
+ temp = get_globalcfg<int>(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size");\r
+ m_xranConf.ru_conf.fftSize = 0;\r
+ while (temp >>= 1)\r
+ ++m_xranConf.ru_conf.fftSize;\r
+\r
+ m_xranConf.ru_conf.byteOrder = XRAN_NE_BE_BYTE_ORDER;\r
+ m_xranConf.ru_conf.iqOrder = XRAN_I_Q_ORDER;\r
+\r
+ m_xranConf.log_level = 0;\r
+/*\r
+ m_xranConf.bbdev_enc = nullptr;\r
+ m_xranConf.bbdev_dec = nullptr;\r
+ m_xranConf.ttiCb = nullptr;\r
+ m_xranConf.ttiCbParam = nullptr;\r
+*/\r
+ }\r
+\r
+ ~xranLibWraper()\r
+ {\r
+ }\r
+\r
+ int SetUp()\r
+ {\r
+ int i;\r
+\r
+ printf("O-DU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",\r
+ m_xranInit.p_o_du_addr[0],\r
+ m_xranInit.p_o_du_addr[1],\r
+ m_xranInit.p_o_du_addr[2],\r
+ m_xranInit.p_o_du_addr[3],\r
+ m_xranInit.p_o_du_addr[4],\r
+ m_xranInit.p_o_du_addr[5]);\r
+\r
+ printf("O-RU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",\r
+ m_xranInit.p_o_ru_addr[0],\r
+ m_xranInit.p_o_ru_addr[1],\r
+ m_xranInit.p_o_ru_addr[2],\r
+ m_xranInit.p_o_ru_addr[3],\r
+ m_xranInit.p_o_ru_addr[4],\r
+ m_xranInit.p_o_ru_addr[5]);\r
+\r
+ printf("eAxCID - %d:%d:%d:%d (%04x, %04x, %04x, %04x)\n",\r
+ m_xranInit.eAxCId_conf.bit_cuPortId,\r
+ m_xranInit.eAxCId_conf.bit_bandSectorId,\r
+ m_xranInit.eAxCId_conf.bit_ccId,\r
+ m_xranInit.eAxCId_conf.bit_ruPortId,\r
+ m_xranInit.eAxCId_conf.mask_cuPortId,\r
+ m_xranInit.eAxCId_conf.mask_bandSectorId,\r
+ m_xranInit.eAxCId_conf.mask_ccId,\r
+ m_xranInit.eAxCId_conf.mask_ruPortId);\r
+\r
+ printf("Total BF Weights : %d\n", m_xranInit.totalBfWeights);\r
+\r
+ xran_init(0, NULL, &m_xranInit, &argv[0], &m_xranhandle);\r
+\r
+ for(i = 0; i < XRAN_MAX_SECTOR_NR; i++)\r
+ m_nSectorIndex[i] = i;\r
+\r
+ /* set to maximum length to support multiple cases */\r
+ m_nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/\r
+ m_nSW_ToFpga_FTH_TxBufferLen = 13168; /* 273*12*4 + 64*/\r
+\r
+ if(init_memory() < 0) {\r
+ std::cout << "Fatal Error on Initialization !!!" << std::endl;\r
+ std::cout << "INIT FAILED" << std::endl;\r
+ return (-1);\r
+ }\r
+\r
+ std::cout << "INIT DONE" << std::endl;\r
+ return (0);\r
+ }\r
+\r
+ void TearDown()\r
+ {\r
+ if(m_xranhandle) {\r
+ xran_close(m_xranhandle);\r
+ m_xranhandle = nullptr;\r
+ std::cout << "CLOSE DONE" << std::endl;\r
+ }\r
+ else\r
+ std::cout << "ALREADY CLOSED" << std::endl;\r
+ }\r
+\r
+ int Init(struct xran_fh_config *pCfg = nullptr)\r
+ {\r
+ xran_status_t status;\r
+ int32_t nSectorNum;\r
+ int32_t i, j, k, z;\r
+ void *ptr;\r
+ void *mb;\r
+ uint32_t *u32dptr;\r
+ uint16_t *u16dptr;\r
+ uint8_t *u8dptr;\r
+ SWXRANInterfaceTypeEnum eInterfaceType;\r
+ int32_t cc_id, ant_id, sym_id, tti;\r
+ int32_t flowId;\r
+ char *pos = NULL;\r
+ struct xran_prb_map *pRbMap = NULL;\r
+\r
+\r
+ /* Update member variables */\r
+ if(pCfg)\r
+ memcpy(&m_xranConf, pCfg, sizeof(struct xran_fh_config));\r
+\r
+ /* Init timer context */\r
+ xran_lib_ota_tti = 0;\r
+ xran_lib_ota_sym = 0;\r
+ xran_lib_ota_sym_idx = 0;\r
+ for(i=0; i < MAX_NUM_OF_XRAN_CTX; i++)\r
+ m_timer_ctx[i].tti_to_process = i;\r
+\r
+ nSectorNum = get_num_cc();\r
+\r
+ /* Cat B RU support */\r
+ if(get_rucategory() == XRAN_CATEGORY_B) {\r
+ /* 10 * [14*32*273*2*2] = 4892160 bytes */\r
+ iq_bfw_buffer_size_dl = (m_nSlots * N_SYM_PER_SLOT * get_num_antelmtrx() * get_num_dlrbs() * 4L);\r
+ iq_bfw_buffer_size_ul = (m_nSlots * N_SYM_PER_SLOT * get_num_antelmtrx() * get_num_ulrbs() * 4L);\r
+\r
+ for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(get_num_cc() * get_num_eaxc()); i++) {\r
+ p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl);\r
+ tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl;\r
+ if(p_tx_dl_bfw_buffer[i] == NULL)\r
+ return(-1);\r
+\r
+ memset(p_tx_dl_bfw_buffer[i], 'D', iq_bfw_buffer_size_dl);\r
+ tx_dl_bfw_buffer_position[i] = 0;\r
+\r
+ p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_ul);\r
+ tx_ul_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_ul;\r
+ if(p_tx_ul_bfw_buffer[i] == NULL)\r
+ return (-1);\r
+\r
+ memset(p_tx_ul_bfw_buffer[i], 'U', iq_bfw_buffer_size_ul);\r
+ tx_ul_bfw_buffer_position[i] = 0;\r
+ }\r
+ }\r
+\r
+ /* Init RB map */\r
+ for(cc_id = 0; cc_id <nSectorNum; cc_id++) {\r
+ for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) {\r
+ for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++) {\r
+ flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;\r
+\r
+ /* C-plane DL */\r
+ pRbMap = (struct xran_prb_map *)m_sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;\r
+ if(pRbMap) {\r
+ pRbMap->dir = XRAN_DIR_DL;\r
+ pRbMap->xran_port = 0;\r
+ pRbMap->band_id = 0;\r
+ pRbMap->cc_id = cc_id;\r
+ pRbMap->ru_port_id = ant_id;\r
+ pRbMap->tti_id = tti;\r
+ pRbMap->start_sym_id = 0;\r
+\r
+ pRbMap->nPrbElm = 1;\r
+ pRbMap->prbMap[0].nRBStart = 0;\r
+ pRbMap->prbMap[0].nRBSize = get_num_dlrbs();\r
+ pRbMap->prbMap[0].nStartSymb = 0;\r
+ pRbMap->prbMap[0].numSymb = 14;\r
+ pRbMap->prbMap[0].nBeamIndex = 0;\r
+ pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;\r
+\r
+ if(get_rucategory() == XRAN_CATEGORY_A) {\r
+ pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_ID_BASED;\r
+ pRbMap->prbMap[0].bf_weight_update = 0;\r
+ //pRbMap->prbMap[0].bf_attribute.weight[];\r
+ //pRbMap->prbMap[0].bf_precoding.weight[];\r
+ }\r
+ else if(get_rucategory() == XRAN_CATEGORY_B) {\r
+ int idxElm;\r
+ int iPrb;\r
+ char *dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];\r
+ struct xran_prb_elm* p_prbMap = NULL;\r
+ int num_antelm;\r
+\r
+ pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;\r
+ pRbMap->prbMap[0].bf_weight_update = 1;\r
+\r
+ num_antelm = get_num_antelmtrx();\r
+#if 0\r
+ /* populate beam weights to C-plane for each elm */\r
+ pRbMap->bf_weight.nAntElmTRx = num_antelm;\r
+ for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){\r
+ p_prbMap = &pRbMap->prbMap[idxElm];\r
+ for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++) {\r
+ /* copy BF W IQs for 1 PRB of */\r
+ rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4);\r
+ }\r
+ }\r
+#endif\r
+ } /* else if(get_rucategory() == XRAN_CATEGORY_B) */\r
+ } /* if(pRbMap) */\r
+ else {\r
+ std::cout << "DL pRbMap ==NULL" << std::endl;\r
+ }\r
+\r
+ /* C-plane UL */\r
+ pRbMap = (struct xran_prb_map *)m_sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;\r
+ if(pRbMap) {\r
+ pRbMap->dir = XRAN_DIR_UL;\r
+ pRbMap->xran_port = 0;\r
+ pRbMap->band_id = 0;\r
+ pRbMap->cc_id = cc_id;\r
+ pRbMap->ru_port_id = ant_id;\r
+ pRbMap->tti_id = tti;\r
+ pRbMap->start_sym_id = 0;\r
+\r
+ pRbMap->nPrbElm = 1;\r
+ pRbMap->prbMap[0].nRBStart = 0;\r
+ pRbMap->prbMap[0].nRBSize = get_num_ulrbs();\r
+ pRbMap->prbMap[0].nStartSymb = 0;\r
+ pRbMap->prbMap[0].numSymb = 14;\r
+ pRbMap->prbMap[0].nBeamIndex = 0;\r
+ pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;\r
+\r
+ if(get_rucategory() == XRAN_CATEGORY_A) {\r
+ pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_ID_BASED;\r
+ pRbMap->prbMap[0].bf_weight_update = 0;\r
+ //pRbMap->prbMap[0].bf_attribute.weight[];\r
+ //pRbMap->prbMap[0].bf_precoding.weight[];\r
+ }\r
+ else if(get_rucategory() == XRAN_CATEGORY_B) {\r
+ int idxElm;\r
+ int iPrb;\r
+ char *ul_bfw_pos = ((char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId];\r
+ struct xran_prb_elm* p_prbMap = NULL;\r
+ int num_antelm;\r
+\r
+ pRbMap->prbMap[0].BeamFormingType = XRAN_BEAM_WEIGHT;\r
+ pRbMap->prbMap[0].bf_weight_update = 1;\r
+\r
+ num_antelm = get_num_antelmtrx();\r
+#if 0\r
+ /* populate beam weights to C-plane for each elm */\r
+ pRbMap->bf_weight.nAntElmTRx = num_antelm;\r
+ for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){\r
+ p_prbMap = &pRbMap->prbMap[idxElm];\r
+ for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++){\r
+ /* copy BF W IQs for 1 PRB of */\r
+ rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (ul_bfw_pos + (iPrb*num_antelm)*4), num_antelm*4);\r
+ }\r
+ }\r
+#endif\r
+ } /* else if(get_rucategory() == XRAN_CATEGORY_B) */\r
+\r
+ } /* if(pRbMap) */\r
+ else {\r
+ std::cout << "UL: pRbMap ==NULL" << std::endl;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return (0);\r
+ }\r
+\r
+ void Cleanup()\r
+ {\r
+ int i;\r
+\r
+ if(get_rucategory() == XRAN_CATEGORY_B) {\r
+ for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(get_num_cc() * get_num_eaxc()); i++) {\r
+ if(p_tx_dl_bfw_buffer[i]) {\r
+ free(p_tx_dl_bfw_buffer[i]);\r
+ p_tx_dl_bfw_buffer[i] == NULL;\r
+ }\r
+\r
+ if(p_tx_ul_bfw_buffer[i]) {\r
+ free(p_tx_ul_bfw_buffer[i]);\r
+ p_tx_ul_bfw_buffer[i] == NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return;\r
+ }\r
+\r
+\r
+ void Open(xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up,\r
+ void *fh_rx_callback, void *fh_rx_prach_callback)\r
+ {\r
+ struct xran_fh_config *pXranConf;\r
+ int32_t nSectorNum;\r
+ int i, j, k, z;\r
+ struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];\r
+ struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];\r
+ struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];\r
+ struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];\r
+ struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];\r
+\r
+#if 0\r
+ xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);\r
+ xran_reg_physide_cb(xranHandle, physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);\r
+ xran_reg_physide_cb(xranHandle, physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX);\r
+#endif\r
+ nSectorNum = get_num_cc();\r
+\r
+ for(i=0; i<nSectorNum; i++) {\r
+ for(j=0; j<XRAN_N_FE_BUF_LEN; j++) {\r
+ for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++) {\r
+ pFthTxBuffer[i][z][j] = &(m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);\r
+ pFthTxPrbMapBuffer[i][z][j] = &(m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);\r
+ pFthRxBuffer[i][z][j] = &(m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);\r
+ pFthRxPrbMapBuffer[i][z][j] = &(m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);\r
+ pFthRxRachBuffer[i][z][j] = &(m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);\r
+ }\r
+ }\r
+ }\r
+\r
+ if(m_nInstanceHandle[0] != NULL) {\r
+ for(i = 0; i<nSectorNum; i++) {\r
+ xran_5g_fronthault_config(m_nInstanceHandle[0][i],\r
+ pFthTxBuffer[i], pFthTxPrbMapBuffer[i],\r
+ pFthRxBuffer[i], pFthRxPrbMapBuffer[i],\r
+ (void (*)(void *, xran_status_t))fh_rx_callback, &pFthRxBuffer[i][0]);\r
+\r
+ xran_5g_prach_req(m_nInstanceHandle[0][i], pFthRxRachBuffer[i],\r
+ (void (*)(void *, xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i][0]);\r
+ }\r
+ }\r
+\r
+ xran_register_cb_mbuf2ring(send_cp, send_up);\r
+\r
+ xran_open(m_xranhandle, &m_xranConf);\r
+ }\r
+\r
+ void Close()\r
+ {\r
+ if(m_xranhandle)\r
+ xran_close(m_xranhandle);\r
+ }\r
+\r
+ int Start()\r
+ {\r
+ if(m_xranhandle)\r
+ return(xran_start(m_xranhandle));\r
+ else\r
+ return (-1);\r
+ }\r
+\r
+ int Stop()\r
+ {\r
+ if(m_xranhandle)\r
+ return(xran_stop(m_xranhandle));\r
+ else\r
+ return (-1);\r
+ }\r
+\r
+ /* emulation of timer */\r
+ void update_tti()\r
+ {\r
+ tti_ota_cb(nullptr, get_timer_ctx());\r
+ }\r
+\r
+ void update_symbol_index()\r
+ {\r
+ xran_lib_ota_sym_idx++;\r
+ if((xran_lib_ota_sym_idx % N_SYM_PER_SLOT) == 0) {\r
+ update_tti();\r
+ }\r
+\r
+ xran_lib_ota_sym++;\r
+ if(xran_lib_ota_sym >= N_SYM_PER_SLOT)\r
+ xran_lib_ota_sym = 0;\r
+ }\r
+\r
+ int apply_cpenable(bool flag)\r
+ {\r
+ struct xran_device_ctx *pCtx = xran_dev_get_ctx();\r
+\r
+ if(is_running())\r
+ return (-1);\r
+\r
+ if(pCtx == nullptr)\r
+ return (-1);\r
+\r
+ if(flag == true) {\r
+ m_xranInit.enableCP = 1;\r
+ pCtx->enableCP = 1;\r
+ }\r
+ else {\r
+ m_xranInit.enableCP = 0;\r
+ pCtx->enableCP = 0;\r
+ }\r
+\r
+ return (0);\r
+ }\r
+\r
+\r
+ int get_slot_config(const std::string &cfgname, struct xran_frame_config *pCfg)\r
+ {\r
+ int numcfg, i, j;\r
+ std::vector<int> slotcfg;\r
+\r
+ numcfg = get_globalcfg<int>(cfgname, "period");\r
+ pCfg->nTddPeriod = numcfg;\r
+ for(i=0; i < numcfg; i++) {\r
+ std::stringstream slotcfgname;\r
+\r
+ slotcfgname << "slot" << i;\r
+ std::vector<int> slotcfg = get_globalcfg_array<int>(cfgname, slotcfgname.str());\r
+\r
+ for(j=0; j < slotcfg.size(); j++)\r
+ pCfg->sSlotConfig[i].nSymbolType[j] = slotcfg[j];\r
+ pCfg->sSlotConfig[i].reserved[0] = 0; pCfg->sSlotConfig[i].reserved[1] = 0;\r
+ }\r
+\r
+ return (numcfg);\r
+ }\r
+\r
+ int get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, bool nSub6)\r
+ {\r
+ if(nNumerology > 3)\r
+ return (-1);\r
+\r
+ if(nSub6) {\r
+ if (nNumerology < 3) {\r
+ /* F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB */\r
+ switch(nBandwidth) {\r
+ case PHY_BW_5MHZ: return(nNumRbsPerSymF1[nNumerology][0]);\r
+ case PHY_BW_10MHZ: return(nNumRbsPerSymF1[nNumerology][1]);\r
+ case PHY_BW_15MHZ: return(nNumRbsPerSymF1[nNumerology][2]);\r
+ case PHY_BW_20MHZ: return(nNumRbsPerSymF1[nNumerology][3]);\r
+ case PHY_BW_25MHZ: return(nNumRbsPerSymF1[nNumerology][4]);\r
+ case PHY_BW_30MHZ: return(nNumRbsPerSymF1[nNumerology][5]);\r
+ case PHY_BW_40MHZ: return(nNumRbsPerSymF1[nNumerology][6]);\r
+ case PHY_BW_50MHZ: return(nNumRbsPerSymF1[nNumerology][7]);\r
+ case PHY_BW_60MHZ: return(nNumRbsPerSymF1[nNumerology][8]);\r
+ case PHY_BW_70MHZ: return(nNumRbsPerSymF1[nNumerology][9]);\r
+ case PHY_BW_80MHZ: return(nNumRbsPerSymF1[nNumerology][10]);\r
+ case PHY_BW_90MHZ: return(nNumRbsPerSymF1[nNumerology][11]);\r
+ case PHY_BW_100MHZ: return(nNumRbsPerSymF1[nNumerology][12]);\r
+ }\r
+ }\r
+ }\r
+ else { /* if(nSub6) */\r
+ if((nNumerology >= 2) && (nNumerology <= 3)) {\r
+ nNumerology -= 2;\r
+ /* F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB */\r
+ switch(nBandwidth) {\r
+ case PHY_BW_50MHZ: return(nNumRbsPerSymF2[nNumerology][0]); break;\r
+ case PHY_BW_100MHZ: return(nNumRbsPerSymF2[nNumerology][1]); break;\r
+ case PHY_BW_200MHZ: return(nNumRbsPerSymF2[nNumerology][2]); break;\r
+ case PHY_BW_400MHZ: return(nNumRbsPerSymF2[nNumerology][3]); break;\r
+ }\r
+ }\r
+ }\r
+\r
+ return(-1);\r
+ }\r
+\r
+ void *get_xranhandle() { return(m_xranhandle); }\r
+ void *get_timer_ctx() { return((void *)&m_timer_ctx[0]); }\r
+\r
+ int get_symbol_index() { return (xran_lib_ota_sym); }\r
+\r
+ bool is_running() { return((xran_get_if_state() == XRAN_RUNNING)?true:false); }\r
+\r
+ enum xran_category get_rucategory() { return(m_xranConf.ru_conf.xranCat); }\r
+\r
+ int get_numerology() { return(m_xranConf.frame_conf.nNumerology); }\r
+ int get_duplextype() { return(m_xranConf.frame_conf.nFrameDuplexType); }\r
+ int get_num_cc() { return(m_xranConf.nCC); }\r
+ int get_num_eaxc() { return(m_xranConf.neAxc); }\r
+ int get_num_dlrbs() { return(m_xranConf.nDLRBs); }\r
+ int get_num_ulrbs() { return(m_xranConf.nULRBs); }\r
+ int get_num_antelmtrx() { return(m_xranConf.nAntElmTRx); }\r
+\r
+ bool is_cpenable() { return(m_xranInit.enableCP); };\r
+ bool is_prachenable() { return(m_xranInit.prachEnable); };\r
+ bool is_dynamicsection() { return(m_xranInit.DynamicSectionEna?true:false); }\r
+\r
+ void get_cfg_prach(struct xran_prach_config *pCfg)\r
+ {\r
+ if(pCfg)\r
+ memcpy(pCfg, &m_xranConf.prach_conf, sizeof(struct xran_prach_config));\r
+ }\r
+\r
+ void get_cfg_frame(struct xran_frame_config *pCfg)\r
+ {\r
+ if(pCfg)\r
+ memcpy(pCfg, &m_xranConf.frame_conf, sizeof(struct xran_frame_config));\r
+ }\r
+\r
+ void get_cfg_ru(struct xran_ru_config *pCfg)\r
+ {\r
+ if(pCfg)\r
+ memcpy(pCfg, &m_xranConf.ru_conf, sizeof(struct xran_ru_config));\r
+ }\r
+\r
+ void get_cfg_fh(struct xran_fh_config *pCfg)\r
+ {\r
+ if(pCfg)\r
+ memcpy(pCfg, &m_xranConf, sizeof(struct xran_fh_config));\r
+ }\r
+\r
+};\r
+\r
+\r
+/* external declaration for the instance */\r
+extern xranLibWraper *xranlib;\r
+\r
+\r
+#endif //XRAN_LIB_WRAP_HPP\r
Code Review / o-du / phy.git / blobdiff