-#######################################################################
+#******************************************************************************
#
-# <COPYRIGHT_TAG>
+# Copyright (c) 2019 Intel.
#
-#######################################################################
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#******************************************************************************/
+
# This is simple configuration file. Use '#' sign for comments
+instanceId=0 # 0,1,2,... in case more than 1 application started on the same system
appMode=0 # lls-CU(0) | RU(1)
xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU)
-ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
-antNum=4 # Number of Antennas per CC (default: 4)
+ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12)
+antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B
##Numerology
mu=0 #15Khz Sub Carrier Spacing
nFrameDuplexType=0 # 0 - FDD 1 - TDD
nTddPeriod=0 #TDD priod e.g. DDDS 4
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
#xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec
Gps_Beta=0
ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-
-llsCUMac=00:11:22:33:44:66 # asigned MAC of lls-CU VF
-ruMac=00:11:22:33:44:55 #RU VF for RU app
-#ruMac=3c:fd:fe:9e:93:68 #RU PF for tcpdump
-
-numSlots=20 #number of slots per IQ files
-#fd 10Mhz 2
-#antC0=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC0=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC1=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC2=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC3=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC4=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC5=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC6=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC7=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC8=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC9=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC10=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC11=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC12=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC13=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC14=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC15=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC16=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC17=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC18=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC19=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC20=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC21=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC22=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC23=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC24=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC25=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC26=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC27=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC28=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC29=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC30=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC31=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC32=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC33=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC34=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC35=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC36=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC37=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC38=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC39=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC40=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC41=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC42=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC43=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-antC44=./usecase/mu0_20mhz/12/uliq0.bin #CC0
-antC45=./usecase/mu0_20mhz/12/uliq1.bin #CC0
-antC46=./usecase/mu0_20mhz/12/uliq2.bin #CC0
-antC47=./usecase/mu0_20mhz/12/uliq3.bin #CC0
-
-
-#antC0=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/ant_1.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/ant_2.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/ant_3.bin #CC0
-
-#antC0=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC1=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC2=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-#antC3=./usecase/mu0_20mhz/12/ant_0.bin #CC0
-
-#antC4=./usecase/mu0_20mhz/12/ant_4.bin #CC1
-#antC5=./usecase/mu0_20mhz/12/ant_5.bin #CC1
-#antC6=./usecase/mu0_20mhz/12/ant_6.bin #CC1
-#antC7=./usecase/mu0_20mhz/12/ant_7.bin #CC1
-#antC8=./usecase/mu0_20mhz/12/ant_8.bin #CC2
-#antC9=./usecase/mu0_20mhz/12/ant_9.bin #CC2
-#antC10=./usecase/mu0_20mhz/12/ant_10.bin #CC2
-#antC11=./usecase/mu0_20mhz/12/ant_11.bin #CC2
-#antC12=./usecase/mu0_20mhz/12/ant_12.bin #CC3
-#antC13=./usecase/mu0_20mhz/12/ant_13.bin #CC3
-#antC14=./usecase/mu0_20mhz/12/ant_14.bin #CC3
-#antC15=./usecase/mu0_20mhz/12/ant_15.bin #CC3
-#antC16=./usecase/mu0_20mhz/12/ant_0.bin #CC4
-#antC17=./usecase/mu0_20mhz/12/ant_1.bin #CC4
-#antC18=./usecase/mu0_20mhz/12/ant_2.bin #CC4
-#antC19=./usecase/mu0_20mhz/12/ant_3.bin #CC4
-#antC20=./usecase/mu0_20mhz/12/ant_4.bin #CC5
-#antC21=./usecase/mu0_20mhz/12/ant_5.bin #CC5
-#antC22=./usecase/mu0_20mhz/12/ant_6.bin #CC5
-#antC23=./usecase/mu0_20mhz/12/ant_7.bin #CC5
-#antC24=./usecase/mu0_20mhz/12/ant_8.bin #CC6
-#antC25=./usecase/mu0_20mhz/12/ant_9.bin #CC6
-#antC26=./usecase/mu0_20mhz/12/ant_10.bin #CC6
-#antC27=./usecase/mu0_20mhz/12/ant_11.bin #CC6
-#antC28=./usecase/mu0_20mhz/12/ant_12.bin #CC7
-#antC29=./usecase/mu0_20mhz/12/ant_13.bin #CC7
-#antC30=./usecase/mu0_20mhz/12/ant_14.bin #CC7
-#antC31=./usecase/mu0_20mhz/12/ant_15.bin #CC7
-#antC32=./usecase/mu0_20mhz/12/ant_0.bin #CC8
-#antC33=./usecase/mu0_20mhz/12/ant_1.bin #CC8
-#antC34=./usecase/mu0_20mhz/12/ant_2.bin #CC8
-#antC35=./usecase/mu0_20mhz/12/ant_3.bin #CC8
-#antC36=./usecase/mu0_20mhz/12/ant_4.bin #CC9
-#antC37=./usecase/mu0_20mhz/12/ant_5.bin #CC9
-#antC38=./usecase/mu0_20mhz/12/ant_6.bin #CC9
-#antC39=./usecase/mu0_20mhz/12/ant_7.bin #CC9
-#antC40=./usecase/mu0_20mhz/12/ant_8.bin #CC10
-#antC41=./usecase/mu0_20mhz/12/ant_9.bin #CC10
-#antC42=./usecase/mu0_20mhz/12/ant_10.bin #CC10
-#antC43=./usecase/mu0_20mhz/12/ant_11.bin #CC10
-#antC44=./usecase/mu0_20mhz/12/ant_12.bin #CC11
-#antC45=./usecase/mu0_20mhz/12/ant_13.bin #CC11
-#antC46=./usecase/mu0_20mhz/12/ant_14.bin #CC11
-#antC47=./usecase/mu0_20mhz/12/ant_15.bin #CC11
-
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+#Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=40 #number of slots per IQ files
+
+antC0=./usecase/mu0_20mhz/ant_0.bin #CC0
+antC1=./usecase/mu0_20mhz/ant_1.bin #CC0
+antC2=./usecase/mu0_20mhz/ant_2.bin #CC0
+antC3=./usecase/mu0_20mhz/ant_3.bin #CC0
+antC4=./usecase/mu0_20mhz/ant_0.bin #CC1
+antC5=./usecase/mu0_20mhz/ant_1.bin #CC1
+antC6=./usecase/mu0_20mhz/ant_2.bin #CC1
+antC7=./usecase/mu0_20mhz/ant_3.bin #CC1
+antC8=./usecase/mu0_20mhz/ant_0.bin #CC2
+antC9=./usecase/mu0_20mhz/ant_1.bin #CC2
+antC10=./usecase/mu0_20mhz/ant_2.bin #CC2
+antC11=./usecase/mu0_20mhz/ant_3.bin #CC2
+antC12=./usecase/mu0_20mhz/ant_0.bin #CC3
+antC13=./usecase/mu0_20mhz/ant_1.bin #CC3
+antC14=./usecase/mu0_20mhz/ant_2.bin #CC3
+antC15=./usecase/mu0_20mhz/ant_3.bin #CC3
+antC16=./usecase/mu0_20mhz/ant_0.bin #CC4
+antC17=./usecase/mu0_20mhz/ant_1.bin #CC4
+antC18=./usecase/mu0_20mhz/ant_2.bin #CC4
+antC19=./usecase/mu0_20mhz/ant_3.bin #CC4
+antC20=./usecase/mu0_20mhz/ant_0.bin #CC5
+antC21=./usecase/mu0_20mhz/ant_1.bin #CC5
+antC22=./usecase/mu0_20mhz/ant_2.bin #CC5
+antC23=./usecase/mu0_20mhz/ant_3.bin #CC5
+antC24=./usecase/mu0_20mhz/ant_0.bin #CC6
+antC25=./usecase/mu0_20mhz/ant_1.bin #CC6
+antC26=./usecase/mu0_20mhz/ant_2.bin #CC6
+antC27=./usecase/mu0_20mhz/ant_3.bin #CC6
+antC28=./usecase/mu0_20mhz/ant_0.bin #CC7
+antC29=./usecase/mu0_20mhz/ant_1.bin #CC7
+antC30=./usecase/mu0_20mhz/ant_2.bin #CC7
+antC31=./usecase/mu0_20mhz/ant_3.bin #CC7
+antC32=./usecase/mu0_20mhz/ant_0.bin #CC8
+antC33=./usecase/mu0_20mhz/ant_1.bin #CC8
+antC34=./usecase/mu0_20mhz/ant_2.bin #CC8
+antC35=./usecase/mu0_20mhz/ant_3.bin #CC8
+antC36=./usecase/mu0_20mhz/ant_0.bin #CC9
+antC37=./usecase/mu0_20mhz/ant_1.bin #CC9
+antC38=./usecase/mu0_20mhz/ant_2.bin #CC9
+antC39=./usecase/mu0_20mhz/ant_3.bin #CC9
+antC40=./usecase/mu0_20mhz/ant_0.bin #CC10
+antC41=./usecase/mu0_20mhz/ant_1.bin #CC10
+antC42=./usecase/mu0_20mhz/ant_2.bin #CC10
+antC43=./usecase/mu0_20mhz/ant_3.bin #CC10
+antC44=./usecase/mu0_20mhz/ant_0.bin #CC11
+antC45=./usecase/mu0_20mhz/ant_1.bin #CC11
+antC46=./usecase/mu0_20mhz/ant_2.bin #CC11
+antC47=./usecase/mu0_20mhz/ant_3.bin #CC11
+
+rachEanble=1 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,75,0,14,0,1,0,16,1
+nPrbElemUl=1
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,75,0,14,0,1,0,16,1
+###########################################################
+
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
##Debug
-debugStop=0 #stop app on 1pps boundary (gps_second % 30)
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled
c_plane_vlan_tag=1 #VLAN Tag used for C-Plane
u_plane_vlan_tag=2 #VLAN Tag used for U-Plane
##RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
Tadv_cp_dl=25 #in us TODO: update per RU implementation
#C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
#Reception Window C-plane DL
-T2a_min_cp_dl=400 #in us
-T2a_max_cp_dl=1120 #in us
+T2a_min_cp_dl=400 #in us
+T2a_max_cp_dl=1120 #in us
#Reception Window C-plane UL
-T2a_min_cp_ul=400 #in us
-T2a_max_cp_ul=1120 #in us
+T2a_min_cp_ul=400 #in us
+T2a_max_cp_ul=1120 #in us
#Reception Window U-plane
T2a_min_up=200 # in us
Code Review / o-du / phy.git / blobdiff