* INTC Contribution to the O-RAN F Release for O-DU Low

[o-du/phy.git] / fhi_lib / app / usecase / cat_b / mu1_100mhz / 104 / config_file_o_ru.dat

diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat
index 8d31d15..cf3f7a8 100644 (file)
--- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat
+++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat
@@ -64,15 +64,20 @@ MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protoco
 Gps_Alpha=0    #alpha and beta value as in section 9.7.2 of ORAN spec
 Gps_Beta=0
 
-ioCore=10
-systemCore=10
-pktProcCore=10
-pktAuxCore=10
-timingCore=11
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55    # O-RU VF for O-RU app
-
-numSlots=10 #number of slots per IQ files
+ioCore=15
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
 antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin   #CC0
 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin   #CC0
 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin   #CC0
@@ -107,11 +112,14 @@ antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin  #CC3
 antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin  #CC3
 antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin  #CC3
 
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
 prachConfigIndex=189
 
-srsEanble=1 # Enable (1)| disable (0) SRS 
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # enable (1)| disable (0) srs
+srsSym=4 # deprecated
+srsSlot=3           # scheduled srs slot within tdd period
+srsNdmOffset=3      # delay offset to start ndm srs u-plane
+srsNdmTxDuration=4  # tx duration for ndm srts u-plane (numberof of symbols)
 
 antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin   
 antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin   
@@ -199,6 +207,9 @@ PrbElemUl0=0,30,0,14,0,1,1,9,1
 PrbElemUl1=30,30,0,14,1,1,1,9,1
 PrbElemUl2=60,30,0,14,2,1,1,9,1
 
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
 ###########################################################
 
 ## control of IQ byte order