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O-RAN E Maintenance Release contribution for ODULOW
[o-du/phy.git] / fhi_lib / app / usecase / cat_a / mu0_10mhz / config_file_o_ru.dat
diff --git a/fhi_lib/app/usecase/mu0_10mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_ru.dat
similarity index 59%
rename from fhi_lib/app/usecase/mu0_10mhz/config_file_o_ru.dat
rename to fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_ru.dat
index a972a17..051ba45 100644 (file)
--- a/fhi_lib/app/usecase/mu0_10mhz/config_file_o_ru.dat
+++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_ru.dat
@@ -37,7 +37,7 @@ nULFftSize=1024
 nFrameDuplexType=0 # 0 - FDD 1 - TDD
 nTddPeriod=0 #TDD priod e.g. DDDS 4
 
-MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single 
+MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single
  #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame)
 Gps_Alpha=0    #alpha and beta value as in section 9.7.2 of ORAN spec
 Gps_Beta=0
@@ -55,64 +55,64 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
 duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
 ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
 
-numSlots=40 #number of slots per IQ files
-
-antC0=./usecase/mu0_10mhz/ant_0.bin    #CC0  
-antC1=./usecase/mu0_10mhz/ant_1.bin    #CC0  
-antC2=./usecase/mu0_10mhz/ant_2.bin    #CC0  
-antC3=./usecase/mu0_10mhz/ant_3.bin    #CC0  
-antC4=./usecase/mu0_10mhz/ant_4.bin    #CC1  
-antC5=./usecase/mu0_10mhz/ant_5.bin    #CC1  
-antC6=./usecase/mu0_10mhz/ant_6.bin    #CC1  
-antC7=./usecase/mu0_10mhz/ant_7.bin    #CC1  
-antC8=./usecase/mu0_10mhz/ant_8.bin    #CC2  
-antC9=./usecase/mu0_10mhz/ant_9.bin    #CC2  
-antC10=./usecase/mu0_10mhz/ant_10.bin  #CC2   
-antC11=./usecase/mu0_10mhz/ant_11.bin  #CC2   
-antC12=./usecase/mu0_10mhz/ant_12.bin  #CC3   
-antC13=./usecase/mu0_10mhz/ant_13.bin  #CC3   
-antC14=./usecase/mu0_10mhz/ant_14.bin  #CC3   
-antC15=./usecase/mu0_10mhz/ant_15.bin  #CC3   
-antC16=./usecase/mu0_10mhz/ant_0.bin   #CC4   
-antC17=./usecase/mu0_10mhz/ant_1.bin   #CC4   
-antC18=./usecase/mu0_10mhz/ant_2.bin   #CC4   
-antC19=./usecase/mu0_10mhz/ant_3.bin   #CC4   
-antC20=./usecase/mu0_10mhz/ant_4.bin   #CC5   
-antC21=./usecase/mu0_10mhz/ant_5.bin   #CC5   
-antC22=./usecase/mu0_10mhz/ant_6.bin   #CC5   
-antC23=./usecase/mu0_10mhz/ant_7.bin   #CC5   
-antC24=./usecase/mu0_10mhz/ant_8.bin   #CC6   
-antC25=./usecase/mu0_10mhz/ant_9.bin   #CC6   
-antC26=./usecase/mu0_10mhz/ant_10.bin  #CC6   
-antC27=./usecase/mu0_10mhz/ant_11.bin  #CC6   
-antC28=./usecase/mu0_10mhz/ant_12.bin  #CC7   
-antC29=./usecase/mu0_10mhz/ant_13.bin  #CC7   
-antC30=./usecase/mu0_10mhz/ant_14.bin  #CC7   
-antC31=./usecase/mu0_10mhz/ant_15.bin  #CC7   
-antC32=./usecase/mu0_10mhz/ant_0.bin   #CC8  
-antC33=./usecase/mu0_10mhz/ant_1.bin   #CC8  
-antC34=./usecase/mu0_10mhz/ant_2.bin   #CC8  
-antC35=./usecase/mu0_10mhz/ant_3.bin   #CC8  
-antC36=./usecase/mu0_10mhz/ant_4.bin   #CC9  
-antC37=./usecase/mu0_10mhz/ant_5.bin   #CC9  
-antC38=./usecase/mu0_10mhz/ant_6.bin   #CC9  
-antC39=./usecase/mu0_10mhz/ant_7.bin   #CC9  
-antC40=./usecase/mu0_10mhz/ant_8.bin   #CC10 
-antC41=./usecase/mu0_10mhz/ant_9.bin   #CC10 
-antC42=./usecase/mu0_10mhz/ant_10.bin  #CC10 
-antC43=./usecase/mu0_10mhz/ant_11.bin  #CC10 
-antC44=./usecase/mu0_10mhz/ant_12.bin  #CC11 
-antC45=./usecase/mu0_10mhz/ant_13.bin  #CC11 
-antC46=./usecase/mu0_10mhz/ant_14.bin  #CC11 
-antC47=./usecase/mu0_10mhz/ant_15.bin  #CC11 
+numSlots=20 #number of slots per IQ files
+
+antC0=./usecase/cat_a/mu0_10mhz/ant_0.bin    #CC0
+antC1=./usecase/cat_a/mu0_10mhz/ant_1.bin    #CC0
+antC2=./usecase/cat_a/mu0_10mhz/ant_2.bin    #CC0
+antC3=./usecase/cat_a/mu0_10mhz/ant_3.bin    #CC0
+antC4=./usecase/cat_a/mu0_10mhz/ant_4.bin    #CC1
+antC5=./usecase/cat_a/mu0_10mhz/ant_5.bin    #CC1
+antC6=./usecase/cat_a/mu0_10mhz/ant_6.bin    #CC1
+antC7=./usecase/cat_a/mu0_10mhz/ant_7.bin    #CC1
+antC8=./usecase/cat_a/mu0_10mhz/ant_8.bin    #CC2
+antC9=./usecase/cat_a/mu0_10mhz/ant_9.bin    #CC2
+antC10=./usecase/cat_a/mu0_10mhz/ant_10.bin  #CC2
+antC11=./usecase/cat_a/mu0_10mhz/ant_11.bin  #CC2
+antC12=./usecase/cat_a/mu0_10mhz/ant_12.bin  #CC3
+antC13=./usecase/cat_a/mu0_10mhz/ant_13.bin  #CC3
+antC14=./usecase/cat_a/mu0_10mhz/ant_14.bin  #CC3
+antC15=./usecase/cat_a/mu0_10mhz/ant_15.bin  #CC3
+antC16=./usecase/cat_a/mu0_10mhz/ant_0.bin   #CC4
+antC17=./usecase/cat_a/mu0_10mhz/ant_1.bin   #CC4
+antC18=./usecase/cat_a/mu0_10mhz/ant_2.bin   #CC4
+antC19=./usecase/cat_a/mu0_10mhz/ant_3.bin   #CC4
+antC20=./usecase/cat_a/mu0_10mhz/ant_4.bin   #CC5
+antC21=./usecase/cat_a/mu0_10mhz/ant_5.bin   #CC5
+antC22=./usecase/cat_a/mu0_10mhz/ant_6.bin   #CC5
+antC23=./usecase/cat_a/mu0_10mhz/ant_7.bin   #CC5
+antC24=./usecase/cat_a/mu0_10mhz/ant_8.bin   #CC6
+antC25=./usecase/cat_a/mu0_10mhz/ant_9.bin   #CC6
+antC26=./usecase/cat_a/mu0_10mhz/ant_10.bin  #CC6
+antC27=./usecase/cat_a/mu0_10mhz/ant_11.bin  #CC6
+antC28=./usecase/cat_a/mu0_10mhz/ant_12.bin  #CC7
+antC29=./usecase/cat_a/mu0_10mhz/ant_13.bin  #CC7
+antC30=./usecase/cat_a/mu0_10mhz/ant_14.bin  #CC7
+antC31=./usecase/cat_a/mu0_10mhz/ant_15.bin  #CC7
+antC32=./usecase/cat_a/mu0_10mhz/ant_0.bin   #CC8
+antC33=./usecase/cat_a/mu0_10mhz/ant_1.bin   #CC8
+antC34=./usecase/cat_a/mu0_10mhz/ant_2.bin   #CC8
+antC35=./usecase/cat_a/mu0_10mhz/ant_3.bin   #CC8
+antC36=./usecase/cat_a/mu0_10mhz/ant_4.bin   #CC9
+antC37=./usecase/cat_a/mu0_10mhz/ant_5.bin   #CC9
+antC38=./usecase/cat_a/mu0_10mhz/ant_6.bin   #CC9
+antC39=./usecase/cat_a/mu0_10mhz/ant_7.bin   #CC9
+antC40=./usecase/cat_a/mu0_10mhz/ant_8.bin   #CC10
+antC41=./usecase/cat_a/mu0_10mhz/ant_9.bin   #CC10
+antC42=./usecase/cat_a/mu0_10mhz/ant_10.bin  #CC10
+antC43=./usecase/cat_a/mu0_10mhz/ant_11.bin  #CC10
+antC44=./usecase/cat_a/mu0_10mhz/ant_12.bin  #CC11
+antC45=./usecase/cat_a/mu0_10mhz/ant_13.bin  #CC11
+antC46=./usecase/cat_a/mu0_10mhz/ant_14.bin  #CC11
+antC47=./usecase/cat_a/mu0_10mhz/ant_15.bin  #CC11
 
 rachEanble=1 # Enable (1)| disable (0) PRACH configuration
 prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index
 
-antPrachC0=./usecase/mu0_10mhz/ant_0.bin
-antPrachC1=./usecase/mu0_10mhz/ant_1.bin
-antPrachC2=./usecase/mu0_10mhz/ant_2.bin
-antPrachC3=./usecase/mu0_10mhz/ant_3.bin
+antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin
+antPrachC1=./usecase/cat_a/mu0_10mhz/ant_1.bin
+antPrachC2=./usecase/cat_a/mu0_10mhz/ant_2.bin
+antPrachC3=./usecase/cat_a/mu0_10mhz/ant_3.bin
 
 ## control of IQ byte order
 iqswap=0 #do swap of IQ before send buffer to eth
@@ -133,16 +133,16 @@ Tadv_cp_dl=25 #in us  TODO: update per RU implementation
               #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
 
 #Reception Window C-plane DL
-T2a_min_cp_dl=400  #in us  
-T2a_max_cp_dl=1120 #in us 
+T2a_min_cp_dl=400  #in us
+T2a_max_cp_dl=850 #in us
 
 #Reception Window C-plane UL
-T2a_min_cp_ul=400 #in us  
-T2a_max_cp_ul=1120 #in us 
+T2a_min_cp_ul=400 #in us
+T2a_max_cp_ul=850 #in us
 
 #Reception Window U-plane
 T2a_min_up=200  # in us
-T2a_max_up=1120 # in us
+T2a_max_up=800 # in us
 
 #Transmission Window
 Ta3_min=160 #in us
O-RAN DU Physical Layer