1 /******************************************************************************
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3 * Copyright (c) 2019 Intel.
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5 * Licensed under the Apache License, Version 2.0 (the "License");
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6 * you may not use this file except in compliance with the License.
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7 * You may obtain a copy of the License at
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9 * http://www.apache.org/licenses/LICENSE-2.0
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11 * Unless required by applicable law or agreed to in writing, software
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12 * distributed under the License is distributed on an "AS IS" BASIS,
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13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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14 * See the License for the specific language governing permissions and
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15 * limitations under the License.
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17 *******************************************************************************/
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21 #include <sys/syscall.h>
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26 #include <sys/time.h>
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31 #include <pthread.h>
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32 #include <sys/stat.h>
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38 #include "xran_mlog_lnx.h"
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40 #include "xran_fh_o_du.h"
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41 #include "xran_compression.h"
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42 #include "xran_cp_api.h"
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43 #include "xran_sync_api.h"
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44 #include "xran_mlog_task_id.h"
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46 #define MAX_BBU_POOL_CORE_MASK (4)
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49 #define SW_FPGA_TOTAL_BUFFER_LEN 4*1024*1024*1024
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50 #define SW_FPGA_SEGMENT_BUFFER_LEN 1*1024*1024*1024
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51 #define SW_FPGA_FH_TOTAL_BUFFER_LEN 1*1024*1024*1024
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52 #define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192)
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54 #define NSEC_PER_SEC 1000000000
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56 #define MAX_PKT_BURST (448+4) // 4x14x8
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57 #define N_MAX_BUFFER_SEGMENT MAX_PKT_BURST
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59 #define MAIN_PRIORITY 98
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60 #define NUM_OF_SUBFRAME_PER_FRAME (10)
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62 enum app_state state;
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64 uint64_t tick_per_usec;
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65 static volatile uint64_t timer_last_irq_tick = 0;
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66 static uint64_t tsc_resolution_hz = 0;
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68 RuntimeConfig startupConfiguration = {0};
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71 uint32_t nFpgaToSW_FTH_RxBufferLen;
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72 uint32_t nFpgaToSW_PRACH_RxBufferLen;
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73 uint32_t nSW_ToFpga_FTH_TxBufferLen;
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75 static struct xran_fh_init xranInit;
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76 void * xranHandle = NULL;
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78 struct xran_fh_config xranConf;
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79 struct xran_fh_config *pXranConf = NULL;
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83 uint32_t phaseFlag :1;
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84 uint32_t NRARFCN :22;
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85 uint32_t SULFreShift :1;
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86 uint32_t SULFlag :1;
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90 typedef struct XranLibConfig
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92 uint32_t nDriverCoreId;
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93 uint32_t nTimingAdvance;
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95 uint32_t nFhBufIntFlag;
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96 uint32_t nSectorNum;
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97 uint32_t nNrOfSlotInSf;
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98 uint32_t nNrofSfInFrame;
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99 void * pFthInstanceHandles;
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100 }XranLibConfigStruct;
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103 XRANFTHTX_PRB_MAP_OUT,
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104 XRANFTHTX_SEC_DESC_OUT,
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106 XRANFTHRX_PRB_MAP_IN,
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107 XRANFTHTX_SEC_DESC_IN,
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110 MAX_SW_XRAN_INTERFACE_NUM
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111 }SWXRANInterfaceTypeEnum;
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114 * manage one cell's all Ethernet frames for one DL or UL LTE subframe
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117 /* -1-this subframe is not used in current frame format
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118 0-this subframe can be transmitted, i.e., data is ready
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119 1-this subframe is waiting transmission, i.e., data is not ready
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120 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1,
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123 int32_t bValid ; // when UL rx, it is subframe index.
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124 int32_t nSegToBeGen;
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125 int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE
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126 // -1 means that DL packet to be transmitted is not ready in BS
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127 int32_t nSegTransferred; // number of data segments has been transmitted or received
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128 struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool
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129 struct xran_buffer_list sBufferList;
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130 } BbuIoBufCtrlStruct;
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133 uint64_t nCoreMask;
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134 int16_t cpuSocketId;
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135 uint8_t nDriverCoreId;
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138 struct rte_mempool *bbuio_buf_pool;
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141 BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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142 BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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143 BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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144 BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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145 BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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148 BbuIoBufCtrlStruct sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
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150 /* buffers lists */
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151 struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
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152 struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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153 struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
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154 struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
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155 struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
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157 /* Cat B SRS buffers */
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158 struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
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160 void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector
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161 uint32_t nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool
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162 uint16_t nInstanceNum;
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164 uint64_t nTscTiming[XRAN_N_FE_BUF_LEN]; // records the TSC when a timing packet is received.
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165 } BbuXranIoIfStruct;
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167 static BbuXranIoIfStruct gsXranIoIf;
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168 static XranLibConfigStruct *gpXranLibConfig = NULL;
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170 extern long rx_counter;
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171 extern long tx_counter;
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172 extern long tx_bytes_counter;
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173 extern long rx_bytes_counter;
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174 extern long tx_bytes_per_sec;
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175 extern long rx_bytes_per_sec;
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176 long old_rx_counter = 0;
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177 long old_tx_counter = 0;
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181 #define CPU_HZ tick_per_usec //us
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183 /* Application User space functions */
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184 void xran_fh_rx_callback(void *pCallbackTag, int32_t status);
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185 void xran_fh_rx_prach_callback(void *pCallbackTag, int32_t status);
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187 static BbuXranIoIfStruct *xran_get_ctx(void)
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189 return &gsXranIoIf;
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192 static void print_menu()
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194 puts("+---------------------------------------+");
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195 puts("| Press 1 to start 5G NR XRAN traffic |");
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196 puts("| Press 2 reserved for future use |");
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197 puts("| Press 3 to quit |");
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198 puts("+---------------------------------------+");
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201 static int32_t get_xran_sfidx(uint8_t nNrOfSlotInSf)
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203 int32_t nSfIdx = -1;
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204 uint32_t nFrameIdx;
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205 uint32_t nSubframeIdx;
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209 uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
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210 nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf
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211 + nSubframeIdx*nNrOfSlotInSf
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214 printf("\nxranTime is %d, return is %d, radio frame is %d, subframe is %d slot is %d tsc is %llu us",
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226 void xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
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228 uint64_t t1 = MLogTick();
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229 uint32_t mlogVar[10];
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230 uint32_t mlogVarCnt = 0;
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231 uint8_t Numerlogy = xranConf.frame_conf.nNumerology;
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232 uint8_t nNrOfSlotInSf = 1<<Numerlogy;
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233 int32_t sfIdx = get_xran_sfidx(nNrOfSlotInSf);
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235 mlogVar[mlogVarCnt++] = 0xCCCCCCCC;
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236 mlogVar[mlogVarCnt++] = status >> 16; /* tti */
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237 mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */
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238 mlogVar[mlogVarCnt++] = (uint32_t)sfIdx;
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239 MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
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242 MLogTask(PID_GNB_SYM_CB, t1, MLogTick());
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246 void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
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248 uint64_t t1 = MLogTick();
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249 uint32_t mlogVar[10];
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250 uint32_t mlogVarCnt = 0;
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252 mlogVar[mlogVarCnt++] = 0xDDDDDDDD;
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253 mlogVar[mlogVarCnt++] = status >> 16; /* tti */
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254 mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */
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255 MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
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258 MLogTask(PID_GNB_PRACH_CB, t1, MLogTick());
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261 void xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status)
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263 uint64_t t1 = MLogTick();
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264 uint32_t mlogVar[10];
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265 uint32_t mlogVarCnt = 0;
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267 mlogVar[mlogVarCnt++] = 0xCCCCCCCC;
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268 mlogVar[mlogVarCnt++] = status >> 16; /* tti */
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269 mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */
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270 MLogAddVariables(mlogVarCnt, mlogVar, MLogTick());
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273 MLogTask(PID_GNB_SRS_CB, t1, MLogTick());
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277 //-------------------------------------------------------------------------------------------
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278 /** @ingroup group_nbiot_source_auxlib_timer
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285 * This function reads the rtdsc clock and returns the current value in there.
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288 //-------------------------------------------------------------------------------------------
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289 unsigned long timer_get_ticks(void)
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294 unsigned long tsc_64;
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302 __asm volatile("rdtsc" :
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306 ret = ((unsigned long)tsc.tsc_64);
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310 //-------------------------------------------------------------------------------------------
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311 /** @ingroup group_lte_source_auxlib_timer
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315 * @return 0 if SUCCESS
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318 * This function gets the clock speed of the core and figures out number of ticks per usec.
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319 * It is used by l1app and testmac applications to initialize the mlog utility
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322 //-------------------------------------------------------------------------------------------
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323 int timer_set_tsc_freq_from_clock(void)
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325 #define NS_PER_SEC 1E9
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326 struct timespec sleeptime = {.tv_nsec = 5E8 }; /* 1/2 second */
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327 struct timespec t_start, t_end;
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328 uint64_t tsc_resolution_hz = 0;
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330 if (clock_gettime(CLOCK_MONOTONIC_RAW, &t_start) == 0)
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332 unsigned long ns, end, start = timer_get_ticks();
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333 nanosleep(&sleeptime,NULL);
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334 clock_gettime(CLOCK_MONOTONIC_RAW, &t_end);
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335 end = timer_get_ticks();
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336 ns = ((t_end.tv_sec - t_start.tv_sec) * NS_PER_SEC);
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337 ns += (t_end.tv_nsec - t_start.tv_nsec);
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339 double secs = (double)ns/NS_PER_SEC;
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340 tsc_resolution_hz = (unsigned long)((end - start)/secs);
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342 tick_per_usec = (tsc_resolution_hz / 1000000);
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343 printf("System clock (rdtsc) resolution %lu [Hz]\n", tsc_resolution_hz);
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344 printf("Ticks per us %lu\n", tick_per_usec);
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351 int physide_dl_tti_call_back(void * param)
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353 uint64_t t1 = MLogTick();
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355 MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
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359 int physide_ul_half_slot_call_back(void * param)
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361 uint64_t t1 = MLogTick();
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363 MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
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367 int physide_ul_full_slot_call_back(void * param)
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369 uint64_t t1 = MLogTick();
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371 MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick());
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375 int32_t init_xran(void)
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377 BbuXranIoIfStruct *psBbuIo = xran_get_ctx();
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378 xran_status_t status;
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379 int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
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380 int32_t nSectorNum;
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381 int32_t i, j, k, z;
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389 SWXRANInterfaceTypeEnum eInterfaceType;
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391 XranLibConfigStruct *ptrLibConfig;
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393 struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
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394 struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
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395 struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
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396 struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
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397 struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN];
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398 struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN];
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400 for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
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402 nSectorIndex[nSectorNum] = nSectorNum;
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405 nSectorNum = numCCPorts;
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406 printf ("XRAN front haul xran_mm_init \n");
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407 status = xran_mm_init (xranHandle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN);
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408 if (status != XRAN_STATUS_SUCCESS)
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410 printf ("Failed at XRAN front haul xran_mm_init \n");
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414 psBbuIo->nInstanceNum = numCCPorts;
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416 for (k = 0; k < XRAN_PORTS_NUM; k++) {
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417 status = xran_sector_get_instances (xranHandle, psBbuIo->nInstanceNum,&psBbuIo->nInstanceHandle[k][0]);
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418 if (status != XRAN_STATUS_SUCCESS)
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420 printf ("get sector instance failed %d for XRAN nInstanceNum %d\n",k, psBbuIo->nInstanceNum);
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423 for (i = 0; i < psBbuIo->nInstanceNum; i++){
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424 printf("%s [%d]: CC %d handle %p\n", __FUNCTION__, k, i, psBbuIo->nInstanceHandle[0][i]);
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428 printf("Sucess xran_mm_init \n");
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429 gpXranLibConfig = (XranLibConfigStruct*)malloc(sizeof(XranLibConfigStruct));
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430 ptrLibConfig = gpXranLibConfig;
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434 ptrLibConfig->nDriverCoreId = psBbuIo->nDriverCoreId;
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435 ptrLibConfig->pFecInstanceHandles = &(psBbuIo->nInstanceHandle[FPGA_FEC][0]);
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436 ptrLibConfig->pFthInstanceHandles = &(psBbuIo->nInstanceHandle[FPGA_FRONTHAUL][0]);
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437 ptrLibConfig->nTimingAdvance = psFPGAInitPara->nTimeAdvance;
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438 ptrLibConfig->nFhConfig = psFPGAInitPara->nEthPorts;
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439 ptrLibConfig->nFhBufIntFlag = 0; //need init fronthaul buffer, then set to 1.
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440 ptrLibConfig->nNrofSfInFrame = NUM_OF_SUBFRAME_PER_FRAME;
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441 ptrLibConfig->nNrOfSlotInSf = pConfigParams->nNumOfSlotPerSubframe;
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442 if (pConfigParams->nNumerology < 3)
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444 ptrLibConfig->nSectorNum = psFPGAInitPara->nSecNum;
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450 printf ("could not allocate ptrLibConfig in init_xran\n");
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454 printf("nSectorNum %d\n", nSectorNum);
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457 for(i = 0; i<nSectorNum; i++)
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459 eInterfaceType = XRANFTHTX_OUT;
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460 printf("nSectorIndex[%d] = %d\n",i, nSectorIndex[i]);
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461 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
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462 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
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463 if(XRAN_STATUS_SUCCESS != status) {
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464 rte_panic("Failed at xran_bm_init , status %d\n", status);
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466 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
\r
468 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
\r
469 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0;
\r
470 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
471 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
472 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
473 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
\r
474 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulTxBuffers[j][i][z][0];
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476 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
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478 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol
\r
479 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
\r
480 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
\r
481 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
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482 if(XRAN_STATUS_SUCCESS != status){
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483 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
\r
485 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
\r
486 psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
\r
489 u32dptr = (uint32_t*)(ptr);
\r
490 uint8_t *ptr_temp = (uint8_t *)ptr;
\r
491 memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen);
\r
492 // ptr_temp[0] = j; // TTI
\r
493 // ptr_temp[1] = i; // Sec
\r
494 // ptr_temp[2] = z; // Ant
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495 // ptr_temp[3] = k; // sym
\r
502 eInterfaceType = XRANFTHTX_SEC_DESC_OUT;
\r
503 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
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504 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
\r
505 if(XRAN_STATUS_SUCCESS != status) {
\r
506 rte_panic("Failed at xran_bm_init , status %d\n", status);
\r
509 eInterfaceType = XRANFTHTX_PRB_MAP_OUT;
\r
510 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
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511 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
\r
512 if(XRAN_STATUS_SUCCESS != status) {
\r
513 rte_panic("Failed at xran_bm_init , status %d\n", status);
\r
516 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
\r
518 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
\r
519 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
\r
520 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
521 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
522 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
523 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
\r
524 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulTxPrbMapBuffers[j][i][z];
\r
527 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
\r
528 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
\r
529 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
\r
530 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
\r
531 if(XRAN_STATUS_SUCCESS != status) {
\r
532 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
\r
534 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
\r
535 psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
\r
541 struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
\r
542 if (startupConfiguration.appMode == APP_O_DU)
\r
543 memcpy(ptr, &startupConfiguration.PrbMapDl, sizeof(struct xran_prb_map));
\r
545 memcpy(ptr, &startupConfiguration.PrbMapUl, sizeof(struct xran_prb_map));
\r
547 for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
\r
548 struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
\r
549 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
\r
550 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT],&sd_ptr, &sd_mb);
\r
551 if(XRAN_STATUS_SUCCESS != status){
\r
552 rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status);
\r
554 pPrbElem->p_sec_desc[k] = sd_ptr;
\r
563 for(i = 0; i<nSectorNum; i++)
\r
565 eInterfaceType = XRANFTHRX_IN;
\r
566 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
\r
567 if(XRAN_STATUS_SUCCESS != status)
\r
569 printf("Failed at xran_bm_init, status %d\n", status);
\r
570 iAssert(status == XRAN_STATUS_SUCCESS);
\r
573 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
\r
575 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
\r
576 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0;
\r
577 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
578 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
579 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
580 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
\r
581 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulRxBuffers[j][i][z][0];
\r
582 for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
\r
584 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nFpgaToSW_FTH_RxBufferLen; // 1 symbols 3200bytes
\r
585 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
\r
586 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
\r
587 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
\r
588 if(XRAN_STATUS_SUCCESS != status) {
\r
589 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
\r
591 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
\r
592 psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb;
\r
594 u32dptr = (uint32_t*)(ptr);
\r
595 uint8_t *ptr_temp = (uint8_t *)ptr;
\r
596 memset(u32dptr, 0x0, nFpgaToSW_FTH_RxBufferLen);
\r
597 // ptr_temp[0] = j; // TTI
\r
598 // ptr_temp[1] = i; // Sec
\r
599 // ptr_temp[2] = z; // Ant
\r
600 // ptr_temp[3] = k; // sym
\r
607 eInterfaceType = XRANFTHTX_SEC_DESC_IN;
\r
608 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
\r
609 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc));
\r
610 if(XRAN_STATUS_SUCCESS != status) {
\r
611 rte_panic("Failed at xran_bm_init , status %d\n", status);
\r
613 eInterfaceType = XRANFTHRX_PRB_MAP_IN;
\r
614 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
\r
615 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map));
\r
616 if(XRAN_STATUS_SUCCESS != status) {
\r
617 rte_panic("Failed at xran_bm_init, status %d\n", status);
\r
620 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) {
\r
621 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
\r
622 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0;
\r
623 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
624 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
625 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
626 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT;
\r
627 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulRxPrbMapBuffers[j][i][z];
\r
629 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map);
\r
630 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1;
\r
631 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0;
\r
632 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
\r
633 if(XRAN_STATUS_SUCCESS != status) {
\r
634 rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status);
\r
636 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr;
\r
637 psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb;
\r
642 struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr;
\r
644 if (startupConfiguration.appMode == APP_O_DU)
\r
645 memcpy(ptr, &startupConfiguration.PrbMapUl, sizeof(struct xran_prb_map));
\r
647 memcpy(ptr, &startupConfiguration.PrbMapDl, sizeof(struct xran_prb_map));
\r
649 for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){
\r
650 struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id];
\r
651 for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){
\r
652 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN],&sd_ptr, &sd_mb);
\r
653 if(XRAN_STATUS_SUCCESS != status){
\r
654 rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status);
\r
656 pPrbElem->p_sec_desc[k] = sd_ptr;
\r
666 // add prach rx buffer
\r
667 for(i = 0; i<nSectorNum; i++)
\r
669 eInterfaceType = XRANFTHRACH_IN;
\r
670 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*XRAN_MAX_ANTENNA_NR*XRAN_NUM_OF_SYMBOL_PER_SLOT, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
\r
671 if(XRAN_STATUS_SUCCESS != status) {
\r
672 rte_panic("Failed at xran_bm_init, status %d\n", status);
\r
674 for(j = 0;j < XRAN_N_FE_BUF_LEN; j++)
\r
676 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
\r
677 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0;
\r
678 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
679 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
680 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
681 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANTENNA_NR; // ant number.
\r
682 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHPrachRxBuffers[j][i][z][0];
\r
683 for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++)
\r
685 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN;
\r
686 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
\r
687 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
\r
688 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
\r
689 if(XRAN_STATUS_SUCCESS != status) {
\r
690 rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status);
\r
692 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
\r
693 psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
\r
695 u32dptr = (uint32_t*)(ptr);
\r
696 memset(u32dptr, 0x0, FPGA_TO_SW_PRACH_RX_BUFFER_LEN);
\r
703 /* add SRS rx buffer */
\r
704 for(i = 0; i<nSectorNum; i++)
\r
706 eInterfaceType = XRANSRS_IN;
\r
707 status = xran_bm_init(psBbuIo->nInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],
\r
708 XRAN_N_FE_BUF_LEN*XRAN_MAX_ANT_ARRAY_ELM_NR*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen);
\r
710 if(XRAN_STATUS_SUCCESS != status) {
\r
711 rte_panic("Failed at xran_bm_init, status %d\n", status);
\r
713 for(j = 0; j < XRAN_N_FE_BUF_LEN; j++)
\r
715 for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
\r
716 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0;
\r
717 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1;
\r
718 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1;
\r
719 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0;
\r
720 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANT_ARRAY_ELM_NR; /* ant number */
\r
721 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHSrsRxBuffers[j][i][z][0];
\r
722 for(k = 0; k < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; k++)
\r
724 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen;
\r
725 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1;
\r
726 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0;
\r
727 status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb);
\r
728 if(XRAN_STATUS_SUCCESS != status) {
\r
729 rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status);
\r
731 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr;
\r
732 psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb;
\r
734 u32dptr = (uint32_t*)(ptr);
\r
735 memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen);
\r
743 for(i=0; i<nSectorNum; i++)
\r
745 for(j=0; j<XRAN_N_FE_BUF_LEN; j++)
\r
747 for(z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
\r
748 pFthTxBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
\r
749 pFthTxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
\r
750 pFthRxBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
\r
751 pFthRxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
\r
752 pFthRxRachBuffer[i][z][j] = &(psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
\r
755 for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR; z++){
\r
756 pFthRxSrsBuffer[i][z][j] = &(psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList);
\r
761 if(NULL != psBbuIo->nInstanceHandle[0])
\r
763 /* add pusch callback */
\r
764 for (i = 0; i<nSectorNum; i++)
\r
766 xran_5g_fronthault_config (psBbuIo->nInstanceHandle[0][i],
\r
768 pFthTxPrbMapBuffer[i],
\r
770 pFthRxPrbMapBuffer[i],
\r
771 xran_fh_rx_callback, &pFthRxBuffer[i][0]);
\r
774 /* add prach callback here */
\r
775 for (i = 0; i<nSectorNum; i++)
\r
777 xran_5g_prach_req(psBbuIo->nInstanceHandle[0][i], pFthRxRachBuffer[i],
\r
778 xran_fh_rx_prach_callback,&pFthRxRachBuffer[i][0]);
\r
781 /* add SRS callback here */
\r
782 for (i = 0; i<nSectorNum; i++) {
\r
783 xran_5g_srs_req(psBbuIo->nInstanceHandle[0][i], pFthRxSrsBuffer[i],
\r
784 xran_fh_rx_srs_callback,&pFthRxSrsBuffer[i][0]);
\r
787 ptrLibConfig->nFhBufIntFlag = 1;
\r
793 int init_xran_iq_content(void)
\r
795 BbuXranIoIfStruct *psBbuIo = xran_get_ctx();
\r
796 xran_status_t status;
\r
797 int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
\r
798 int32_t nSectorNum;
\r
799 int32_t cc_id, ant_id, sym_id, tti;
\r
802 uint8_t frame_id = 0;
\r
803 uint8_t subframe_id = 0;
\r
804 uint8_t slot_id = 0;
\r
813 struct xran_prb_map *pRbMap = NULL;
\r
815 for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
\r
817 nSectorIndex[nSectorNum] = nSectorNum;
\r
819 nSectorNum = numCCPorts;
\r
820 printf ("init_xran_iq_content\n");
\r
823 for(cc_id = 0; cc_id <nSectorNum; cc_id++)
\r
825 for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) {
\r
826 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
\r
827 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
\r
829 flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
\r
830 if(p_tx_play_buffer[flowId]){
\r
832 pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
\r
834 if (xranInit.DynamicSectionEna == 0){
\r
835 pRbMap->dir = XRAN_DIR_DL;
\r
836 pRbMap->xran_port = 0;
\r
837 pRbMap->band_id = 0;
\r
838 pRbMap->cc_id = cc_id;
\r
839 pRbMap->ru_port_id = ant_id;
\r
840 pRbMap->tti_id = tti;
\r
841 pRbMap->start_sym_id = 0;
\r
842 pRbMap->nPrbElm = 1;
\r
843 pRbMap->prbMap[0].nStartSymb = 0;
\r
844 pRbMap->prbMap[0].numSymb = 14;
\r
845 pRbMap->prbMap[0].nRBStart = 0;
\r
846 pRbMap->prbMap[0].nRBSize = pXranConf->nDLRBs;
\r
847 pRbMap->prbMap[0].nBeamIndex = 0;
\r
848 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
\r
849 pRbMap->prbMap[0].iqWidth = 16;
\r
850 } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
\r
851 && startupConfiguration.appMode == APP_O_DU
\r
852 && sym_id == 0){ /* BF Ws are per slot */
\r
854 char* dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
\r
855 struct xran_prb_elm* p_pRbMapElm = NULL;
\r
856 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
\r
857 p_pRbMapElm = &pRbMap->prbMap[idxElm];
\r
858 p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx;
\r
859 if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update){
\r
860 int16_t ext_len = 9600;
\r
861 int16_t ext_sec_total = 0;
\r
862 int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
\r
864 int16_t *ptr = NULL;
\r
867 ext_buf += (RTE_PKTMBUF_HEADROOM +
\r
868 sizeof (struct xran_ecpri_hdr) +
\r
869 sizeof(struct xran_cp_radioapp_section1));
\r
871 ext_len -= (RTE_PKTMBUF_HEADROOM +
\r
872 sizeof (struct xran_ecpri_hdr) +
\r
873 sizeof(struct xran_cp_radioapp_section1));
\r
874 ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
\r
876 (int16_t *) (dl_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4),
\r
877 p_pRbMapElm->nRBSize,
\r
878 pXranConf->nAntElmTRx,
\r
879 p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
\r
880 if(ext_sec_total > 0){
\r
881 p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
\r
882 p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
\r
884 rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
\r
887 rte_panic("xran_malloc return NULL\n");
\r
893 printf("DL pRbMap ==NULL\n");
\r
897 pos = ((char*)p_tx_play_buffer[flowId]) + tx_play_buffer_position[flowId];
\r
898 ptr = psBbuIo->sFrontHaulTxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
\r
902 u8dptr = (uint8_t*)ptr;
\r
903 int16_t payload_len = 0;
\r
905 uint8_t *dst = (uint8_t *)u8dptr;
\r
906 uint8_t *src = (uint8_t *)pos;
\r
907 struct xran_prb_elm* p_prbMapElm = &pRbMap->prbMap[idxElm];
\r
908 dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod);
\r
909 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
\r
910 struct xran_section_desc *p_sec_desc = NULL;
\r
911 p_prbMapElm = &pRbMap->prbMap[idxElm];
\r
912 p_sec_desc = p_prbMapElm->p_sec_desc[sym_id];
\r
914 if(p_sec_desc == NULL){
\r
915 printf ("p_sec_desc == NULL\n");
\r
918 src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L);
\r
920 if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) {
\r
921 payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
\r
922 rte_memcpy(dst, src, payload_len);
\r
924 } else if (p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT) {
\r
925 struct xranlib_compress_request bfp_com_req;
\r
926 struct xranlib_compress_response bfp_com_rsp;
\r
928 memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request));
\r
929 memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response));
\r
931 bfp_com_req.data_in = (int16_t*)src;
\r
932 bfp_com_req.numRBs = p_prbMapElm->nRBSize;
\r
933 bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L;
\r
934 bfp_com_req.compMethod = p_prbMapElm->compMethod;
\r
935 bfp_com_req.iqWidth = p_prbMapElm->iqWidth;
\r
937 bfp_com_rsp.data_out = (int8_t*)dst;
\r
938 bfp_com_rsp.len = 0;
\r
940 if(xranlib_compress_avx512(&bfp_com_req, &bfp_com_rsp) < 0){
\r
941 printf ("compression failed [%d]\n",
\r
942 p_prbMapElm->compMethod);
\r
945 payload_len = bfp_com_rsp.len;
\r
948 printf ("p_prbMapElm->compMethod == %d is not supported\n",
\r
949 p_prbMapElm->compMethod);
\r
953 /* update RB map for given element */
\r
954 p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr);
\r
955 p_sec_desc->iq_buffer_len = payload_len;
\r
957 /* add headroom for ORAN headers between IQs for chunk of RBs*/
\r
958 dst += payload_len;
\r
959 dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod);
\r
963 printf("ptr ==NULL\n");
\r
968 pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
\r
970 if (xranInit.DynamicSectionEna == 0){
\r
971 pRbMap->dir = XRAN_DIR_UL;
\r
972 pRbMap->xran_port = 0;
\r
973 pRbMap->band_id = 0;
\r
974 pRbMap->cc_id = cc_id;
\r
975 pRbMap->ru_port_id = ant_id;
\r
976 pRbMap->tti_id = tti;
\r
977 pRbMap->start_sym_id = 0;
\r
978 pRbMap->nPrbElm = 1;
\r
979 pRbMap->prbMap[0].nRBStart = 0;
\r
980 pRbMap->prbMap[0].nRBSize = pXranConf->nULRBs;
\r
981 pRbMap->prbMap[0].nStartSymb = 0;
\r
982 pRbMap->prbMap[0].numSymb = 14;
\r
983 pRbMap->prbMap[0].p_sec_desc[sym_id]->iq_buffer_offset = 0;
\r
984 pRbMap->prbMap[0].p_sec_desc[sym_id]->iq_buffer_len = pXranConf->nULRBs *4L;
\r
985 pRbMap->prbMap[0].nBeamIndex = 0;
\r
986 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
\r
987 } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
\r
988 && startupConfiguration.appMode == APP_O_DU
\r
991 char * ul_bfw_pos = ((char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId];
\r
992 struct xran_prb_elm* p_pRbMapElm = NULL;
\r
994 for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){
\r
995 p_pRbMapElm = &pRbMap->prbMap[idxElm];
\r
996 p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx;
\r
997 if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update){
\r
998 int16_t ext_len = 9600;
\r
999 int16_t ext_sec_total = 0;
\r
1000 int8_t * ext_buf =(int8_t*) xran_malloc(ext_len);
\r
1002 int16_t *ptr = NULL;
\r
1005 ext_buf += (RTE_PKTMBUF_HEADROOM +
\r
1006 sizeof (struct xran_ecpri_hdr) +
\r
1007 sizeof(struct xran_cp_radioapp_section1));
\r
1009 ext_len -= (RTE_PKTMBUF_HEADROOM +
\r
1010 sizeof (struct xran_ecpri_hdr) +
\r
1011 sizeof(struct xran_cp_radioapp_section1));
\r
1012 ptr = (int16_t*)(ul_bfw_pos +(p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4);
\r
1013 ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf,
\r
1015 (int16_t *) (ul_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4),
\r
1016 p_pRbMapElm->nRBSize,
\r
1017 pXranConf->nAntElmTRx,
\r
1018 p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod);
\r
1019 if(ext_sec_total > 0){
\r
1020 p_pRbMapElm->bf_weight.p_ext_section = ext_buf;
\r
1021 p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total;
\r
1023 rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total);
\r
1026 rte_panic("xran_malloc return NULL\n");
\r
1032 printf("DL pRbMap ==NULL\n");
\r
1036 tx_play_buffer_position[flowId] += pXranConf->nDLRBs*N_SC_PER_PRB*4;
\r
1038 if(tx_play_buffer_position[flowId] >= tx_play_buffer_size[flowId])
\r
1039 tx_play_buffer_position[flowId] = 0;
\r
1041 if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B
\r
1042 && startupConfiguration.appMode == APP_O_DU
\r
1044 tx_dl_bfw_buffer_position[flowId] += (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4;
\r
1045 if(tx_dl_bfw_buffer_position[flowId] >= tx_dl_bfw_buffer_size[flowId])
\r
1046 tx_dl_bfw_buffer_position[flowId] = 0;
\r
1048 tx_ul_bfw_buffer_position[flowId] += (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4;
\r
1049 if(tx_ul_bfw_buffer_position[flowId] >= tx_ul_bfw_buffer_size[flowId])
\r
1050 tx_ul_bfw_buffer_position[flowId] = 0;
\r
1053 //printf("flowId %d\n", flowId);
\r
1058 /* prach TX for RU only */
\r
1059 if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
\r
1060 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
\r
1061 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
\r
1062 flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
\r
1064 if(p_tx_prach_play_buffer[flowId]){
\r
1065 pos = ((char*)p_tx_prach_play_buffer[flowId]);
\r
1067 ptr = psBbuIo->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
\r
1070 u32dptr = (uint32_t*)(ptr);
\r
1071 /* duplicate full PRACH (repetition * occassions ) in every symbol */
\r
1072 memset(u32dptr,0 , PRACH_PLAYBACK_BUFFER_BYTES);
\r
1073 rte_memcpy(u32dptr, pos, RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, tx_prach_play_buffer_size[flowId]));
\r
1076 printf("ptr ==NULL\n");
\r
1079 //printf("flowId %d\n", flowId);
\r
1085 /* SRS TX for RU only */
\r
1086 if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
\r
1087 for(ant_id = 0; ant_id < XRAN_MAX_ANT_ARRAY_ELM_NR; ant_id++){
\r
1088 for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) {
\r
1089 flowId = XRAN_MAX_ANT_ARRAY_ELM_NR*cc_id + ant_id;
\r
1091 if(p_tx_srs_play_buffer[flowId]){
\r
1092 pos = ((char*)p_tx_srs_play_buffer[flowId]) + tx_srs_play_buffer_position[flowId];
\r
1093 ptr = psBbuIo->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
\r
1095 if(startupConfiguration.srsSymMask & (1 << sym_id) ){
\r
1097 u32dptr = (uint32_t*)(ptr);
\r
1098 memset(u32dptr,0 , pXranConf->nULRBs*N_SC_PER_PRB*4);
\r
1099 rte_memcpy(u32dptr, pos, pXranConf->nULRBs*N_SC_PER_PRB*4);
\r
1102 printf("ptr ==NULL\n");
\r
1106 tx_srs_play_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
\r
1108 if(tx_srs_play_buffer_position[flowId] >= tx_srs_play_buffer_size[flowId])
\r
1109 tx_srs_play_buffer_position[flowId] = 0;
\r
1111 //printf("flowId %d\n", flowId);
\r
1122 void stop_xran(void)
\r
1124 xran_status_t status = 0;
\r
1125 SWXRANInterfaceTypeEnum eInterfaceType;
\r
1127 free(gpXranLibConfig);
\r
1128 gpXranLibConfig = NULL;
\r
1130 status += xran_mm_destroy(xranHandle)*2;
\r
1132 if(XRAN_STATUS_SUCCESS != status)
\r
1134 printf("Failed at xran_mm_destroy, status %d\n",status);
\r
1135 iAssert(status == XRAN_STATUS_SUCCESS);
\r
1139 int get_xran_iq_content(void)
\r
1141 BbuXranIoIfStruct *psBbuIo = xran_get_ctx();
\r
1142 xran_status_t status;
\r
1143 int32_t nSectorIndex[XRAN_MAX_SECTOR_NR];
\r
1144 int32_t nSectorNum;
\r
1145 int32_t cc_id, ant_id, sym_id, tti;
\r
1148 uint8_t frame_id = 0;
\r
1149 uint8_t subframe_id = 0;
\r
1150 uint8_t slot_id = 0;
\r
1154 uint32_t *u32dptr;
\r
1155 uint16_t *u16dptr;
\r
1160 for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++)
\r
1162 nSectorIndex[nSectorNum] = nSectorNum;
\r
1164 nSectorNum = numCCPorts;
\r
1165 printf ("get_xran_iq_content\n");
\r
1168 for(cc_id = 0; cc_id <nSectorNum; cc_id++)
\r
1170 for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti++) {
\r
1171 for(ant_id = 0; ant_id < XRAN_MAX_ANTENNA_NR; ant_id++){
\r
1172 int32_t idxElm = 0;
\r
1173 struct xran_prb_map *pRbMap = NULL;
\r
1174 struct xran_prb_elm *pRbElm = NULL;
\r
1175 struct xran_section_desc *p_sec_desc = NULL;
\r
1176 pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData;
\r
1177 if(pRbMap == NULL)
\r
1179 flowId = XRAN_MAX_ANTENNA_NR * cc_id + ant_id;
\r
1180 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
\r
1181 pRbElm = &pRbMap->prbMap[0];
\r
1182 if(pRbMap->nPrbElm == 1){
\r
1183 if(p_rx_log_buffer[flowId]) {
\r
1184 pos = ((char*)p_rx_log_buffer[flowId]) + rx_log_buffer_position[flowId];
\r
1185 ptr = psBbuIo->sFrontHaulRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
\r
1187 u32dptr = (uint32_t*)(ptr);
\r
1188 char* my_ptr =(char *)ptr;
\r
1189 rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L);
\r
1191 printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id);
\r
1195 for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
\r
1196 pRbElm = &pRbMap->prbMap[idxElm];
\r
1197 p_sec_desc = pRbElm->p_sec_desc[sym_id];
\r
1198 if(p_rx_log_buffer[flowId] && p_sec_desc){
\r
1199 if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){
\r
1200 pos = ((char*)p_rx_log_buffer[flowId]) + rx_log_buffer_position[flowId];
\r
1201 ptr = p_sec_desc->pData;
\r
1203 int32_t payload_len = 0;
\r
1204 u32dptr = (uint32_t*)(ptr);
\r
1205 if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){
\r
1206 struct xranlib_decompress_request bfp_decom_req;
\r
1207 struct xranlib_decompress_response bfp_decom_rsp;
\r
1209 memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request));
\r
1210 memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response));
\r
1212 bfp_decom_req.data_in = (int8_t *)u32dptr;
\r
1213 bfp_decom_req.numRBs = pRbElm->nRBSize;
\r
1214 bfp_decom_req.len = (3* pRbElm->iqWidth + 1)*pRbElm->nRBSize;
\r
1215 bfp_decom_req.compMethod = pRbElm->compMethod;
\r
1216 bfp_decom_req.iqWidth = pRbElm->iqWidth;
\r
1218 bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4);
\r
1219 bfp_decom_rsp.len = 0;
\r
1221 if(xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp) < 0){
\r
1222 printf ("compression failed [%d]\n",
\r
1223 pRbElm->compMethod);
\r
1226 payload_len = bfp_decom_rsp.len;
\r
1229 rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4);
\r
1236 rx_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
\r
1238 if(rx_log_buffer_position[flowId] >= rx_log_buffer_size[flowId])
\r
1239 rx_log_buffer_position[flowId] = 0;
\r
1242 /* prach RX for O-DU only */
\r
1243 if(startupConfiguration.appMode == APP_O_DU) {
\r
1244 flowId = XRAN_MAX_ANTENNA_NR * cc_id + ant_id;
\r
1245 for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++){
\r
1246 if(p_prach_log_buffer[flowId]){
\r
1247 /* (0-79 slots) 10ms of IQs */
\r
1248 pos = ((char*)p_prach_log_buffer[flowId]) + prach_log_buffer_position[flowId];
\r
1249 ptr = psBbuIo->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; //8192 144
\r
1251 u32dptr = (uint32_t*)(ptr);
\r
1252 rte_memcpy(pos, u32dptr, PRACH_PLAYBACK_BUFFER_BYTES);
\r
1254 printf("ptr ==NULL\n");
\r
1256 prach_log_buffer_position[flowId] += PRACH_PLAYBACK_BUFFER_BYTES;
\r
1258 if(prach_log_buffer_position[flowId] >= prach_log_buffer_size[flowId])
\r
1259 prach_log_buffer_position[flowId] = 0;
\r
1261 //printf("flowId %d\n", flowId);
\r
1267 /* SRS RX for O-DU only */
\r
1268 if(startupConfiguration.appMode == APP_O_DU) {
\r
1269 for(ant_id = 0; ant_id < XRAN_MAX_ANT_ARRAY_ELM_NR; ant_id++){
\r
1270 flowId = XRAN_MAX_ANT_ARRAY_ELM_NR*cc_id + ant_id;
\r
1271 for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++){
\r
1272 if(p_srs_log_buffer[flowId]){
\r
1273 pos = ((char*)p_srs_log_buffer[flowId]) + srs_log_buffer_position[flowId];
\r
1274 ptr = psBbuIo->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData;
\r
1276 u32dptr = (uint32_t*)(ptr);
\r
1277 rte_memcpy(pos, u32dptr, pXranConf->nULRBs*N_SC_PER_PRB*4);
\r
1279 printf("ptr ==NULL\n");
\r
1281 srs_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4;
\r
1283 if(srs_log_buffer_position[flowId] >= srs_log_buffer_size[flowId])
\r
1284 srs_log_buffer_position[flowId] = 0;
\r
1286 //printf("flowId %d\n", flowId);
\r
1297 void version_print(void)
\r
1299 char sysversion[100];
\r
1300 char *compilation_date = __DATE__;
\r
1301 char *compilation_time = __TIME__;
\r
1306 snprintf(sysversion, 99, "Version: %s", VERSIONX);
\r
1307 nLen = strlen(sysversion);
\r
1310 printf("===========================================================================================================\n");
\r
1311 printf("SAMPLE-APP VERSION\n");
\r
1312 printf("===========================================================================================================\n");
\r
1314 printf("%s\n", sysversion);
\r
1315 printf("build-date: %s\n", compilation_date);
\r
1316 printf("build-time: %s\n", compilation_time);
\r
1319 int main(int argc, char *argv[])
\r
1324 char filename[256];
\r
1325 char prefix_name[256];
\r
1326 uint32_t nCenterFreq;
\r
1328 struct stat st = {0};
\r
1329 uint32_t filenameLength = strlen(argv[1]);
\r
1330 char *pCheckName1 = NULL, *pCheckName2 = NULL;
\r
1331 enum xran_if_state xran_curr_if_state = XRAN_INIT;
\r
1333 uint64_t nMask = (uint64_t)1;
\r
1334 uint16_t nCoreUsage[4*64+1];
\r
1335 uint16_t nCoreId[4*64];
\r
1336 float nTotal = 0.0;
\r
1337 uint64_t nTotalTime;
\r
1338 uint64_t nUsedTime;
\r
1339 uint32_t nCoreUsed;
\r
1340 float nUsedPercent;
\r
1344 errx(2, "Need two argument - the PCI address of the network port");
\r
1345 if (filenameLength >= 256)
\r
1347 printf("Config file name input is too long, exiting!\n");
\r
1353 //add for Klocworks
\r
1354 len = strlen(argv[1]) + 1;
\r
1355 if (len > (sizeof(filename) - 10))
\r
1356 len = (sizeof(filename) - 10);
\r
1357 strncpy(filename, argv[1], (sizeof(filename) - 10));
\r
1358 filename[len] = '\0';
\r
1360 if (xran_is_synchronized() != 0)
\r
1361 printf("Machine is not synchronized using PTP!\n");
\r
1363 printf("Machine is synchronized using PTP!\n");
\r
1365 memset(&startupConfiguration, 0, sizeof(RuntimeConfig));
\r
1367 if (parseConfigFile(filename, (RuntimeConfig*)&startupConfiguration) != 0) {
\r
1368 printf("Configuration file error.\n");
\r
1372 if(startupConfiguration.ant_file[0] == NULL){
\r
1373 printf("it looks like test vector for antennas were not provided\n");
\r
1377 if (startupConfiguration.numCC > XRAN_MAX_SECTOR_NR) {
\r
1378 printf("Number of cells %d exceeds max number supported %d!\n", startupConfiguration.numCC, XRAN_MAX_SECTOR_NR);
\r
1379 startupConfiguration.numCC = XRAN_MAX_SECTOR_NR;
\r
1382 if (startupConfiguration.antElmTRx > XRAN_MAX_ANT_ARRAY_ELM_NR) {
\r
1383 printf("Number of Antenna elements %d exceeds max number supported %d!\n", startupConfiguration.antElmTRx, XRAN_MAX_ANT_ARRAY_ELM_NR);
\r
1384 startupConfiguration.antElmTRx = XRAN_MAX_ANT_ARRAY_ELM_NR;
\r
1387 numCCPorts = startupConfiguration.numCC;
\r
1388 num_eAxc = startupConfiguration.numAxc;
\r
1390 printf("numCCPorts %d num_eAxc%d\n", numCCPorts, num_eAxc);
\r
1392 if (startupConfiguration.mu_number <= 1){
\r
1393 nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/
\r
1394 nFpgaToSW_PRACH_RxBufferLen = 8192;
\r
1395 nSW_ToFpga_FTH_TxBufferLen = 13168 + /* 273*12*4 + 64* + ETH AND ORAN HDRs */
\r
1396 XRAN_MAX_SECTIONS_PER_SYM* (RTE_PKTMBUF_HEADROOM + sizeof(struct ether_hdr) +
\r
1397 sizeof(struct xran_ecpri_hdr) +
\r
1398 sizeof(struct radio_app_common_hdr) +
\r
1399 sizeof(struct data_section_hdr));
\r
1400 } else if (startupConfiguration.mu_number == 3){
\r
1401 nFpgaToSW_FTH_RxBufferLen = 3328;
\r
1402 nFpgaToSW_PRACH_RxBufferLen = 8192;
\r
1403 nSW_ToFpga_FTH_TxBufferLen = 3328 +
\r
1404 XRAN_MAX_SECTIONS_PER_SYM * (RTE_PKTMBUF_HEADROOM + sizeof(struct ether_hdr) +
\r
1405 sizeof(struct xran_ecpri_hdr) +
\r
1406 sizeof(struct radio_app_common_hdr) +
\r
1407 sizeof(struct data_section_hdr));
\r
1409 printf("given numerology is not supported %d\n", startupConfiguration.mu_number);
\r
1412 printf("nSW_ToFpga_FTH_TxBufferLen %d\n", nSW_ToFpga_FTH_TxBufferLen);
\r
1414 memset(&xranInit, 0, sizeof(struct xran_fh_init));
\r
1416 if(startupConfiguration.appMode == APP_O_DU) {
\r
1417 printf("set O-DU\n");
\r
1418 xranInit.io_cfg.id = 0;/* O-DU */
\r
1419 xranInit.io_cfg.core = startupConfiguration.io_core;
\r
1420 xranInit.io_cfg.system_core = 0;
\r
1421 xranInit.io_cfg.pkt_proc_core = startupConfiguration.io_core+1;
\r
1422 xranInit.io_cfg.pkt_aux_core = 0; /* do not start*/
\r
1423 xranInit.io_cfg.timing_core = startupConfiguration.io_core+2;
\r
1425 printf("set O-RU\n");
\r
1426 xranInit.io_cfg.id = 1; /* O-RU*/
\r
1427 xranInit.io_cfg.core = startupConfiguration.io_core;
\r
1428 xranInit.io_cfg.system_core = 0;
\r
1429 xranInit.io_cfg.pkt_proc_core = startupConfiguration.io_core+1;
\r
1430 xranInit.io_cfg.pkt_aux_core = 0; /* do not start */
\r
1431 xranInit.io_cfg.timing_core = startupConfiguration.io_core+2;
\r
1434 xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
\r
1436 if(startupConfiguration.xranCat == XRAN_CATEGORY_A){
\r
1437 xranInit.eAxCId_conf.mask_cuPortId = 0xf000;
\r
1438 xranInit.eAxCId_conf.mask_bandSectorId = 0x0f00;
\r
1439 xranInit.eAxCId_conf.mask_ccId = 0x00f0;
\r
1440 xranInit.eAxCId_conf.mask_ruPortId = 0x000f;
\r
1441 xranInit.eAxCId_conf.bit_cuPortId = 12;
\r
1442 xranInit.eAxCId_conf.bit_bandSectorId = 8;
\r
1443 xranInit.eAxCId_conf.bit_ccId = 4;
\r
1444 xranInit.eAxCId_conf.bit_ruPortId = 0;
\r
1446 xranInit.eAxCId_conf.mask_cuPortId = 0xf000;
\r
1447 xranInit.eAxCId_conf.mask_bandSectorId = 0x0c00;
\r
1448 xranInit.eAxCId_conf.mask_ccId = 0x0300;
\r
1449 xranInit.eAxCId_conf.mask_ruPortId = 0x00ff; /* more than [0-127] eAxC */
\r
1450 xranInit.eAxCId_conf.bit_cuPortId = 12;
\r
1451 xranInit.eAxCId_conf.bit_bandSectorId = 10;
\r
1452 xranInit.eAxCId_conf.bit_ccId = 8;
\r
1453 xranInit.eAxCId_conf.bit_ruPortId = 0;
\r
1456 xranInit.io_cfg.dpdk_dev[XRAN_UP_VF] = argv[2];
\r
1457 xranInit.io_cfg.dpdk_dev[XRAN_CP_VF] = argv[3];
\r
1458 xranInit.mtu = startupConfiguration.mtu;
\r
1460 xranInit.p_o_du_addr = (int8_t *)&startupConfiguration.o_du_addr;
\r
1461 xranInit.p_o_ru_addr = (int8_t *)&startupConfiguration.o_ru_addr;
\r
1463 sprintf(prefix_name, "wls_%d",startupConfiguration.instance_id);
\r
1464 xranInit.filePrefix = prefix_name;
\r
1466 xranInit.totalBfWeights = startupConfiguration.totalBfWeights;
\r
1468 xranInit.Tadv_cp_dl = startupConfiguration.Tadv_cp_dl;
\r
1469 xranInit.T2a_min_cp_dl = startupConfiguration.T2a_min_cp_dl;
\r
1470 xranInit.T2a_max_cp_dl = startupConfiguration.T2a_max_cp_dl;
\r
1471 xranInit.T2a_min_cp_ul = startupConfiguration.T2a_min_cp_ul;
\r
1472 xranInit.T2a_max_cp_ul = startupConfiguration.T2a_max_cp_ul;
\r
1473 xranInit.T2a_min_up = startupConfiguration.T2a_min_up;
\r
1474 xranInit.T2a_max_up = startupConfiguration.T2a_max_up;
\r
1475 xranInit.Ta3_min = startupConfiguration.Ta3_min;
\r
1476 xranInit.Ta3_max = startupConfiguration.Ta3_max;
\r
1477 xranInit.T1a_min_cp_dl = startupConfiguration.T1a_min_cp_dl;
\r
1478 xranInit.T1a_max_cp_dl = startupConfiguration.T1a_max_cp_dl;
\r
1479 xranInit.T1a_min_cp_ul = startupConfiguration.T1a_min_cp_ul;
\r
1480 xranInit.T1a_max_cp_ul = startupConfiguration.T1a_max_cp_ul;
\r
1481 xranInit.T1a_min_up = startupConfiguration.T1a_min_up;
\r
1482 xranInit.T1a_max_up = startupConfiguration.T1a_max_up;
\r
1483 xranInit.Ta4_min = startupConfiguration.Ta4_min;
\r
1484 xranInit.Ta4_max = startupConfiguration.Ta4_max;
\r
1486 xranInit.enableCP = startupConfiguration.enableCP;
\r
1487 xranInit.prachEnable = startupConfiguration.enablePrach;
\r
1488 xranInit.srsEnable = startupConfiguration.enableSrs;
\r
1489 xranInit.debugStop = startupConfiguration.debugStop;
\r
1490 xranInit.debugStopCount = startupConfiguration.debugStopCount;
\r
1491 xranInit.DynamicSectionEna = startupConfiguration.DynamicSectionEna;
\r
1492 xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED;
\r
1493 xranInit.GPS_Alpha = startupConfiguration.GPS_Alpha;
\r
1494 xranInit.GPS_Beta = startupConfiguration.GPS_Beta;
\r
1496 xranInit.cp_vlan_tag = startupConfiguration.cp_vlan_tag;
\r
1497 xranInit.up_vlan_tag = startupConfiguration.up_vlan_tag;
\r
1499 printf("IQ files size is %d slots\n", startupConfiguration.numSlots);
\r
1501 iq_playback_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
\r
1502 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
\r
1505 iq_playback_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
\r
1506 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
\r
1510 /* 10 * [14*32*273*2*2] = 4892160 bytes */
\r
1511 iq_bfw_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * startupConfiguration.antElmTRx *
\r
1512 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA)
\r
1515 /* 10 * [14*32*273*2*2] = 4892160 bytes */
\r
1516 iq_bfw_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT *
\r
1517 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
\r
1520 /* 10 * [1*273*2*2] = 349440 bytes */
\r
1521 iq_srs_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB *
\r
1522 app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA)
\r
1525 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1526 p_tx_play_buffer[i] = (int16_t*)malloc(iq_playback_buffer_size_dl);
\r
1527 tx_play_buffer_size[i] = (int32_t)iq_playback_buffer_size_dl;
\r
1529 if (p_tx_play_buffer[i] == NULL)
\r
1532 tx_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ant_file[i],
\r
1533 "DL IFFT IN IQ Samples in binary format",
\r
1534 (uint8_t*) p_tx_play_buffer[i],
\r
1535 tx_play_buffer_size[i],
\r
1537 tx_play_buffer_position[i] = 0;
\r
1540 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
\r
1541 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1543 p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl);
\r
1544 tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl;
\r
1546 if (p_tx_dl_bfw_buffer[i] == NULL)
\r
1549 tx_dl_bfw_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.dl_bfw_file[i],
\r
1550 "DL BF weights IQ Samples in binary format",
\r
1551 (uint8_t*) p_tx_dl_bfw_buffer[i],
\r
1552 tx_dl_bfw_buffer_size[i],
\r
1554 tx_dl_bfw_buffer_position[i] = 0;
\r
1558 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
\r
1560 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1561 p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_ul);
\r
1562 tx_ul_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_ul;
\r
1564 if (p_tx_ul_bfw_buffer[i] == NULL)
\r
1567 tx_ul_bfw_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ul_bfw_file[i],
\r
1568 "UL BF weights IQ Samples in binary format",
\r
1569 (uint8_t*) p_tx_ul_bfw_buffer[i],
\r
1570 tx_ul_bfw_buffer_size[i],
\r
1572 tx_ul_bfw_buffer_position[i] = 0;
\r
1576 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
\r
1577 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1578 p_tx_prach_play_buffer[i] = (int16_t*)malloc(PRACH_PLAYBACK_BUFFER_BYTES);
\r
1579 tx_prach_play_buffer_size[i] = (int32_t)PRACH_PLAYBACK_BUFFER_BYTES;
\r
1581 if (p_tx_prach_play_buffer[i] == NULL)
\r
1584 memset(p_tx_prach_play_buffer[i], 0, PRACH_PLAYBACK_BUFFER_BYTES);
\r
1586 tx_prach_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.prach_file[i],
\r
1587 "PRACH IQ Samples in binary format",
\r
1588 (uint8_t*) p_tx_prach_play_buffer[i],
\r
1589 tx_prach_play_buffer_size[i],
\r
1591 tx_prach_play_buffer_position[i] = 0;
\r
1595 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
\r
1597 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
1600 p_tx_srs_play_buffer[i] = (int16_t*)malloc(iq_srs_buffer_size_ul);
\r
1601 tx_srs_play_buffer_size[i] = (int32_t)iq_srs_buffer_size_ul;
\r
1603 if (p_tx_srs_play_buffer[i] == NULL)
\r
1606 memset(p_tx_srs_play_buffer[i], 0, iq_srs_buffer_size_ul);
\r
1607 tx_prach_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ul_srs_file[i],
\r
1608 "SRS IQ Samples in binary format",
\r
1609 (uint8_t*) p_tx_srs_play_buffer[i],
\r
1610 tx_srs_play_buffer_size[i],
\r
1613 tx_srs_play_buffer_position[i] = 0;
\r
1618 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1620 p_rx_log_buffer[i] = (int16_t*)malloc(iq_playback_buffer_size_ul);
\r
1621 rx_log_buffer_size[i] = (int32_t)iq_playback_buffer_size_ul;
\r
1623 if (p_rx_log_buffer[i] == NULL)
\r
1626 rx_log_buffer_position[i] = 0;
\r
1628 memset(p_rx_log_buffer[i], 0, rx_log_buffer_size[i]);
\r
1631 /* log of prach */
\r
1632 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1634 p_prach_log_buffer[i] = (int16_t*)malloc(startupConfiguration.numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES);
\r
1635 prach_log_buffer_size[i] = (int32_t)startupConfiguration.numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES;
\r
1637 if (p_prach_log_buffer[i] == NULL)
\r
1640 memset(p_prach_log_buffer[i], 0, prach_log_buffer_size[i]);
\r
1641 prach_log_buffer_position[i] = 0;
\r
1645 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
\r
1647 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
1650 p_srs_log_buffer[i] = (int16_t*)malloc(iq_srs_buffer_size_ul);
\r
1651 srs_log_buffer_size[i] = (int32_t)iq_srs_buffer_size_ul;
\r
1653 if (p_srs_log_buffer[i] == NULL)
\r
1656 memset(p_srs_log_buffer[i], 0, iq_srs_buffer_size_ul);
\r
1657 srs_log_buffer_position[i] = 0;
\r
1661 if (stat("./logs", &st) == -1) {
\r
1662 mkdir("./logs", 0777);
\r
1665 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1667 sprintf(filename, "./logs/%s-play_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1668 sys_save_buf_to_file_txt(filename,
\r
1669 "DL IFFT IN IQ Samples in human readable format",
\r
1670 (uint8_t*) p_tx_play_buffer[i],
\r
1671 tx_play_buffer_size[i],
\r
1674 sprintf(filename, "./logs/%s-play_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1675 sys_save_buf_to_file(filename,
\r
1676 "DL IFFT IN IQ Samples in binary format",
\r
1677 (uint8_t*) p_tx_play_buffer[i],
\r
1678 tx_play_buffer_size[i]/sizeof(short),
\r
1682 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
\r
1683 sprintf(filename, "./logs/%s-dl_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1684 sys_save_buf_to_file_txt(filename,
\r
1685 "DL Beamformig weights IQ Samples in human readable format",
\r
1686 (uint8_t*) p_tx_dl_bfw_buffer[i],
\r
1687 tx_dl_bfw_buffer_size[i],
\r
1690 sprintf(filename, "./logs/%s-dl_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1691 sys_save_buf_to_file(filename,
\r
1692 "DL Beamformig weightsIQ Samples in binary format",
\r
1693 (uint8_t*) p_tx_dl_bfw_buffer[i],
\r
1694 tx_dl_bfw_buffer_size[i]/sizeof(short),
\r
1698 sprintf(filename, "./logs/%s-ul_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1699 sys_save_buf_to_file_txt(filename,
\r
1700 "UL Beamformig weights IQ Samples in human readable format",
\r
1701 (uint8_t*) p_tx_ul_bfw_buffer[i],
\r
1702 tx_ul_bfw_buffer_size[i],
\r
1705 sprintf(filename, "./logs/%s-ul_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1706 sys_save_buf_to_file(filename,
\r
1707 "UL Beamformig weightsIQ Samples in binary format",
\r
1708 (uint8_t*) p_tx_ul_bfw_buffer[i],
\r
1709 tx_ul_bfw_buffer_size[i]/sizeof(short),
\r
1714 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
\r
1715 sprintf(filename, "./logs/%s-play_prach_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1716 sys_save_buf_to_file_txt(filename,
\r
1717 "PRACH IQ Samples in human readable format",
\r
1718 (uint8_t*) p_tx_prach_play_buffer[i],
\r
1719 tx_prach_play_buffer_size[i],
\r
1722 sprintf(filename, "./logs/%s-play_prach_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1723 sys_save_buf_to_file(filename,
\r
1724 "PRACH IQ Samples in binary format",
\r
1725 (uint8_t*) p_tx_prach_play_buffer[i],
\r
1726 tx_prach_play_buffer_size[i]/sizeof(short),
\r
1731 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs && startupConfiguration.xranCat == XRAN_CATEGORY_B){
\r
1733 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
1737 sprintf(filename, "./logs/%s-play_srs_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1738 sys_save_buf_to_file_txt(filename,
\r
1739 "SRS IQ Samples in human readable format",
\r
1740 (uint8_t*) p_tx_srs_play_buffer[i],
\r
1741 tx_srs_play_buffer_size[i],
\r
1744 sprintf(filename, "./logs/%s-play_srs_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
1745 sys_save_buf_to_file(filename,
\r
1746 "SRS IQ Samples in binary format",
\r
1747 (uint8_t*) p_tx_srs_play_buffer[i],
\r
1748 tx_srs_play_buffer_size[i]/sizeof(short),
\r
1753 if (startupConfiguration.iqswap == 1){
\r
1754 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1755 printf("TX: Swap I and Q to match RU format: [%d]\n",i);
\r
1757 /* swap I and Q */
\r
1759 signed short *ptr = (signed short *) p_tx_play_buffer[i];
\r
1760 signed short temp;
\r
1762 for (j = 0; j < (int32_t)(tx_play_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
1764 ptr[j] = ptr[j + 1];
\r
1765 ptr[j + 1] = temp;
\r
1768 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
\r
1769 printf("DL BFW: Swap I and Q to match RU format: [%d]\n",i);
\r
1771 /* swap I and Q */
\r
1773 signed short *ptr = (signed short *) p_tx_dl_bfw_buffer[i];
\r
1774 signed short temp;
\r
1776 for (j = 0; j < (int32_t)(tx_dl_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
1778 ptr[j] = ptr[j + 1];
\r
1779 ptr[j + 1] = temp;
\r
1782 printf("UL BFW: Swap I and Q to match RU format: [%d]\n",i);
\r
1784 /* swap I and Q */
\r
1786 signed short *ptr = (signed short *) p_tx_ul_bfw_buffer[i];
\r
1787 signed short temp;
\r
1789 for (j = 0; j < (int32_t)(tx_ul_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
1791 ptr[j] = ptr[j + 1];
\r
1792 ptr[j + 1] = temp;
\r
1798 if (startupConfiguration.appMode == APP_O_RU){
\r
1799 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1800 printf("PRACH: Swap I and Q to match RU format: [%d]\n",i);
\r
1802 /* swap I and Q */
\r
1804 signed short *ptr = (signed short *) p_tx_prach_play_buffer[i];
\r
1805 signed short temp;
\r
1807 for (j = 0; j < (int32_t)(tx_prach_play_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
1809 ptr[j] = ptr[j + 1];
\r
1810 ptr[j + 1] = temp;
\r
1816 if (startupConfiguration.appMode == APP_O_RU){
\r
1818 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
1820 printf("SRS: Swap I and Q to match RU format: [%d]\n",i);
\r
1822 /* swap I and Q */
\r
1824 signed short *ptr = (signed short *) p_tx_srs_play_buffer[i];
\r
1825 signed short temp;
\r
1827 for (j = 0; j < (int32_t)(tx_srs_play_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
1829 ptr[j] = ptr[j + 1];
\r
1830 ptr[j + 1] = temp;
\r
1838 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1840 sprintf(filename, "./logs/swap_IQ_play_ant%d.txt", i);
\r
1841 sys_save_buf_to_file_txt(filename,
\r
1842 "DL IFFT IN IQ Samples in human readable format",
\r
1843 (uint8_t*) p_tx_play_buffer[i],
\r
1844 tx_play_buffer_size[i],
\r
1848 if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0){
\r
1849 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1850 printf("TX: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
\r
1851 for (j = 0; j < tx_play_buffer_size[i]/sizeof(short); j++){
\r
1852 p_tx_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_play_buffer[i][j]);
\r
1855 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){
\r
1856 printf("DL BFW: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
\r
1857 for (j = 0; j < tx_dl_bfw_buffer_size[i]/sizeof(short); j++){
\r
1858 p_tx_dl_bfw_buffer[i][j] = rte_cpu_to_be_16(p_tx_dl_bfw_buffer[i][j]);
\r
1860 printf("UL BFW: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
\r
1861 for (j = 0; j < tx_ul_bfw_buffer_size[i]/sizeof(short); j++){
\r
1862 p_tx_ul_bfw_buffer[i][j] = rte_cpu_to_be_16(p_tx_ul_bfw_buffer[i][j]);
\r
1867 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){
\r
1868 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1869 printf("PRACH: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
\r
1870 for (j = 0; j < tx_prach_play_buffer_size[i]/sizeof(short); j++){
\r
1871 p_tx_prach_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_prach_play_buffer[i][j]);
\r
1876 if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){
\r
1878 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
1880 printf("SRS: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i);
\r
1881 for (j = 0; j < tx_srs_play_buffer_size[i]/sizeof(short); j++){
\r
1882 p_tx_srs_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_srs_play_buffer[i][j]);
\r
1890 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
1892 sprintf(filename, "./logs/swap_be_play_ant%d.txt", i);
\r
1893 sys_save_buf_to_file_txt(filename,
\r
1894 "DL IFFT IN IQ Samples in human readable format",
\r
1895 (uint8_t*) p_tx_play_buffer[i],
\r
1896 tx_play_buffer_size[i],
\r
1901 memset(&xranConf, 0, sizeof(struct xran_fh_config));
\r
1902 pXranConf = &xranConf;
\r
1904 pXranConf->nDLRBs = app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA);
\r
1905 pXranConf->nULRBs = app_xran_get_num_rbs(startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA);
\r
1907 if(startupConfiguration.DynamicSectionEna == 0){
\r
1908 struct xran_prb_map* pRbMap;
\r
1910 pRbMap = &startupConfiguration.PrbMapDl;
\r
1912 pRbMap->dir = XRAN_DIR_DL;
\r
1913 pRbMap->xran_port = 0;
\r
1914 pRbMap->band_id = 0;
\r
1915 pRbMap->cc_id = 0;
\r
1916 pRbMap->ru_port_id = 0;
\r
1917 pRbMap->tti_id = 0;
\r
1918 pRbMap->start_sym_id = 0;
\r
1919 pRbMap->nPrbElm = 1;
\r
1920 pRbMap->prbMap[0].nStartSymb = 0;
\r
1921 pRbMap->prbMap[0].numSymb = 14;
\r
1922 pRbMap->prbMap[0].nRBStart = 0;
\r
1923 pRbMap->prbMap[0].nRBSize = pXranConf->nDLRBs;
\r
1924 pRbMap->prbMap[0].nBeamIndex = 0;
\r
1925 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
\r
1926 pRbMap->prbMap[0].iqWidth = 16;
\r
1928 pRbMap = &startupConfiguration.PrbMapUl;
\r
1929 pRbMap->dir = XRAN_DIR_UL;
\r
1930 pRbMap->xran_port = 0;
\r
1931 pRbMap->band_id = 0;
\r
1932 pRbMap->cc_id = 0;
\r
1933 pRbMap->ru_port_id = 0;
\r
1934 pRbMap->tti_id = 0;
\r
1935 pRbMap->start_sym_id = 0;
\r
1936 pRbMap->nPrbElm = 1;
\r
1937 pRbMap->prbMap[0].nStartSymb = 0;
\r
1938 pRbMap->prbMap[0].numSymb = 14;
\r
1939 pRbMap->prbMap[0].nRBStart = 0;
\r
1940 pRbMap->prbMap[0].nRBSize = pXranConf->nULRBs;
\r
1941 pRbMap->prbMap[0].nBeamIndex = 0;
\r
1942 pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE;
\r
1943 pRbMap->prbMap[0].iqWidth = 16;
\r
1946 timer_set_tsc_freq_from_clock();
\r
1947 xret = xran_init(argc, argv, &xranInit, argv[0], &xranHandle);
\r
1948 if(xret != XRAN_STATUS_SUCCESS){
\r
1949 printf("xran_init failed %d\n", xret);
\r
1953 if(xranHandle == NULL)
\r
1957 pXranConf->sector_id = 0;
\r
1958 pXranConf->nCC = numCCPorts;
\r
1959 pXranConf->neAxc = num_eAxc;
\r
1960 pXranConf->neAxcUl = startupConfiguration.numUlAxc;
\r
1961 pXranConf->nAntElmTRx = startupConfiguration.antElmTRx;
\r
1963 pXranConf->frame_conf.nFrameDuplexType = startupConfiguration.nFrameDuplexType;
\r
1964 pXranConf->frame_conf.nNumerology = startupConfiguration.mu_number;
\r
1965 pXranConf->frame_conf.nTddPeriod = startupConfiguration.nTddPeriod;
\r
1967 for (i = 0; i < startupConfiguration.nTddPeriod; i++){
\r
1968 pXranConf->frame_conf.sSlotConfig[i] = startupConfiguration.sSlotConfig[i];
\r
1971 pXranConf->prach_conf.nPrachSubcSpacing = startupConfiguration.mu_number;
\r
1972 pXranConf->prach_conf.nPrachFreqStart = 0;
\r
1973 pXranConf->prach_conf.nPrachFilterIdx = XRAN_FILTERINDEX_PRACH_ABC;
\r
1974 pXranConf->prach_conf.nPrachConfIdx = startupConfiguration.prachConfigIndex;
\r
1975 pXranConf->prach_conf.nPrachFreqOffset = -792;
\r
1977 pXranConf->srs_conf.symbMask = startupConfiguration.srsSymMask;
\r
1978 pXranConf->srs_conf.eAxC_offset = 2 * startupConfiguration.numAxc; /* PUSCH, PRACH, SRS */
\r
1980 pXranConf->ru_conf.xranCat = startupConfiguration.xranCat;
\r
1981 pXranConf->ru_conf.iqWidth = startupConfiguration.PrbMapDl.prbMap[0].iqWidth;
\r
1983 if (startupConfiguration.compression == 0)
\r
1984 pXranConf->ru_conf.compMeth = XRAN_COMPMETHOD_NONE;
\r
1986 pXranConf->ru_conf.compMeth = XRAN_COMPMETHOD_BLKFLOAT;
\r
1988 pXranConf->ru_conf.fftSize = 0;
\r
1989 while (startupConfiguration.nULFftSize >>= 1)
\r
1990 ++pXranConf->ru_conf.fftSize;
\r
1992 pXranConf->ru_conf.byteOrder = (startupConfiguration.nebyteorderswap == 1) ? XRAN_NE_BE_BYTE_ORDER : XRAN_CPU_LE_BYTE_ORDER ;
\r
1993 pXranConf->ru_conf.iqOrder = (startupConfiguration.iqswap == 1) ? XRAN_Q_I_ORDER : XRAN_I_Q_ORDER;
\r
1995 printf("FFT Order %d\n", pXranConf->ru_conf.fftSize);
\r
1997 nCenterFreq = startupConfiguration.nDLAbsFrePointA + (((pXranConf->nDLRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(startupConfiguration.mu_number));
\r
1998 pXranConf->nDLCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq);
\r
1999 printf("DL center freq %d DL NR-ARFCN %d\n", nCenterFreq, pXranConf->nDLCenterFreqARFCN);
\r
2001 nCenterFreq = startupConfiguration.nULAbsFrePointA + (((pXranConf->nULRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(startupConfiguration.mu_number));
\r
2002 pXranConf->nULCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq);
\r
2003 printf("UL center freq %d UL NR-ARFCN %d\n", nCenterFreq, pXranConf->nULCenterFreqARFCN);
\r
2005 pXranConf->bbdev_dec = NULL;
\r
2006 pXranConf->bbdev_enc = NULL;
\r
2008 pXranConf->log_level = 1;
\r
2010 if(startupConfiguration.maxFrameId)
\r
2011 pXranConf->ru_conf.xran_max_frame = startupConfiguration.maxFrameId;
\r
2013 if(init_xran() != 0)
\r
2016 xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI);
\r
2017 xran_reg_physide_cb(xranHandle, physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX);
\r
2018 xran_reg_physide_cb(xranHandle, physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX);
\r
2020 init_xran_iq_content();
\r
2022 xret = xran_open(xranHandle, pXranConf);
\r
2024 if(xret != XRAN_STATUS_SUCCESS){
\r
2025 printf("xran_open failed %d\n", xret);
\r
2029 sprintf(filename, "mlog-%s", startupConfiguration.appMode == 0 ? "o-du" : "o-ru");
\r
2031 /* MLogOpen(0, 32, 0, 0xFFFFFFFF, filename);*/
\r
2033 MLogOpen(256, 3, 20000, 0, filename);
\r
2036 puts("----------------------------------------");
\r
2037 printf("MLog Info: virt=0x%016lx size=%d\n", MLogGetFileLocation(), MLogGetFileSize());
\r
2038 puts("----------------------------------------");
\r
2041 uint64_t nActiveCoreMask[MAX_BBU_POOL_CORE_MASK] = {0};
\r
2042 nActiveCoreMask[0] = 1 << xranInit.io_cfg.timing_core;
\r
2043 uint32_t numCarriers = startupConfiguration.numCC;
\r
2045 MLogAddTestCase(nActiveCoreMask, numCarriers);
\r
2047 fcntl(0, F_SETFL, fcntl(0, F_GETFL) | O_NONBLOCK);
\r
2049 state = APP_RUNNING;
\r
2050 printf("Start XRAN traffic\n");
\r
2051 xran_start(xranHandle);
\r
2055 struct xran_common_counters x_counters;
\r
2058 xran_curr_if_state = xran_get_if_state();
\r
2059 if(xran_get_common_counters(xranHandle, &x_counters) == XRAN_STATUS_SUCCESS) {
\r
2061 xran_get_time_stats(&nTotalTime, &nUsedTime, &nCoreUsed, 1);
\r
2062 nUsedPercent = ((float)nUsedTime * 100.0) / (float)nTotalTime;
\r
2064 printf("[%s][rx %ld pps %ld kbps %ld][tx %ld pps %ld kbps %ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld] IO Util: %5.2f %%\n",
\r
2065 ((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"),
\r
2067 rx_counter-old_rx_counter,
\r
2068 rx_bytes_per_sec*8/1000L,
\r
2070 tx_counter-old_tx_counter,
\r
2071 tx_bytes_per_sec*8/1000L,
\r
2072 x_counters.Rx_on_time,
\r
2073 x_counters.Rx_early,
\r
2074 x_counters.Rx_late,
\r
2075 x_counters.Rx_corrupt,
\r
2076 x_counters.Rx_pkt_dupl,
\r
2077 x_counters.Total_msgs_rcvd,
\r
2080 if(rx_counter > old_rx_counter)
\r
2081 old_rx_counter = rx_counter;
\r
2082 if(tx_counter > old_tx_counter)
\r
2083 old_tx_counter = tx_counter;
\r
2085 if(rx_counter > 0 && tx_counter > 0)
\r
2086 MLogSetMask(0xFFFFFFFF);
\r
2088 printf("error xran_get_common_counters\n");
\r
2091 if (xran_curr_if_state == XRAN_STOPPED){
\r
2094 if (NULL == fgets(input, 10, stdin)) {
\r
2098 const int sel_opt = atoi(input);
\r
2099 switch (sel_opt) {
\r
2101 xran_start(xranHandle);
\r
2102 printf("Start XRAN traffic\n");
\r
2107 xran_stop(xranHandle);
\r
2108 printf("Stop XRAN traffic\n");
\r
2109 state = APP_STOPPED;
\r
2112 puts("Wrong option passed!");
\r
2115 if (APP_STOPPED == state)
\r
2119 get_xran_iq_content();
\r
2121 puts("Closing l1 app... Ending all threads...");
\r
2122 xran_close(xranHandle);
\r
2126 puts("Dump IQs...");
\r
2128 if (startupConfiguration.iqswap == 1){
\r
2129 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
2130 printf("RX: Swap I and Q to match CPU format: [%d]\n",i);
\r
2132 /* swap I and Q */
\r
2134 signed short *ptr = (signed short *) p_rx_log_buffer[i];
\r
2135 signed short temp;
\r
2137 for (j = 0; j < (int32_t)(rx_log_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
2139 ptr[j] = ptr[j + 1];
\r
2140 ptr[j + 1] = temp;
\r
2145 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
\r
2147 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
2149 printf("SRS: Swap I and Q to match CPU format: [%d]\n",i);
\r
2151 /* swap I and Q */
\r
2153 signed short *ptr = (signed short *) p_srs_log_buffer[i];
\r
2154 signed short temp;
\r
2156 for (j = 0; j < (int32_t)(srs_log_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
2158 ptr[j] = ptr[j + 1];
\r
2159 ptr[j + 1] = temp;
\r
2166 if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0) {
\r
2168 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
2169 printf("RX: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i);
\r
2170 for (j = 0; j < rx_log_buffer_size[i]/sizeof(short); j++){
\r
2171 p_rx_log_buffer[i][j] = rte_be_to_cpu_16(p_rx_log_buffer[i][j]);
\r
2175 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
\r
2177 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
2179 printf("SRS: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i);
\r
2180 for (j = 0; j < srs_log_buffer_size[i]/sizeof(short); j++){
\r
2181 p_srs_log_buffer[i][j] = rte_be_to_cpu_16(p_srs_log_buffer[i][j]);
\r
2187 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
2189 sprintf(filename, "./logs/%s-rx_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
2190 sys_save_buf_to_file_txt(filename,
\r
2191 "UL FFT OUT IQ Samples in human readable format",
\r
2192 (uint8_t*) p_rx_log_buffer[i],
\r
2193 rx_log_buffer_size[i],
\r
2196 sprintf(filename, "./logs/%s-rx_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
2197 sys_save_buf_to_file(filename,
\r
2198 "UL FFT OUT IQ Samples in binary format",
\r
2199 (uint8_t*) p_rx_log_buffer[i],
\r
2200 rx_log_buffer_size[i]/sizeof(short),
\r
2204 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){
\r
2206 i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx);
\r
2208 sprintf(filename, "./logs/%s-srs_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
2209 sys_save_buf_to_file_txt(filename,
\r
2210 "SRS UL FFT OUT IQ Samples in human readable format",
\r
2211 (uint8_t*) p_srs_log_buffer[i],
\r
2212 srs_log_buffer_size[i],
\r
2215 sprintf(filename, "./logs/%s-srs_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
2216 sys_save_buf_to_file(filename,
\r
2217 "SRS UL FFT OUT IQ Samples in binary format",
\r
2218 (uint8_t*) p_srs_log_buffer[i],
\r
2219 srs_log_buffer_size[i]/sizeof(short),
\r
2224 if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enablePrach){
\r
2225 if (startupConfiguration.iqswap == 1){
\r
2226 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
2227 printf("PRACH: Swap I and Q to match CPU format: [%d]\n",i);
\r
2229 /* swap I and Q */
\r
2231 signed short *ptr = (signed short *) p_prach_log_buffer[i];
\r
2232 signed short temp;
\r
2234 for (j = 0; j < (int32_t)(prach_log_buffer_size[i]/sizeof(short)) ; j = j + 2){
\r
2236 ptr[j] = ptr[j + 1];
\r
2237 ptr[j + 1] = temp;
\r
2244 if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0){
\r
2245 for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
2246 printf("PRACH: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i);
\r
2247 for (j = 0; j < prach_log_buffer_size[i]/sizeof(short); j++){
\r
2248 p_prach_log_buffer[i][j] = rte_be_to_cpu_16(p_prach_log_buffer[i][j]);
\r
2254 for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) {
\r
2256 sprintf(filename, "./logs/%s-prach_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
2257 sys_save_buf_to_file_txt(filename,
\r
2258 "PRACH FFT OUT IQ Samples in human readable format",
\r
2259 (uint8_t*) p_prach_log_buffer[i],
\r
2260 prach_log_buffer_size[i],
\r
2263 sprintf(filename, "./logs/%s-prach_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i);
\r
2264 sys_save_buf_to_file(filename,
\r
2265 "PRACH FFT OUT IQ Samples in binary format",
\r
2266 (uint8_t*) p_prach_log_buffer[i],
\r
2267 prach_log_buffer_size[i]/sizeof(short),
\r