1 /******************************************************************************
3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
21 #include <arpa/inet.h>
26 #include "xran_fh_o_du.h"
28 #include "xran_pkt_up.h"
29 #include "xran_cp_api.h"
30 #include "xran_up_api.h"
32 #include "xran_mlog_lnx.h"
34 extern enum app_state state;
36 int iq_playback_buffer_size_dl = IQ_PLAYBACK_BUFFER_BYTES;
37 int iq_playback_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES;
39 int iq_bfw_buffer_size_dl = IQ_PLAYBACK_BUFFER_BYTES;
40 int iq_bfw_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES;
42 int iq_srs_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES;
44 uint8_t numCCPorts = 1;
45 /* Number of antennas supported by front-end */
48 /* Number of CPRI ports supported by front-end */
50 int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
51 int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
52 int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
54 int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
55 int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
56 int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
58 int16_t *p_tx_srs_play_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
59 int32_t tx_srs_play_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
60 int32_t tx_srs_play_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
62 int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
63 int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
64 int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
66 int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
67 int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
68 int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
70 int16_t *p_srs_log_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
71 int32_t srs_log_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
72 int32_t srs_log_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
74 int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED];
75 int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
77 int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED];
78 int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
80 /* beamforming weights for UL (O-DU) */
81 int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
82 int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
83 int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
85 /* beamforming weights for UL (O-DU) */
86 int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
87 int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
88 int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
90 /* beamforming weights for UL (O-RU) */
91 int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
92 int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
93 int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
95 /* beamforming weights for UL (O-RU) */
96 int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
97 int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
98 int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
100 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
101 uint16_t nNumRbsPerSymF1[3][13] =
103 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
104 {25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0}, // Numerology 0 (15KHz)
105 {11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273}, // Numerology 1 (30KHz)
106 {0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135} // Numerology 2 (60KHz)
109 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
110 uint16_t nNumRbsPerSymF2[2][4] =
112 // 50Mhz 100MHz 200MHz 400MHz
113 {66, 132, 264, 0}, // Numerology 2 (60KHz)
114 {32, 66, 132, 264} // Numerology 3 (120KHz)
117 // 38.211 - Table 4.2.1
118 uint16_t nSubCarrierSpacing[5] =
127 // TTI interval in us (slot duration)
128 uint16_t nTtiInterval[4] =
137 // F1 Tables 38.101-1 Table F.5.3. Window length for normal CP
138 uint16_t nCpSizeF1[3][13][2] =
140 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
141 {{40, 36}, {80, 72}, {120, 108}, {160, 144}, {160, 144}, {240, 216}, {320, 288}, {320, 288}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}}, // Numerology 0 (15KHz)
142 {{22, 18}, {44, 36}, {66, 54}, {88, 72}, {88, 72}, {132, 108}, {176, 144}, {176, 144}, {264, 216}, {264, 216}, {352, 288}, {352, 288}, {352, 288}}, // Numerology 1 (30KHz)
143 { {0, 0}, {26, 18}, {39, 27}, {52, 36}, {52, 36}, {78, 54}, {104, 72}, {104, 72}, {156, 108}, {156, 108}, {208, 144}, {208, 144}, {208, 144}}, // Numerology 2 (60KHz)
146 // F2 Tables 38.101-2 Table F.5.3. Window length for normal CP
147 int16_t nCpSizeF2[2][4][2] =
149 // 50Mhz 100MHz 200MHz 400MHz
150 { {0, 0}, {104, 72}, {208, 144}, {416, 288}}, // Numerology 2 (60KHz)
151 {{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
154 uint32_t gMaxSlotNum;
157 uint32_t gDLResetAdvance;
158 uint32_t gDLProcAdvance;
159 uint32_t gULProcAdvance;
161 static uint16_t g_NumSlotTDDLoop[XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP };
162 static uint16_t g_NumDLSymSp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
163 static uint16_t g_NumULSymSp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
164 static uint8_t g_SlotType[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}};
165 float g_UlRate[XRAN_MAX_SECTOR_NR] = {0.0};
166 float g_DlRate[XRAN_MAX_SECTOR_NR] = {0.0};
168 uint32_t app_xran_get_tti_interval(uint8_t nMu)
172 return nTtiInterval[nMu];
176 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
182 uint32_t app_xran_get_scs(uint8_t nMu)
186 return nSubCarrierSpacing[nMu];
190 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
199 //-------------------------------------------------------------------------------------------
200 /** @ingroup group_nr5g_source_phy_common
202 * @param[in] nNumerology - Numerology determine sub carrier spacing, Value: 0->4 0: 15khz, 1: 30khz, 2: 60khz 3: 120khz, 4: 240khz
203 * @param[in] nBandwidth - Carrier bandwidth for in MHz. Value: 5->400
204 * @param[in] nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
206 * @return Number of RBs in cell
209 * Returns number of RBs based on 38.101-1 and 38.101-2 for the cell
212 //-------------------------------------------------------------------------------------------
213 uint16_t app_xran_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
218 if (nAbsFrePointA <= 6000000)
220 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
226 numRBs = nNumRbsPerSymF1[nNumerology][0];
229 case PHY_BW_10_0_MHZ:
230 numRBs = nNumRbsPerSymF1[nNumerology][1];
233 case PHY_BW_15_0_MHZ:
234 numRBs = nNumRbsPerSymF1[nNumerology][2];
237 case PHY_BW_20_0_MHZ:
238 numRBs = nNumRbsPerSymF1[nNumerology][3];
241 case PHY_BW_25_0_MHZ:
242 numRBs = nNumRbsPerSymF1[nNumerology][4];
245 case PHY_BW_30_0_MHZ:
246 numRBs = nNumRbsPerSymF1[nNumerology][5];
249 case PHY_BW_40_0_MHZ:
250 numRBs = nNumRbsPerSymF1[nNumerology][6];
253 case PHY_BW_50_0_MHZ:
254 numRBs = nNumRbsPerSymF1[nNumerology][7];
257 case PHY_BW_60_0_MHZ:
258 numRBs = nNumRbsPerSymF1[nNumerology][8];
261 case PHY_BW_70_0_MHZ:
262 numRBs = nNumRbsPerSymF1[nNumerology][9];
265 case PHY_BW_80_0_MHZ:
266 numRBs = nNumRbsPerSymF1[nNumerology][10];
269 case PHY_BW_90_0_MHZ:
270 numRBs = nNumRbsPerSymF1[nNumerology][11];
273 case PHY_BW_100_0_MHZ:
274 numRBs = nNumRbsPerSymF1[nNumerology][12];
285 if ((nNumerology >= 2) && (nNumerology <= 3))
287 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
290 case PHY_BW_50_0_MHZ:
291 numRBs = nNumRbsPerSymF2[nNumerology-2][0];
294 case PHY_BW_100_0_MHZ:
295 numRBs = nNumRbsPerSymF2[nNumerology-2][1];
298 case PHY_BW_200_0_MHZ:
299 numRBs = nNumRbsPerSymF2[nNumerology-2][2];
302 case PHY_BW_400_0_MHZ:
303 numRBs = nNumRbsPerSymF2[nNumerology-2][3];
316 printf("ERROR: %s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA);
320 printf("%s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA, numRBs);
326 //-------------------------------------------------------------------------------------------
327 /** @ingroup phy_cal_nrarfcn
329 * @param[in] center frequency
334 * This calculates NR-ARFCN value according to center frequency
337 //-------------------------------------------------------------------------------------------
338 uint32_t app_xran_cal_nrarfcn(uint32_t nCenterFreq)
340 uint32_t nDeltaFglobal,nFoffs,nNoffs;
341 uint32_t nNRARFCN = 0;
343 if(nCenterFreq > 0 && nCenterFreq < 3000*1000)
349 else if(nCenterFreq >= 3000*1000 && nCenterFreq < 24250*1000)
355 else if(nCenterFreq >= 24250*1000 && nCenterFreq <= 100000*1000)
363 printf("@@@@ incorrect center frerquency %d\n",nCenterFreq);
367 nNRARFCN = ((nCenterFreq - nFoffs)/nDeltaFglobal) + nNoffs;
369 printf("%s: nCenterFreq[%d] nDeltaFglobal[%d] nFoffs[%d] nNoffs[%d] nNRARFCN[%d]\n", __FUNCTION__, nCenterFreq, nDeltaFglobal, nFoffs, nNoffs, nNRARFCN);
373 int32_t app_xran_slot_limit(int32_t nSfIdx)
376 nSfIdx += gMaxSlotNum;
379 while (nSfIdx >= gMaxSlotNum) {
380 nSfIdx -= gMaxSlotNum;
386 void app_xran_clear_slot_type(uint32_t nPhyInstanceId)
388 g_UlRate[nPhyInstanceId] = 0.0;
389 g_DlRate[nPhyInstanceId] = 0.0;
390 g_NumSlotTDDLoop[nPhyInstanceId] = 1;
393 int32_t app_xran_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config *psSlotConfig)
395 uint32_t nSlotNum, nSymNum, nVal, i;
396 uint32_t numDlSym, numUlSym, numGuardSym;
397 uint32_t numDlSlots = 0, numUlSlots = 0, numSpDlSlots = 0, numSpUlSlots = 0, numSpSlots = 0;
398 char sSlotPattern[XRAN_SLOT_TYPE_LAST][10] = {"IN\0", "DL\0", "UL\0", "SP\0", "FD\0"};
400 // nPhyInstanceId Carrier ID
401 // nFrameDuplexType 0 = FDD 1 = TDD
402 // nTddPeriod Tdd Periodicity
403 // psSlotConfig[80] Slot Config Structure for nTddPeriod Slots
405 g_UlRate[nPhyInstanceId] = 0.0;
406 g_DlRate[nPhyInstanceId] = 0.0;
407 g_NumSlotTDDLoop[nPhyInstanceId] = nTddPeriod;
409 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
411 g_SlotType[nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID;
412 g_NumDLSymSp[nPhyInstanceId][i] = 0;
413 g_NumULSymSp[nPhyInstanceId][i] = 0;
416 if (nFrameDuplexType == XRAN_FDD)
418 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
420 g_SlotType[nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD;
422 g_NumSlotTDDLoop[nPhyInstanceId] = 1;
423 g_DlRate[nPhyInstanceId] = 1.0;
424 g_UlRate[nPhyInstanceId] = 1.0;
428 for (nSlotNum = 0; nSlotNum < nTddPeriod; nSlotNum++)
433 for (nSymNum = 0; nSymNum < XRAN_NUM_OF_SYMBOL_PER_SLOT; nSymNum++)
435 switch(psSlotConfig[nSlotNum].nSymbolType[nSymNum])
437 case XRAN_SYMBOL_TYPE_DL:
440 case XRAN_SYMBOL_TYPE_GUARD:
449 // printf("nSlotNum[%d] : numDlSym[%d] numGuardSym[%d] numUlSym[%d]\n", nSlotNum, numDlSym, numGuardSym, numUlSym);
451 if ((numUlSym == 0) && (numGuardSym == 0))
453 g_SlotType[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL;
456 else if ((numDlSym == 0) && (numGuardSym == 0))
458 g_SlotType[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL;
463 g_SlotType[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP;
469 g_NumDLSymSp[nPhyInstanceId][nSlotNum] = numDlSym;
474 g_NumULSymSp[nPhyInstanceId][nSlotNum] = numUlSym;
478 // printf(" numDlSlots[%d] numUlSlots[%d] numSpSlots[%d] numSpDlSlots[%d] numSpUlSlots[%d]\n", numDlSlots, numUlSlots, numSpSlots, numSpDlSlots, numSpUlSlots);
481 g_DlRate[nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod;
482 g_UlRate[nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod;
485 printf("set_slot_type: nPhyInstanceId[%d] nFrameDuplexType[%d], nTddPeriod[%d]\n",
486 nPhyInstanceId, nFrameDuplexType, nTddPeriod);
488 printf("DLRate[%f] ULRate[%f]\n", g_DlRate[nPhyInstanceId], g_UlRate[nPhyInstanceId]);
490 nVal = (g_NumSlotTDDLoop[nPhyInstanceId] < 10) ? g_NumSlotTDDLoop[nPhyInstanceId] : 10;
492 printf("SlotPattern:\n");
494 for (nSlotNum = 0; nSlotNum < nVal; nSlotNum++)
496 printf("%d ", nSlotNum);
501 for (nSlotNum = 0, i = 0; nSlotNum < g_NumSlotTDDLoop[nPhyInstanceId]; nSlotNum++)
503 printf("%s ", sSlotPattern[g_SlotType[nPhyInstanceId][nSlotNum]]);
505 if ((i == 10) && ((nSlotNum+1) < g_NumSlotTDDLoop[nPhyInstanceId]))
508 printf(" %3d ", nSlotNum);
517 int32_t app_xran_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType)
519 int32_t nSfIdxMod, nSfType, ret = 0;
521 nSfIdxMod = app_xran_slot_limit(nSlotdx) % ((g_NumSlotTDDLoop[nCellIdx] > 0) ? g_NumSlotTDDLoop[nCellIdx]: 1);
522 nSfType = g_SlotType[nCellIdx][nSfIdxMod];
524 if (nSfType == nType)
528 else if (nSfType == XRAN_SLOT_TYPE_SP)
530 if ((nType == XRAN_SLOT_TYPE_DL) && g_NumDLSymSp[nCellIdx][nSfIdxMod])
535 if ((nType == XRAN_SLOT_TYPE_UL) && g_NumULSymSp[nCellIdx][nSfIdxMod])
540 else if (nSfType == XRAN_SLOT_TYPE_FDD)
550 void sys_save_buf_to_file(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num)
554 if (filename && bufname)
557 printf("Storing %s to file %s: ", bufname, filename);
558 file = fopen(filename, "wb");
561 printf("can't open file %s!!!", filename);
566 num = fwrite(pBuffer, buffers_num, size, file);
569 printf("from addr (0x%lx) size (%d) bytes num (%d)", (uint64_t)pBuffer, size, num);
575 printf(" the file name, buffer name are not set!!!");
580 printf(" the %s is free: size = %d bytes!!!", bufname, size);
584 int sys_load_file_to_buff(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num)
586 unsigned int file_size = 0;
591 if (filename && bufname)
594 printf("Loading file %s to %s: ", filename, bufname);
595 file = fopen(filename, "rb");
600 printf("can't open file %s!!!", filename);
605 fseek(file, 0, SEEK_END);
606 file_size = ftell(file);
607 fseek(file, 0, SEEK_SET);
609 if ((file_size > size) || (file_size == 0))
612 printf("Reading IQ samples from file: File Size: %d [Buffer Size: %d]\n", file_size, size);
614 num = fread(pBuffer, buffers_num, size, file);
617 printf("from addr (0x%lx) size (%d) bytes num (%d)", (uint64_t)pBuffer, file_size, num);
624 printf(" the file name, buffer name are not set!!!");
629 printf(" the %s is free: size = %d bytes!!!", bufname, size);
635 void sys_save_buf_to_file_txt(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num)
644 if (filename && bufname)
647 printf("Storing %s to file %s: ", bufname, filename);
648 file = fopen(filename, "w");
651 printf("can't open file %s!!!", filename);
658 signed short *ptr = (signed short*)pBuffer;
659 for (i = 0; i < (size/((unsigned int)sizeof(signed short) /** 2 * 2 * 2*/)); i = i + 2)
662 ret = fprintf(file,"%d %d\n", ptr[i], ptr[i + 1]);
664 ret = fprintf(file,"%d %d ", ptr[i], ptr[i + 1]);
665 /* I data => Ramp data, from 1 to 792.
666 Q data => Contains time information of the current symbol:
667 Bits [15:14] = Antenna-ID
668 Bits [13:12] =
\9300
\94
669 Bits [11:8] = Subframe-ID
671 Bits [3:0] = Symbol-ID */
672 fprintf(file, "0x%04x: ant %d Subframe-ID %d Slot-ID %d Symbol-ID %d\n",
673 ptr[i + 1], (ptr[i + 1]>>14) & 0x3, (ptr[i + 1]>>8) & 0xF, (ptr[i + 1]>>4) & 0xF, (ptr[i + 1]>>0) & 0xF);
677 printf("fprintf %d\n", ret);
685 printf("from addr (0x%lx) size (%d) IQ num (%d)", (uint64_t)pBuffer, size, num);
691 printf(" the file name, buffer name are not set!!!");
696 printf(" the %s is free: size = %d bytes!!!", bufname, size);