SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
+ /*TODO: will remove the above parameter which is stopping multiUE allocation
+ * for PDCCH*/
+ uint32_t usedRbgForPdcch[FREQ_DOM_RSRC_SIZE]; /*Bitmap for used RBG during PDCCH allocation in this slot.*/
uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
DciInfo *ulGrant;
void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
+uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue);
/*Paging Functions*/
void schProcPagingCfg(SchCellCb *cell);
return k2Found;
}
+/*
+ * * @brief : This Function fills the Coreset and SS info based on PDCCH Cfg received for a UE
+ *
+ * Function : fillUeCoresetAndSsInfo
+ *
+ * For a Coreset, capture the following details which will be used during pdcch allocation
+ * [Step 1]: Count number of RBG and calculate TotalPRBs which can be used
+ * [Step 2]: Get the reference pointer for Coreset and Its SearchSpace.
+ * [Step 3]: A CCE will have 6 RBs in TOTAL. If duration increases, CCE will
+ * occupy less number of PRBs(1RB x 1 OFDM Symbol). Eg. If duration = 2, then
+ * instead of 6 PRBs, CCE will only occupy 3 PRBs and 2 OFDM symbols.
+ * [Step 4]: Based on CoresetSize, fill AggLvl-CQI mapping by calculating the dciSize.
+ * [Step 5]: Calculate Y value for this coreset and UE
+ *
+ * @Params[in]: UeCb,
+ * [return]: ROK, RFAILED : Memory allocation failure.
+ **/
+uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue)
+{
+ uint8_t cRSetIdx = 0,ssIdx = 0;
+ uint16_t rbgCount = 0;
+ SchPdcchConfig *pdcchCfg = NULLP;
+
+ pdcchCfg = &ue->ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg;
+ if(pdcchCfg == NULLP)
+ {
+ DU_LOG("\nERROR --> SCH: PDCCH Cfg is not received thus skip filling of Coreset & SS info");
+ return RFAILED;
+ }
+ for(cRSetIdx = 0; cRSetIdx < pdcchCfg->numCRsetToAddMod; cRSetIdx++ )
+ {
+ /*[Step 1]: *//*Size of coreset: Number of PRBs in a coreset*/
+ rbgCount = countRBGFrmCoresetFreqRsrc(pdcchCfg->cRSetToAddModList[cRSetIdx].freqDomainRsrc);
+ if(rbgCount)
+ {
+ ue->pdcchInfo[cRSetIdx].totalPrbs = ((rbgCount) * NUM_PRBS_PER_RBG);
+ }
+ else
+ {
+ DU_LOG("\nERROR --> SCH : CORESETSize is zero in fillCoresetAndSsConfg");
+ continue;
+ }
+ /*[Step 2]:*/
+ ue->pdcchInfo[cRSetIdx].cRSetRef = &pdcchCfg->cRSetToAddModList[cRSetIdx];
+ for(ssIdx = 0; ssIdx < pdcchCfg->numSearchSpcToAddMod; ssIdx++)
+ {
+ if(pdcchCfg->searchSpcToAddModList[ssIdx].cRSetId == pdcchCfg->cRSetToAddModList[cRSetIdx].cRSetId)
+ {
+ ue->pdcchInfo[cRSetIdx].ssRef = &pdcchCfg->searchSpcToAddModList[ssIdx];
+ break;
+ }
+ }
+
+ /*[Step 3]:*/
+ /*nrOfPRBPerCce is Number of PRBs occupied by a CCE based on Duration*/
+ ue->pdcchInfo[cRSetIdx].nrOfPRBPerCce = NUM_PRBS_PER_RBG/pdcchCfg->cRSetToAddModList[cRSetIdx].duration;
+ ue->pdcchInfo[cRSetIdx].totalCceCount = rbgCount * pdcchCfg->cRSetToAddModList[cRSetIdx].duration;
+
+ /*[Step 4]:*/
+ fillCqiAggLvlMapping(&ue->pdcchInfo[cRSetIdx]);
+
+ /*[Step 5]:*/
+ if(RFAILED == schUpdValY(ue, &ue->pdcchInfo[cRSetIdx]))
+ {
+ return RFAILED;
+ }
+ }
+ return ROK;
+}
+
+
/**********************************************************************
End of file
**********************************************************************/
cmLListInit(&ueCb->hqUlmap[idx]->hqList);
}
ret = fillSchUeCbFrmCfgReq(inst, ueCb, ueCfg);
-
+
+ if(fillUeCoresetAndSsInfo(ueCb) == RFAILED)
+ {
+ DU_LOG("\nERROR --> SCH : Memory Allocation Failed");
+ return RFAILED;
+ }
if(ret == ROK)
{
/* If UE has initiated RACH and then UE context is created, it means UE is
SchUeRecfgRsp recfgRsp;
Inst inst = pst->dstInst - SCH_INST_START;
memset(&recfgRsp, 0, sizeof(SchUeRecfgRsp));
-
+
if(!ueRecfg)
{
DU_LOG("\nERROR --> SCH : Modifying Ue Config request failed at SchModUeConfigReq()");
/* Search if UE already configured */
GET_UE_ID(ueRecfg->crnti, ueId);
ueCb = &cellCb->ueCb[ueId -1];
-
+
if(!ueCb)
{
DU_LOG("\nERROR --> SCH : SchUeCb not found at SchModUeConfigReq() ");
{
/* Found the UeCb to Reconfig */
ret = fillSchUeCbFrmRecfgReq(inst, ueCb, ueRecfg);
+ if(fillUeCoresetAndSsInfo(ueCb) == RFAILED)
+ {
+ DU_LOG("\nERROR --> SCH : Memory Allocation Failed");
+ return RFAILED;
+ }
if(ret == ROK)
{
ueCb->cellCb = cellCb;
* ****************************************************************/
void deleteSchUeCb(SchUeCb *ueCb)
{
- uint8_t timeDomRsrcIdx = 0, ueLcIdx = 0, idx =0;
+ uint8_t timeDomRsrcIdx = 0, ueLcIdx = 0, slotIdx =0, cRSetIdx = 0;
SchPucchCfg *pucchCfg = NULLP;
SchPdschConfig *pdschCfg = NULLP;
{
if(ueCb->hqDlmap)
{
- for (idx = 0; idx<ueCb->cellCb->numSlots; idx++)
+ for (slotIdx = 0; slotIdx<ueCb->cellCb->numSlots; slotIdx++)
{
- if(ueCb->hqDlmap[idx])
+ if(ueCb->hqDlmap[slotIdx])
{
- cmLListDeleteLList(&ueCb->hqDlmap[idx]->hqList);
- SCH_FREE(ueCb->hqDlmap[idx], sizeof(SchHqDlMap));
+ cmLListDeleteLList(&ueCb->hqDlmap[slotIdx]->hqList);
+ SCH_FREE(ueCb->hqDlmap[slotIdx], sizeof(SchHqDlMap));
}
}
SCH_FREE(ueCb->hqDlmap, sizeof(SchHqDlMap*)*(ueCb->cellCb->numSlots));
if(ueCb->hqUlmap)
{
- for (idx = 0; idx<ueCb->cellCb->numSlots; idx++)
+ for (slotIdx = 0; slotIdx<ueCb->cellCb->numSlots; slotIdx++)
{
- if(ueCb->hqUlmap[idx])
+ if(ueCb->hqUlmap[slotIdx])
{
- cmLListDeleteLList(&ueCb->hqUlmap[idx]->hqList);
- SCH_FREE(ueCb->hqUlmap[idx], sizeof(SchHqUlMap));
+ cmLListDeleteLList(&ueCb->hqUlmap[slotIdx]->hqList);
+ SCH_FREE(ueCb->hqUlmap[slotIdx], sizeof(SchHqUlMap));
}
}
SCH_FREE(ueCb->hqUlmap, sizeof(SchHqUlMap*)*(ueCb->cellCb->numSlots));
ueCb->ueDrxInfoPres = false;
}
#endif
+
+ for(cRSetIdx=0; cRSetIdx < MAX_NUM_CRSET; cRSetIdx++)
+ {
+ SCH_FREE(ueCb->pdcchInfo[cRSetIdx].y, (sizeof(uint32_t) * ueCb->cellCb->numSlots));
+ }
memset(ueCb, 0, sizeof(SchUeCb));
}
}
* Modulation Scheme is numbered based on bit rate as follows
* QPSK = 2, 16QAM = 4, 64QAM = 6
* */
-unsigned long cqiTable1[MAX_NUM_CQI_IDX][3] = {
+float cqiTable1[MAX_NUM_CQI_IDX][3] = {
{ 0, 0, 0}, /*index 0*/
{ 2, 78, 0.1523}, /*index 1*/
{ 2, 120, 0.2344}, /*index 2*/
freeBlock->endPrb = MAX_NUM_RB-1;
addNodeToLList(&schDlSlotInfo->prbAlloc.freePrbBlockList, freeBlock, NULL);
}
+ memset(schDlSlotInfo->usedRbgForPdcch, 0, (sizeof(uint32_t) * FREQ_DOM_RSRC_SIZE));
}
/**
/*CQI table number 1 is used Spec 38.214 Table 5.2.2.1-2 by default.
*TODO: cqi-table param in CSI-RepotConfig(3gpp 38.331) will report
* which table to be used*/
- pdcchBits = dciSize / cqiTable1[cqiIdx][2];
+ pdcchBits = ceil(dciSize / cqiTable1[cqiIdx][2]);
for(aggLvlIdx = 0; (aggLvlIdx < MAX_NUM_AGG_LVL) && (pdcchBits != 0); aggLvlIdx++)
{
numOfBitsAvailForAggLevel = (totalRE_PerAggLevel[aggLvlIdx] * cqiTable1[cqiIdx][0]);
* in pdcch allocation
*
* @params[in] : SchUeCb, PdcchInfo
+ * [return] : uint8_t ROK, RFAILED : Memory allocation status
*
* */
-void schUpdValY(SchUeCb *ueCb, SchPdcchInfo *pdcchInfo)
+uint8_t schUpdValY(SchUeCb *ueCb, SchPdcchInfo *pdcchInfo)
{
uint8_t slotIdx = 0;
SCH_ALLOC(pdcchInfo->y, (sizeof(uint32_t) * ueCb->cellCb->numSlots));
+ if(pdcchInfo->y == NULLP)
+ {
+ DU_LOG("\nERROR --> SCH: Memory Allocation of Y failed");
+ return RFAILED;
+ }
for(slotIdx= 0 ; slotIdx < ueCb->cellCb->numSlots; slotIdx++)
{
pdcchInfo->y[slotIdx] = schCalY(pdcchInfo->cRSetRef->cRSetId, pdcchInfo->y[slotIdx - 1]);
}
}
+ return ROK;
}
/**********************************************************************
End of file
uint8_t countRBGFrmCoresetFreqRsrc(uint8_t *freqDomainRsrc);
uint8_t findSsStartSymbol(uint8_t *mSymbolsWithinSlot);
void fillCqiAggLvlMapping(SchPdcchInfo *pdcchInfo);
-void schUpdValY(SchUeCb *ueCb, SchPdcchInfo *pdcchInfo);
+uint8_t schUpdValY(SchUeCb *ueCb, SchPdcchInfo *pdcchInfo);
#if 0
/*Will be enabled for debugging*/
void printLcLL(CmLListCp *lcLL);