[Epic-ID: ODUHIGH-475][Task-ID: ODUHIGH-572] Fix LWR_MAC creation during PHY as INTEL_L1

Change-Id: Iabcebcfe0d348729f638d5c9982fa96655577891
Signed-off-by: svaidhya <svaidhya@radisys.com>

diff --git a/src/mt/mt_ss.h b/src/mt/mt_ss.h
index 68c0213..e213b7d 100755 (executable)
--- a/src/mt/mt_ss.h
+++ b/src/mt/mt_ss.h
@@ -66,7 +66,7 @@
 #ifndef INTEL_WLS_MEM
 #define SS_MAX_STSKS                    9
 #else
-#define SS_MAX_STSKS                    7 
+#define SS_MAX_STSKS                    8 
 #endif
 #endif 
 #endif /* SS_MULTICORE_SUPPORT */