#include "CNUEPagingIdentity.h"
#include "PagingCell-Item.h"
#include "UL-DCCH-Message.h"
+ #include "DRX-ConfigRrc.h"
#include "cu_stub_sctp.h"
#include "cu_stub_egtp.h"
}
else if(rrcMsgType == RRC_SETUP_COMPLETE)
{
- DU_LOG("\nINFO --> F1AP : Sending Security mode command");
- char secModeBuf[9]={0x00, 0x02, 0x22, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00};
+ DU_LOG("\nINFO --> F1AP : Sending NAS Security mode command");
+ char secModeBuf[30]={0x00, 0x02, 0x2e, 0x82, 0xaf, 0xc0, 0x7d, 0x1c, 0x4e, 0xfc, 0x80, 0x0f, 0xc0,
+ 0x0b, 0xa0, 0x20, 0x40, 0x9e, 0x0e, 0x1e, 0x0e, 0x1c, 0x26, 0xc0, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00};
+ bufLen =30;
+ rrcContainer->size = bufLen;
+ CU_ALLOC(rrcContainer->buf, rrcContainer->size);
+ if(rrcContainer->buf != NULLP)
+ {
+ memset(rrcContainer->buf, 0, bufLen);
+ memcpy(rrcContainer->buf, secModeBuf, bufLen);
+ }
+ else
+ {
+ DU_LOG("\nERROR --> F1AP : Memory allocation failure for RRC Container buffer");
+ ret = RFAILED;
+ }
+ }
+ else if(rrcMsgType == NAS_SECURITY_MODE_COMPLETE)
+ {
+ DU_LOG("\nINFO --> F1AP : Sending RRC Security mode command");
+ char secModeBuf[9]={0x00, 0x03, 0x22, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00};
bufLen =9;
rrcContainer->size = bufLen;
CU_ALLOC(rrcContainer->buf, rrcContainer->size);
ret = RFAILED;
}
}
- else if(rrcMsgType == SECURITY_MODE_COMPLETE)
+ else if(rrcMsgType == RRC_SECURITY_MODE_COMPLETE)
{
/*Hardcoded RRC Container from reference logs*/
DU_LOG("\nINFO --> F1AP : Sending Registration accept");
- char buf[14] ={0x00, 0x03, 0x2a, 0x80, 0xaf, 0xc0, 0x08, 0x40, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00};
+ char buf[14] ={0x00, 0x04, 0x2a, 0x80, 0xaf, 0xc0, 0x08, 0x40, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00};
bufLen =14;
rrcContainer->size = bufLen;
CU_ALLOC(rrcContainer->buf, rrcContainer->size);
case RRC_SETUP_COMPLETE:
rrcMsgType = RRC_SETUP_COMPLETE;
break;
- case SECURITY_MODE_COMPLETE:
- rrcMsgType = SECURITY_MODE_COMPLETE;
+ case NAS_SECURITY_MODE_COMPLETE:
+ rrcMsgType = NAS_SECURITY_MODE_COMPLETE;
+ break;
+ case RRC_SECURITY_MODE_COMPLETE:
+ rrcMsgType = RRC_SECURITY_MODE_COMPLETE;
break;
case REGISTRATION_COMPLETE:
rrcMsgType = REGISTRATION_COMPLETE;
return rrcMsgType;
}
+ #ifdef NR_DRX
+ /*******************************************************************
+ *
+ * @brief fill long cycle offset value of drx
+ *
+ * @details
+ *
+ * Function : fillLongCycleOffsetValue
+ *
+ * Functionality: fill long cycle offset value of drx
+ *
+ * @params[in] DrxLongCycleStartOffset drxLongCycleStartOffset,
+ * struct DRX_ConfigRrc__drx_LongCycleStartOffset recvedLongCycleOffsetVal
+ *
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+ void fillLongCycleOffsetValue(DrxLongCycleStartOffset *drxLongCycleStartOffset, struct DRX_ConfigRrc__recvedLongCycleOffsetVal *recvedLongCycleOffsetVal)
+ {
+
+ drxLongCycleStartOffset->drxLongCycleStartOffsetChoice = recvedLongCycleOffsetVal->present;
+ switch(recvedLongCycleOffsetVal->present)
+ {
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms10:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms10;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms20:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms20;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms32:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms32;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms40:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms40;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms60:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms60;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms64:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms64;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms70:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms70;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms80:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms80;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms128:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms128;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms160:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms160;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms256:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms256;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms320:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms320;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms512:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms512;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms640:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms640;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms1024:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms1024;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms1280:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms1280;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms2048:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms2048;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms2560:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms2560;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms5120:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms5120;
+ break;
+ }
+ case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms10240:
+ {
+ drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms10240;
+ break;
+ }
+ default :
+ break;
+ }
+ }
+
+ /*******************************************************************
+ *
+ * @brief Extract configuration from DRX_ConfigRrc
+ * and store the drx configuration in UeCb
+ *
+ * @details
+ *
+ * Function : storeDrxCfgInUeCb
+ *
+ * Functionality: Store drx configuration in UeCb
+ *
+ * @params[in] (struct DRX_ConfigRrc *setup, DrxCfg *drxCfg)
+ *
+ * @return void
+ * ****************************************************************/
+ void storeDrxCfgInUeCb(struct DRX_ConfigRrc *drxSetup, DrxCfg *drxCfg)
+ {
+ if(drxSetup)
+ {
+ switch(drxSetup->drx_onDurationTimer.present)
+ {
+ case DRX_ConfigRrc__drx_onDurationTimer_PR_NOTHING:
+ break;
+ case DRX_ConfigRrc__drx_onDurationTimer_PR_milliSeconds:
+ {
+ drxCfg->drxOnDurationTimer.onDurationTimerValInMs = true;
+ drxCfg->drxOnDurationTimer.onDurationtimerValue.milliSeconds=drxSetup->drx_onDurationTimer.choice.milliSeconds;
+ break;
+ }
+ case DRX_ConfigRrc__drx_onDurationTimer_PR_subMilliSeconds:
+ {
+ drxCfg->drxOnDurationTimer.onDurationTimerValInMs = false;
+ drxCfg->drxOnDurationTimer.onDurationtimerValue.subMilliSeconds = drxSetup->drx_onDurationTimer.choice.subMilliSeconds;
+ break;
+ }
+ }
+ }
+ fillLongCycleOffsetValue(&drxCfg->drxLongCycleStartOffset, &drxSetup->drx_LongCycleStartOffset);
+ drxCfg->drxInactivityTimer = drxSetup->drx_InactivityTimer;
+ drxCfg->drxHarqRttTimerDl = drxSetup->drx_HARQ_RTT_TimerDL;
+ drxCfg->drxHarqRttTimerUl = drxSetup->drx_HARQ_RTT_TimerUL;
+ drxCfg->drxRetransmissionTimerDl = drxSetup->drx_RetransmissionTimerDL;
+ drxCfg->drxRetransmissionTimerUl = drxSetup->drx_RetransmissionTimerUL;
+ drxCfg->drxSlotOffset = drxSetup->drx_SlotOffset;
+ if(drxSetup->shortDRX)
+ {
+ drxCfg->shortDrxPres=true;
+ drxCfg->shortDrx.drxShortCycle = drxSetup->shortDRX->drx_ShortCycle;
+ drxCfg->shortDrx.drxShortCycleTimer = drxSetup->shortDRX->drx_ShortCycleTimer;
+ }
+ else
+ drxCfg->shortDrxPres=false;
+ }
+ #endif
+
/*******************************************************************
*
* @brief Extract configuration from CellGroupConfig
RLC_BearerConfig_t *rlcCfg = NULLP;
RLC_Config_t *rlcLcCfg = NULLP;
LogicalChannelConfig_t *macLcCfg = NULLP;
+ #ifdef NR_DRX
+ DrxCfg drxCfg;
+ #endif
if(ueCb == NULLP)
{
return RFAILED;
}
+ #ifdef NR_DRX
+ if(cellGrpCfg->mac_CellGroupConfig)
+ {
+ if(cellGrpCfg->mac_CellGroupConfig->drx_ConfigRrc)
+ {
+ switch(cellGrpCfg->mac_CellGroupConfig->drx_ConfigRrc->present)
+ {
+ case MAC_CellGroupConfig__drx_ConfigRrc_PR_NOTHING:
+ break;
+
+ case MAC_CellGroupConfig__drx_ConfigRrc_PR_setup:
+ {
+ storeDrxCfgInUeCb(cellGrpCfg->mac_CellGroupConfig->drx_ConfigRrc->choice.setup, &ueCb->drxCfg);
+ break;
+ }
+
+ case MAC_CellGroupConfig__drx_ConfigRrc_PR_release:
+ break;
+ }
+ }
+ }
+ #endif
+
for(rbIdx = 0; rbIdx < cellGrpCfg->rlc_BearerToAddModList->list.count; rbIdx++)
{
srbFound = false;
if(rval.code == RC_FAIL || rval.code == RC_WMORE)
{
- DU_LOG("\nERROR --> F1AP : ASN decode failed");
+ DU_LOG("\nERROR --> F1AP : ASN decode failed in extractDuToCuRrcCont");
return RFAILED;
}
printf("\n");
}
return ret;
}
-
+ /*******************************************************************
+ *
+ * @brief Build the drx cycle
+ *
+ * @details
+ *
+ * Function : BuildDrxCycle
+ *
+ * Functionality: Build drx cycle IE
+ *
+ * @params[in] pointer to DRXCycle_t
+ *
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ ******************************************************************/
+ uint8_t BuildDrxCycle(DRXCycle_t *drxCycle)
+ {
+ drxCycle->longDRXCycleLength = LongDRXCycleLength_ms40;
+ CU_ALLOC(drxCycle->shortDRXCycleLength, sizeof(ShortDRXCycleLength_t));
+ if(!drxCycle->shortDRXCycleLength)
+ {
+ DU_LOG("\nERROR --> F1AP : Memory allocation failed for shortDRXCycleLength");
+ return RFAILED;
+ }
+ *(drxCycle->shortDRXCycleLength) = ShortDRXCycleLength_ms4;
+
+ CU_ALLOC(drxCycle->shortDRXCycleTimer, sizeof(ShortDRXCycleTimer_t));
+ if(!drxCycle->shortDRXCycleTimer)
+ {
+ DU_LOG("\nERROR --> F1AP : Memory allocation failed for shortDRXCycleTimer");
+ return RFAILED;
+ }
+ *(drxCycle->shortDRXCycleTimer) = 4;
+ return ROK;
+ }
/*******************************************************************
*
* @brief Free CuToDuContainer
if(ueCb->state == UE_HANDOVER_IN_PROGRESS)
elementCnt = 7;
else
+ {
+ #ifdef NR_DRX
+ elementCnt = 12;
+ #else
elementCnt = 11;
+ #endif
+ }
ueSetReq->protocolIEs.list.count = elementCnt;
ueSetReq->protocolIEs.list.size = elementCnt * sizeof(UEContextSetupRequestIEs_t *);
if(ueCb->state != UE_HANDOVER_IN_PROGRESS)
{
+ /*Drx cycle*/
+ #ifdef NR_DRX
+ idx++;
+ ueSetReq->protocolIEs.list.array[idx]->id = ProtocolIE_ID_id_DRXCycle;
+ ueSetReq->protocolIEs.list.array[idx]->criticality = Criticality_ignore;
+ ueSetReq->protocolIEs.list.array[idx]->value.present = UEContextSetupRequestIEs__value_PR_DRXCycle;
+ if(BuildDrxCycle(&ueSetReq->protocolIEs.list.array[idx]->value.choice.DRXCycle) != ROK)
+ {
+ DU_LOG("\nERROR --> F1AP : Failed to build drx cycle");
+ break;
+ }
+ #endif
/*Special Cells to be SetupList*/
idx++;
ueSetReq->protocolIEs.list.array[idx]->id = ProtocolIE_ID_id_SCell_ToBeSetup_List;
rrcMsgType = setDlRRCMsgType(ueCb);
if(rrcMsgType == RRC_SETUP_COMPLETE)
{
- DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for Security Mode Command");
+ DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for NAS Security Mode Command");
+ ret = BuildAndSendDLRRCMessageTransfer(duId, ueCb, srbId, rrcMsgType);
+ }
+ if(rrcMsgType == NAS_SECURITY_MODE_COMPLETE)
+ {
+ DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for RRC Security Mode Command");
ret = BuildAndSendDLRRCMessageTransfer(duId, ueCb, srbId, rrcMsgType);
}
- else if(rrcMsgType == SECURITY_MODE_COMPLETE)
+ else if(rrcMsgType == RRC_SECURITY_MODE_COMPLETE)
{
DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for RRC Registration Accept");
BuildAndSendDLRRCMessageTransfer(duId, ueCb, srbId, rrcMsgType);
Code Review / o-du / l2.git / commitdiff