src/codec_utils/RRC/DRX-ConfigRrc.h

   1 /*
   2  * Generated by asn1c-0.9.29 (http://lionet.info/asn1c)
   3  * From ASN.1 module "NR-RRC-Definitions"
   4  *      found in "02_Aug/rrc_15_3_asn.asn1"
   5  *      `asn1c -D ./Aug02 -fcompound-names -fno-include-deps -findirect-choice -gen-PER -no-gen-example`
   6  */
   7
   8 #ifndef _DRX_ConfigRrc_H_
   9 #define _DRX_ConfigRrc_H_
  10
  11
  12 #include <asn_application.h>
  13
  14 /* Including external dependencies */
  15 #include <NativeEnumerated.h>
  16 #include <NativeInteger.h>
  17 #include <constr_CHOICE.h>
  18 #include <constr_SEQUENCE.h>
  19
  20 #ifdef __cplusplus
  21 extern "C" {
  22 #endif
  23
  24 /* Dependencies */
  25 typedef enum DRX_ConfigRrc__drx_onDurationTimer_PR {
  26         DRX_ConfigRrc__drx_onDurationTimer_PR_NOTHING,  /* No components present */
  27         DRX_ConfigRrc__drx_onDurationTimer_PR_subMilliSeconds,
  28         DRX_ConfigRrc__drx_onDurationTimer_PR_milliSeconds
  29 } DRX_ConfigRrc__drx_onDurationTimer_PR;
  30 typedef enum DRX_ConfigRrc__drx_onDurationTimer__milliSeconds {
  31         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms1    = 0,
  32         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms2    = 1,
  33         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms3    = 2,
  34         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms4    = 3,
  35         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms5    = 4,
  36         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms6    = 5,
  37         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms8    = 6,
  38         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms10   = 7,
  39         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms20   = 8,
  40         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms30   = 9,
  41         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms40   = 10,
  42         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms50   = 11,
  43         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms60   = 12,
  44         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms80   = 13,
  45         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms100  = 14,
  46         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms200  = 15,
  47         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms300  = 16,
  48         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms400  = 17,
  49         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms500  = 18,
  50         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms600  = 19,
  51         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms800  = 20,
  52         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms1000 = 21,
  53         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms1200 = 22,
  54         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_ms1600 = 23,
  55         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare8 = 24,
  56         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare7 = 25,
  57         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare6 = 26,
  58         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare5 = 27,
  59         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare4 = 28,
  60         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare3 = 29,
  61         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare2 = 30,
  62         DRX_ConfigRrc__drx_onDurationTimer__milliSeconds_spare1 = 31
  63 } e_DRX_ConfigRrc__drx_onDurationTimer__milliSeconds;
  64 typedef enum DRX_ConfigRrc__drx_InactivityTimer {
  65         DRX_ConfigRrc__drx_InactivityTimer_ms0  = 0,
  66         DRX_ConfigRrc__drx_InactivityTimer_ms1  = 1,
  67         DRX_ConfigRrc__drx_InactivityTimer_ms2  = 2,
  68         DRX_ConfigRrc__drx_InactivityTimer_ms3  = 3,
  69         DRX_ConfigRrc__drx_InactivityTimer_ms4  = 4,
  70         DRX_ConfigRrc__drx_InactivityTimer_ms5  = 5,
  71         DRX_ConfigRrc__drx_InactivityTimer_ms6  = 6,
  72         DRX_ConfigRrc__drx_InactivityTimer_ms8  = 7,
  73         DRX_ConfigRrc__drx_InactivityTimer_ms10 = 8,
  74         DRX_ConfigRrc__drx_InactivityTimer_ms20 = 9,
  75         DRX_ConfigRrc__drx_InactivityTimer_ms30 = 10,
  76         DRX_ConfigRrc__drx_InactivityTimer_ms40 = 11,
  77         DRX_ConfigRrc__drx_InactivityTimer_ms50 = 12,
  78         DRX_ConfigRrc__drx_InactivityTimer_ms60 = 13,
  79         DRX_ConfigRrc__drx_InactivityTimer_ms80 = 14,
  80         DRX_ConfigRrc__drx_InactivityTimer_ms100        = 15,
  81         DRX_ConfigRrc__drx_InactivityTimer_ms200        = 16,
  82         DRX_ConfigRrc__drx_InactivityTimer_ms300        = 17,
  83         DRX_ConfigRrc__drx_InactivityTimer_ms500        = 18,
  84         DRX_ConfigRrc__drx_InactivityTimer_ms750        = 19,
  85         DRX_ConfigRrc__drx_InactivityTimer_ms1280       = 20,
  86         DRX_ConfigRrc__drx_InactivityTimer_ms1920       = 21,
  87         DRX_ConfigRrc__drx_InactivityTimer_ms2560       = 22,
  88         DRX_ConfigRrc__drx_InactivityTimer_spare9       = 23,
  89         DRX_ConfigRrc__drx_InactivityTimer_spare8       = 24,
  90         DRX_ConfigRrc__drx_InactivityTimer_spare7       = 25,
  91         DRX_ConfigRrc__drx_InactivityTimer_spare6       = 26,
  92         DRX_ConfigRrc__drx_InactivityTimer_spare5       = 27,
  93         DRX_ConfigRrc__drx_InactivityTimer_spare4       = 28,
  94         DRX_ConfigRrc__drx_InactivityTimer_spare3       = 29,
  95         DRX_ConfigRrc__drx_InactivityTimer_spare2       = 30,
  96         DRX_ConfigRrc__drx_InactivityTimer_spare1       = 31
  97 } e_DRX_ConfigRrc__drx_InactivityTimer;
  98 typedef enum DRX_ConfigRrc__drx_RetransmissionTimerDL {
  99         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl0    = 0,
 100         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl1    = 1,
 101         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl2    = 2,
 102         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl4    = 3,
 103         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl6    = 4,
 104         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl8    = 5,
 105         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl16   = 6,
 106         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl24   = 7,
 107         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl33   = 8,
 108         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl40   = 9,
 109         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl64   = 10,
 110         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl80   = 11,
 111         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl96   = 12,
 112         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl112  = 13,
 113         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl128  = 14,
 114         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl160  = 15,
 115         DRX_ConfigRrc__drx_RetransmissionTimerDL_sl320  = 16,
 116         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare15        = 17,
 117         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare14        = 18,
 118         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare13        = 19,
 119         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare12        = 20,
 120         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare11        = 21,
 121         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare10        = 22,
 122         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare9 = 23,
 123         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare8 = 24,
 124         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare7 = 25,
 125         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare6 = 26,
 126         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare5 = 27,
 127         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare4 = 28,
 128         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare3 = 29,
 129         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare2 = 30,
 130         DRX_ConfigRrc__drx_RetransmissionTimerDL_spare1 = 31
 131 } e_DRX_ConfigRrc__drx_RetransmissionTimerDL;
 132 typedef enum DRX_ConfigRrc__drx_RetransmissionTimerUL {
 133         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl0    = 0,
 134         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl1    = 1,
 135         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl2    = 2,
 136         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl4    = 3,
 137         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl6    = 4,
 138         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl8    = 5,
 139         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl16   = 6,
 140         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl24   = 7,
 141         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl33   = 8,
 142         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl40   = 9,
 143         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl64   = 10,
 144         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl80   = 11,
 145         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl96   = 12,
 146         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl112  = 13,
 147         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl128  = 14,
 148         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl160  = 15,
 149         DRX_ConfigRrc__drx_RetransmissionTimerUL_sl320  = 16,
 150         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare15        = 17,
 151         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare14        = 18,
 152         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare13        = 19,
 153         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare12        = 20,
 154         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare11        = 21,
 155         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare10        = 22,
 156         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare9 = 23,
 157         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare8 = 24,
 158         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare7 = 25,
 159         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare6 = 26,
 160         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare5 = 27,
 161         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare4 = 28,
 162         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare3 = 29,
 163         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare2 = 30,
 164         DRX_ConfigRrc__drx_RetransmissionTimerUL_spare1 = 31
 165 } e_DRX_ConfigRrc__drx_RetransmissionTimerUL;
 166 typedef enum DRX_ConfigRrc__drx_LongCycleStartOffset_PR {
 167         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_NOTHING,     /* No components present */
 168         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms10,
 169         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms20,
 170         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms32,
 171         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms40,
 172         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms60,
 173         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms64,
 174         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms70,
 175         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms80,
 176         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms128,
 177         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms160,
 178         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms256,
 179         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms320,
 180         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms512,
 181         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms640,
 182         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms1024,
 183         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms1280,
 184         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms2048,
 185         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms2560,
 186         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms5120,
 187         DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms10240
 188 } DRX_ConfigRrc__drx_LongCycleStartOffset_PR;
 189 typedef enum DRX_ConfigRrc__shortDRX__drx_ShortCycle {
 190         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms2     = 0,
 191         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms3     = 1,
 192         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms4     = 2,
 193         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms5     = 3,
 194         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms6     = 4,
 195         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms7     = 5,
 196         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms8     = 6,
 197         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms10    = 7,
 198         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms14    = 8,
 199         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms16    = 9,
 200         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms20    = 10,
 201         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms30    = 11,
 202         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms32    = 12,
 203         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms35    = 13,
 204         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms40    = 14,
 205         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms64    = 15,
 206         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms80    = 16,
 207         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms128   = 17,
 208         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms160   = 18,
 209         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms256   = 19,
 210         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms320   = 20,
 211         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms512   = 21,
 212         DRX_ConfigRrc__shortDRX__drx_ShortCycle_ms640   = 22,
 213         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare9  = 23,
 214         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare8  = 24,
 215         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare7  = 25,
 216         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare6  = 26,
 217         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare5  = 27,
 218         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare4  = 28,
 219         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare3  = 29,
 220         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare2  = 30,
 221         DRX_ConfigRrc__shortDRX__drx_ShortCycle_spare1  = 31
 222 } e_DRX_ConfigRrc__shortDRX__drx_ShortCycle;
 223
 224 /* DRX-ConfigRrc */
 225 typedef struct DRX_ConfigRrc {
 226         struct DRX_ConfigRrc__drx_onDurationTimer {
 227                 DRX_ConfigRrc__drx_onDurationTimer_PR present;
 228                 union DRX_ConfigRrc__drx_onDurationTimer_u {
 229                         long     subMilliSeconds;
 230                         long     milliSeconds;
 231                 } choice;
 232
 233                 /* Context for parsing across buffer boundaries */
 234                 asn_struct_ctx_t _asn_ctx;
 235         } drx_onDurationTimer;
 236         long     drx_InactivityTimer;
 237         long     drx_HARQ_RTT_TimerDL;
 238         long     drx_HARQ_RTT_TimerUL;
 239         long     drx_RetransmissionTimerDL;
 240         long     drx_RetransmissionTimerUL;
 241         struct DRX_ConfigRrc__drx_LongCycleStartOffset {
 242                 DRX_ConfigRrc__drx_LongCycleStartOffset_PR present;
 243                 union DRX_ConfigRrc__drx_LongCycleStartOffset_u {
 244                         long     ms10;
 245                         long     ms20;
 246                         long     ms32;
 247                         long     ms40;
 248                         long     ms60;
 249                         long     ms64;
 250                         long     ms70;
 251                         long     ms80;
 252                         long     ms128;
 253                         long     ms160;
 254                         long     ms256;
 255                         long     ms320;
 256                         long     ms512;
 257                         long     ms640;
 258                         long     ms1024;
 259                         long     ms1280;
 260                         long     ms2048;
 261                         long     ms2560;
 262                         long     ms5120;
 263                         long     ms10240;
 264                 } choice;
 265
 266                 /* Context for parsing across buffer boundaries */
 267                 asn_struct_ctx_t _asn_ctx;
 268         } drx_LongCycleStartOffset;
 269         struct DRX_ConfigRrc__shortDRX {
 270                 long     drx_ShortCycle;
 271                 long     drx_ShortCycleTimer;
 272
 273                 /* Context for parsing across buffer boundaries */
 274                 asn_struct_ctx_t _asn_ctx;
 275         } *shortDRX;
 276         long     drx_SlotOffset;
 277
 278         /* Context for parsing across buffer boundaries */
 279         asn_struct_ctx_t _asn_ctx;
 280 } DRX_ConfigRrc_t;
 281
 282 /* Implementation */
 283 /* extern asn_TYPE_descriptor_t asn_DEF_milliSeconds_4; // (Use -fall-defs-global to expose) */
 284 /* extern asn_TYPE_descriptor_t asn_DEF_drx_InactivityTimer_37; // (Use -fall-defs-global to expose) */
 285 /* extern asn_TYPE_descriptor_t asn_DEF_drx_RetransmissionTimerDL_72;   // (Use -fall-defs-global to expose) */
 286 /* extern asn_TYPE_descriptor_t asn_DEF_drx_RetransmissionTimerUL_105;  // (Use -fall-defs-global to expose) */
 287 /* extern asn_TYPE_descriptor_t asn_DEF_drx_ShortCycle_160;     // (Use -fall-defs-global to expose) */
 288 extern asn_TYPE_descriptor_t asn_DEF_DRX_ConfigRrc;
 289 extern asn_SEQUENCE_specifics_t asn_SPC_DRX_ConfigRrc_specs_1;
 290 extern asn_TYPE_member_t asn_MBR_DRX_ConfigRrc_1[9];
 291
 292 #ifdef __cplusplus
 293 }
 294 #endif
 295
 296 #endif  /* _DRX_ConfigRrc_H_ */
 297 #include <asn_internal.h>