1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define EVENT_SCH_GEN_CFG 1
21 #define EVENT_SCH_CELL_CFG 2
22 #define EVENT_SCH_CELL_CFG_CFM 3
23 #define EVENT_DL_SCH_INFO 4
24 #define EVENT_UL_SCH_INFO 5
25 #define EVENT_RACH_IND_TO_SCH 6
26 #define EVENT_CRC_IND_TO_SCH 7
27 #define EVENT_DL_RLC_BO_INFO_TO_SCH 8
28 #define EVENT_ADD_UE_CONFIG_REQ_TO_SCH 9
29 #define EVENT_UE_CONFIG_RSP_TO_MAC 10
30 #define EVENT_SLOT_IND_TO_SCH 11
31 #define EVENT_SHORT_BSR 12
32 #define EVENT_UCI_IND_TO_SCH 13
33 #define EVENT_MODIFY_UE_CONFIG_REQ_TO_SCH 14
34 #define EVENT_UE_RECONFIG_RSP_TO_MAC 15
35 #define EVENT_UE_DELETE_REQ_TO_SCH 16
36 #define EVENT_UE_DELETE_RSP_TO_MAC 17
37 #define EVENT_CELL_DELETE_REQ_TO_SCH 18
38 #define EVENT_CELL_DELETE_RSP_TO_MAC 19
39 #define EVENT_LONG_BSR 20
40 #define EVENT_SLICE_CFG_REQ_TO_SCH 21
41 #define EVENT_SLICE_CFG_RSP_TO_MAC 22
42 #define EVENT_SLICE_RECFG_REQ_TO_SCH 23
43 #define EVENT_SLICE_RECFG_RSP_TO_MAC 24
44 #define EVENT_RACH_RESOURCE_REQUEST_TO_SCH 25
45 #define EVENT_RACH_RESOURCE_RESPONSE_TO_MAC 26
46 #define EVENT_RACH_RESOURCE_RELEASE_TO_SCH 27
47 #define EVENT_PAGING_IND_TO_SCH 28
48 #define EVENT_DL_PAGING_ALLOC 29
49 #define EVENT_DL_REL_HQ_PROC 30
50 #define EVENT_DL_HARQ_IND_TO_SCH 31
52 #define MAX_SSB_IDX 1 /* forcing it as 1 for now. Right value is 64 */
53 #define SCH_SSB_MASK_SIZE 1
55 #define MAX_NUM_PRG 1 /* max value should be later 275 */
56 #define MAX_DIG_BF_INTERFACES 0 /* max value should be later 255 */
57 #define MAX_CODEWORDS 1 /* max should be 2 */
58 #define SCH_HARQ_PROC_ID 1 /* harq proc id */
59 #define SCH_ALLOC_TYPE_1 1 /*sch res alloc type */
61 /* Datatype in UL SCH Info */
62 #define SCH_DATATYPE_PUSCH 1
63 #define SCH_DATATYPE_PUSCH_UCI 2
64 #define SCH_DATATYPE_UCI 4
65 #define SCH_DATATYPE_SRS 8
66 #define SCH_DATATYPE_PRACH 16
68 #define MAX_NUMBER_OF_CRC_IND_BITS 1
69 #define MAX_NUMBER_OF_UCI_IND_BITS 1
70 #define MAX_SR_BITS_IN_BYTES 1
71 #define MAX_HARQ_BITS_IN_BYTES 1
72 #define MAX_NUM_LOGICAL_CHANNEL_GROUPS 8
73 #define MAX_NUM_SR_CFG_PER_CELL_GRP 8 /* Max number of scheduling request config per cell group */
74 #define MAX_NUM_TAGS 4 /* Max number of timing advance groups */
75 #define MAX_NUM_BWP 4 /* Max number of BWP per serving cell */
76 #define MAX_NUM_CRSET 3 /* Max number of control resource set in add/modify/release list */
77 #define MAX_NUM_SEARCH_SPC 10 /* Max number of search space in add/modify/release list */
78 #define FREQ_DOM_RSRC_SIZE 6 /* i.e. 6 bytes because Size of frequency domain resource is 45 bits */
79 #define MONITORING_SYMB_WITHIN_SLOT_SIZE 2 /* i.e. 2 bytes because size of monitoring symbols within slot is 14 bits */
80 #define MAX_NUM_DL_ALLOC 16 /* Max number of pdsch time domain downlink allocation */
81 #define MAX_NUM_UL_ALLOC 16 /* Max number of pusch time domain uplink allocation */
83 /* PUCCH Configuration Macro */
84 #define MAX_NUM_PUCCH_RESRC 128
85 #define MAX_NUM_PUCCH_RESRC_SET 4
86 #define MAX_NUM_PUCCH_PER_RESRC_SET 32
87 #define MAX_NUM_SPATIAL_RELATIONS 8
88 #define MAX_NUM_PUCCH_P0_PER_SET 8
89 #define MAX_NUM_PATH_LOSS_REF_RS 4
90 #define MAX_NUM_DL_DATA_TO_UL_ACK 15
91 #define QPSK_MODULATION 2
93 #define RAR_PAYLOAD_SIZE 10 /* As per spec 38.321, sections 6.1.5 and 6.2.3, RAR PDU is 8 bytes long and 2 bytes of padding */
94 #define TX_PAYLOAD_HDR_LEN 32 /* Intel L1 requires adding a 32 byte header to transmitted payload */
95 #define UL_TX_BUFFER_SIZE 5
97 #define MAX_NUM_CONFIG_SLOTS 160 /*Max number of slots as per the numerology*/
98 #define MAX_NUM_K0_IDX 16 /* Max number of pdsch time domain downlink allocation */
99 #define MAX_NUM_K1_IDX 8 /* As per spec 38.213 section 9.2.3 Max number of PDSCH-to-HARQ resource indication */
100 #define MIN_NUM_K1_IDX 4 /* Min K1 values */
101 #define MAX_NUM_K2_IDX 16 /* PUSCH time domain UL resource allocation list */
102 #define DEFAULT_K0_VALUE 0 /* As per 38.331, PDSCH-TimeDomainResourceAllocation field descriptions */
103 /* As per 38.331, PUSCH-TimeDomainResourceAllocationList field descriptions */
104 #define DEFAULT_K2_VALUE_FOR_SCS15 1
105 #define DEFAULT_K2_VALUE_FOR_SCS30 1
106 #define DEFAULT_K2_VALUE_FOR_SCS60 2
107 #define DEFAULT_K2_VALUE_FOR_SCS120 3
109 #define ADD_DELTA_TO_TIME(crntTime, toFill, incr, numOfSlot) \
111 if ((crntTime.slot + incr) > (numOfSlot - 1)) \
113 toFill.sfn = (crntTime.sfn + 1); \
117 toFill.sfn = crntTime.sfn; \
119 toFill.slot = (crntTime.slot + incr) % numOfSlot; \
120 if (toFill.sfn >= MAX_SFN) \
122 toFill.sfn%=MAX_SFN; \
130 RRC_CONNECTED_USERS_RSRC
150 RESOURCE_UNAVAILABLE,
187 TIME_ALIGNMENT_TIMER_MS500,
188 TIME_ALIGNMENT_TIMER_MS750,
189 TIME_ALIGNMENT_TIMER_MS1280,
190 TIME_ALIGNMENT_TIMER_MS1920,
191 TIME_ALIGNMENT_TIMER_MS2560,
192 TIME_ALIGNMENT_TIMER_MS5120,
193 TIME_ALIGNMENT_TIMER_MS10240,
194 TIME_ALIGNMENT_TIMER_INFINITE
195 }SchTimeAlignmentTimer;
199 PHR_PERIODIC_TIMER_SF10,
200 PHR_PERIODIC_TIMER_SF20,
201 PHR_PERIODIC_TIMER_SF50,
202 PHR_PERIODIC_TIMER_SF100,
203 PHR_PERIODIC_TIMER_SF200,
204 PHR_PERIODIC_TIMER_SF500,
205 PHR_PERIODIC_TIMER_SF1000,
206 PHR_PERIODIC_TIMER_INFINITE
207 }SchPhrPeriodicTimer;
211 PHR_PROHIBIT_TIMER_SF0,
212 PHR_PROHIBIT_TIMER_SF10,
213 PHR_PROHIBIT_TIMER_SF20,
214 PHR_PROHIBIT_TIMER_SF50,
215 PHR_PROHIBIT_TIMER_SF100,
216 PHR_PROHIBIT_TIMER_SF200,
217 PHR_PROHIBIT_TIMER_SF500,
218 PHR_PROHIBIT_TIMER_SF1000
219 }SchPhrProhibitTimer;
223 PHR_TX_PWR_FACTOR_CHANGE_DB1,
224 PHR_TX_PWR_FACTOR_CHANGE_DB3,
225 PHR_TX_PWR_FACTOR_CHANGE_DB6,
226 PHR_TX_PWR_FACTOR_CHANGE_INFINITE
227 }SchPhrTxPwrFactorChange;
237 HARQ_ACK_CODEBOOK_SEMISTATIC,
238 HARQ_ACK_CODEBOOK_DYNAMIC
239 }SchPdschHarqAckCodebook;
243 NUM_HARQ_PROC_FOR_PDSCH_N2,
244 NUM_HARQ_PROC_FOR_PDSCH_N4,
245 NUM_HARQ_PROC_FOR_PDSCH_N6,
246 NUM_HARQ_PROC_FOR_PDSCH_N10,
247 NUM_HARQ_PROC_FOR_PDSCH_N16
248 }SchNumHarqProcForPdsch;
252 MAX_CODE_BLOCK_GROUP_PER_TB_N2,
253 MAX_CODE_BLOCK_GROUP_PER_TB_N4,
254 MAX_CODE_BLOCK_GROUP_PER_TB_N6,
255 MAX_CODE_BLOCK_GROUP_PER_TB_N8
256 }SchMaxCodeBlkGrpPerTB;
260 PDSCH_X_OVERHEAD_XOH_6,
261 PDSCH_X_OVERHEAD_XOH_12,
262 PDSCH_X_OVERHEAD_XOH_18
267 DMRS_ADDITIONAL_POS0,
268 DMRS_ADDITIONAL_POS1,
270 }SchDmrsAdditionPosition;
274 RESOURCE_ALLOCTION_TYPE_0,
275 RESOURCE_ALLOCTION_TYPE_1,
276 RESOURCE_ALLOCTION_DYN_SWITCH
277 }SchResourceAllocType;
281 TIME_DOMAIN_RSRC_ALLOC_MAPPING_TYPE_A,
282 TIME_DOMAIN_RSRC_ALLOC_MAPPING_TYPE_B
283 }SchTimeDomRsrcAllocMappingType;
287 ENABLED_TRANSFORM_PRECODER,
288 DISABLED_TRANSFORM_PRECODER
289 }SchTransformPrecoder;
293 INTERLEAVED_CCE_REG_MAPPING = 1,
294 NONINTERLEAVED_CCE_REG_MAPPING
299 SLOT_PERIODICITY_AND_OFFSET_SL_1 = 1,
300 SLOT_PERIODICITY_AND_OFFSET_SL_2,
301 SLOT_PERIODICITY_AND_OFFSET_SL_4,
302 SLOT_PERIODICITY_AND_OFFSET_SL_5,
303 SLOT_PERIODICITY_AND_OFFSET_SL_8,
304 SLOT_PERIODICITY_AND_OFFSET_SL_10,
305 SLOT_PERIODICITY_AND_OFFSET_SL_16,
306 SLOT_PERIODICITY_AND_OFFSET_SL_20,
307 SLOT_PERIODICITY_AND_OFFSET_SL_40,
308 SLOT_PERIODICITY_AND_OFFSET_SL_80,
309 SLOT_PERIODICITY_AND_OFFSET_SL_160,
310 SLOT_PERIODICITY_AND_OFFSET_SL_320,
311 SLOT_PERIODICITY_AND_OFFSET_SL_640,
312 SLOT_PERIODICITY_AND_OFFSET_SL_1280,
313 SLOT_PERIODICITY_AND_OFFSET_SL_2560
314 }SchMSlotPeriodAndOffset;
324 SEARCH_SPACE_TYPE_COMMON = 1,
325 SEARCH_SPACE_TYPE_UE_SPECIFIC
330 SCH_QOS_NON_DYNAMIC = 1,
336 AGGREGATION_LEVEL_N0,
337 AGGREGATION_LEVEL_N1,
338 AGGREGATION_LEVEL_N2,
339 AGGREGATION_LEVEL_N3,
340 AGGREGATION_LEVEL_N4,
341 AGGREGATION_LEVEL_N5,
342 AGGREGATION_LEVEL_N6,
354 CODE_WORDS_SCHED_BY_DCI_N1,
355 CODE_WORDS_SCHED_BY_DCI_N2
356 }SchCodeWordsSchedByDci;
360 STATIC_BUNDLING_TYPE = 1,
361 DYNAMIC_BUNDLING_TYPE
367 SCH_SET1_SIZE_WIDEBAND,
368 SCH_SET1_SIZE_N2_WIDEBAND,
369 SCH_SET1_SIZE_N4_WIDEBAND
370 }SchBundlingSizeSet1;
375 SCH_SET2_SIZE_WIDEBAND
376 }SchBundlingSizeSet2;
418 SCH_MCS_TABLE_QAM_64,
419 SCH_MCS_TABLE_QAM_256,
420 SCH_MCS_TABLE_QAM_64_LOW_SE
433 DATA_TRANSMISSION_ALLOWED,
434 STOP_DATA_TRANSMISSION,
435 RESTART_DATA_TRANSMISSION
436 }SchDataTransmission;
439 typedef struct timeDomainAlloc
445 typedef struct resAllocType0
447 uint8_t rbBitmap[36];
450 typedef struct resAllocType1
456 typedef struct resAllocType1 FreqDomainRsrc;
460 uint32_t ssbPbchPwr; /* SSB block power */
461 uint8_t scsCommon; /* subcarrier spacing for common [0-3]*/
462 uint8_t ssbOffsetPointA; /* SSB sub carrier offset from point A */
463 SchSSBPeriod ssbPeriod; /* SSB Periodicity in msec */
464 uint8_t ssbSubcOffset; /* Subcarrier Offset(Kssb) */
465 uint32_t nSSBMask[SCH_SSB_MASK_SIZE]; /* Bitmap for actually transmitted SSB. */
467 /*Ref:Spec 38.331 "ssb-PositionsInBurst", Value 0 in Bitmap => corresponding SS/PBCH block is not transmitted
468 *value 1 => corresponding SS/PBCH block is transmitted*/
469 uint8_t totNumSsb; /*S = Total Number of Actual SSB transmitted*/
472 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-32 BWP Information */
473 typedef struct bwpCfg
475 uint8_t subcarrierSpacing;
476 uint8_t cyclicPrefix;
477 FreqDomainRsrc freqAlloc;
483 uint16_t beamIdx[MAX_DIG_BF_INTERFACES];
486 typedef struct beamformingInfo
490 uint8_t digBfInterfaces;
491 Prg prg[MAX_NUM_PRG];
494 /* SIB1 PDSCH structures */
496 typedef struct codewordinfo
498 uint16_t targetCodeRate;
506 typedef struct dmrsInfo
508 uint16_t dlDmrsSymbPos;
509 uint8_t dmrsConfigType;
510 uint16_t dlDmrsScramblingId;
512 uint8_t numDmrsCdmGrpsNoData;
515 uint8_t nrOfDmrsSymbols;
519 typedef struct pdschFreqAlloc
521 uint8_t resourceAllocType;
522 /* since we are using type-1, rbBitmap excluded */
523 uint8_t rbBitmap[36];
526 uint8_t vrbPrbMapping;
529 typedef struct pdschTimeAlloc
536 typedef struct txPowerPdschInfo
538 uint8_t powerControlOffset;
539 uint8_t powerControlOffsetSS;
542 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-43 PDSCH Configuration */
543 typedef struct pdschCfg
548 uint8_t numCodewords;
549 CodewordInfo codeword[MAX_CODEWORDS];
550 uint16_t dataScramblingId;
552 uint8_t transmissionScheme;
555 PdschFreqAlloc pdschFreqAlloc;
556 PdschTimeAlloc pdschTimeAlloc;
557 BeamformingInfo beamPdschInfo;
558 TxPowerPdschInfo txPdschPower;
560 /* SIB1 PDSCH structures end */
562 /* SIB1 interface structure */
564 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-35 CORESET Configuration */
565 typedef struct coresetCfg
568 uint8_t startSymbolIndex;
569 uint8_t durationSymbols;
570 uint8_t freqDomainResource[6];
571 uint8_t cceRegMappingType;
572 uint8_t regBundleSize;
573 uint8_t interleaverSize;
576 uint8_t coresetPoolIndex;
577 uint8_t precoderGranularity;
579 uint8_t aggregationLevel;
582 typedef struct txPowerPdcchInfo
584 uint8_t beta_pdcch_1_0;
585 uint8_t powerControlOffsetSS;
588 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-42 DL-DCI Configuration */
592 uint16_t scramblingId;
593 uint16_t scramblingRnti;
596 BeamformingInfo beamPdcchInfo;
597 TxPowerPdcchInfo txPdcchPower;
601 typedef struct pdcchCfg
603 /* coreset-0 configuration */
604 CoresetCfg coresetCfg;
606 DlDCI dci; /* as of now its only one DCI, later it will be numDlCi */
608 /* end of SIB1 PDCCH structures */
610 typedef struct pageCfg
612 uint8_t numPO; /*Derived from Ns*/
613 bool poPresent; /*FirstPDCCH-MonitoringPO is present or not*/
614 uint16_t pagingOcc[MAX_PO_PER_PF]; /*FirstPDCCH-Monitoring Paging Occasion*/
619 /* parameters recieved from DU-APP */
621 uint16_t sib1RepetitionPeriod;
622 uint8_t coresetZeroIndex; /* derived from 4 LSB of pdcchSib1 present in MIB */
623 uint8_t searchSpaceZeroIndex; /* derived from 4 MSB of pdcchSib1 present in MIB */
626 /* parameters derived in scheduler */
629 PdcchCfg sib1PdcchCfg;
630 PageCfg pageCfg; /*Config of Paging*/
633 typedef struct schRachCfg
635 uint8_t prachCfgIdx; /* PRACH config idx */
636 uint8_t prachSubcSpacing; /* Subcarrier spacing of RACH */
637 uint16_t msg1FreqStart; /* Msg1-FrequencyStart */
638 uint8_t msg1Fdm; /* PRACH FDM (1,2,4,8) */
639 uint8_t rootSeqLen; /* root sequence length */
640 uint16_t rootSeqIdx; /* Root sequence index */
641 uint8_t numRootSeq; /* Number of root sequences required for FD */
642 uint16_t k1; /* Frequency Offset for each FD */
643 uint8_t totalNumRaPreamble; /* Total number of RA preambles */
644 uint8_t ssbPerRach; /* SSB per RACH occassion */
645 uint8_t numCbPreamblePerSsb; /* Number of CB preamble per SSB */
646 uint8_t prachMultCarrBand; /* Presence of Multiple carriers in Band */
647 uint8_t raContResTmr; /* RA Contention Resoultion Timer */
648 uint8_t rsrpThreshSsb; /* RSRP Threshold SSB */
649 uint8_t raRspWindow; /* RA Response Window */
650 uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
653 typedef struct schBwpParams
655 FreqDomainRsrc freqAlloc;
657 uint8_t cyclicPrefix;
660 typedef struct schCandidatesInfo
669 typedef struct schSearchSpaceCfg
671 uint8_t searchSpaceId;
673 uint8_t freqDomainRsrc[FREQ_DOM_RSRC_SIZE]; /* Frequency domain resource */
674 uint16_t monitoringSlot;
676 uint16_t monitoringSymbol;
677 SchCandidatesInfo candidate;
680 typedef struct schPdcchCfgCmn
682 SchSearchSpaceCfg commonSearchSpace;
683 uint8_t raSearchSpaceId;
686 typedef struct schPdschCfgCmnTimeDomRsrcAlloc
691 uint8_t lengthSymbol;
692 }SchPdschCfgCmnTimeDomRsrcAlloc;
694 typedef struct schPdschCfgCmn
696 uint8_t numTimeDomAlloc;
697 SchPdschCfgCmnTimeDomRsrcAlloc timeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
700 typedef struct schPucchCfgCmn
702 uint8_t pucchResourceCommon;
703 uint8_t pucchGroupHopping;
706 /* PUSCH Time Domain Resource Allocation */
707 typedef struct schPuschTimeDomRsrcAlloc
710 SchTimeDomRsrcAllocMappingType mappingType;
712 uint8_t symbolLength;
713 }SchPuschTimeDomRsrcAlloc;
715 typedef struct schPuschCfgCmn
717 uint8_t numTimeDomRsrcAlloc;
718 SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[MAX_NUM_UL_ALLOC]; /* PUSCH time domain UL resource allocation list */
721 typedef struct schK1TimingInfo
724 uint8_t k1Indexes[MAX_NUM_K1_IDX];
727 typedef struct schK0TimingInfo
730 SchK1TimingInfo k1TimingInfo;
733 typedef struct schK0K1TimingInfo
736 SchK0TimingInfo k0Indexes[MAX_NUM_K0_IDX];
739 typedef struct schK0K1TimingInfoTbl
742 SchK0K1TimingInfo k0k1TimingInfo[MAX_NUM_CONFIG_SLOTS];
743 }SchK0K1TimingInfoTbl;
745 typedef struct schBwpDlCfg
748 SchPdcchCfgCmn pdcchCommon;
749 SchPdschCfgCmn pdschCommon;
750 SchK0K1TimingInfoTbl k0K1InfoTbl;
753 typedef struct schK2TimingInfo
756 uint8_t k2Indexes[MAX_NUM_K2_IDX];
759 typedef struct schK2TimingInfoTbl
762 SchK2TimingInfo k2TimingInfo[MAX_NUM_CONFIG_SLOTS];
765 typedef struct schBwpUlCfg
768 SchPucchCfgCmn pucchCommon;
769 SchPuschCfgCmn puschCommon;
770 SchK2TimingInfoTbl msg3K2InfoTbl;
771 SchK2TimingInfoTbl k2InfoTbl;
774 typedef struct schPlmnInfoList
777 uint8_t numSliceSupport; /* Total slice supporting */
778 Snssai **snssai; /* List of supporting snssai*/
781 typedef struct schHqCfgParam
783 uint8_t maxDlDataHqTx;
785 uint8_t maxUlDataHqTx;
789 /* The following list of structures is taken from the DRX-Config section of specification 33.331. */
791 typedef struct schDrxOnDurationTimer
793 bool onDurationTimerValInMs;
796 uint8_t subMilliSeconds;
797 uint16_t milliSeconds;
798 }onDurationtimerValue;
799 }SchDrxOnDurationTimer;
801 typedef struct schDrxLongCycleStartOffset
803 uint16_t drxLongCycleStartOffsetChoice;
804 uint16_t drxLongCycleStartOffsetVal;
805 }SchDrxLongCycleStartOffset;
807 typedef struct schShortDrx
809 uint16_t drxShortCycle;
810 uint8_t drxShortCycleTimer;
813 typedef struct schDrxCfg
815 SchDrxOnDurationTimer drxOnDurationTimer;
816 uint16_t drxInactivityTimer;
817 uint8_t drxHarqRttTimerDl;
818 uint8_t drxHarqRttTimerUl;
819 uint16_t drxRetransmissionTimerDl;
820 uint16_t drxRetransmissionTimerUl;
821 SchDrxLongCycleStartOffset drxLongCycleStartOffset;
823 SchShortDrx shortDrx;
824 uint8_t drxSlotOffset;
828 typedef struct schCellCfg
830 uint16_t cellId; /* Cell Id */
831 uint16_t phyCellId; /* Physical cell id */
832 uint8_t numerology; /* Supported numerology */
833 SchDuplexMode dupMode; /* Duplex type: TDD/FDD */
834 uint8_t bandwidth; /* Supported B/W */
835 uint32_t dlFreq; /* DL Frequency */
836 uint32_t ulFreq; /* UL Frequency */
837 SchSsbCfg ssbSchCfg; /* SSB config */
838 SchSib1Cfg sib1SchCfg; /* SIB1 config */
839 SchRachCfg schRachCfg; /* PRACH config */
840 SchBwpDlCfg schInitialDlBwp; /* Initial DL BWP */
841 SchBwpUlCfg schInitialUlBwp; /* Initial UL BWP */
842 SchPlmnInfoList plmnInfoList; /* Consits of PlmnId and Snssai list */
845 TDDCfg tddCfg; /* TDD Cfg */
849 typedef struct schCellCfgCfm
851 uint16_t cellId; /* Cell Id */
853 SchFailureCause cause;
856 typedef struct ssbInfo
858 uint8_t ssbIdx; /* SSB Index */
859 TimeDomainAlloc tdAlloc; /* Time domain allocation */
860 FreqDomainRsrc fdAlloc; /* Freq domain allocation */
863 typedef struct sib1AllocInfo
866 PdcchCfg sib1PdcchCfg;
869 typedef struct prachSchInfo
871 uint8_t numPrachOcas; /* Num Prach Ocassions */
872 uint8_t prachFormat; /* PRACH Format */
873 uint8_t numRa; /* Freq domain ocassion */
874 uint8_t prachStartSymb; /* Freq domain ocassion */
877 /* Interface structure signifying DL broadcast allocation for SSB, SIB1 */
878 typedef struct dlBrdcstAlloc
880 uint16_t crnti; /* SI-RNTI */
881 /* Ssb transmission is determined as follows:
882 * 0 : No tranamission
883 * 1 : SSB Transmission
884 * 2 : SSB Repetition */
885 uint8_t ssbTransmissionMode;
886 uint8_t ssbIdxSupported;
887 SsbInfo ssbInfo[MAX_SSB_IDX];
888 bool systemInfoIndicator;
890 /* Sib1 transmission is determined as follows:
891 * 0 : No tranamission
892 * 1 : SIB1 Transmission
893 * 2 : SIB1 Repetition */
894 uint8_t sib1TransmissionMode;
895 Sib1AllocInfo sib1Alloc;
898 typedef struct msg3UlGrant
902 FreqDomainRsrc msg3FreqAlloc;
909 typedef struct rarInfo
916 uint8_t rarPdu[RAR_PAYLOAD_SIZE];
920 typedef struct rarAlloc
926 PdcchCfg rarPdcchCfg;
927 PdschCfg rarPdschCfg;
930 typedef struct dlMsgInfo
938 uint8_t harqFeedbackInd;
941 uint16_t dlMsgPduLen;
945 typedef struct lcSchInfo
948 uint32_t schBytes; /* Number of scheduled bytes */
951 typedef struct dlMsgSchedInfo
955 LcSchInfo lcSchInfo[MAX_NUM_LC]; /* Scheduled LC info */
957 PdcchCfg dlMsgPdcchCfg;
958 PdschCfg dlMsgPdschCfg;
964 typedef struct dlMsgAlloc
967 uint8_t numSchedInfo;
968 DlMsgSchInfo dlMsgSchedInfo[2];
971 typedef struct schSlotValue
973 SlotTimingInfo currentTime;
974 SlotTimingInfo broadcastTime;
975 SlotTimingInfo rarTime;
976 SlotTimingInfo dlMsgTime;
977 SlotTimingInfo ulDciTime;
980 typedef struct freqDomainAlloc
982 uint8_t resAllocType; /* Resource allocation type */
990 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-36 DCI Format0_0 Configuration */
991 typedef struct format0_0
993 uint8_t resourceAllocType;
994 FreqDomainAlloc freqAlloc;
995 TimeDomainAlloc timeAlloc;
1006 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-40 DCI Format 0_1 Configuration */
1007 typedef struct format0_1
1009 uint8_t carrierIndicator;
1011 uint8_t bwpIndicator;
1012 uint8_t resourceAlloc;
1013 FreqDomainRsrc freqAlloc;
1014 TimeDomainAlloc timeAlloc;
1021 uint8_t firstDownlinkAssignmentIndex;
1022 uint8_t secondDownlinkAssignmentIndex;
1024 uint8_t srsResourceSetIndicator;
1025 uint8_t srsResourceIndicator;
1027 uint8_t antennaPorts;
1030 uint8_t cbgTransmissionInfo;
1032 uint8_t betaOffsetIndicator;
1033 bool dmrsSequenceInitialization;
1034 bool ulschIndicatior;
1037 typedef struct dciFormat
1039 FormatType formatType; /* DCI Format */
1042 Format0_0 format0_0; /* Format 0_0 */
1043 Format0_1 format0_1; /* Format 0_1 */
1047 typedef struct dciInfo
1049 uint16_t crnti; /* CRNTI */
1050 BwpCfg bwpCfg; /* BWP Cfg */
1051 CoresetCfg coresetCfg; /* Coreset1 Cfg */
1052 DciFormat dciFormatInfo; /* Dci Format */
1053 DlDCI dciInfo; /* DlDCI */
1057 /* Reference -> O-RAN.WG8.AAD.0-v07.00, Section 11.2.4.3.8 DL Scheduling Information */
1058 typedef struct dlSchedInfo
1060 uint16_t cellId; /* Cell Id */
1061 SchSlotValue schSlotValue;
1063 /* Allocation for broadcast messages */
1064 bool isBroadcastPres;
1065 DlBrdcstAlloc brdcstAlloc;
1067 /* Allocation for RAR message */
1068 RarAlloc *rarAlloc[MAX_NUM_UE];
1070 /* UL grant in response to BSR */
1073 /* Allocation from dedicated DL msg */
1074 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE];
1078 typedef struct dlPageAlloc
1081 SlotTimingInfo dlPageTime;
1086 PdcchCfg pagePdcchCfg;
1087 PdschCfg pagePdschCfg;
1088 uint16_t dlPagePduLen;
1092 typedef struct tbInfo
1094 uint8_t mcs; /* MCS */
1095 uint8_t ndi; /* NDI */
1096 uint8_t rv; /* Redundancy Version */
1097 uint16_t tbSize; /* TB Size */
1098 uint8_t qamOrder; /* Modulation Order */
1099 SchMcsTable mcsTable; /* MCS Table */
1102 typedef struct schPuschInfo
1104 uint8_t harqProcId; /* HARQ Process ID */
1105 FreqDomainAlloc fdAlloc; /* Freq domain allocation */
1106 TimeDomainAlloc tdAlloc; /* Time domain allocation */
1107 TbInfo tbInfo; /* TB info */
1109 uint8_t dmrsMappingType;
1110 uint8_t nrOfDmrsSymbols;
1115 typedef struct harqInfo
1117 uint16_t harqAckBitLength;
1118 uint8_t betaOffsetHarqAck;
1121 typedef struct csiInfo
1124 uint8_t betaOffsetCsi;
1127 typedef struct harqAckInfo
1129 uint16_t harqBitLength;
1132 typedef struct csiPartInfo
1137 typedef struct schPucchFormatCfg
1139 uint8_t interSlotFreqHop;
1141 uint8_t maxCodeRate;
1147 typedef struct schPucchInfo
1149 FreqDomainAlloc fdAlloc;
1150 TimeDomainAlloc tdAlloc;
1152 HarqFdbkInfo harqInfo;
1153 csiFdbkInfo csiInfo;
1154 BeamformingInfo beamPucchInfo;
1155 uint8_t pucchFormat;
1156 uint8_t intraFreqHop;
1157 uint16_t secondPrbHop;
1158 uint8_t initialCyclicShift;
1166 typedef struct schPuschUci
1168 uint8_t harqProcId; /* HARQ Process ID */
1169 FreqDomainAlloc fdAlloc; /* Freq domain allocation */
1170 TimeDomainAlloc tdAlloc; /* Time domain allocation */
1171 TbInfo tbInfo; /* TB information */
1172 HarqInfo harqInfo; /* Harq Information */
1173 CsiInfo csiInfo; /* Csi information*/
1176 typedef struct ulSchedInfo
1178 uint16_t cellId; /* Cell Id */
1179 uint16_t crnti; /* CRNI */
1180 SlotTimingInfo slotIndInfo; /* Slot Info: sfn, slot number */
1181 uint8_t dataType; /* Type of info being scheduled */
1182 SchPrachInfo prachSchInfo; /* Prach scheduling info */
1183 SchPuschInfo schPuschInfo; /* Pusch scheduling info */
1184 SchPuschUci schPuschUci; /* Pusch Uci */
1185 SchPucchInfo schPucchInfo; /* Pucch and Uci scheduling info */
1188 typedef struct rachIndInfo
1192 SlotTimingInfo timingInfo;
1196 uint8_t preambleIdx;
1201 typedef struct crcIndInfo
1205 SlotTimingInfo timingInfo;
1207 uint8_t crcInd[MAX_NUMBER_OF_CRC_IND_BITS];
1210 typedef struct boInfo
1213 uint32_t dataVolume;
1216 typedef struct dlRlcBOInfo
1221 uint32_t dataVolume;
1224 /* Info of Scheduling Request to Add/Modify */
1225 typedef struct schSchedReqInfo
1228 SchSrProhibitTimer srProhibitTmr;
1229 SchSrTransMax srTransMax;
1232 /* Scheduling Request Configuration */
1233 typedef struct schSchedReqCfg
1235 uint8_t addModListCount;
1236 SchSchedReqInfo addModList[MAX_NUM_SR_CFG_PER_CELL_GRP]; /* List of Scheduling req to be added/modified */
1237 uint8_t relListCount;
1238 uint8_t relList[MAX_NUM_SR_CFG_PER_CELL_GRP]; /* list of scheduling request Id to be deleted */
1241 /* Info of Tag to Add/Modify */
1242 typedef struct schTagInfo
1245 SchTimeAlignmentTimer timeAlignmentTmr;
1248 /* Timing Advance Group Configuration */
1249 typedef struct schTagCfg
1251 uint8_t addModListCount;
1252 SchTagInfo addModList[MAX_NUM_TAGS]; /* List of Tag to Add/Modify */
1253 uint8_t relListCount;
1254 uint8_t relList[MAX_NUM_TAGS]; /* list of Tag Id to release */
1257 /* Configuration for Power headroom reporting */
1258 typedef struct schPhrCfg
1260 SchPhrPeriodicTimer periodicTmr;
1261 SchPhrProhibitTimer prohibitTmr;
1262 SchPhrTxPwrFactorChange txpowerFactorChange;
1265 bool type2OtherCell;
1266 SchPhrModeOtherCG modeOtherCG;
1269 /* MAC cell Group configuration */
1270 typedef struct schMacCellGrpCfg
1272 SchSchedReqCfg schedReqCfg;
1274 SchPhrCfg phrCfg; /* To be used only if phrCfgSetupPres is true */
1277 SchDrxCfg drxCfg; /* Drx configuration */
1281 /* Physical Cell Group Configuration */
1282 typedef struct schPhyCellGrpCfg
1284 SchPdschHarqAckCodebook pdschHarqAckCodebook;
1288 /* Control resource set info */
1289 typedef struct schControlRsrcSet
1291 uint8_t cRSetId; /* Control resource set id */
1292 uint8_t freqDomainRsrc[FREQ_DOM_RSRC_SIZE]; /* Frequency domain resource */
1294 SchREGMappingType cceRegMappingType;
1295 SchPrecoderGranul precoderGranularity;
1296 uint16_t dmrsScramblingId;
1299 /* Search Space info */
1300 typedef struct schSearchSpace
1302 uint8_t searchSpaceId;
1304 SchMSlotPeriodAndOffset mSlotPeriodicityAndOffset;
1305 uint8_t mSymbolsWithinSlot[MONITORING_SYMB_WITHIN_SLOT_SIZE];
1306 SchAggrLevel numCandidatesAggLevel1; /* Number of candidates for aggregation level 1 */
1307 SchAggrLevel numCandidatesAggLevel2; /* Number of candidates for aggregation level 2 */
1308 SchAggrLevel numCandidatesAggLevel4; /* Number of candidates for aggregation level 4 */
1309 SchAggrLevel numCandidatesAggLevel8; /* Number of candidates for aggregation level 8 */
1310 SchAggrLevel numCandidatesAggLevel16; /* Number of candidates for aggregation level 16 */
1311 SchSearchSpaceType searchSpaceType;
1312 uint8_t ueSpecificDciFormat;
1315 /* PDCCH cofniguration */
1316 typedef struct schPdcchConfig
1318 uint8_t numCRsetToAddMod;
1319 SchControlRsrcSet cRSetToAddModList[MAX_NUM_CRSET]; /* List of control resource set to add/modify */
1320 uint8_t numCRsetToRel;
1321 uint8_t cRSetToRelList[MAX_NUM_CRSET]; /* List of control resource set to release */
1322 uint8_t numSearchSpcToAddMod;
1323 SchSearchSpace searchSpcToAddModList[MAX_NUM_SEARCH_SPC]; /* List of search space to add/modify */
1324 uint8_t numSearchSpcToRel;
1325 uint8_t searchSpcToRelList[MAX_NUM_SEARCH_SPC]; /* List of search space to release */
1328 /* PDSCH time domain resource allocation */
1329 typedef struct schPdschTimeDomRsrcAlloc
1332 SchTimeDomRsrcAllocMappingType mappingType;
1333 uint8_t startSymbol;
1334 uint8_t symbolLength;
1335 }SchPdschTimeDomRsrcAlloc;
1338 typedef struct schPdschBundling
1340 struct schStaticBundling
1342 SchBundlingSizeSet2 size;
1344 struct schDynamicBundling
1346 SchBundlingSizeSet1 sizeSet1;
1347 SchBundlingSizeSet2 sizeSet2;
1348 }SchDynamicBundling;
1351 /* DMRS downlink configuration */
1352 typedef struct schDmrsDlCfg
1354 SchDmrsAdditionPosition addPos; /* DMRS additional position */
1357 /* PDSCH Configuration */
1358 typedef struct schPdschConfig
1360 SchDmrsDlCfg dmrsDlCfgForPdschMapTypeA;
1361 SchResourceAllocType resourceAllocType;
1362 uint8_t numTimeDomRsrcAlloc;
1363 SchPdschTimeDomRsrcAlloc timeDomRsrcAllociList[MAX_NUM_DL_ALLOC]; /* PDSCH time domain DL resource allocation list */
1365 SchCodeWordsSchedByDci numCodeWordsSchByDci; /* Number of code words scheduled by DCI */
1366 SchBundlingType bundlingType;
1367 SchPdschBundling bundlingInfo;
1370 /* Initial Downlink BWP */
1371 typedef struct schInitalDlBwp
1374 SchPdcchConfig pdcchCfg;
1376 SchPdschConfig pdschCfg;
1378 SchK0K1TimingInfoTbl k0K1InfoTbl;
1381 /* BWP Downlink common */
1382 typedef struct schBwpDlCommon
1386 /* Downlink BWP information */
1387 typedef struct schDlBwpInfo
1392 /* PDCCH Serving Cell configuration */
1393 typedef struct schPdschServCellCfg
1395 uint8_t *maxMimoLayers;
1396 SchNumHarqProcForPdsch numHarqProcForPdsch;
1397 SchMaxCodeBlkGrpPerTB *maxCodeBlkGrpPerTb;
1398 bool *codeBlkGrpFlushInd;
1399 SchPdschXOverhead *xOverhead;
1400 }SchPdschServCellCfg;
1402 /* PUCCH Configuration */
1403 typedef struct schPucchResrcSetInfo
1406 uint8_t resrcListCount;
1407 uint8_t resrcList[MAX_NUM_PUCCH_PER_RESRC_SET];
1408 uint8_t maxPayLoadSize;
1409 }SchPucchResrcSetInfo;
1411 typedef struct schPucchResrcSetCfg
1413 uint8_t resrcSetToAddModListCount;
1414 SchPucchResrcSetInfo resrcSetToAddModList[MAX_NUM_PUCCH_RESRC_SET];
1415 uint8_t resrcSetToRelListCount;
1416 uint8_t resrcSetToRelList[MAX_NUM_PUCCH_RESRC];
1417 }SchPucchResrcSetCfg;
1419 typedef struct schPucchFormat0
1421 uint8_t initialCyclicShift;
1423 uint8_t startSymbolIdx;
1426 typedef struct schPucchFormat1
1428 uint8_t initialCyclicShift;
1430 uint8_t startSymbolIdx;
1434 typedef struct schPucchFormat2_3
1438 uint8_t startSymbolIdx;
1441 typedef struct schPucchFormat4
1446 uint8_t startSymbolIdx;
1449 typedef struct schPucchResrcInfo
1453 uint8_t intraFreqHop;
1454 uint16_t secondPrbHop;
1455 uint8_t pucchFormat;
1457 SchPucchFormat0 *format0;
1458 SchPucchFormat1 *format1;
1459 SchPucchFormat2_3 *format2;
1460 SchPucchFormat2_3 *format3;
1461 SchPucchFormat4 *format4;
1465 typedef struct schPucchResrcCfg
1467 uint8_t resrcToAddModListCount;
1468 SchPucchResrcInfo resrcToAddModList[MAX_NUM_PUCCH_RESRC];
1469 uint8_t resrcToRelListCount;
1470 uint8_t resrcToRelList[MAX_NUM_PUCCH_RESRC];
1474 typedef struct schSchedReqResrcInfo
1478 uint8_t periodicity;
1481 }SchSchedReqResrcInfo;
1483 typedef struct schPucchSchedReqCfg
1485 uint8_t schedAddModListCount;
1486 SchSchedReqResrcInfo schedAddModList[MAX_NUM_SR_CFG_PER_CELL_GRP];
1487 uint8_t schedRelListCount;
1488 uint8_t schedRelList[MAX_NUM_SR_CFG_PER_CELL_GRP];
1489 }SchPucchSchedReqCfg;
1491 typedef struct schSpatialRelationInfo
1493 uint8_t spatialRelationId;
1494 uint8_t servCellIdx;
1495 uint8_t pathLossRefRSId;
1497 uint8_t closeLoopIdx;
1498 }SchSpatialRelationInfo;
1500 typedef struct schPucchSpatialCfg
1502 uint8_t spatialAddModListCount;
1503 SchSpatialRelationInfo spatialAddModList[MAX_NUM_SPATIAL_RELATIONS];
1504 uint8_t spatialRelListCount;
1505 uint8_t spatialRelList[MAX_NUM_SPATIAL_RELATIONS];
1506 }SchPucchSpatialCfg;
1508 typedef struct schP0PucchCfg
1514 typedef struct schPathLossRefRSCfg
1516 uint8_t pathLossRefRSId;
1517 }SchPathLossRefRSCfg;
1519 typedef struct schPucchMultiCsiCfg
1521 uint8_t multiCsiResrcListCount;
1522 uint8_t multiCsiResrcList[MAX_NUM_PUCCH_RESRC-1];
1523 }SchPucchMultiCsiCfg;
1525 typedef struct schPucchDlDataToUlAck
1527 uint8_t dlDataToUlAckListCount;
1528 uint8_t dlDataToUlAckList[MAX_NUM_DL_DATA_TO_UL_ACK];
1529 }SchPucchDlDataToUlAck;
1531 typedef struct schPucchPowerControl
1539 SchP0PucchCfg p0Set[MAX_NUM_PUCCH_P0_PER_SET];
1540 uint8_t pathLossRefRSListCount;
1541 SchPathLossRefRSCfg pathLossRefRSList[MAX_NUM_PATH_LOSS_REF_RS];
1542 }SchPucchPowerControl;
1544 typedef struct schPucchCfg
1546 SchPucchResrcSetCfg *resrcSet;
1547 SchPucchResrcCfg *resrc;
1548 SchPucchFormatCfg *format1;
1549 SchPucchFormatCfg *format2;
1550 SchPucchFormatCfg *format3;
1551 SchPucchFormatCfg *format4;
1552 SchPucchSchedReqCfg *schedReq;
1553 SchPucchMultiCsiCfg *multiCsiCfg;
1554 SchPucchSpatialCfg *spatialInfo;
1555 SchPucchDlDataToUlAck *dlDataToUlAck;
1556 SchPucchPowerControl *powerControl;
1559 /* Transform precoding disabled */
1560 typedef struct schTransPrecodDisabled
1562 uint16_t scramblingId0;
1563 }SchTransPrecodDisabled;
1565 /* DMRS Uplink configuration */
1566 typedef struct SchDmrsUlCfg
1568 SchDmrsAdditionPosition addPos; /* DMRS additional position */
1569 SchTransPrecodDisabled transPrecodDisabled; /* Transform precoding disabled */
1572 /* PUSCH Configuration */
1573 typedef struct schPuschCfg
1575 uint8_t dataScramblingId;
1576 SchDmrsUlCfg dmrsUlCfgForPuschMapTypeA;
1577 SchResourceAllocType resourceAllocType;
1578 uint8_t numTimeDomRsrcAlloc;
1579 SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[MAX_NUM_UL_ALLOC]; /* PUSCH time domain UL resource allocation list */
1580 SchTransformPrecoder transformPrecoder;
1583 /* Initial Uplink BWP */
1584 typedef struct schInitialUlBwp
1587 SchPucchCfg pucchCfg;
1589 SchPuschCfg puschCfg;
1591 SchK2TimingInfoTbl k2InfoTbl;
1594 /* Uplink BWP information */
1595 typedef struct schUlBwpInfo
1600 /* Serving cell configuration */
1601 typedef struct schServCellRecfgInfo
1603 SchInitalDlBwp initDlBwp;
1604 uint8_t numDlBwpToAddOrMod;
1605 SchDlBwpInfo dlBwpToAddOrModList[MAX_NUM_BWP];
1606 uint8_t numDlBwpToRel;
1607 SchDlBwpInfo dlBwpToRelList[MAX_NUM_BWP];
1608 uint8_t firstActvDlBwpId;
1609 uint8_t defaultDlBwpId;
1610 uint8_t *bwpInactivityTmr;
1611 SchPdschServCellCfg pdschServCellCfg;
1612 SchInitialUlBwp initUlBwp;
1613 uint8_t numUlBwpToAddOrMod;
1614 SchUlBwpInfo ulBwpToAddOrModList[MAX_NUM_BWP];
1615 uint8_t numUlBwpToRel;
1616 SchUlBwpInfo ulBwpToRelList[MAX_NUM_BWP];
1617 uint8_t firstActvUlBwpId;
1618 }SchServCellRecfgInfo;
1620 /* Serving cell configuration */
1621 typedef struct schServCellCfgInfo
1623 SchInitalDlBwp initDlBwp;
1624 uint8_t numDlBwpToAdd;
1625 SchDlBwpInfo dlBwpToAddList[MAX_NUM_BWP];
1626 uint8_t firstActvDlBwpId;
1627 uint8_t defaultDlBwpId;
1628 uint8_t *bwpInactivityTmr;
1629 SchPdschServCellCfg pdschServCellCfg;
1630 SchInitialUlBwp initUlBwp;
1631 uint8_t numUlBwpToAdd;
1632 SchUlBwpInfo ulBwpToAddList[MAX_NUM_BWP];
1633 uint8_t firstActvUlBwpId;
1634 }SchServCellCfgInfo;
1636 typedef struct schNonDynFiveQi
1641 uint16_t maxDataBurstVol;
1644 typedef struct schDynFiveQi
1647 uint16_t packetDelayBudget;
1648 uint8_t packetErrRateScalar;
1649 uint8_t packetErrRateExp;
1651 uint8_t delayCritical;
1653 uint16_t maxDataBurstVol;
1656 typedef struct schNgRanAllocAndRetPri
1658 uint8_t priorityLevel;
1659 uint8_t preEmptionCap;
1660 uint8_t preEmptionVul;
1661 }SchNgRanAllocAndRetPri;
1663 typedef struct schGrbQosFlowInfo
1665 uint32_t maxFlowBitRateDl;
1666 uint32_t maxFlowBitRateUl;
1667 uint32_t guarFlowBitRateDl;
1668 uint32_t guarFlowBitRateUl;
1672 typedef struct schDrbQos
1674 SchQosType fiveQiType; /* Dynamic or non-dynamic */
1677 SchNonDynFiveQi nonDyn5Qi;
1678 SchDynFiveQi dyn5Qi;
1680 SchNgRanAllocAndRetPri ngRanRetPri;
1681 SchGrbQosFlowInfo grbQosFlowInfo;
1682 uint16_t pduSessionId;
1683 uint32_t ulPduSessAggMaxBitRate; /* UL PDU Session Aggregate max bit rate */
1686 /* Special cell configuration */
1687 typedef struct schSpCellCfg
1689 uint8_t servCellIdx;
1690 SchServCellCfgInfo servCellCfg;
1693 /* Special cell Reconfiguration */
1694 typedef struct schSpCellRecfg
1696 uint8_t servCellIdx;
1697 SchServCellRecfgInfo servCellRecfg;
1700 /* Uplink logical channel configuration */
1701 typedef struct SchUlLcCfg
1706 uint8_t pbr; // prioritisedBitRate
1707 uint8_t bsd; // bucketSizeDuration
1710 /* Downlink logical channel configuration */
1711 typedef struct schDlLcCfg
1713 uint8_t lcp; // logical Channel Prioritization
1716 /* Logical Channel configuration */
1717 typedef struct schLcCfg
1721 SchDrbQosInfo *drbQos;
1726 /* Aggregate max bit rate */
1727 typedef struct schAmbrCfg
1729 uint32_t ulBr; /* Ul BitRate */
1732 typedef struct schModulationInfo
1736 SchMcsTable mcsTable;
1739 /* UE configuration */
1740 typedef struct schUeCfgReq
1746 bool macCellGrpCfgPres;
1747 SchMacCellGrpCfg macCellGrpCfg;
1748 bool phyCellGrpCfgPres;
1749 SchPhyCellGrpCfg phyCellGrpCfg;
1751 SchSpCellCfg spCellCfg;
1752 SchAmbrCfg *ambrCfg;
1753 SchModulationInfo dlModInfo;
1754 SchModulationInfo ulModInfo;
1755 uint8_t numLcsToAdd;
1756 SchLcCfg schLcCfg[MAX_NUM_LC];
1759 /* UE Re-configuration */
1760 typedef struct schUeRecfgReq
1766 bool macCellGrpRecfgPres;
1767 SchMacCellGrpCfg macCellGrpRecfg;
1768 bool phyCellGrpRecfgPres;
1769 SchPhyCellGrpCfg phyCellGrpRecfg;
1770 bool spCellRecfgPres;
1771 SchSpCellRecfg spCellRecfg;
1772 SchAmbrCfg *ambrRecfg;
1773 SchModulationInfo dlModInfo;
1774 SchModulationInfo ulModInfo;
1775 uint8_t numLcsToAdd;
1776 SchLcCfg schLcCfgAdd[MAX_NUM_LC];
1777 uint8_t numLcsToDel;
1778 uint8_t lcIdToDel[MAX_NUM_LC];
1779 uint8_t numLcsToMod;
1780 SchLcCfg schLcCfgMod[MAX_NUM_LC];
1781 SchDataTransmission dataTransmissionInfo;
1783 bool drxConfigIndicatorRelease;
1787 typedef struct schUeCfgRsp
1794 SchFailureCause cause;
1797 /*As per WG8, UE ReCFG and UECFG have same structure definition*/
1798 typedef struct schUeCfgRsp SchUeRecfgRsp;
1800 typedef struct schRachRsrcReq
1802 SlotTimingInfo slotInd;
1806 uint8_t ssbIdx[MAX_NUM_SSB];
1809 typedef struct schCfraSsbResource
1812 uint8_t raPreambleIdx;
1813 }SchCfraSsbResource;
1815 typedef struct schCfraRsrc
1818 SchCfraSsbResource ssbResource[MAX_NUM_SSB];
1821 typedef struct schRachRsrcRsp
1826 SchCfraResource cfraResource;
1829 typedef struct schRachRsrcRel
1831 SlotTimingInfo slotInd;
1834 SchCfraResource cfraResource;
1837 typedef struct schUeDelete
1843 typedef struct schUeDeleteRsp
1851 typedef struct schCellDeleteReq
1857 typedef struct schCellDeleteRsp
1861 SchFailureCause cause;
1864 typedef struct dataVolInfo
1870 typedef struct ulBufferStatusRptInd
1876 DataVolInfo dataVolInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
1877 }UlBufferStatusRptInd;
1879 typedef struct srUciIndInfo
1883 SlotTimingInfo slotInd;
1885 uint8_t srPayload[MAX_SR_BITS_IN_BYTES];
1888 typedef struct dlHarqInd
1892 SlotTimingInfo slotInd;
1894 uint8_t harqPayload[MAX_HARQ_BITS_IN_BYTES];
1897 typedef struct schRrmPolicyRatio
1901 uint8_t dedicatedRatio;
1904 typedef struct schRrmPolicyOfSlice
1907 SchRrmPolicyRatio rrmPolicyRatioInfo;
1908 }SchRrmPolicyOfSlice;
1910 typedef struct schSliceCfgReq
1912 uint8_t numOfConfiguredSlice;
1913 SchRrmPolicyOfSlice **listOfSlices;
1916 typedef struct sliceRsp
1923 typedef struct schSliceCfgRsp
1925 uint8_t numSliceCfgRsp;
1926 SliceRsp **listOfSliceCfgRsp;
1929 /*As per ORAN-WG8, Slice Cfg and Recfg are same structures*/
1930 typedef struct schSliceCfgReq SchSliceRecfgReq;
1931 typedef struct schSliceCfgRsp SchSliceRecfgRsp;
1933 typedef struct schPageInd
1942 typedef struct schUeHqInfo
1948 typedef struct schRlsHqInfo
1952 SchUeHqInfo *ueHqInfo;
1955 /* function declarations */
1956 uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason);
1957 uint8_t MacMessageRouter(Pst *pst, void *msg);
1958 uint8_t SchMessageRouter(Pst *pst, void *msg);
1960 /**********************************************************************
1962 **********************************************************************/