src/5gnrsch/sch_crc.c

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17  *******************************************************************************/
  18 #include "common_def.h"
  19 #include "tfu.h"
  20 #include "lrg.h"
  21 #include "tfu.x"
  22 #include "lrg.x"
  23 #include "du_log.h"
  24 #include "du_app_mac_inf.h"
  25 #include "mac_sch_interface.h"
  26 #include "sch.h"
  27 #include "sch_utils.h"
  28
  29 /**
  30  * @brief Process CRC indication
  31  *
  32  * @details
  33  *
  34  *     Function : schProcessCrcInd
  35  *
  36  *      This function process CRC indication
  37  *
  38  *  @param[in]  CrcIndInfo *crcInd, recvd crc indication
  39  *  @param[in]  Inst schInst, scheduler inst
  40  *  @return
  41  *      -# ROK
  42  *      -# RFAILED
  43  **/
  44 uint8_t schProcessCrcInd(CrcIndInfo *crcInd, Inst schInst)
  45 {
  46    SchCellCb *cell = schCb[schInst].cells[schInst];
  47    uint16_t count=0;
  48    uint8_t  ueId=0;
  49    SchUlHqProcCb *hqP = NULLP;
  50
  51    while(count  <crcInd->numCrcInd)
  52    {
  53       GET_UE_ID(crcInd->crnti, ueId);
  54       if (cell->raCb[ueId-1].raState == SCH_RA_STATE_MSG3_PENDING)
  55       {
  56          if (crcInd->crcInd[count])
  57          {
  58             /* failure case*/
  59             if (cell->raCb[ueId-1].msg3HqProc.tbInfo.txCntr < cell->cellCfg.schRachCfg.maxMsg3Tx)
  60             {
  61                addUeToBeScheduled(cell, ueId);
  62                cell->raCb[ueId - 1].retxMsg3HqProc = &cell->raCb[ueId - 1].msg3HqProc;
  63             }
  64             else
  65             {
  66                /*Release all contexts of the UE RA*/
  67             }
  68          }
  69          else
  70          {
  71             /* pass case*/
  72             /*Dedicated preamble case need to be added*/
  73             cell->raCb[ueId-1].raState = SCH_RA_STATE_MSG4_PENDING;
  74             /*HARQ init part is in ADD UE CONFIG now, could be moved here*/
  75          }
  76       }
  77       else
  78       {
  79          if (cell->ueCb[ueId-1].hqUlmap[crcInd->timingInfo.slot]->hqList.count == 0)
  80          {
  81             DU_LOG("\n ERROR no harq stored in ul hq map at slot %d ue id %d\n",crcInd->timingInfo.slot, ueId);
  82             continue;
  83          }
  84          if (cell->ueCb[ueId-1].hqUlmap[crcInd->timingInfo.slot]->hqList.first == 0)
  85          {
  86             DU_LOG("\n ERROR NULL harq stored in ul hq map at slot %d ue id %d\n",crcInd->timingInfo.slot, ueId);
  87             continue;
  88          }
  89          hqP = (SchUlHqProcCb*) cell->ueCb[ueId-1].hqUlmap[crcInd->timingInfo.slot]->hqList.first->node;
  90          if(hqP == NULLP)
  91          {
  92             continue;
  93          }
  94          else
  95          {
  96             if (crcInd->crcInd[count])
  97             {
  98                /* failure case*/
  99                schUlHqProcessNack(hqP);
 100             }
 101             else
 102             {
 103                /* pass case*/
 104                schUlHqProcessAck(hqP);
 105             }
 106          }
 107          cmLListDelFrm(&(cell->ueCb[ueId-1].hqUlmap[crcInd->timingInfo.slot]->hqList), &hqP->ulSlotLnk);
 108       }
 109       count++;
 110    }
 111    return ROK;
 112 }
 113 /**********************************************************************
 114   End of file
 115  **********************************************************************/