1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 #define SCH_MAX_NUM_UL_HQ_PROC 16
63 #define SCH_MAX_NUM_DL_HQ_PROC 16
64 #define SCH_MAX_NUM_MSG3_TX 2
65 #define SCH_MAX_NUM_DL_HQ_TX 3
66 #define SCH_MAX_NUM_UL_HQ_TX 3
67 #define SCH_MAX_NUM_MSG4_TX 2
71 #define ROOT_SEQ_LEN_1 139
72 #define ROOT_SEQ_LEN_2 839
75 /* As per 38.331 the largest offset which can be used in of size 10240.
76 * But using this much size of array can cause memory related issue so thats why
77 * taking this size which are a multiple of the larger size */
78 #define MAX_DRX_SIZE 512
81 #define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/
83 typedef struct schDlHqProcCb SchDlHqProcCb;
84 typedef struct schUlHqEnt SchUlHqEnt;
85 typedef struct schRaReq SchRaReq;
86 typedef struct schDlHqEnt SchDlHqEnt;
87 typedef struct schCellCb SchCellCb;
88 typedef struct schUeCb SchUeCb;
107 SCH_UE_STATE_INACTIVE,
109 SCH_UE_HANDIN_IN_PROGRESS
114 SCH_RA_STATE_MSG2_HANDLE,
115 SCH_RA_STATE_MSG3_PENDING,
116 SCH_RA_STATE_MSG4_PENDING,
117 SCH_RA_STATE_MSG4_DONE
122 SCH_LC_STATE_INACTIVE,
149 /*Following structures to keep record and estimations of PRB allocated for each
150 * LC taking into consideration the RRM policies*/
151 typedef struct lcInfo
153 uint8_t lcId; /*LCID for which BO are getting recorded*/
154 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
155 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
156 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
159 typedef struct schUlHqTbCb
167 SchMcsTable mcsTable;
173 uint8_t cntrRetxAllocFail;
177 typedef struct schDlHqTbCb
190 uint8_t isAckNackDtx;
191 uint8_t cntrRetxAllocFail;
192 //InfUeTbInfo tbCompInfo;
197 typedef struct schDrxHarqCb
199 uint32_t rttExpIndex;
201 uint32_t retxStrtIndex;
202 CmLList *retxStrtNode;
203 uint32_t retxExpIndex;
204 CmLList *retxExpNode;
208 typedef struct schUlHqProcCb
210 uint8_t procId; /*!< HARQ Process ID */
212 uint8_t maxHqTxPerHqP;
218 void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
219 CmLList ulHqProcLink;
220 uint8_t puschResType; /*!< Resource allocation type */
221 uint16_t puschStartPrb;
222 uint16_t puschNumPrb;
223 uint8_t dmrsMappingType;
224 uint8_t nrOfDmrsSymbols;
226 SlotTimingInfo puschTime;
228 SchDrxHarqCb ulDrxHarqCb;
234 uint8_t procId; /*!< HARQ Process ID */
236 uint8_t maxHqTxPerHqP;
239 SchDlHqTbCb tbInfo[2];
241 void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
242 CmLList dlHqProcLink;
243 SlotTimingInfo pucchTime;
245 SchDrxHarqCb dlDrxHarqCb;
250 SchCellCb *cell; /*!< Contains the pointer to cell*/
251 SchUeCb *ue; /*!< Contains the pointer to ue*/
252 CmLListCp free; /*!< List of free HARQ processes */
253 CmLListCp inUse; /*!< List of in-use HARQ processes */
254 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
255 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
256 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
260 SchCellCb *cell; /*!< Contains the pointer to cell */
261 SchUeCb *ue; /*!< Contains the pointer to UE */
262 CmLListCp free; /*!< List of free HARQ processes */
263 CmLListCp inUse; /*!< List of in-use HARQ processes */
264 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
265 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
266 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
271 * Structure holding LTE MAC's General Configuration information.
273 typedef struct schGenCb
275 uint8_t tmrRes; /*!< Timer resolution */
276 uint8_t startCellId; /*!< Starting Cell Id */
278 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
279 of RLC control BO and SRB BO on
280 PCell. val 0 means don't force*/
281 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
285 typedef struct freePrbBlock
294 * PRB allocations for a symbol within a slot
296 typedef struct schPrbAlloc
298 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
299 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
304 * scheduler allocationsfor DL per cell.
306 typedef struct schDlSlotInfo
308 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
309 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
310 uint8_t ssbIdxSupported; /*!< Max SSB index */
311 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
312 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
313 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
314 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
315 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
317 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
320 typedef struct schRaCb
325 uint16_t dlMsgPduLen;
326 SchUlHqProcCb msg3HqProc;
327 SchUlHqProcCb *retxMsg3HqProc;
335 * scheduler allocationsfor UL per cell.
337 typedef struct schUlSlotInfo
339 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
340 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
341 bool puschPres; /*!< PUSCH presence field */
342 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
343 bool pucchPres; /*!< PUCCH presence field */
344 SchPucchInfo schPucchInfo; /*!< PUCCH info */
345 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
346 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
351 * BSR info per slot per UE.
353 typedef struct bsrInfo
355 uint8_t priority; /* CG priority */
356 uint32_t dataVol; /* Data volume requested in bytes */
359 typedef struct schLcCtxt
361 uint8_t lcId; // logical Channel ID
362 uint8_t lcp; // logical Channel Prioritization
365 uint16_t pduSessionId; /*Pdu Session Id*/
366 Snssai *snssai; /*S-NSSAI assoc with LCID*/
367 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
368 uint16_t rsvdDedicatedPRB;
371 typedef struct schDlCb
373 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
376 typedef struct schUlLcCtxt
383 uint8_t pbr; // prioritisedBitRate
384 uint8_t bsd; // bucketSizeDuration
385 uint16_t pduSessionId; /*Pdu Session Id*/
386 Snssai *snssai; /*S-NSSAI assoc with LCID*/
387 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
388 uint16_t rsvdDedicatedPRB;
391 typedef struct schUlCb
393 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
396 typedef struct schUeCfgCb
401 bool macCellGrpCfgPres;
402 SchMacCellGrpCfg macCellGrpCfg;
403 bool phyCellGrpCfgPres;
404 SchPhyCellGrpCfg phyCellGrpCfg;
406 SchSpCellRecfg spCellCfg;
408 SchModulationInfo dlModInfo;
409 SchModulationInfo ulModInfo;
410 SchDataTransmission dataTransmissionAction;
413 typedef struct schHqDlMap
418 typedef struct schHqUlMap
424 typedef struct schDrxUeCb
426 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
427 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
428 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
429 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
430 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
431 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
432 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
433 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
434 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
435 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
436 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
437 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
438 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
439 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
440 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
441 bool shortCyclePresent; /* set this value if shortCycle is Present */
442 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
443 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
444 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
445 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
446 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
447 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
448 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
449 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
450 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
451 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
452 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
453 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
454 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
455 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
456 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
463 typedef struct schUeCb
470 SchCfraResource cfraResource;
473 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
478 SchDlHqProcCb *msg4HqProc;
479 SchDlHqProcCb *retxMsg4HqProc;
480 SchHqDlMap **hqDlmap;
481 SchHqUlMap **hqUlmap;
493 typedef struct schRaReq
496 RachIndInfo *rachInd;
498 SchUeCb *ueCb; /* Filled only if isCFRA = true */
499 SlotTimingInfo winStartTime;
500 SlotTimingInfo winEndTime;
503 typedef struct schPageInfo
505 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
506 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
507 SlotTimingInfo pageTxTime; /*Start Paging window*/
508 uint8_t mcs; /*MCS index*/
509 uint16_t msgLen; /*Pdu length */
510 uint8_t *pagePdu; /*RRC Page PDU bit string*/
513 typedef struct schPagingOcc
516 uint8_t pagingOccSlot;
519 typedef struct schPageCb
521 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
522 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
526 typedef struct schDrxCb
528 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
529 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
530 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
531 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
532 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
533 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
534 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
535 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
536 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
537 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
541 typedef struct schAllApis
543 uint8_t (* SchCellCfgReq)(SchCellCb *cellCb);
544 void (* SchCellDeleteReq)(SchCellCb *cellCb);
545 uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb);
546 void (* SchModUeConfigReq)(SchUeCb *ueCb);
547 void (* SchUeDeleteReq)(SchUeCb *ueCb);
548 void (* SchDlHarqInd)();
549 void (* SchPagingInd)();
550 void (* SchRachRsrcReq)();
551 void (* SchRachRsrcRel)();
552 void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId);
553 void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId);
554 void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId);
555 void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId);
556 void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId);
557 void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action);
558 void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP);
559 void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP);
560 void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node);
561 void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node);
562 uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId);
563 void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node);
564 uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP);
565 uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP);
566 void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP);
567 void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP);
568 void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP);
569 void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP);
570 void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst);
571 uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \
572 bool isRetx, SchDlHqProcCb **hqP);
573 uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
574 uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
577 typedef struct schHqCfgParam
579 uint8_t maxDlDataHqTx;
581 uint8_t maxUlDataHqTx;
586 /* parameters derived in scheduler */
589 PdcchCfg sib1PdcchCfg;
590 PdschCfg sib1PdschCfg;
595 * Cell Control block per cell.
597 typedef struct schCellCb
599 uint16_t cellId; /*!< Cell ID */
600 Inst instIdx; /*!< Index of the scheduler instance */
601 Inst macInst; /*!< Index of the MAC instance */
602 uint16_t numSlots; /*!< Number of slots in current frame */
603 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
604 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
605 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
606 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
607 bool firstSsbTransmitted;
608 bool firstSib1Transmitted;
609 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
610 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
611 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
612 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
613 uint16_t numActvUe; /*!< Number of active UEs */
614 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
615 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
616 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
617 SchPageCb pageCb; /*!< Page Record at Schedular*/
619 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
620 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
621 uint8_t slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT];
624 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
626 SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
627 SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
628 void *schSpcCell; /*Ref of Scheduler specific structure*/
630 SchK0K1TimingInfoTbl k0K1InfoTbl;
631 SchK2TimingInfoTbl msg3K2InfoTbl;
632 SchK2TimingInfoTbl k2InfoTbl;
633 SchSib1Cfg sib1SchCfg; /* SIB1 config */
634 uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
638 typedef struct schSliceCfg
640 uint8_t numOfSliceConfigured;
641 SchRrmPolicyOfSlice **listOfSlices;
646 * Control block for sch
650 TskInit schInit; /*!< Task Init info */
651 SchGenCb genCfg; /*!< General Config info */
652 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
653 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
654 SchAllApis allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
655 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
656 SchSliceCfg sliceCfg;
659 /* Declaration for scheduler control blocks */
660 SchCb schCb[SCH_MAX_INST];
662 /* function declarations */
663 short int schActvTmr(Ent ent,Inst inst);
664 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
666 /* Configuration related function declarations */
667 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
668 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
669 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
670 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
671 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
672 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
673 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
674 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
675 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
677 /* Incoming message handler function declarations */
678 uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg);
679 uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd);
680 uint8_t SchProcRachInd(Pst *pst, RachIndInfo *rachInd);
681 uint8_t SchProcCrcInd(Pst *pst, CrcIndInfo *crcInd);
682 uint8_t SchProcDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo);
683 uint8_t SchAddUeConfigReq(Pst *pst, SchUeCfgReq *ueCfgToSch);
684 uint8_t SchProcBsr(Pst *pst, UlBufferStatusRptInd *bsrInd);
685 uint8_t SchProcSrUciInd(Pst *pst, SrUciIndInfo *uciInd);
686 uint8_t SchModUeConfigReq(Pst *pst, SchUeRecfgReq *ueRecfgToSch);
687 uint8_t SchProcUeDeleteReq(Pst *pst, SchUeDelete *ueDelete);
688 uint8_t SchProcCellDeleteReq(Pst *pst, SchCellDeleteReq *schCellDelete);
689 uint8_t SchProcSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq);
690 uint8_t SchProcSliceRecfgReq(Pst *pst, SchSliceRecfgReq *schSliceRecfgReq);
691 uint8_t SchProcRachRsrcReq(Pst *pst, SchRachRsrcReq *schRachRsrcReq);
692 uint8_t SchProcRachRsrcRel(Pst *pst, SchRachRsrcRel *schRachRsrcRel);
693 uint8_t SchProcPagingInd(Pst *pst, SchPageInd *pageInd);
694 uint8_t SchProcDlHarqInd(Pst *pst, DlHarqInd *dlHarqInd);
696 /* DL scheduling related function declarations */
697 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
698 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
699 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
700 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
701 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
702 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
703 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
704 bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP);
705 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
706 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
707 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *msg4Alloc,\
708 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
709 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
710 uint16_t *startPrb, uint16_t numPrb);
711 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti, bool isRetx, SchDlHqProcCb* hqP);
712 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
713 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
714 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
716 /* UL scheduling related function declarations */
717 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
718 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
719 uint8_t schCalcPrachNumRb(SchCellCb *cell);
720 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
721 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
722 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
723 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
724 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
725 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
726 uint16_t *startPrb, uint16_t numPrb);
727 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
729 /*Generic Functions*/
730 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
731 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
732 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
733 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
734 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
735 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
738 void schProcPagingCfg(SchCellCb *cell);
739 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
740 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
741 uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime, \
742 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
743 /*DL HARQ Functions*/
744 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
745 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
746 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
747 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
748 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
749 void schDlHqEntDelete(SchUeCb *ueCb);
751 /*UL HARQ Functions*/
752 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
753 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
754 void schUlHqProcessNack(SchUlHqProcCb *hqP);
755 void schUlHqProcessAck(SchUlHqProcCb *hqP);
756 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
757 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
758 void schUlHqEntDelete(SchUeCb *ueCb);
760 /* UE Manager HARQ Fun*/
761 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
763 /* Round Robbin Scheduler funtions*/
764 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
765 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
766 void schMsg4Complete(SchUeCb *ueCb);
767 /**********************************************************************
769 **********************************************************************/