gerrit.o-ran-sc Code Review - o-du/phy.git/blob - docs/Setup-Configuration

2 ..\r

3 .. Licensed under the Apache License, Version 2.0 (the "License");\r

4 .. you may not use this file except in compliance with the License.\r

5 .. You may obtain a copy of the License at\r

6 ..\r

7 .. http://www.apache.org/licenses/LICENSE-2.0\r

8 ..\r

9 .. Unless required by applicable law or agreed to in writing, software\r

10 .. distributed under the License is distributed on an "AS IS" BASIS,\r

11 .. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r

12 .. See the License for the specific language governing permissions and\r

13 .. limitations under the License.\r

14 \r

15 .. |br| raw:: html\r

16 \r

17 <br />\r

18 \r

19 Setup Configuration\r

20 ===================\r

21 \r

22 A.1 Setup Configuration\r

23 -----------------------\r

24 The configuration shown in Figure 26 shows how to set up a test\r

25 environment to execute xRAN scenarios where O-DU and 0-RU are simulated\r

26 using the sample application. This setup allows development and\r

27 prototyping as well as testing of xRAN specific functionality. The O-DU\r

28 side can be instantiated with a full 5G NR L1 reference as well. The\r

29 configuration differences of the 5G NR l1app configuration are provided\r

30 below. Steps for running the sample application on the O-DU side and\r

31 0-RU side are the same, except configuration file options may be\r

32 different.\r

33 \r

34 .. image:: images/Setup-for-xRAN-Testing.jpg\r

35 :width: 400\r

36 :alt: Figure 26. Setup for xRAN Testing\r

37 \r

38 Figure 26. Setup for xRAN Testing\r

39 \r

40 .. image:: images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3.jpg\r

41 :width: 400\r

42 :alt: Figure 27. Setup for xRAN Testing with PHY and Configuration C3\r

43 \r

44 Figure 27. Setup for xRAN Testing with PHY and Configuration C3\r

45 \r

46 A.2 Prerequisites\r

47 -----------------\r

48 Each server in Figure 26 requires the following:\r

49 \r

50 - Wolfpass server according to recommended BOM for FlexRAN such as\r

51 Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20\r

52 cores (two sockets)\r

53 \r

54 - BIOS settings:\r

55 \r

56 - Intel® Virtualization Technology Enabled\r

57 \r

58 - Intel® VT for Directed I/O - Enabled\r

59 \r

60 - ACS Control - Enabled\r

61 \r

62 - Coherency Support - Disabled\r

63 \r

64 - Front Haul networking cards:\r

65 \r

66 - Intel® Ethernet Converged Network Adapter XL710-QDA2\r

67 \r

68 - Intel® Ethernet Converged Network Adapter XXV710-DA2\r

69 \r

70 - Intel® Ethernet Converged Network Adapter E810-CQDA2\r

71 \r

72 - Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000\r

73 \r

74 - Back (Mid) Haul networking card can be either:\r

75 \r

76 - Intel® Ethernet Connection X722 for 10GBASE-T\r

77 \r

78 - Intel® 82599ES 10-Gigabit SFI/SFP+ Network Connection\r

79 \r

80 - Other networking cards capable of HW timestamping for PTP synchronization.\r

81 \r

82 - Both Back (mid) Haul and Front Haul NIC require support for PTP HW timestamping.\r

83 \r

84 The recommended configuration for NICs is::\r

85 \r

86 ethtool -i enp33s0f0\r

87 driver: i40e\r

88 version: 2.14.13\r

89 firmware-version: 8.20 0x80009bd4 1.2879.0\r

90 expansion-rom-version:\r

91 bus-info: 0000:21:00.0\r

92 supports-statistics: yes\r

93 supports-test: yes\r

94 supports-eeprom-access: yes\r

95 supports-register-dump: yes\r

96 supports-priv-flags: yes\r

97 ethtool -T enp33s0f0\r

98 Time stamping parameters for enp33s0f0:\r

99 Capabilities:\r

100 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)\r

101 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)\r

102 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)\r

103 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)\r

104 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)\r

105 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)\r

106 PTP Hardware Clock: 4\r

107 Hardware Transmit Timestamp Modes:\r

108 off (HWTSTAMP_TX_OFF)\r

109 on (HWTSTAMP_TX_ON)\r

110 Hardware Receive Filter Modes:\r

111 none (HWTSTAMP_FILTER_NONE)\r

112 ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)\r

113 ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)\r

114 ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)\r

115 ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)\r

116 ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)\r

117 ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)\r

118 ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)\r

119 ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)\r

120 ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)\r

121 ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)\r

122 ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)\r

123 \r

124 The recommended configuration for Columbiaville NICs (base on Intel®\r

125 Ethernet 800 Series (Columbiaville) CVL 2.3 release is::\r

126 \r

127 ethtool -i enp81s0f0\r

128 driver: ice\r

129 version: 1.3.2\r

130 firmware-version: 2.3 0x80005D18\r

131 expansion-rom-version:\r

132 bus-info: 0000:51:00.0\r

133 supports-statistics: yes\r

134 supports-test: yes\r

135 supports-eeprom-access: yes\r

136 supports-register-dump: yes\r

137 supports-priv-flags: yes\r

138 ethtool -T enp81s0f0\r

139 Time stamping parameters for enp81s0f0:\r

140 Capabilities:\r

141 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)\r

142 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)\r

143 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)\r

144 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)\r

145 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)\r

146 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)\r

147 PTP Hardware Clock: 1\r

148 Hardware Transmit Timestamp Modes:\r

149 off (HWTSTAMP_TX_OFF)\r

150 on (HWTSTAMP_TX_ON)\r

151 Hardware Receive Filter Modes:\r

152 none (HWTSTAMP_FILTER_NONE)\r

153 all (HWTSTAMP_FILTER_ALL)\r

154 \r

155 Recommended version of\r

156 iavf driver 4.0.2\r

157 ICE COMMS Package version 1.3.24.0\r

158 \r

159 *Note*. If your firmware version does not match with the ones in the output\r

160 images, you can download the correct version from the Intel Download\r

161 Center. It is Intel's repository for the latest software and drivers\r

162 for Intel products. The NVM Update Packages for Windows*, Linux*,\r

163 ESX*, FreeBSD*, and EFI/EFI2 are located at:\r

164 \r

165 ..\r

166 \r

167 https://downloadcenter.intel.com/download/24769 (700 series)\r

168 \r

169 https://downloadcenter.intel.com/download/29736 (E810 series)\r

170 \r

171 PTP Grand Master is required to be available in the network to provide\r

172 synchronization of both O-DU and RU to GPS time.\r

173 \r

174 The software package includes Linux\* CentOS\* operating system and RT\r

175 patch according to FlexRAN Reference Solution Cloud-Native Setup\r

176 document (refer to Table 2). Only real-time HOST is required.\r

177 \r

178 1. Install Intel® C++ Compiler v19.0.3\r

179 \r

180 2. Download DPDK v20.11\r

181 \r

182 3. Patch DPDK with FlexRAN BBDev patch as per given release.\r

183 \r

184 4. Double check that FlexRAN DPDK patch includes changes below relevant\r

185 to O-RAN Front haul::\r

186 \r

187 For Fortville: \r

188 diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\r

189 index 85a6a86..236fbe0 100644\r

190 --- a/drivers/net/i40e/i40e_ethdev.c\r

191 +++ b/drivers/net/i40e/i40e_ethdev.c\r

192 @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\r

193 /* Map queues with MSIX interrupt */\r

194 main_vsi->nb_used_qps = dev->data->nb_rx_queues -\r

195 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;\r

196 - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);\r

197 + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE);\r

198 i40e_vsi_enable_queues_intr(main_vsi);\r

199 \r

200 /* Map VMDQ VSI queues with MSIX interrupt */\r

201 @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\r

202 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);\r

203 }\r

204 + i40e_aq_debug_write_global_register(hw,\r

205 + 0x0012A504,\r

206 + 0, NULL);\r

207 +\r

208 /* enable FDIR MSIX interrupt */\r

209 if (pf->fdir.fdir_vsi) {\r

210 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,\r

211 diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\r

212 index 001c301..6f9ffdb 100644\r

213 --- a/drivers/net/i40e/i40e_ethdev_vf.c\r

214 +++ b/drivers/net/i40e/i40e_ethdev_vf.c\r

215 @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off {\r

216 \r

217 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;\r

218 map_info->num_vectors = 1;\r

219 - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;\r

220 + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE;\r

221 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;\r

222 /* Alway use default dynamic MSIX interrupt */\r

223 map_info->vecmap[0].vector_id = vector_id;\r

224 diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\r

225 index 26b1927..018eb8f 100644\r

226 --- a/drivers/net/ixgbe/ixgbe_ethdev.c\r

227 +++ b/drivers/net/ixgbe/ixgbe_ethdev.c\r

228 @@ -3705,7 +3705,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\r

229 * except for 82598EB, which remains constant.\r

230 */\r

231 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&\r

232 - hw->mac.type != ixgbe_mac_82598EB)\r

233 + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != ixgbe_mac_82599EB)\r

234 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;\r

235 }\r

236 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */\r

237 diff --git a/lib/librte_eal/common/include/rte_dev.h b/lib/librte_eal/common/include/rte_dev.h\r

238 old mode 100644\r

239 new mode 100755\r

240 \r

241 for Columbiaville\r

242 diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\r

243 index de189daba..d9aff341c 100644\r

244 --- a/drivers/net/ice/ice_ethdev.c\r

245 +++ b/drivers/net/ice/ice_ethdev.c\r

246 @@ -2604,8 +2604,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,\r

247 \r

248 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",\r

249 base_queue + i, msix_vect);\r

250 - /* set ITR0 value */\r

251 - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);\r

252 + /* set ITR0 value\r

253 + * Empirical configuration for optimal real time latency\r

254 + * reduced interrupt throttling to 2 ms\r

255 + * Columbiaville pre-PRQ : local patch subject to change\r

256 + */\r

257 + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);\r

258 + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), QRX_ITR_NO_EXPR_M);\r

259 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);\r

260 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);\r

261 }\r

262 \r

263 5.Build and install DPDK::\r

264 \r

265 See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html\r

266 \r

267 6.Make below file changes in dpdk that assure i40e to get best\r

268 latency of packet processing::\r

269 \r

270 --- i40e.h 2018-11-30 11:27:00.000000000 +0000\r

271 +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000\r

272 @@ -451,7 +451,7 @@\r

273 \r

274 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \\r

275 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \\r

276 - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \\r

277 + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \\r

278 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \\r

279 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \\r

280 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))\r

281 \r

282 --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000\r

283 +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000\r

284 @@ -15296,6 +15296,9 @@\r

285 pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;\r

286 /* print a string summarizing features */\r

287 i40e_print_features(pf);\r

288 + \r

289 + /* write to this register to clear rx descriptor */\r

290 + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL);\r

291 \r

292 return 0;\r

293 \r

294 A.3 Configuration of System\r

295 ---------------------------\r

296 1.Boot Linux with the following arguments::\r

297 \r

298 cat /proc/cmdline\r

299 BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro\r

300 crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt\r

301 usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0\r

302 intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll\r

303 hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G\r

304 isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20\r

305 nohz_full=1-19,21-39\r

306 \r

307 2. Boot Linux with the following arguments for Icelake CPU::\r

308 \r

309 cat /proc/cmdline\r

310 BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64\r

311 root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root\r

312 rd.lvm.lv=centos/swap rhgb quiet intel_iommu=off usbcore.autosuspend=-1\r

313 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0\r

314 intel_pstate=disable cgroup_disable=memory mce=off hugepagesz=1G\r

315 hugepages=40 hugepagesz=2M hugepages=0 default_hugepagesz=1G\r

316 isolcpus=1-23,25-47 rcu_nocbs=1-23,25-47 kthread_cpus=0 irqaffinity=0\r

317 nohz_full=1-23,25-47\r

318 \r

319 3. Download from Intel Website and install updated version of i40e\r

320 driver if needed. The current recommended version of i40e is 2.14.13.\r

321 However, any latest version of i40e after 2.9.21 expected to be\r

322 functional for O-RAN FH.\r

323 \r

324 4. For Columbiaville download Intel® Ethernet 800 Series (Columbiaville)\r

325 CVL2.3 B0/C0 Sampling Sample Validation Kit (SVK) from Intel Customer\r

326 Content Library. The current recommended version of ICE driver is\r

327 1.3.2 with ICE COMMS Package version 1.3.24.0. IAVF recommended\r

328 version 4.0.2\r

329 \r

330 5. Identify PCIe Bus address of the Front Haul NIC (Fortville)::\r

331 \r

332 lspci|grep Eth\r

333 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

334 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

335 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

336 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

337 \r

338 6. Identify PCIe Bus address of the Front Haul NIC (Columbiaville)::\r

339 \r

340 lspci \|grep Eth\r

341 18:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

342 18:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

343 18:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

344 18:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

345 51:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

346 51:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

347 51:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

348 51:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r

349 \r

350 7. Identify the Ethernet device name::\r

351 \r

352 ethtool -i enp33s0f0\r

353 driver: i40e\r

354 version: 2.14.13\r

355 firmware-version: 8.20 0x80009bd4 1.2879.0 \r

356 expansion-rom-version:\r

357 bus-info: 0000:21:00.0\r

358 supports-statistics: yes\r

359 supports-test: yes\r

360 supports-eeprom-access: yes\r

361 supports-register-dump: yes\r

362 supports-priv-flags: yesEnable \r

363 \r

364 or ::\r

365 \r

366 ethtool -i enp81s0f0\r

367 driver: ice\r

368 version: 1.3.2\r

369 firmware-version: 2.3 0x80005D18\r

370 expansion-rom-version:\r

371 bus-info: 0000:51:00.0\r

372 supports-statistics: yes\r

373 supports-test: yes\r

374 supports-eeprom-access: yes\r

375 supports-register-dump: yes\r

376 supports-priv-flags: yes \r

377 \r

378 8. Enable 3 virtual functions (VFs) on the each of two ports of each\r

379 NIC::\r

380 \r

381 #!/bin/bash\r

382 \r

383 echo 0 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs\r

384 echo 0 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs\r

385 \r

386 echo 0 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs\r

387 echo 0 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs\r

388 \r

389 modprobe -r iavf\r

390 modprobe iavf\r

391 \r

392 echo 3 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs\r

393 echo 3 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs\r

394 \r

395 echo 3 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs\r

396 echo 3 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs\r

397 \r

398 a=8\r

399 \r

400 if [ -z "$1" ]\r

401 then\r

402 b=0\r

403 elif [ $1 -lt $a ]\r

404 then\r

405 b=$1\r

406 else\r

407 echo " Usage $0 qos with 0<= qos <= 7 with 0 as a default if no qos is provided"\r

408 exit 1\r

409 fi\r

410 \r

411 #O-DU\r

412 ip link set enp136s0f0 vf 0 mac 00:11:22:33:00:00 vlan 1 qos $b\r

413 ip link set enp136s0f1 vf 0 mac 00:11:22:33:00:10 vlan 1 qos $b\r

414 \r

415 ip link set enp136s0f0 vf 1 mac 00:11:22:33:01:00 vlan 2 qos $b\r

416 ip link set enp136s0f1 vf 1 mac 00:11:22:33:01:10 vlan 2 qos $b\r

417 \r

418 ip link set enp136s0f0 vf 2 mac 00:11:22:33:02:00 vlan 3 qos $b\r

419 ip link set enp136s0f1 vf 2 mac 00:11:22:33:02:10 vlan 3 qos $b\r

420 \r

421 #O-RU\r

422 ip link set enp134s0f0 vf 0 mac 00:11:22:33:00:01 vlan 1 qos $b\r

423 ip link set enp134s0f1 vf 0 mac 00:11:22:33:00:11 vlan 1 qos $b\r

424 \r

425 ip link set enp134s0f0 vf 1 mac 00:11:22:33:01:01 vlan 2 qos $b\r

426 ip link set enp134s0f1 vf 1 mac 00:11:22:33:01:11 vlan 2 qos $b\r

427 \r

428 ip link set enp134s0f0 vf 2 mac 00:11:22:33:02:01 vlan 3 qos $b\r

429 ip link set enp134s0f1 vf 2 mac 00:11:22:33:02:11 vlan 3 qos $b\r

430 \r

431 where output is next::\r

432 \r

433 ip link show\r

434 ...\r

435 9: enp134s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r

436 link/ether 3c:fd:fe:b9:f9:60 brd ff:ff:ff:ff:ff:ff\r

437 vf 0 MAC 00:11:22:33:00:01, vlan 1, spoof checking on, link-state auto, trust off\r

438 vf 1 MAC 00:11:22:33:01:01, vlan 2, spoof checking on, link-state auto, trust off\r

439 vf 2 MAC 00:11:22:33:02:01, vlan 3, spoof checking on, link-state auto, trust off\r

440 11: enp134s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r

441 link/ether 3c:fd:fe:b9:f9:61 brd ff:ff:ff:ff:ff:ff\r

442 vf 0 MAC 00:11:22:33:00:11, vlan 1, spoof checking on, link-state auto, trust off\r

443 vf 1 MAC 00:11:22:33:01:11, vlan 2, spoof checking on, link-state auto, trust off\r

444 vf 2 MAC 00:11:22:33:02:11, vlan 3, spoof checking on, link-state auto, trust off\r

445 12: enp136s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r

446 link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff\r

447 vf 0 MAC 00:11:22:33:00:00, vlan 1, spoof checking on, link-state auto, trust off\r

448 vf 1 MAC 00:11:22:33:01:00, vlan 2, spoof checking on, link-state auto, trust off\r

449 vf 2 MAC 00:11:22:33:02:00, vlan 3, spoof checking on, link-state auto, trust off\r

450 14: enp136s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r

451 link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff\r

452 vf 0 MAC 00:11:22:33:00:10, vlan 1, spoof checking on, link-state auto, trust off\r

453 vf 1 MAC 00:11:22:33:01:10, vlan 2, spoof checking on, link-state auto, trust off\r

454 vf 2 MAC 00:11:22:33:02:10, vlan 3, spoof checking on, link-state auto, trust off\r

455 ...\r

456 \r

457 \r

458 \r

459 \r

460 More information about VFs supported by Intel NICs can be found at\r

461 https://doc.dpdk.org/guides/nics/intel_vf.html.\r

462 \r

463 The resulting configuration can look like the listing below, where six\r

464 new VFs were added for each O-DU and O-RU port:::\r

465 \r

466 lspci|grep Eth\r

467 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

468 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

469 86:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) \r

470 86:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

471 86:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) \r

472 86:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

473 86:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

474 86:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

475 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

476 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r

477 88:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

478 88:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

479 88:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

480 88:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

481 88:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

482 88:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r

483 \r

484 9. Example where O-DU and O-RU simulation run on the same system:\r

485 \r

486 O-DU:::\r

487 \r

488 cat ./run_o_du.sh\r

489 #! /bin/bash\r

490 \r

491 ulimit -c unlimited\r

492 echo 1 > /proc/sys/kernel/core_uses_pid\r

493 \r

494 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_du.cfg --num_eth_vfs 6 \\r

495 --vf_addr_o_xu_a "0000:88:02.0,0000:88:0a.0" \\r

496 --vf_addr_o_xu_b "0000:88:02.1,0000:88:0a.1" \\r

497 --vf_addr_o_xu_c "0000:88:02.2,0000:88:0a.2"\r

498 \r

499 \r

500 O-RU::\r

501 \r

502 cat ./run_o_ru.sh\r

503 #! /bin/bash\r

504 ulimit -c unlimited\r

505 echo 1 > /proc/sys/kernel/core_uses_pid\r

506 \r

507 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg --num_eth_vfs 6 \\r

508 --vf_addr_o_xu_a "0000:86:02.0,0000:86:0a.0" \\r

509 --vf_addr_o_xu_b "0000:86:02.1,0000:86:0a.1" \\r

510 --vf_addr_o_xu_c "0000:86:02.2,0000:86:0a.2"\r

511 \r

512 \r

513 Install and Configure Sample Application\r

514 ========================================\r

515 \r

516 To install and configure the sample application:\r

517 \r

518 1. Set up the environment::\r

519 \r

520 For Skylake and Cascadelake\r

521 export GTEST_ROOT=pwd/gtest-1.7.0\r

522 export RTE_SDK=pwd/dpdk-20.11\r

523 export RTE_TARGET=x86_64-native-linuxapp-icc\r

524 export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk\r

525 export WIRELESS_SDK_TARGET_ISA=avx512\r

526 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc\r

527 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}\r

528 export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog\r

529 export XRAN_DIR=pwd/flexran_xran\r

530 \r

531 for Icelake\r

532 export GTEST_ROOT=pwd/gtest-1.7.0\r

533 export RTE_SDK=pwd/dpdk-20.11\r

534 export RTE_TARGET=x86_64-native-linuxapp-icc\r

535 export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk\r

536 export WIRELESS_SDK_TARGET_ISA=snc\r

537 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc\r

538 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}\r

539 export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog\r

540 export XRAN_DIR=pwd/flexran_xran\r

541 \r

542 2. export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library::\r

543 \r

544 [turner@xran home]$ cd $MLOG_DIR\r

545 [turner@xran xran]$ ./build.sh\r

546 \r

547 3. Compile xRAN library and test the application::\r

548 \r

549 [turner@xran home]$ cd $XRAN_DIR\r

550 [turner@xran xran]$ ./build.sh\r

551 \r

552 4. Configure the sample app.\r

553 \r

554 IQ samples can be generated using Octave\* and script\r

555 libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64\r

556 compatible with get_test.m)\r

557 \r

558 Other IQ sample test vectors can be used as well. The format of IQ\r

559 samples is binary int16_t I and Q for N slots of the OTA RF signal. For\r

560 example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms =\r

561 3548160 bytes per antenna. Refer to comments in gen_test.m to correctly\r

562 specify the configuration for IQ test vector generation.\r

563 \r

564 Update usecase_du.dat (or usecase_ru.cfg) with a suitable configuration\r

565 for your scenario.\r

566 \r

567 Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable\r

568 configuration for your scenario.\r

569 \r

570 Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1\r

571 used for U-plane and C-plane correspondingly.\r

572 \r

573 5. Run the application using run_o_du.sh (run_o_ru.sh).\r

574 \r

575 Install and Configure FlexRAN 5G NR L1 Application\r

576 ==================================================\r

577 \r

578 The 5G NR layer 1 application can be used for executing the scenario for\r

579 mmWave with either the RU sample application or just the O-DU side. The\r

580 current release supports the constant configuration of the slot pattern\r

581 and RB allocation on the PHY side. The build process follows the same\r

582 basic steps as for the sample application above and is similar to\r

583 compiling 5G NR l1app for mmWave with Front Haul FPGA. Please follow the\r

584 general build process in the FlexRAN 5G NR Reference Solution L1 User\r

585 Guide (refer to *Table 2*.)\r

586 \r

587 1. xRAN library is enabled by default l1 application:\r

588 \r

589 2. Build the 5G NR L1 application using the command::\r

590 \r

591 ./flexran_build.sh -r 5gnr_mmw -i avx512 -m sdk -m fb -m mlog –m wls -m\r

592 5gnr_l1app_mmw -m xran -m 5gnr_testmac\r

593 \r

594 3. Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and\r

595 xrancfg_sub6.xml (or other xml if it is mmwave or massive MIMO). ::\r

596 \r

597 <XranConfig>\r

598 <version>20.08</version>\r

599 \r

600 <oRuNum>1</oRuNum>\r

601 \r

602 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>\r

603 \r

604 <oRuLinesNumber>1</oRuLinesNumber>\r

605 \r

606 \r

607 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>\r

608 <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>\r

609 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>\r

610 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>\r

611 \r

612 \r

613 <PciBusAddoRu1Vf0>0000:51:01.4</PciBusAddoRu1Vf0>\r

614 <PciBusAddoRu1Vf1>0000:51:01.5</PciBusAddoRu1Vf1>\r

615 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>\r

616 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>\r

617 \r

618 \r

619 <PciBusAddoRu2Vf0>0000:51:02.0</PciBusAddoRu2Vf0>\r

620 <PciBusAddoRu2Vf1>0000:51:02.1</PciBusAddoRu2Vf1>\r

621 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>\r

622 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>\r

623 \r

624 \r

625 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>\r

626 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>\r

627 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>\r

628 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>\r

629 \r

630 \r

631 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>\r

632 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>\r

633 \r

634 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>\r

635 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>\r

636 \r

637 \r

638 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>\r

639 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>\r

640 \r

641 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>\r

642 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>\r

643 \r

644 \r

645 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>\r

646 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>\r

647 \r

648 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>\r

649 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>\r

650 \r

651 \r

652 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>\r

653 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>\r

654 \r

655 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>\r

656 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>\r

657 \r

658 \r

659 <oRu0NumCc>1</oRu0NumCc>\r

660 \r

661 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>\r

662 \r

663 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>\r

664 \r

665 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>\r

666 \r

667 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>\r

668 \r

669 <oRu0Cc4PhyId>4</oRu0Cc4PhyId>\r

670 \r

671 <oRu0Cc5PhyId>5</oRu0Cc5PhyId>\r

672 \r

673 <oRu0Cc6PhyId>6</oRu0Cc6PhyId>\r

674 \r

675 <oRu0Cc7PhyId>7</oRu0Cc7PhyId>\r

676 \r

677 <oRu0Cc8PhyId>8</oRu0Cc8PhyId>\r

678 \r

679 <oRu0Cc9PhyId>9</oRu0Cc9PhyId>\r

680 \r

681 <oRu0Cc10PhyId>10</oRuCc10PhyId>\r

682 \r

683 <oRu0Cc11PhyId>11</oRu0Cc11PhyId>\r

684 \r

685 \r

686 <oRu1NumCc>1</oRu1NumCc>\r

687 \r

688 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>\r

689 \r

690 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>\r

691 \r

692 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>\r

693 \r

694 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>\r

695 \r

696 \r

697 <oRu2NumCc>1</oRu2NumCc>\r

698 \r

699 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>\r

700 \r

701 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>\r

702 \r

703 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>\r

704 \r

705 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>\r

706 \r

707 \r

708 <xRANThread>19, 96, 0</xRANThread>\r

709 \r

710 \r

711 <xRANWorker>0x0, 96, 0</xRANWorker>\r

712 \r

713 <Category>0</Category>\r

714 \r

715 \r

716 <xranPmdSleep>0</xranPmdSleep>\r

717 \r

718 \r

719 \r

720 <Tadv_cp_dl>25</Tadv_cp_dl>\r

721 \r

722 <T2a_min_cp_dl>50</T2a_min_cp_dl>\r

723 <T2a_max_cp_dl>140</T2a_max_cp_dl>\r

724 \r

725 <T2a_min_cp_ul>50</T2a_min_cp_ul>\r

726 <T2a_max_cp_ul>140</T2a_max_cp_ul>\r

727 \r

728 <T2a_min_up>25</T2a_min_up>\r

729 <T2a_max_up>140</T2a_max_up>\r

730 \r

731 <Ta3_min>20</Ta3_min>\r

732 <Ta3_max>32</Ta3_max>\r

733 \r

734 \r

735 \r

736 <MTU>9600</MTU>\r

737 \r

738 <c_plane_vlan_tag>1</c_plane_vlan_tag>\r

739 <u_plane_vlan_tag>2</u_plane_vlan_tag>\r

740 \r

741 \r

742 <T1a_min_cp_dl>70</T1a_min_cp_dl>\r

743 <T1a_max_cp_dl>100</T1a_max_cp_dl>\r

744 \r

745 <T1a_min_cp_ul>60</T1a_min_cp_ul>\r

746 <T1a_max_cp_ul>70</T1a_max_cp_ul>\r

747 \r

748 <T1a_min_up>35</T1a_min_up>\r

749 <T1a_max_up>50</T1a_max_up>\r

750 \r

751 <Ta4_min>0</Ta4_min>\r

752 <Ta4_max>45</Ta4_max>\r

753 \r

754 \r

755 <EnableCp>1</EnableCp>\r

756 \r

757 <DynamicSectionEna>0</DynamicSectionEna>\r

758 \r

759 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>\r

760 <xRANSFNWrap>0</xRANSFNWrap>\r

761 \r

762 <xRANNumDLPRBs>0</xRANNumDLPRBs>\r

763 \r

764 <xRANNumULPRBs>0</xRANNumULPRBs>\r

765 \r

766 <Gps_Alpha>0</Gps_Alpha>\r

767 \r

768 <Gps_Beta>0</Gps_Beta>\r

769 \r

770 \r

771 <xranCompMethod>0</xranCompMethod>\r

772 \r

773 <oRu0nPrbElemDl>1</oRu0nPrbElemDl>\r

774 \r

775 \r

776 <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>\r

777 <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>\r

778 <oRu0PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu0PrbElemDl2>\r

779 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>\r

780 <oRu0PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>\r

781 <oRu0PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>\r

782 <oRu0PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>\r

783 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>\r

784 <oRu0nPrbElemUl>1</nPrbElemUl>\r

785 \r

786 \r

787 <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>\r

788 <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>\r

789 <oRu0PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemUl2>\r

790 <oRu0PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>\r

791 <oRu0PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>\r

792 <oRu0PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>\r

793 <oRu0PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>\r

794 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>\r

795 \r

796 </XranConfig>\r

797 \r

798 4. Modify bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::\r

799 \r

800 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0\r

801 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1\r

802 \r

803 5. Use configuration of test mac per::\r

804 \r

805 /bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r

806 phystart 4 0 40200\r

807 \r

808 TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg\r

809 \r

810 \r

811 6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::\r

812 \r

813 [root@xran flexran] cd ./bin/nr5g/gnb/l1\r

814 [root@xran l1]#./l1.sh –xran\r

815 \r

816 where output corresponding L1 is::\r

817 \r

818 [root@sc12-xran-sub6 l1]# ./l1.sh -xranmmw\r

819 Radio mode with XRAN - mmWave 100Mhz\r

820 DPDK WLS MODE\r

821 kernel.sched_rt_runtime_us = -1\r

822 kernel.shmmax = 2147483648\r

823 kernel.shmall = 2147483648\r

824 Note: Forwarding request to 'systemctl disable irqbalance.service'.\r

825 using configuration file phycfg_xran_mmw.xml\r

826 >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran_mmw.xml\r

827 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r

828 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r

829 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r

830 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r

831 FlexRAN SDK bblib_llr_demapping version #DIRTY#\r

832 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r

833 FlexRAN SDK bblib_reed_muller version #DIRTY#\r

834 FlexRAN SDK bblib_lte_modulation version #DIRTY#\r

835 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r

836 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r

837 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r

838 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r

839 FlexRAN SDK bblib_fd_correlation version #DIRTY#\r

840 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r

841 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r

842 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r

843 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r

844 FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r

845 FlexRAN SDK bblib_fft_ifft version #DIRTY#\r

846 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r

847 FlexRAN SDK bblib_common version #DIRTY#\r

848 FlexRAN SDK bblib_lte_crc version #DIRTY#\r

849 FlexRAN SDK bblib_lte_dft_idft version #DIRTY#\r

850 FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY#\r

851 FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY#\r

852 FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY#\r

853 FlexRAN SDK bblib_zf_matrix_gen version #DIRTY#\r

854 FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY#\r

855 =========================\r

856 5GNR PHY Application\r

857 =========================\r

858 ---------------------------\r

859 PhyCfg.xml Version: 20.04\r

860 ---------------------------\r

861 --version=20.04\r

862 --successiveNoApi=15\r

863 --wls_dev_name=wls0\r

864 --wlsMemorySize=0x3F600000\r

865 --dlIqLog=0\r

866 --ulIqLog=0\r

867 --iqLogDumpToFile=0x0\r

868 --phyMlog=1\r

869 --phyStats=1\r

870 --dpdkMemorySize=8192\r

871 --dpdkIovaMode=0\r

872 --dpdkBasebandFecMode=1\r

873 --dpdkBasebandDevice=0000:1f:00.1\r

874 --radioEnable=4\r

875 --ferryBridgeMode=1\r

876 --ferryBridgeEthPort=1\r

877 --ferryBridgeSyncPorts=0\r

878 --ferryBridgeOptCableLoopback=0\r

879 --radioCfg0PCIeEthDev=0000:19:00.0\r

880 --radioCfg0DpdkRx=1\r

881 --radioCfg0DpdkTx=2\r

882 --radioCfg0TxAnt=2\r

883 --radioCfg0RxAnt=2\r

884 --radioCfg0RxAgc=0\r

885 --radioCfg0NumCell=1\r

886 --radioCfg0Cell0PhyId=0\r

887 --radioCfg0Cell1PhyId=1\r

888 --radioCfg0Cell2PhyId=2\r

889 --radioCfg0Cell3PhyId=3\r

890 --radioCfg0Cell4PhyId=4\r

891 --radioCfg0Cell5PhyId=5\r

892 --radioCfg0riuMac=11:22:33:44:55:66\r

893 --radioCfg1PCIeEthDev=0000:03:00.1\r

894 --radioCfg1DpdkRx=1\r

895 --radioCfg1DpdkTx=1\r

896 --radioCfg1TxAnt=4\r

897 --radioCfg1RxAnt=4\r

898 --radioCfg1RxAgc=0\r

899 --radioCfg1NumCell=1\r

900 --radioCfg1Cell0PhyId=2\r

901 --radioCfg1Cell1PhyId=3\r

902 --radioCfg1Cell2PhyId=2\r

903 --radioCfg1Cell3PhyId=3\r

904 --radioCfg1riuMac=ac:1f:6b:2c:9f:07\r

905 --radioCfg2PCIeEthDev=0000:05:00.0\r

906 --radioCfg2DpdkRx=10\r

907 --radioCfg2DpdkTx=11\r

908 --radioCfg2TxAnt=4\r

909 --radioCfg2RxAnt=4\r

910 --radioCfg2RxAgc=0\r

911 --radioCfg2NumCell=2\r

912 --radioCfg2Cell0PhyId=4\r

913 --radioCfg2Cell1PhyId=5\r

914 --radioCfg2Cell2PhyId=2\r

915 --radioCfg2Cell3PhyId=3\r

916 --radioCfg2riuMac=ac:1f:6b:2c:9f:07\r

917 --radioCfg3PCIeEthDev=0000:05:00.1\r

918 --radioCfg3DpdkRx=12\r

919 --radioCfg3DpdkTx=13\r

920 --radioCfg3TxAnt=4\r

921 --radioCfg3RxAnt=4\r

922 --radioCfg3RxAgc=0\r

923 --radioCfg3NumCell=2\r

924 --radioCfg3Cell0PhyId=6\r

925 --radioCfg3Cell1PhyId=7\r

926 --radioCfg3Cell2PhyId=2\r

927 --radioCfg3Cell3PhyId=3\r

928 --radioCfg3riuMac=ac:1f:6b:2c:9f:07\r

929 --radioCfg4PCIeEthDev=0000:00:08.0\r

930 --radioCfg4DpdkRx=14\r

931 --radioCfg4DpdkTx=15\r

932 --radioCfg4TxAnt=4\r

933 --radioCfg4RxAnt=4\r

934 --radioCfg4RxAgc=0\r

935 --radioCfg4NumCell=2\r

936 --radioCfg4Cell0PhyId=8\r

937 --radioCfg4Cell1PhyId=9\r

938 --radioCfg4Cell2PhyId=2\r

939 --radioCfg4Cell3PhyId=3\r

940 --radioCfg4riuMac=ac:1f:6b:2c:9f:07\r

941 --radioCfg5PCIeEthDev=0000:08:00.0\r

942 --radioCfg5DpdkRx=16\r

943 --radioCfg5DpdkTx=16\r

944 --radioCfg5TxAnt=4\r

945 --radioCfg5RxAnt=4\r

946 --radioCfg5RxAgc=0\r

947 --radioCfg5NumCell=2\r

948 --radioCfg5Cell0PhyId=10\r

949 --radioCfg5Cell1PhyId=11\r

950 --radioCfg5Cell2PhyId=2\r

951 --radioCfg5Cell3PhyId=3\r

952 --radioCfg5riuMac=ac:1f:6b:2c:9f:07\r

953 --radioCfg6PCIeEthDev=0000:00:05.0\r

954 --radioCfg6DpdkRx=16\r

955 --radioCfg6DpdkTx=16\r

956 --radioCfg6TxAnt=4\r

957 --radioCfg6RxAnt=4\r

958 --radioCfg1RxAgc=0\r

959 --radioCfg6NumCell=2\r

960 --radioCfg6Cell0PhyId=12\r

961 --radioCfg6Cell1PhyId=13\r

962 --radioCfg6Cell2PhyId=2\r

963 --radioCfg6Cell3PhyId=3\r

964 --radioCfg6riuMac=ac:1f:6b:2c:9f:07\r

965 --radioCfg7PCIeEthDev=0000:00:06.0\r

966 --radioCfg7DpdkRx=16\r

967 --radioCfg7DpdkTx=16\r

968 --radioCfg7TxAnt=4\r

969 --radioCfg7RxAnt=4\r

970 --radioCfg7RxAgc=0\r

971 --radioCfg7NumCell=2\r

972 --radioCfg7Cell0PhyId=14\r

973 --radioCfg7Cell1PhyId=15\r

974 --radioCfg7Cell2PhyId=2\r

975 --radioCfg7Cell3PhyId=3\r

976 --radioCfg7riuMac=ac:1f:6b:2c:9f:07\r

977 --radioPort0=0\r

978 --radioPort1=1\r

979 --radioPort2=2\r

980 --radioPort3=3\r

981 --radioPort4=4\r

982 --radioPort5=5\r

983 --radioPort6=6\r

984 --radioPort7=7\r

985 --PdschSymbolSplit=0\r

986 --PdschDlWeightSplit=0\r

987 --FecEncSplit=4\r

988 --PuschChanEstSplit=0\r

989 --PuschMmseSplit=0\r

990 --PuschLlrRxSplit=0\r

991 --PuschUlWeightSplit=0\r

992 --FecDecEarlyTermDisable=0\r

993 --FecDecNumIter=0\r

994 --FecDecSplit=4\r

995 --llrOutDecimalDigit=2\r

996 --IrcEnableThreshold=-10\r

997 --CEInterpMethod=0\r

998 --PucchSplit=0\r

999 --SrsCeSplit=0\r

1000 --prachDetectThreshold=10000\r

1001 --MlogSubframes=128\r

1002 --MlogCores=20\r

1003 --MlogSize=3084\r

1004 --systemThread=0, 0, 0\r

1005 --timerThread=0, 96, 0\r

1006 --xRANThread=4, 96, 0\r

1007 --xRANWorker=0x0, 96, 0\r

1008 --FpgaDriverCpuInfo=2, 96, 0\r

1009 --FrontHaulCpuInfo=3, 96, 0\r

1010 --radioDpdkMaster=2, 99, 0\r

1011 --BbuPoolSleepEnable=1\r

1012 --BbuPoolThreadCorePriority=94\r

1013 --BbuPoolThreadCorePolicy=0\r

1014 --BbuPoolThreadDefault_0_63=0x68\r

1015 --BbuPoolThreadDefault_64_127=0x0\r

1016 --BbuPoolThreadSrs_0_63=0x0\r

1017 --BbuPoolThreadSrs_64_127=0x0\r

1018 --BbuPoolThreadDlbeam_0_63=0x0\r

1019 --BbuPoolThreadDlbeam_64_127=0x0\r

1020 --BbuPoolThreadUrllc=8\r

1021 --FrontHaulTimeAdvance=9450\r

1022 --nEthPorts=459523\r

1023 --nPhaseCompFlag=1\r

1024 --nFecFpgaVersionMu3=0xFC101800\r

1025 --nFecFpgaVersionMu0_1=0x0319d420\r

1026 --nFhFpgaVersionMu3=0x8001000F\r

1027 --nFhFpgaVersionMu0_1=0x90010008\r

1028 --dpdkXranDeviceCP=0000:21:02.1\r

1029 --dpdkXranDeviceUP=0000:21:02.0\r

1030 --DuMac=00:11:22:33:44:66\r

1031 --RuMac=00:11:22:33:44:55\r

1032 --Category=0\r

1033 --xranPmdSleep=0\r

1034 --Tadv_cp_dl=25\r

1035 --T2a_min_cp_dl=50\r

1036 --T2a_max_cp_dl=140\r

1037 --T2a_min_cp_ul=50\r

1038 --T2a_max_cp_ul=140\r

1039 --T2a_min_up=25\r

1040 --T2a_max_up=140\r

1041 --Ta3_min=20\r

1042 --Ta3_max=32\r

1043 --MTU=9600\r

1044 --c_plane_vlan_tag=1\r

1045 --u_plane_vlan_tag=2\r

1046 --T1a_min_cp_dl=70\r

1047 --T1a_max_cp_dl=100\r

1048 --T1a_min_cp_ul=60\r

1049 --T1a_max_cp_ul=70\r

1050 --T1a_min_up=35\r

1051 --T1a_max_up=50\r

1052 --Ta4_min=0\r

1053 --Ta4_max=45\r

1054 --DynamicSectionEna=0\r

1055 --xRANSFNWrap=0\r

1056 --xRANNumDLPRBs=0\r

1057 --xRANNumULPRBs=0\r

1058 --Gps_Alpha=0\r

1059 --Gps_Beta=0\r

1060 --xranCompMethod=0\r

1061 --nPrbElemDl=0\r

1062 --PrbElemDl0=0,48,0,14,1,1,1,9,1\r

1063 --PrbElemDl1=48,48,0,14,2,1,1,9,1\r

1064 --PrbElemDl2=96,48,0,14,3,1,1,9,1\r

1065 --PrbElemDl3=144,48,0,14,4,1,1,9,1\r

1066 --PrbElemDl4=144,36,0,14,5,1,1,9,1\r

1067 --PrbElemDl5=180,36,0,14,6,1,1,9,1\r

1068 --PrbElemDl6=216,36,0,14,7,1,1,9,1\r

1069 --PrbElemDl7=252,21,0,14,8,1,1,9,1\r

1070 --nPrbElemUl=0\r

1071 --PrbElemUl0=0,48,0,14,1,1,1,9,1\r

1072 --PrbElemUl1=48,48,0,14,2,1,1,9,1\r

1073 --PrbElemUl2=72,36,0,14,3,1,1,9,1\r

1074 --PrbElemUl3=108,36,0,14,4,1,1,9,1\r

1075 --PrbElemUl4=144,36,0,14,5,1,1,9,1\r

1076 --PrbElemUl5=180,36,0,14,6,1,1,9,1\r

1077 --PrbElemUl6=216,36,0,14,7,1,1,9,1\r

1078 --PrbElemUl7=252,21,0,14,8,1,1,9,1\r

1079 --StreamStats=0\r

1080 --StreamIp=127.0.0.1\r

1081 --StreamPort=2000\r

1082 \r

1083 wls_dev_filename: wls0\r

1084 phycfg_apply: Initialize Radio Interface with XRAN library\r

1085 Setting FecEncSplit to 1 to run on HW accelerator\r

1086 Setting FecDecSplit to 1 to run on HW accelerator\r

1087 \r

1088 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1596249953 [Hz]\r

1089 Ticks per usec 1596\r

1090 MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(20), mlogSize(3084) mlog_mask (-1)\r

1091 mlogSubframes (128), mlogCores(20), mlogSize(3084)\r

1092 localMLogTimerInit\r

1093 System clock (rdtsc) resolution 1596250020 [Hz]\r

1094 Ticks per us 1596\r

1095 MLog Storage: 0x7f6e5b0e3100 -> 0x7f6e5b86b52c [ 7898156 bytes ]\r

1096 localMLogFreqReg: 1596. Storing: 1596\r

1097 Mlog Open successful\r

1098 \r

1099 di_xran_init\r

1100 di_xran_cfg_setup successful\r

1101 xran_init: MTU 9600\r

1102 BBDEV_FEC_ACCL_NR5G\r

1103 hw-accelerated bbdev 0000:1f:00.1\r

1104 total cores 40 c_mask 0x14 core 4 [id] system_core 2 [id] pkt_proc_core 0x0 [mask] pkt_aux_core 0 [id] timing_core 4 [id]\r

1105 xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x14 -n2 --iova-mode=pa --socket-mem=8192 --socket-limit=8192 --proc-type=auto --file-prefix wls0 -w 0000:00:00.0 -w 0000:1f:00.1\r

1106 EAL: Detected 40 lcore(s)\r

1107 EAL: Detected 1 NUMA nodes\r

1108 EAL: Auto-detected process type: PRIMARY\r

1109 EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket\r

1110 EAL: Selected IOVA mode 'PA'\r

1111 EAL: No available hugepages reported in hugepages-2048kB\r

1112 EAL: Probing VFIO support...\r

1113 EAL: VFIO support initialized\r

1114 EAL: PCI device 0000:1f:00.1 on NUMA socket 0\r

1115 EAL: probe driver: 8086:d90 intel_fpga_5gnr_fec_vf\r

1116 EAL: using IOMMU type 1 (Type 1)\r

1117 EAL: PCI device 0000:21:02.0 on NUMA socket 0\r

1118 EAL: probe driver: 8086:154c net_i40e_vf\r

1119 initializing port 0 for TX, drv=net_i40e_vf\r

1120 Port 0 MAC: 00 11 22 33 44 66\r

1121 Port 0: nb_rxd 4096 nb_txd 4096\r

1122 \r

1123 Checking link status portid [0] EAL: PCI device 0000:21:02.1 on NUMA socket 0\r

1124 EAL: probe driver: 8086:154c net_i40e_vf\r

1125 initializing port 1 for TX, drv=net_i40e_vf\r

1126 Port 1 MAC: 00 11 22 33 44 66\r

1127 Port 1: nb_rxd 4096 nb_txd 4096\r

1128 Checking link status portid [1] vf 0 local SRC MAC: 00 11 22 33 44 66\r

1129 vf 0 remote DST MAC: 00 11 22 33 44 55\r

1130 vf 1 local SRC MAC: 00 11 22 33 44 66\r

1131 vf 1 remote DST MAC: 00 11 22 33 44 55\r

1132 xran_init successful, pHandle = 0x5581f440\r

1133 bbdev_init:\r

1134 Socket ID: 0\r

1135 FEC is accelerated through BBDEV: 0000:1f:00.1\r

1136 wls_layer_init[wls0] nWlsMemorySize[1063256064]\r

1137 wls_lib: Open wls0 (DPDK memzone)\r

1138 wls_lib: WLS_Open 0x2bf600000\r

1139 wls_lib: link: 0 <-> 1\r

1140 wls_lib: Mode 0\r

1141 wls_lib: WLS shared management memzone: wls0\r

1142 wls_lib: hugePageSize on the system is 1073741824\r

1143 wls_lib: WLS_Alloc [1063256064] bytes\r

1144 \r

1145 \r

1146 ===========================================================================================================\r

1147 PHY VERSION\r

1148 ===========================================================================================================\r

1149 Version: #DIRTY#\r

1150 IMG-date: Apr 27 2020\r

1151 IMG-time: 12:54:54\r

1152 ===========================================================================================================\r

1153 DEPENDENCIES VERSIONS\r

1154 ===========================================================================================================\r

1155 FlexRAN BBU pooling version #DIRTY#\r

1156 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r

1157 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r

1158 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r

1159 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r

1160 FlexRAN SDK bblib_llr_demapping version #DIRTY#\r

1161 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r

1162 FlexRAN SDK bblib_reed_muller version #DIRTY#\r

1163 FlexRAN SDK bblib_lte_modulation version #DIRTY#\r

1164 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r

1165 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r

1166 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r

1167 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r

1168 FlexRAN SDK bblib_fd_correlation version #DIRTY#\r

1169 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r

1170 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r

1171 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r

1172 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r

1173 FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r

1174 FlexRAN SDK bblib_fft_ifft version #DIRTY#\r

1175 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r

1176 FlexRAN SDK bblib_lte_crc version #DIRTY#\r

1177 FlexRAN SDK bblib_common version #DIRTY#\r

1178 ===========================================================================================================\r

1179 \r

1180 ===========================================================================================================\r

1181 Non BBU threads in application\r

1182 ===========================================================================================================\r

1183 nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 112583] binding on [CPU 0] [PRIO: 0] [POLICY: 1]\r

1184 wls_rx_handler (non-rt): [PID: 112587] binding on [CPU 0]\r

1185 ===========================================================================================================\r

1186 PHY>welcome to application console\r

1187 PHY>Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r

1188 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0\r

1189 phydi_read_write_iq_samples: direction[1] nNumerologyMult[8] fftSize[1024, 11088, SRS: 792] numSubframe[80] numAntenna[2] numPorts[2] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/mu3_100mhz/2/../../../ul/mu3_100mhz/1/uliq00_tst1.bin] filename_in_prach_iq[]\r

1190 Received MSG_TYPE_PHY_CONFIG_REQ: 0\r

1191 Processing MSG_TYPE_PHY_CONFIG_REQ: 0\r

1192 phy_bbupool_set_config: Using cores: 0x0000000000000068 for BBU Pool nBbuPoolSleepEnable: 1\r

1193 BBU Pooling: queueId = 0, the according nCoreNum = 3, the according cpuSetMask = 0x68\r

1194 BBU Pooling: gCoreIdxMap[0] = 3 is available!\r

1195 BBU Pooling: gCoreIdxMap[1] = 5 is available!\r

1196 BBU Pooling: gCoreIdxMap[2] = 6 is available!\r

1197 BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered\r

1198 BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered\r

1199 BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered\r

1200 BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered\r

1201 BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered\r

1202 BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered\r

1203 BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered\r

1204 BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered\r

1205 BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered\r

1206 BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered\r

1207 BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered\r

1208 BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered\r

1209 BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered\r

1210 BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered\r

1211 BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered\r

1212 BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered\r

1213 BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered\r

1214 BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered\r

1215 BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered\r

1216 BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered\r

1217 BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered\r

1218 BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS\r

1219 BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A\r

1220 \r

1221 BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER: DL_L1_PDSCH_SYMBOL_TX\r

1222 BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST\r

1223 BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX\r

1224 BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST\r

1225 BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST\r

1226 BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r

1227 BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7\r

1228 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r

1229 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7\r

1230 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR\r

1231 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR\r

1232 BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE\r

1233 BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A\r

1234 \r

1235 BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST\r

1236 BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST\r

1237 BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST\r

1238 BBU Pooling: next taskList of UL_L1_SRS: UL_L1_POST\r

1239 BBU Pooling: next taskList of DL_L1_POST: N/A\r

1240 \r

1241 BBU Pooling: next taskList of UL_L1_POST: N/A\r

1242 \r

1243 enter RtThread Launch\r

1244 3 thread associated with queue 0:coreIdx 0 1 2\r

1245 Leave RtThread Launch\r

1246 launching Thread 0 Queue 0 uCoreIdx 0 CoreId 3 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

1247 \r

1248 launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

1249 \r

1250 launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

1251 \r

1252 bbupool_core_main: the server's coreNum = 40, the nCore = 3,nRtCoreMask = 0x68, the nFeIfCore = 0,nFeIfCoreMask = 0x0\r

1253 bbupool_core_main pthread_setaffinity_np succeed: coreId = 0, result = 0\r

1254 nr5g_gnb_mac2phy_api_proc_print_phy_init [0]:\r

1255 nCarrierIdx: 0\r

1256 nDMRSTypeAPos: 2\r

1257 nPhyCellId: 100\r

1258 nDLAbsFrePointA: 27968160\r

1259 nULAbsFrePointA: 27968160\r

1260 nDLBandwidth: 100\r

1261 nULBandwidth: 100\r

1262 nDLFftSize: 1024\r

1263 nULFftSize: 1024\r

1264 nSSBPwr: 0\r

1265 nSSBAbsFre: 0\r

1266 nSSBPeriod: 2\r

1267 nSSBSubcSpacing: 3\r

1268 nSSBSubcOffset: 0\r

1269 nSSBPrbOffset: 0\r

1270 nMIB[0]: 255\r

1271 nMIB[1]: 255\r

1272 nMIB[2]: 255\r

1273 nDLK0: 0\r

1274 nULK0: 0\r

1275 nSSBMask[0]: 63\r

1276 nSSBMask[1]: 0\r

1277 nNrOfTxAnt: 2\r

1278 nNrOfRxAnt: 2\r

1279 nNrOfDLPorts: 2\r

1280 nNrOfULPorts: 2\r

1281 nCarrierAggregationLevel: 0\r

1282 nFrameDuplexType: 1\r

1283 nSubcCommon: 3\r

1284 nTddPeriod: 5 (TDD)\r

1285 SlotConfig:\r

1286 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r

1287 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

1288 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

1289 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

1290 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

1291 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

1292 \r

1293 nPrachConfIdx: 81\r

1294 nPrachSubcSpacing: 3\r

1295 nPrachZeroCorrConf: 2\r

1296 nPrachRestrictSet: 0\r

1297 nPrachRootSeqIdx: 0\r

1298 nPrachFreqStart: 0\r

1299 nPrachFdm: 1\r

1300 nPrachSsbRach: 0\r

1301 nPrachNrofRxRU: 2\r

1302 nCyclicPrefix: 0\r

1303 nGroupHopFlag: 0\r

1304 nSequenceHopFlag: 0\r

1305 nHoppingId: 0\r

1306 read_table: File table/common/pss_table.bin of size 381 read_size: 381\r

1307 read_table: File table/common/sss_table.bin of size 128016 read_size: 128016\r

1308 read_table: File table/common/srs_zc_36_plus.bin of size 905916 read_size: 905916\r

1309 read_table: File table/common/pucch_zc_36_plus.bin of size 383040 read_size: 383040\r

1310 read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216 read_size: 81216\r

1311 read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216 read_size: 81216\r

1312 BBU Pooling Info: maximum period length was configured, preMaxSF = 8000, postMasSF = 8000\r

1313 set_slot_type SlotPattern:\r

1314 Slot: 0 1 2 3 4\r

1315 0 DL DL DL SP UL\r

1316 \r

1317 PHYDI-INIT[from 0] PhyInstance: 0\r

1318 \r

1319 ---------------------------------------------------------\r

1320 Global Variables:\r

1321 ---------------------------------------------------------\r

1322 gCarrierAggLevel: 0\r

1323 gCarrierAggLevelInit: 1\r

1324 gSupportedAVX2 1\r

1325 ---------------------------------------------------------\r

1326 \r

1327 Received MSG_TYPE_PHY_START_REQ: 0\r

1328 Processing MSG_TYPE_PHY_START_REQ: 0\r

1329 \r

1330 xran_max_frame 99\r

1331 XRAN_UP_VF: 0x0000\r

1332 XRAN_CP_VF: 0x0001\r

1333 xran_timing_source_thread [CPU 4] [PID: 112582]\r

1334 O-DU: thread_run start time: 04/27/20 20:20:33.000000010 UTC [125]\r

1335 Start C-plane DL 25 us after TTI [trigger on sym 3]\r

1336 Start C-plane UL 55 us after TTI [trigger on sym 7]\r

1337 Start U-plane DL 50 us before OTA [offset in sym -5]\r

1338 Start U-plane UL 45 us OTA [offset in sym 6]\r

1339 C-plane to U-plane delay 25 us after TTI\r

1340 Start Sym timer 8928 ns\r

1341 interval_us 125\r

1342 PHYDI-START[from 0] PhyInstance: 0, Mode: 4, Count: 100040207, Period: 0, NumSlotPerSfn: 80\r

1343 gnb_start_xran: gxRANStarted[0] CC 1 Ant 4 AntElm 0\r

1344 XRAN front haul xran_mm_init\r

1345 xran_sector_get_instances [0]: CC 0 handle 0x7f6e397307c0\r

1346 Handle: 0x1994ce00 Instance: 0x7f6e397307c0\r

1347 gnb_start_xran [0]: CC 0 handle 0x7f6e397307c0\r

1348 Sucess xran_mm_init Instance 0x7f6e397307c0\r

1349 nSectorNum 1\r

1350 ru_0_cc_0_idx_0: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 0] nNumberOfBuffers 2240 nBufferSize 5856\r

1351 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool 0x2e817b900\r

1352 ru_0_cc_0_idx_1: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 1] nNumberOfBuffers 35840 nBufferSize 24\r

1353 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool 0x2e7266c40\r

1354 ru_0_cc_0_idx_2: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 2] nNumberOfBuffers 2240 nBufferSize 48416\r

1355 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool 0x2e5cb4600\r

1356 ru_0_cc_0_idx_3: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 3] nNumberOfBuffers 2240 nBufferSize 5856\r

1357 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool 0x2df2872c0\r

1358 ru_0_cc_0_idx_4: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 4] nNumberOfBuffers 35840 nBufferSize 24\r

1359 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool 0x2de372600\r

1360 ru_0_cc_0_idx_5: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 5] nNumberOfBuffers 2240 nBufferSize 48416\r

1361 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool 0x2dcdbffc0\r

1362 ru_0_cc_0_idx_6: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 6] nNumberOfBuffers 2240 nBufferSize 8192\r

1363 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool 0x2d6392c80\r

1364 gnb_init_xran_cp\r

1365 init xran successfully\r

1366 ----------------------------------------------------------------------------\r

1367 mem_mgr_display_size:\r

1368 Num Memory Alloc: 5,186\r

1369 Total Memory Size: 4,389,524,920\r

1370 ----------------------------------------------------------------------------\r

1371 \r

1372 \r

1373 BBU Pooling: enter multicell Activate!\r

1374 BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at 547270377116554 at sf=0 with queue 0 successfully\r

1375 BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0, activesfn = 4, CellNumInActSfn = 1\r

1376 BBU Pooling: multiCell Activate sucessfully!\r

1377 BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 3 at 547270377104408 at sf=0 with queue 0 successfully\r

1378 BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at 547270377117634 at sf=0 with queue 0 successfully\r

1379 phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5] gNumSlotPerSfn[80]\r

1380 ==== l1app Time: 5001 ms NumCarrier: 1 NumBbuCores: 3 rxPcktCnt: 93621 rachPcktCnt 46811 Total Proc Time: [ 62.00.. 98.39..209.00] usces====\r

1381 ==== [o-du][rx 619683 pps 123936 kbps 2621619][tx 1996407 pps 399281 kbps 9181862] [on_time 619683 early 0 late 0 corrupt 0 pkt_dupl 16 Total 619683] IO Util: 79.61 %\r

1382 \r

1383 \r

1384 7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::\r

1385 \r

1386 [root@xran flexran] cd ./bin/nr5g/gnb/testmac\r

1387 \r

1388 \r

1389 8. To execute test case type::\r

1390 \r

1391 ./l2.sh\r

1392 --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r

1393 \r

1394 \r

1395 where output corresponding to Test MAC::\r

1396 \r

1397 [root@sc12-xran-sub6 testmac]# ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r

1398 kernel.sched_rt_runtime_us = -1\r

1399 kernel.shmmax = 2147483648\r

1400 kernel.shmall = 2147483648\r

1401 Note: Forwarding request to 'systemctl disable irqbalance.service'.\r

1402 start 5GNR Test MAC\r

1403 =========================\r

1404 5GNR Testmac Application\r

1405 =========================\r

1406 testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: testmac_cfg.xml\r

1407 ---------------------------\r

1408 TestMacCfg.xml Version: 20.04\r

1409 ---------------------------\r

1410 --version=20.04\r

1411 --wls_dev_name=wls0\r

1412 --wlsMemorySize=0x3F600000\r

1413 --dpdkIovaMode=0\r

1414 --PhyStartMode=1\r

1415 --PhyStartPeriod=40\r

1416 --PhyStartCount=0\r

1417 --MlogSubframes=128\r

1418 --MlogCores=3\r

1419 --MlogSize=2048\r

1420 --wlsRxThread=1, 90, 0\r

1421 --systemThread=0, 0, 0\r

1422 --runThread=0, 89, 0\r

1423 --urllcThread=19, 90, 0\r

1424 \r

1425 wls_dev_filename: wls0\r

1426 sys_reg_signal_handler:[err] signal handler in NULL\r

1427 sys_reg_signal_handler:[err] signal handler in NULL\r

1428 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1596245684 [Hz]\r

1429 Ticks per usec 1596\r

1430 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r

1431 mlogSubframes (128), mlogCores(3), mlogSize(2048)\r

1432 localMLogTimerInit\r

1433 System clock (rdtsc) resolution 1596250375 [Hz]\r

1434 Ticks per us 1596\r

1435 MLog Storage: 0x7f84cae86100 -> 0x7f84caf46920 [ 788512 bytes ]\r

1436 localMLogFreqReg: 1596. Storing: 1596\r

1437 Mlog Open successful\r

1438 Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0 --iova-mode=pa\r

1439 EAL: Detected 40 lcore(s)\r

1440 EAL: Detected 1 NUMA nodes\r

1441 EAL: Auto-detected process type: SECONDARY\r

1442 EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket_112640_1f1baf0a9b316\r

1443 EAL: Selected IOVA mode 'PA'\r

1444 EAL: Probing VFIO support...\r

1445 EAL: VFIO support initialized\r

1446 EAL: PCI device 0000:19:00.0 on NUMA socket 0\r

1447 EAL: probe driver: 8086:d58 net_i40e\r

1448 EAL: PCI device 0000:19:00.1 on NUMA socket 0\r

1449 EAL: probe driver: 8086:d58 net_i40e\r

1450 EAL: PCI device 0000:1d:00.0 on NUMA socket 0\r

1451 EAL: probe driver: 8086:d58 net_i40e\r

1452 EAL: PCI device 0000:1d:00.1 on NUMA socket 0\r

1453 EAL: probe driver: 8086:d58 net_i40e\r

1454 EAL: PCI device 0000:21:00.0 on NUMA socket 0\r

1455 EAL: probe driver: 8086:158b net_i40e\r

1456 EAL: PCI device 0000:21:00.1 on NUMA socket 0\r

1457 EAL: probe driver: 8086:158b net_i40e\r

1458 EAL: PCI device 0000:21:02.0 on NUMA socket 0\r

1459 EAL: probe driver: 8086:154c net_i40e_vf\r

1460 EAL: using IOMMU type 1 (Type 1)\r

1461 EAL: PCI device 0000:21:02.1 on NUMA socket 0\r

1462 EAL: probe driver: 8086:154c net_i40e_vf\r

1463 EAL: PCI device 0000:21:0a.0 on NUMA socket 0\r

1464 EAL: probe driver: 8086:154c net_i40e_vf\r

1465 EAL: 0000:21:0a.0 cannot find TAILQ entry for PCI device!\r

1466 EAL: Requested device 0000:21:0a.0 cannot be used\r

1467 EAL: PCI device 0000:21:0a.1 on NUMA socket 0\r

1468 EAL: probe driver: 8086:154c net_i40e_vf\r

1469 EAL: 0000:21:0a.1 cannot find TAILQ entry for PCI device!\r

1470 EAL: Requested device 0000:21:0a.1 cannot be used\r

1471 EAL: PCI device 0000:67:00.0 on NUMA socket 0\r

1472 EAL: probe driver: 8086:37d2 net_i40e\r

1473 EAL: PCI device 0000:67:00.1 on NUMA socket 0\r

1474 EAL: probe driver: 8086:37d2 net_i40e\r

1475 wls_lib: Open wls0 (DPDK memzone)\r

1476 wls_lib: WLS_Open 0x2bf600000\r

1477 wls_lib: link: 1 <-> 0\r

1478 wls_lib: Mode 1\r

1479 wls_lib: WLS shared management memzone: wls0\r

1480 wls_lib: hugePageSize on the system is 1073741824\r

1481 wls_lib: WLS_Alloc [1063256064] bytes\r

1482 wls_lib: Connecting to remote peer ...\r

1483 wls_lib: Connected to remote peer\r

1484 wls_mac_create_mem_array: pMemArray[0xf3500f0] pMemArrayMemory[0x280000000] totalSize[1063256064] nBlockSize[262144] numBlocks[4056]\r

1485 WLS_EnqueueBlock [1]\r

1486 WLS inited ok [383]\r

1487 ===========================================================================================================\r

1488 TESTMAC VERSION\r

1489 ===========================================================================================================\r

1490 $Version: #DIRTY# $ (x86)\r

1491 IMG-date: Apr 27 2020\r

1492 IMG-time: 12:55:58\r

1493 ===========================================================================================================\r

1494 ===========================================================================================================\r

1495 Testmac threads in application\r

1496 ===========================================================================================================\r

1497 testmac_run_thread: [PID: 112644] binding on [CPU 0] [PRIO: 89] [POLICY: 1]\r

1498 wls_mac_rx_task: [PID: 112643] binding on [CPU 1] [PRIO: 90] [POLICY: 1]\r

1499 ===========================================================================================================\r

1500 \r

1501 testmac_set_phy_start: mode[1], period[40], count[0]\r

1502 \r

1503 testmac_run_load_files:\r

1504 Loading DL Config Files:\r

1505 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg\r

1506 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg\r

1507 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg\r

1508 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg\r

1509 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg\r

1510 Loading UL Config Files:\r

1511 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg\r

1512 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg\r

1513 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg\r

1514 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg\r

1515 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg\r

1516 Loading FD Config Files:\r

1517 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg\r

1518 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg\r

1519 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg\r

1520 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg\r

1521 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg\r

1522 testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg\r

1523 \r

1524 TESTMAC DL TESTS:\r

1525 Numerology[0] Bandwidth[5]\r

1526 1001 1002 1003 1004 1005 1006 1007 1008\r

1527 Numerology[0] Bandwidth[10]\r

1528 1001 1002 1003 1004 1005 1006 1007 1008\r

1529 Numerology[0] Bandwidth[20]\r

1530 1001 1002 1003 1004 1005 1006 1007 1008\r

1531 Numerology[1] Bandwidth[100]\r

1532 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211\r

1533 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221\r

1534 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241\r

1535 1242 1243 1244 1245 1250 1251 1252 1300 1301 1302\r

1536 1303 1304 1305 1402 1404 1408 1416 1500 1501 1502\r

1537 1503 1504 1505 1506 2213 2214 2215 2217 2218 2219\r

1538 2223 2224 2225 2227 2228 2229 2500 2501 2502 2503\r

1539 2504 3213 3214 3215 3217 3218 3219 3223 3224 3225\r

1540 3227 3228 3229\r

1541 Numerology[3] Bandwidth[100]\r

1542 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011\r

1543 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031\r

1544 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003\r

1545 3030\r

1546 \r

1547 TESTMAC UL TESTS:\r

1548 Numerology[0] Bandwidth[5]\r

1549 1001 1002 1003\r

1550 Numerology[0] Bandwidth[10]\r

1551 1001 1002\r

1552 Numerology[0] Bandwidth[20]\r

1553 1001 1002 1003 1004 1005 1006 1007 1008\r

1554 Numerology[1] Bandwidth[100]\r

1555 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038\r

1556 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074\r

1557 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092\r

1558 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105\r

1559 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117\r

1560 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132\r

1561 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142\r

1562 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160\r

1563 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170\r

1564 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206\r

1565 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216\r

1566 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233\r

1567 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421\r

1568 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431\r

1569 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504\r

1570 1505 1506 1507 1508 1511 1512 1513 1514 1515 1516\r

1571 1540 1541 1542 1563 1564 1565 1566 1567 1568 1569\r

1572 1570 1571 1572 1573 1574 1600 1601 1602 1603 1604\r

1573 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614\r

1574 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624\r

1575 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634\r

1576 1635 1636 1637 1638 1639 1640 1641 1642 1700 1701\r

1577 2236 2237 3236 3237\r

1578 Numerology[3] Bandwidth[100]\r

1579 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012\r

1580 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026\r

1581 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036\r

1582 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051\r

1583 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065\r

1584 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084\r

1585 1085 1086 2001 2002 2003 3001 3002 3003\r

1586 \r

1587 TESTMAC FD TESTS:\r

1588 Numerology[0] Bandwidth[5]\r

1589 1001 6001 8001 10001 12001\r

1590 Numerology[0] Bandwidth[10]\r

1591 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002\r

1592 6002 8002 10002 12002 1003\r

1593 Numerology[0] Bandwidth[20]\r

1594 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021\r

1595 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201\r

1596 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221\r

1597 1222 1223 1224 1225 1226 1227 1228\r

1598 Numerology[1] Bandwidth[40]\r

1599 1001 1002 1003\r

1600 Numerology[1] Bandwidth[100]\r

1601 1001 1200 1201 1202 1203 1204 1205 1206 1207 1208\r

1602 1209 1210 1300 1301 1302 1303 1304 1305 1306 1307\r

1603 1308 1350 1351 1352 1353 1354 1355 1356 1357 1358\r

1604 1370 1371 1372 1373 1401 1402 1403 1404 1405 1406\r

1605 1411 1412 1490 1494 1500 1501 1502 1503 1504 1510\r

1606 1511 1512 1513 1514 1515 1520 1521 1522 1523 1524\r

1607 1525 1526 1527 1528 1529 1530 1531 1532 1540 1541\r

1608 1700 1701 1702 2520 2521 2522 2523 2524 2525 2526\r

1609 2527 2528 2529 2530 2531 2532 3524 3525 3526 3527\r

1610 3528 3529 3530 3531 3532 4524 4525 4526 4527 4528\r

1611 4529 4530 4531 4532\r

1612 Numerology[3] Bandwidth[100]\r

1613 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011\r

1614 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080\r

1615 1081 1082 2001 3001\r

1616 testmac_run_parse_file Parsing config file: ./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r

1617 testmac_set_phy_start: mode[4], period[0], count[100040200]\r

1618 Adding Test[1002]. NumCarr[1], Current Directory: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/\r

1619 Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg\r

1620 ----------------------------------------------------------------------------------------\r

1621 Running Test[1002]. NumCarr[1], Current Directory: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/\r

1622 Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg\r

1623 TESTMAC>welcome to application console\r

1624 \r

1625 MLogRestart\r

1626 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r

1627 mlogSubframes (128), mlogCores(3), mlogSize(2048)\r

1628 localMLogTimerInit\r

1629 System clock (rdtsc) resolution 1596249901 [Hz]\r

1630 Ticks per us 1596\r

1631 MLog Storage: 0x7f84bc000900 -> 0x7f84bc0c1120 [ 788512 bytes ]\r

1632 localMLogFreqReg: 1596. Storing: 1596\r

1633 Mlog Open successful\r

1634 \r

1635 testmac_mac2phy_set_num_cells: Setting Max Cells: 1\r

1636 testmac_config_parse: test_num[1002] test_type[2] numcarrier[1]\r

1637 host_config_set_int Error(nPrachSsbRach, 3): Out of range: [min(0), max(1)]\r

1638 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r

1639 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r

1640 Queueing MSG_TYPE_PHY_CONFIG_REQ(0) and sending list\r

1641 Received MSG_TYPE_PHY_CONFIG_RESP(0)\r

1642 Queueing MSG_TYPE_PHY_START_REQ(0) and sending list\r

1643 Received MSG_TYPE_PHY_START_RESP(0)\r

1644 ==== testmac Time: 5000 ms NumCarrier: 1 Total Proc Time: [ 0.00.. 4.11.. 14.00] usces====\r

1645 Core Utilization [Core: 1] [Util %: 2.97%]\r

1646 ==== testmac Time: 10000 ms NumCarrier: 1 Total Proc Time: [ 2.00.. 4.10.. 13.00] usces====\r

1647 Core Utilization [Core: 1] [Util %: 4.81%]\r

1648 ==== testmac Time: 15000 ms NumCarrier: 1 Total Proc Time: [ 2.00.. 4.10.. 6.00] usces====\r

1649 \r

1650 \r

1651 Configure FlexRAN 5G NR L1 Application for multiple O-RUs with multiple numerologies\r

1652 ====================================================================================\r

1653 \r

1654 The 5G NR layer 1 application can be used for executing the scenario for\r

1655 multiple cells with multiple numerologies. The current release supports\r

1656 the constant configuration of different numerologies on different O-RU\r

1657 ports. It is required that the first O-RU (O-RU0) to be configured with\r

1658 highest numerology. The configuration procedure is similar as described\r

1659 in above section. Please refer to the configuration file located in\r

1660 bin\nr5g\gnb\l1\orancfg\sub3_mu0_20mhz_sub6_mu1_100mhz_4x4\gnb\xrancfg_sub6_oru.xml\r

1661 \r

1662 Install and Configure FlexRAN 5G NR L1 Application for Massive - MIMO\r

1663 =====================================================================\r

1664 \r

1665 The 5G NR layer 1 application can be used for executing the scenario for\r

1666 Massive-MIMO with either the RU sample application or just the O-DU\r

1667 side. 3 cells scenario with 64T64R Massive MIMO is targeted for Icelake\r

1668 system with Columbiavile NIC. The current release supports the constant\r

1669 configuration of the slot pattern and RB allocation on the PHY side.\r

1670 Please follow the general build process in the FlexRAN 5G NR Reference\r

1671 Solution L1 User Guide (refer to Table 2.)\r

1672 \r

1673 1. xRAN library is enabled by default l1 application\r

1674 \r

1675 2. Build the 5G NR L1 application using the command::\r

1676 \r

1677 ./flexran_build.sh -r 5gnr_l1app_sub6 -i snc -m sdk -m fb -m mlog –m wls\r

1678 -m 5gnr_l1app_mmw -m xran -m 5gnr_testmac\r

1679 \r

1680 3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml. ::\r

1681 \r

1682 <XranConfig>\r

1683 <version>20.08</version>\r

1684 \r

1685 <oRuNum>3</oRuNum>\r

1686 \r

1687 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>\r

1688 \r

1689 <oRuLinesNumber>2</oRuLinesNumber>\r

1690 \r

1691 <oRuCUon1Vf>1</oRuCUon1Vf>\r

1692 \r

1693 \r

1694 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>\r

1695 <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>\r

1696 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>\r

1697 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>\r

1698 \r

1699 \r

1700 <PciBusAddoRu1Vf0>0000:51:01.2</PciBusAddoRu1Vf0>\r

1701 <PciBusAddoRu1Vf1>0000:51:01.3</PciBusAddoRu1Vf1>\r

1702 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>\r

1703 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>\r

1704 \r

1705 \r

1706 <PciBusAddoRu2Vf0>0000:51:01.4</PciBusAddoRu2Vf0>\r

1707 <PciBusAddoRu2Vf1>0000:51:01.5</PciBusAddoRu2Vf1>\r

1708 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>\r

1709 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>\r

1710 \r

1711 \r

1712 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>\r

1713 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>\r

1714 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>\r

1715 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>\r

1716 \r

1717 \r

1718 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>\r

1719 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>\r

1720 \r

1721 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>\r

1722 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>\r

1723 \r

1724 \r

1725 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>\r

1726 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>\r

1727 \r

1728 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>\r

1729 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>\r

1730 \r

1731 \r

1732 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>\r

1733 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>\r

1734 \r

1735 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>\r

1736 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>\r

1737 \r

1738 \r

1739 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>\r

1740 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>\r

1741 \r

1742 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>\r

1743 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>\r

1744 \r

1745 \r

1746 <oRu0NumCc>1</oRu0NumCc>\r

1747 \r

1748 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>\r

1749 \r

1750 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>\r

1751 \r

1752 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>\r

1753 \r

1754 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>\r

1755 \r

1756 \r

1757 <oRu1NumCc>1</oRu1NumCc>\r

1758 \r

1759 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>\r

1760 \r

1761 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>\r

1762 \r

1763 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>\r

1764 \r

1765 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>\r

1766 \r

1767 \r

1768 <oRu2NumCc>1</oRu2NumCc>\r

1769 \r

1770 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>\r

1771 \r

1772 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>\r

1773 \r

1774 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>\r

1775 \r

1776 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>\r

1777 \r

1778 \r

1779 <xRANThread>22, 96, 0</xRANThread>\r

1780 \r

1781 \r

1782 <xRANWorker>0x3800000, 96, 0</xRANWorker>\r

1783 \r

1784 <Category>1</Category>\r

1785 \r

1786 \r

1787 <xranPmdSleep>0</xranPmdSleep>\r

1788 \r

1789 \r

1790 <Tadv_cp_dl>25</Tadv_cp_dl>\r

1791 \r

1792 <T2a_min_cp_dl>285</T2a_min_cp_dl>\r

1793 <T2a_max_cp_dl>429</T2a_max_cp_dl>\r

1794 \r

1795 <T2a_min_cp_ul>285</T2a_min_cp_ul>\r

1796 <T2a_max_cp_ul>429</T2a_max_cp_ul>\r

1797 \r

1798 <T2a_min_up>71</T2a_min_up>\r

1799 <T2a_max_up>428</T2a_max_up>\r

1800 \r

1801 <Ta3_min>20</Ta3_min>\r

1802 <Ta3_max>32</Ta3_max>\r

1803 \r

1804 \r

1805 \r

1806 <MTU>9600</MTU>\r

1807 \r

1808 <c_plane_vlan_tag>1</c_plane_vlan_tag>\r

1809 <u_plane_vlan_tag>2</u_plane_vlan_tag>\r

1810 \r

1811 \r

1812 <T1a_min_cp_dl>258</T1a_min_cp_dl>\r

1813 <T1a_max_cp_dl>429</T1a_max_cp_dl>\r

1814 \r

1815 <T1a_min_cp_ul>285</T1a_min_cp_ul>\r

1816 <T1a_max_cp_ul>300</T1a_max_cp_ul>\r

1817 \r

1818 <T1a_min_up>96</T1a_min_up>\r

1819 <T1a_max_up>196</T1a_max_up>\r

1820 \r

1821 <Ta4_min>0</Ta4_min>\r

1822 <Ta4_max>75</Ta4_max>\r

1823 \r

1824 \r

1825 <EnableCp>1</EnableCp>\r

1826 \r

1827 <DynamicSectionEna>0</DynamicSectionEna>\r

1828 \r

1829 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>\r

1830 <xRANSFNWrap>1</xRANSFNWrap>\r

1831 \r

1832 <xRANNumDLPRBs>0</xRANNumDLPRBs>\r

1833 \r

1834 <xRANNumULPRBs>0</xRANNumULPRBs>\r

1835 \r

1836 <Gps_Alpha>0</Gps_Alpha>\r

1837 \r

1838 <Gps_Beta>0</Gps_Beta>\r

1839 \r

1840 \r

1841 <xranCompMethod>1</xranCompMethod>\r

1842 \r

1843 <oRu0nPrbElemDl>6</oRu0nPrbElemDl>\r

1844 \r

1845 \r

1846 <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>\r

1847 <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>\r

1848 <oRu0PrbElemDl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl2>\r

1849 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>\r

1850 <oRu0PrbElemDl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>\r

1851 <oRu0PrbElemDl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>\r

1852 <oRu0PrbElemDl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>\r

1853 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>\r

1854 \r

1855 \r

1856 <oRu0ExtBfwDl0>2,24,0,0,9,1</oRu0ExtBfwDl0>\r

1857 <oRu0ExtBfwDl1>2,24,0,0,9,1</oRu0ExtBfwDl1>\r

1858 <oRu0ExtBfwDl2>2,24,0,0,9,1</oRu0ExtBfwDl2>\r

1859 <oRu0ExtBfwDl3>2,24,0,0,9,1</oRu0ExtBfwDl3>\r

1860 <oRu0ExtBfwDl4>2,24,0,0,9,1</oRu0ExtBfwDl4>\r

1861 <oRu0ExtBfwDl5>2,17,0,0,9,1</oRu0ExtBfwDl5>\r

1862 \r

1863 <oRu0nPrbElemUl>6</oRu0nPrbElemUl>\r

1864 \r

1865 \r

1866 <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>\r

1867 <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>\r

1868 <oRu0PrbElemUl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl2>\r

1869 <oRu0PrbElemUl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>\r

1870 <oRu0PrbElemUl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>\r

1871 <oRu0PrbElemUl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>\r

1872 <oRu0PrbElemUl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>\r

1873 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>\r

1874 \r

1875 \r

1876 <oRu0ExtBfwUl0>2,24,0,0,9,1</oRu0ExtBfwUl0>\r

1877 <oRu0ExtBfwUl1>2,24,0,0,9,1</oRu0ExtBfwUl1>\r

1878 <oRu0ExtBfwUl2>2,24,0,0,9,1</oRu0ExtBfwUl2>\r

1879 <oRu0ExtBfwUl3>2,24,0,0,9,1</oRu0ExtBfwUl3>\r

1880 <oRu0ExtBfwUl4>2,24,0,0,9,1</oRu0ExtBfwUl4>\r

1881 <oRu0ExtBfwUl5>2,17,0,0,9,1</oRu0ExtBfwUl5>\r

1882 \r

1883 <oRu0nPrbElemSrs>1</oRu0nPrbElemSrs>\r

1884 \r

1885 \r

1886 <oRu0PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs0>\r

1887 \r

1888 <oRu1nPrbElemDl>2</oRu1nPrbElemDl>\r

1889 \r

1890 \r

1891 <oRu1PrbElemDl0>0,48,0,14,0,1,1,9,1,0,0</oRu1PrbElemDl0>\r

1892 <oRu1PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemDl1>\r

1893 <oRu1PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu1PrbElemDl2>\r

1894 <oRu1PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu1PrbElemDl3>\r

1895 <oRu1PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemDl4>\r

1896 <oRu1PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemDl5>\r

1897 <oRu1PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemDl6>\r

1898 <oRu1PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemDl7>\r

1899 \r

1900 \r

1901 <oRu1ExtBfwDl0>2,24,0,0,9,1</oRu1ExtBfwDl0>\r

1902 <oRu1ExtBfwDl1>2,24,0,0,9,1</oRu1ExtBfwDl1>\r

1903 \r

1904 <oRu1nPrbElemUl>2</oRu1nPrbElemUl>\r

1905 \r

1906 \r

1907 <oRu1PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu1PrbElemUl0>\r

1908 <oRu1PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemUl1>\r

1909 <oRu1PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu1PrbElemUl2>\r

1910 <oRu1PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu1PrbElemUl3>\r

1911 <oRu1PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemUl4>\r

1912 <oRu1PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemUl5>\r

1913 <oRu1PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemUl6>\r

1914 <oRu1PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemUl7>\r

1915 \r

1916 \r

1917 <oRu1ExtBfwUl0>2,24,0,0,9,1</oRu1ExtBfwUl0>\r

1918 <oRu1ExtBfwUl1>2,24,0,0,9,1</oRu1ExtBfwUl1>\r

1919 \r

1920 <oRu1nPrbElemSrs>1</oRu1nPrbElemSrs>\r

1921 \r

1922 \r

1923 <oRu1PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs0>\r

1924 \r

1925 <oRu2nPrbElemDl>2</oRu2nPrbElemDl>\r

1926 \r

1927 \r

1928 <oRu2PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemDl0>\r

1929 <oRu2PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemDl1>\r

1930 <oRu2PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu2PrbElemDl2>\r

1931 <oRu2PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu2PrbElemDl3>\r

1932 <oRu2PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemDl4>\r

1933 <oRu2PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemDl5>\r

1934 <oRu2PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemDl6>\r

1935 <oRu2PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemDl7>\r

1936 \r

1937 \r

1938 <oRu2ExtBfwDl0>2,24,0,0,9,1</oRu2ExtBfwDl0>\r

1939 <oRu2ExtBfwDl1>2,24,0,0,9,1</oRu2ExtBfwDl1>\r

1940 \r

1941 <oRu2nPrbElemUl>2</oRu2nPrbElemUl>\r

1942 \r

1943 \r

1944 <oRu2PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemUl0>\r

1945 <oRu2PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemUl1>\r

1946 <oRu2PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu2PrbElemUl2>\r

1947 <oRu2PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu2PrbElemUl3>\r

1948 <oRu2PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemUl4>\r

1949 <oRu2PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemUl5>\r

1950 <oRu2PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemUl6>\r

1951 <oRu2PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemUl7>\r

1952 \r

1953 \r

1954 <oRu2ExtBfwUl0>2,24,0,0,9,1</oRu2ExtBfwUl0>\r

1955 <oRu2ExtBfwUl1>2,24,0,0,9,1</oRu2ExtBfwUl1>\r

1956 \r

1957 <oRu2nPrbElemSrs>1</oRu2nPrbElemSrs>\r

1958 \r

1959 \r

1960 <oRu2PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs0>\r

1961 \r

1962 </XranConfig>\r

1963 \r

1964 \r

1965 4. Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::\r

1966 \r

1967 ethDevice0=0000:51:01.0\r

1968 ethDevice1=0000:51:01.1\r

1969 ethDevice2=0000:51:01.2\r

1970 ethDevice3=0000:51:01.3\r

1971 ethDevice4=0000:51:01.4\r

1972 ethDevice5=0000:51:01.5\r

1973 ethDevice6=\r

1974 ethDevice7=\r

1975 ethDevice8=\r

1976 ethDevice9=\r

1977 ethDevice10=\r

1978 ethDevice11=\r

1979 fecDevice0=0000:92:00.0\r

1980 \r

1981 5. Use configuration of test mac per::\r

1982 \r

1983 /bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg\r

1984 phystart 4 0 100200\r

1985 TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg,\r

1986 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg,\r

1987 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r

1988 \r

1989 6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::\r

1990 \r

1991 [root@xran flexran] cd ./bin/nr5g/gnb/l1\r

1992 ./l1.sh -xranmmimo\r

1993 Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB)\r

1994 DPDK WLS MODE\r

1995 kernel.sched_rt_runtime_us = -1\r

1996 kernel.shmmax = 2147483648\r

1997 kernel.shmall = 2147483648\r

1998 Note: Forwarding request to 'systemctl disable irqbalance.service'.\r

1999 using configuration file phycfg_xran.xml\r

2000 using configuration file xrancfg_sub6_mmimo.xml\r

2001 >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran.xml --xranfile=xrancfg_sub6_mmimo.xml\r

2002 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r

2003 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r

2004 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r

2005 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r

2006 FlexRAN SDK bblib_llr_demapping version #DIRTY#\r

2007 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r

2008 FlexRAN SDK bblib_reed_muller version #DIRTY#\r

2009 FlexRAN SDK bblib_lte_modulation version #DIRTY#\r

2010 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r

2011 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r

2012 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r

2013 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r

2014 FlexRAN SDK bblib_fd_correlation version #DIRTY#\r

2015 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r

2016 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r

2017 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r

2018 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r

2019 FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r

2020 FlexRAN SDK bblib_fft_ifft version #DIRTY#\r

2021 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r

2022 FlexRAN SDK bblib_lte_ldpc_decoder version #DIRTY#\r

2023 FlexRAN SDK bblib_lte_ldpc_encoder version #DIRTY#\r

2024 FlexRAN SDK bblib_lte_LDPC_ratematch version #DIRTY#\r

2025 FlexRAN SDK bblib_lte_rate_dematching_5gnr version #DIRTY#\r

2026 FlexRAN SDK bblib_common version #DIRTY#\r

2027 FlexRAN SDK bblib_lte_crc version #DIRTY#\r

2028 FlexRAN SDK bblib_lte_dft_idft version #DIRTY#\r

2029 FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY#\r

2030 FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY#\r

2031 FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY#\r

2032 FlexRAN SDK bblib_zf_matrix_gen version #DIRTY#\r

2033 FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY#\r

2034 =========================\r

2035 5GNR PHY Application\r

2036 =========================\r

2037 \r

2038 \r

2039 --------------------------------------------------------\r

2040 File[phycfg_xran.xml] Version: 20.08\r

2041 --------------------------------------------------------\r

2042 --version=20.08\r

2043 --successiveNoApi=15\r

2044 --wls_dev_name=wls0\r

2045 --wlsMemorySize=0x3F600000\r

2046 --dlIqLog=0\r

2047 --ulIqLog=0\r

2048 --iqLogDumpToFile=0\r

2049 --phyMlog=1\r

2050 --phyStats=1\r

2051 --dpdkMemorySize=18432\r

2052 --dpdkIovaMode=0\r

2053 --dpdkBasebandFecMode=1\r

2054 --dpdkBasebandDevice=0000:92:00.0\r

2055 --radioEnable=4\r

2056 --ferryBridgeMode=1\r

2057 --ferryBridgeEthPort=1\r

2058 --ferryBridgeSyncPorts=0\r

2059 --ferryBridgeOptCableLoopback=0\r

2060 --radioCfg0PCIeEthDev=0000:19:00.0\r

2061 --radioCfg0DpdkRx=1\r

2062 --radioCfg0DpdkTx=2\r

2063 --radioCfg0TxAnt=2\r

2064 --radioCfg0RxAnt=2\r

2065 --radioCfg0RxAgc=0\r

2066 --radioCfg0NumCell=1\r

2067 --radioCfg0Cell0PhyId=0\r

2068 --radioCfg0Cell1PhyId=1\r

2069 --radioCfg0Cell2PhyId=2\r

2070 --radioCfg0Cell3PhyId=3\r

2071 --radioCfg0Cell4PhyId=4\r

2072 --radioCfg0Cell5PhyId=5\r

2073 --radioCfg0riuMac=11:22:33:44:55:66\r

2074 --radioCfg1PCIeEthDev=0000:03:00.1\r

2075 --radioCfg1DpdkRx=1\r

2076 --radioCfg1DpdkTx=1\r

2077 --radioCfg1TxAnt=4\r

2078 --radioCfg1RxAnt=4\r

2079 --radioCfg1RxAgc=0\r

2080 --radioCfg1NumCell=1\r

2081 --radioCfg1Cell0PhyId=2\r

2082 --radioCfg1Cell1PhyId=3\r

2083 --radioCfg1Cell2PhyId=2\r

2084 --radioCfg1Cell3PhyId=3\r

2085 --radioCfg1riuMac=ac:1f:6b:2c:9f:07\r

2086 --radioCfg2PCIeEthDev=0000:05:00.0\r

2087 --radioCfg2DpdkRx=10\r

2088 --radioCfg2DpdkTx=11\r

2089 --radioCfg2TxAnt=4\r

2090 --radioCfg2RxAnt=4\r

2091 --radioCfg2RxAgc=0\r

2092 --radioCfg2NumCell=2\r

2093 --radioCfg2Cell0PhyId=4\r

2094 --radioCfg2Cell1PhyId=5\r

2095 --radioCfg2Cell2PhyId=2\r

2096 --radioCfg2Cell3PhyId=3\r

2097 --radioCfg2riuMac=ac:1f:6b:2c:9f:07\r

2098 --radioCfg3PCIeEthDev=0000:05:00.1\r

2099 --radioCfg3DpdkRx=12\r

2100 --radioCfg3DpdkTx=13\r

2101 --radioCfg3TxAnt=4\r

2102 --radioCfg3RxAnt=4\r

2103 --radioCfg3RxAgc=0\r

2104 --radioCfg3NumCell=2\r

2105 --radioCfg3Cell0PhyId=6\r

2106 --radioCfg3Cell1PhyId=7\r

2107 --radioCfg3Cell2PhyId=2\r

2108 --radioCfg3Cell3PhyId=3\r

2109 --radioCfg3riuMac=ac:1f:6b:2c:9f:07\r

2110 --radioCfg4PCIeEthDev=0000:00:08.0\r

2111 --radioCfg4DpdkRx=14\r

2112 --radioCfg4DpdkTx=15\r

2113 --radioCfg4TxAnt=4\r

2114 --radioCfg4RxAnt=4\r

2115 --radioCfg4RxAgc=0\r

2116 --radioCfg4NumCell=2\r

2117 --radioCfg4Cell0PhyId=8\r

2118 --radioCfg4Cell1PhyId=9\r

2119 --radioCfg4Cell2PhyId=2\r

2120 --radioCfg4Cell3PhyId=3\r

2121 --radioCfg4riuMac=ac:1f:6b:2c:9f:07\r

2122 --radioCfg5PCIeEthDev=0000:08:00.0\r

2123 --radioCfg5DpdkRx=16\r

2124 --radioCfg5DpdkTx=16\r

2125 --radioCfg5TxAnt=4\r

2126 --radioCfg5RxAnt=4\r

2127 --radioCfg5RxAgc=0\r

2128 --radioCfg5NumCell=2\r

2129 --radioCfg5Cell0PhyId=10\r

2130 --radioCfg5Cell1PhyId=11\r

2131 --radioCfg5Cell2PhyId=2\r

2132 --radioCfg5Cell3PhyId=3\r

2133 --radioCfg5riuMac=ac:1f:6b:2c:9f:07\r

2134 --radioCfg6PCIeEthDev=0000:00:05.0\r

2135 --radioCfg6DpdkRx=16\r

2136 --radioCfg6DpdkTx=16\r

2137 --radioCfg6TxAnt=4\r

2138 --radioCfg6RxAnt=4\r

2139 --radioCfg1RxAgc=0\r

2140 --radioCfg6NumCell=2\r

2141 --radioCfg6Cell0PhyId=12\r

2142 --radioCfg6Cell1PhyId=13\r

2143 --radioCfg6Cell2PhyId=2\r

2144 --radioCfg6Cell3PhyId=3\r

2145 --radioCfg6riuMac=ac:1f:6b:2c:9f:07\r

2146 --radioCfg7PCIeEthDev=0000:00:06.0\r

2147 --radioCfg7DpdkRx=16\r

2148 --radioCfg7DpdkTx=16\r

2149 --radioCfg7TxAnt=4\r

2150 --radioCfg7RxAnt=4\r

2151 --radioCfg7RxAgc=0\r

2152 --radioCfg7NumCell=2\r

2153 --radioCfg7Cell0PhyId=14\r

2154 --radioCfg7Cell1PhyId=15\r

2155 --radioCfg7Cell2PhyId=2\r

2156 --radioCfg7Cell3PhyId=3\r

2157 --radioCfg7riuMac=ac:1f:6b:2c:9f:07\r

2158 --radioPort0=0\r

2159 --radioPort1=1\r

2160 --radioPort2=2\r

2161 --radioPort3=3\r

2162 --radioPort4=4\r

2163 --radioPort5=5\r

2164 --radioPort6=6\r

2165 --radioPort7=7\r

2166 --PdschSymbolSplit=0\r

2167 --PdschDlWeightSplit=0\r

2168 --FecEncSplit=4\r

2169 --PuschChanEstSplit=0\r

2170 --PuschMmseSplit=0\r

2171 --PuschLlrRxSplit=0\r

2172 --PuschUlWeightSplit=0\r

2173 --FecDecEarlyTermDisable=0\r

2174 --FecDecNumIter=12\r

2175 --FecDecSplit=4\r

2176 --llrOutDecimalDigit=2\r

2177 --IrcEnableThreshold=-10\r

2178 --PuschNoiseScale=2\r

2179 --CEInterpMethod=0\r

2180 --PucchSplit=0\r

2181 --SrsCeSplit=0\r

2182 --prachDetectThreshold=0\r

2183 --MlogSubframes=128\r

2184 --MlogCores=40\r

2185 --MlogSize=10000\r

2186 --systemThread=2, 0, 0\r

2187 --timerThread=0, 96, 0\r

2188 --FpgaDriverCpuInfo=3, 96, 0\r

2189 --FrontHaulCpuInfo=3, 96, 0\r

2190 --radioDpdkMaster=2, 99, 0\r

2191 --BbuPoolSleepEnable=1\r

2192 --BbuPoolThreadCorePriority=94\r

2193 --BbuPoolThreadCorePolicy=0\r

2194 --BbuPoolThreadDefault_0_63=0xF0\r

2195 --BbuPoolThreadDefault_64_127=0x0\r

2196 --BbuPoolThreadSrs_0_63=0x0\r

2197 --BbuPoolThreadSrs_64_127=0x0\r

2198 --BbuPoolThreadDlbeam_0_63=0x0\r

2199 --BbuPoolThreadDlbeam_64_127=0x0\r

2200 --BbuPoolThreadUrllc=0x100\r

2201 --FrontHaulTimeAdvance=7450\r

2202 --nEthPorts=462607\r

2203 --nPhaseCompFlag=0\r

2204 --nFecFpgaVersionMu3=0x20010900\r

2205 --nFecFpgaVersionMu0_1=0x0423D420\r

2206 --nFhFpgaVersionMu3=0x8001000F\r

2207 --nFhFpgaVersionMu0_1=0x90010008\r

2208 --StreamStats=0\r

2209 --StreamIp=10.255.83.5\r

2210 --StreamPort=4010\r

2211 \r

2212 wls_dev_filename: wls0\r

2213 phycfg_apply: Initialize Radio Interface with XRAN library\r

2214 Setting FecEncSplit to 1 to run on HW accelerator\r

2215 Setting FecDecSplit to 1 to run on HW accelerator\r

2216 \r

2217 \r

2218 \r

2219 --------------------------------------------------------\r

2220 File[xrancfg_sub6_mmimo.xml] Version: 20.08\r

2221 --------------------------------------------------------\r

2222 --version=20.08\r

2223 --oRuNum=3\r

2224 --oRuEthLinkSpeed=25\r

2225 --oRuLinesNumber=2\r

2226 --oRuCUon1Vf=1\r

2227 --PciBusAddoRu0Vf0=0000:51:01.0\r

2228 --PciBusAddoRu0Vf1=0000:51:01.1\r

2229 --PciBusAddoRu0Vf2=0000:51:01.2\r

2230 --PciBusAddoRu0Vf3=0000:51:01.3\r

2231 --PciBusAddoRu1Vf0=0000:51:01.2\r

2232 --PciBusAddoRu1Vf1=0000:51:01.3\r

2233 --PciBusAddoRu1Vf2=0000:51:01.6\r

2234 --PciBusAddoRu1Vf3=0000:51:01.7\r

2235 --PciBusAddoRu2Vf0=0000:51:01.4\r

2236 --PciBusAddoRu2Vf1=0000:51:01.5\r

2237 --PciBusAddoRu2Vf2=0000:51:02.2\r

2238 --PciBusAddoRu2Vf3=0000:51:02.3\r

2239 --PciBusAddoRu3Vf0=0000:00:00.0\r

2240 --PciBusAddoRu3Vf1=0000:00:00.0\r

2241 --PciBusAddoRu3Vf2=0000:00:00.0\r

2242 --PciBusAddoRu3Vf3=0000:00:00.0\r

2243 --oRuRem0Mac0=00:11:22:33:00:01\r

2244 --oRuRem0Mac1=00:11:22:33:00:11\r

2245 --oRuRem0Mac2=00:11:22:33:00:21\r

2246 --oRuRem0Mac3=00:11:22:33:00:31\r

2247 --oRuRem1Mac0=00:11:22:33:01:01\r

2248 --oRuRem1Mac1=00:11:22:33:01:11\r

2249 --oRuRem1Mac2=00:11:22:33:01:21\r

2250 --oRuRem1Mac3=00:11:22:33:01:31\r

2251 --oRuRem2Mac0=00:11:22:33:02:01\r

2252 --oRuRem2Mac1=00:11:22:33:02:11\r

2253 --oRuRem2Mac2=00:11:22:33:02:21\r

2254 --oRuRem2Mac3=00:11:22:33:02:31\r

2255 --oRuRem3Mac0=00:11:22:33:03:01\r

2256 --oRuRem3Mac1=00:11:22:33:03:11\r

2257 --oRuRem3Mac2=00:11:22:33:03:21\r

2258 --oRuRem3Mac3=00:11:22:33:03:31\r

2259 --oRu0NumCc=1\r

2260 --oRu0Cc0PhyId=0\r

2261 --oRu0Cc1PhyId=1\r

2262 --oRu0Cc2PhyId=2\r

2263 --oRu0Cc3PhyId=3\r

2264 --oRu1NumCc=1\r

2265 --oRu1Cc0PhyId=1\r

2266 --oRu1Cc1PhyId=1\r

2267 --oRu1Cc2PhyId=2\r

2268 --oRu1Cc3PhyId=3\r

2269 --oRu2NumCc=1\r

2270 --oRu2Cc0PhyId=2\r

2271 --oRu2Cc1PhyId=1\r

2272 --oRu2Cc2PhyId=2\r

2273 --oRu2Cc3PhyId=3\r

2274 --xRANThread=22, 96, 0\r

2275 --xRANWorker=0x3800000, 96, 0\r

2276 --Category=1\r

2277 --xranPmdSleep=0\r

2278 --Tadv_cp_dl=25\r

2279 --T2a_min_cp_dl=285\r

2280 --T2a_max_cp_dl=429\r

2281 --T2a_min_cp_ul=285\r

2282 --T2a_max_cp_ul=429\r

2283 --T2a_min_up=71\r

2284 --T2a_max_up=428\r

2285 --Ta3_min=20\r

2286 --Ta3_max=32\r

2287 --MTU=9600\r

2288 --c_plane_vlan_tag=1\r

2289 --u_plane_vlan_tag=2\r

2290 --T1a_min_cp_dl=258\r

2291 --T1a_max_cp_dl=429\r

2292 --T1a_min_cp_ul=285\r

2293 --T1a_max_cp_ul=300\r

2294 --T1a_min_up=96\r

2295 --T1a_max_up=196\r

2296 --Ta4_min=0\r

2297 --Ta4_max=75\r

2298 --EnableCp=1\r

2299 --DynamicSectionEna=0\r

2300 --DynamicSectionEnaUL=0\r

2301 --xRANSFNWrap=1\r

2302 --xRANNumDLPRBs=0\r

2303 --xRANNumULPRBs=0\r

2304 --Gps_Alpha=0\r

2305 --Gps_Beta=0\r

2306 --xranCompMethod=1\r

2307 --oRu0nPrbElemDl=6\r

2308 --oRu0PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0\r

2309 --oRu0PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0\r

2310 --oRu0PrbElemDl2=96,48,0,14,2,1,1,9,1,0,0\r

2311 --oRu0PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0\r

2312 --oRu0PrbElemDl4=192,48,0,14,5,1,1,9,1,0,0\r

2313 --oRu0PrbElemDl5=240,33,0,14,6,1,1,9,1,0,0\r

2314 --oRu0PrbElemDl6=240,33,0,14,7,1,1,9,1,0,0\r

2315 --oRu0PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0\r

2316 --oRu0ExtBfwDl0=2,24,0,0,9,1\r

2317 --oRu0ExtBfwDl1=2,24,0,0,9,1\r

2318 --oRu0ExtBfwDl2=2,24,0,0,9,1\r

2319 --oRu0ExtBfwDl3=2,24,0,0,9,1\r

2320 --oRu0ExtBfwDl4=2,24,0,0,9,1\r

2321 --oRu0ExtBfwDl5=2,17,0,0,9,1\r

2322 --oRu0nPrbElemUl=6\r

2323 --oRu0PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0\r

2324 --oRu0PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0\r

2325 --oRu0PrbElemUl2=96,48,0,14,2,1,1,9,1,0,0\r

2326 --oRu0PrbElemUl3=144,48,0,14,4,1,1,9,1,0,0\r

2327 --oRu0PrbElemUl4=192,48,0,14,5,1,1,9,1,0,0\r

2328 --oRu0PrbElemUl5=240,33,0,14,6,1,1,9,1,0,0\r

2329 --oRu0PrbElemUl6=240,33,0,14,7,1,1,9,1,0,0\r

2330 --oRu0PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0\r

2331 --oRu0ExtBfwUl0=2,24,0,0,9,1\r

2332 --oRu0ExtBfwUl1=2,24,0,0,9,1\r

2333 --oRu0ExtBfwUl2=2,24,0,0,9,1\r

2334 --oRu0ExtBfwUl3=2,24,0,0,9,1\r

2335 --oRu0ExtBfwUl4=2,24,0,0,9,1\r

2336 --oRu0ExtBfwUl5=2,17,0,0,9,1\r

2337 --oRu0nPrbElemSrs=1\r

2338 --oRu0PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0\r

2339 --oRu1nPrbElemDl=2\r

2340 --oRu1PrbElemDl0=0,48,0,14,0,1,1,9,1,0,0\r

2341 --oRu1PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0\r

2342 --oRu1PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0\r

2343 --oRu1PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0\r

2344 --oRu1PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0\r

2345 --oRu1PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0\r

2346 --oRu1PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0\r

2347 --oRu1PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0\r

2348 --oRu1ExtBfwDl0=2,24,0,0,9,1\r

2349 --oRu1ExtBfwDl1=2,24,0,0,9,1\r

2350 --oRu1nPrbElemUl=2\r

2351 --oRu1PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0\r

2352 --oRu1PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0\r

2353 --oRu1PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0\r

2354 --oRu1PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0\r

2355 --oRu1PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0\r

2356 --oRu1PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0\r

2357 --oRu1PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0\r

2358 --oRu1PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0\r

2359 --oRu1ExtBfwUl0=2,24,0,0,9,1\r

2360 --oRu1ExtBfwUl1=2,24,0,0,9,1\r

2361 --oRu1nPrbElemSrs=1\r

2362 --oRu1PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0\r

2363 --oRu2nPrbElemDl=2\r

2364 --oRu2PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0\r

2365 --oRu2PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0\r

2366 --oRu2PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0\r

2367 --oRu2PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0\r

2368 --oRu2PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0\r

2369 --oRu2PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0\r

2370 --oRu2PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0\r

2371 --oRu2PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0\r

2372 --oRu2ExtBfwDl0=2,24,0,0,9,1\r

2373 --oRu2ExtBfwDl1=2,24,0,0,9,1\r

2374 --oRu2nPrbElemUl=2\r

2375 --oRu2PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0\r

2376 --oRu2PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0\r

2377 --oRu2PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0\r

2378 --oRu2PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0\r

2379 --oRu2PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0\r

2380 --oRu2PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0\r

2381 --oRu2PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0\r

2382 --oRu2PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0\r

2383 --oRu2ExtBfwUl0=2,24,0,0,9,1\r

2384 --oRu2ExtBfwUl1=2,24,0,0,9,1\r

2385 --oRu2nPrbElemSrs=1\r

2386 --oRu2PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0\r

2387 \r

2388 \r

2389 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1496526035 [Hz]\r

2390 Ticks per usec 1496\r

2391 MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(40), mlogSize(10000) mlog_mask (-1)\r

2392 mlogSubframes (128), mlogCores(40), mlogSize(10000)\r

2393 localMLogTimerInit\r

2394 System clock (rdtsc) resolution 1496525824 [Hz]\r

2395 Ticks per us 1496\r

2396 MLog Storage: 0x7f7403835100 -> 0x7f740690b830 [ 51210032 bytes ]\r

2397 localMLogFreqReg: 1496. Storing: 1496\r

2398 Mlog Open successful\r

2399 \r

2400 gnb_io_xran_init\r

2401 num_o_ru 3 EthLinesNumber 2 where VFs 1 per EthLine\r

2402 VF[0] 0000:51:01.0 [C+U Plane]\r

2403 VF[1] 0000:51:01.1 [C+U Plane]\r

2404 VF[2] 0000:51:01.2 [C+U Plane]\r

2405 VF[3] 0000:51:01.3 [C+U Plane]\r

2406 VF[4] 0000:51:01.4 [C+U Plane]\r

2407 VF[5] 0000:51:01.5 [C+U Plane]\r

2408 oRu0nPrbElemDl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2409 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2410 oRu0nPrbElemDl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2411 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2412 oRu0nPrbElemDl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2413 (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2414 oRu0nPrbElemDl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2415 (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2416 oRu0nPrbElemDl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2417 (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2418 oRu0nPrbElemDl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2419 (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2420 oRu0nPrbElemUl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2421 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2422 oRu0nPrbElemUl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2423 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2424 oRu0nPrbElemUl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2425 (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2426 oRu0nPrbElemUl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2427 (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2428 oRu0nPrbElemUl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2429 (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2430 oRu0nPrbElemUl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2431 (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2432 oRu0nPrbElemSrs0: oRu0: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2433 oRu1nPrbElemDl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 0, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2434 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2435 oRu1nPrbElemDl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2436 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2437 oRu1nPrbElemUl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2438 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2439 oRu1nPrbElemUl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2440 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2441 oRu1nPrbElemSrs0: oRu1: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2442 oRu2nPrbElemDl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2443 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2444 oRu2nPrbElemDl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2445 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2446 oRu2nPrbElemUl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2447 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2448 oRu2nPrbElemUl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2449 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r

2450 oRu2nPrbElemSrs0: oRu2: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r

2451 gnb_io_xran_cfg_setup successful\r

2452 xran_init: MTU 9600\r

2453 xran_init: MTU 9600\r

2454 xran_init: MTU 9600\r

2455 PF Eth line speed 25G\r

2456 PF Eth lines per O-xU port 2\r

2457 BBDEV_FEC_ACCL_NR5G\r

2458 hw-accelerated bbdev 0000:92:00.0\r

2459 total cores 48 c_mask 0x3c00004 core 22 [id] system_core 2 [id] pkt_proc_core 0x3800000 [mask] pkt_aux_core 0 [id] timing_core 22 [id]\r

2460 xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x3c00004 -n2 --iova-mode=pa --socket-mem=18432 --socket-limit=18432 --proc-type=auto --file-prefix wls0 -w 0000:00:00.0 -w 0000:92:00.0\r

2461 EAL: Detected 48 lcore(s)\r

2462 EAL: Detected 1 NUMA nodes\r

2463 EAL: Auto-detected process type: PRIMARY\r

2464 EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket\r

2465 EAL: Selected IOVA mode 'PA'\r

2466 EAL: No available hugepages reported in hugepages-2048kB\r

2467 EAL: Probing VFIO support...\r

2468 EAL: PCI device 0000:92:00.0 on NUMA socket 0\r

2469 EAL: probe driver: 8086:d8f intel_fpga_5gnr_fec_pf\r

2470 xran_init_mbuf_pool: socket 0\r

2471 EAL: PCI device 0000:51:01.0 on NUMA socket 0\r

2472 EAL: probe driver: 8086:1889 net_iavf\r

2473 initializing port 0 for TX, drv=net_iavf\r

2474 Port 0 MAC: 00 11 22 33 00 00\r

2475 Port 0: nb_rxd 4096 nb_txd 4096\r

2476 [0] mempool_rx__0\r

2477 [0] mempool_small__0\r

2478 iavf_init_rss(): RSS is enabled by PF by default\r

2479 \r

2480 Checking link status portid [0] ... done\r

2481 Port 0 Link Up - speed 100000 Mbps - full-duplex\r

2482 EAL: PCI device 0000:51:01.1 on NUMA socket 0\r

2483 EAL: probe driver: 8086:1889 net_iavf\r

2484 initializing port 1 for TX, drv=net_iavf\r

2485 Port 1 MAC: 00 11 22 33 00 10\r

2486 Port 1: nb_rxd 4096 nb_txd 4096\r

2487 [1] mempool_rx__1\r

2488 [1] mempool_small__1\r

2489 iavf_init_rss(): RSS is enabled by PF by default\r

2490 \r

2491 Checking link status portid [1] ... done\r

2492 Port 1 Link Up - speed 100000 Mbps - full-duplex\r

2493 EAL: PCI device 0000:51:01.2 on NUMA socket 0\r

2494 EAL: probe driver: 8086:1889 net_iavf\r

2495 initializing port 2 for TX, drv=net_iavf\r

2496 Port 2 MAC: 00 11 22 33 01 00\r

2497 Port 2: nb_rxd 4096 nb_txd 4096\r

2498 [2] mempool_rx__2\r

2499 [2] mempool_small__2\r

2500 iavf_init_rss(): RSS is enabled by PF by default\r

2501 \r

2502 Checking link status portid [2] ... done\r

2503 Port 2 Link Up - speed 100000 Mbps - full-duplex\r

2504 EAL: PCI device 0000:51:01.3 on NUMA socket 0\r

2505 EAL: probe driver: 8086:1889 net_iavf\r

2506 initializing port 3 for TX, drv=net_iavf\r

2507 Port 3 MAC: 00 11 22 33 01 10\r

2508 Port 3: nb_rxd 4096 nb_txd 4096\r

2509 [3] mempool_rx__3\r

2510 [3] mempool_small__3\r

2511 iavf_init_rss(): RSS is enabled by PF by default\r

2512 \r

2513 Checking link status portid [3] ... done\r

2514 Port 3 Link Up - speed 100000 Mbps - full-duplex\r

2515 EAL: PCI device 0000:51:01.4 on NUMA socket 0\r

2516 EAL: probe driver: 8086:1889 net_iavf\r

2517 initializing port 4 for TX, drv=net_iavf\r

2518 Port 4 MAC: 00 11 22 33 02 00\r

2519 Port 4: nb_rxd 4096 nb_txd 4096\r

2520 [4] mempool_rx__4\r

2521 [4] mempool_small__4\r

2522 iavf_init_rss(): RSS is enabled by PF by default\r

2523 \r

2524 Checking link status portid [4] ... done\r

2525 Port 4 Link Up - speed 100000 Mbps - full-duplex\r

2526 EAL: PCI device 0000:51:01.5 on NUMA socket 0\r

2527 EAL: probe driver: 8086:1889 net_iavf\r

2528 initializing port 5 for TX, drv=net_iavf\r

2529 Port 5 MAC: 00 11 22 33 02 10\r

2530 Port 5: nb_rxd 4096 nb_txd 4096\r

2531 [5] mempool_rx__5\r

2532 [5] mempool_small__5\r

2533 iavf_init_rss(): RSS is enabled by PF by default\r

2534 \r

2535 Checking link status portid [5] ... done\r

2536 Port 5 Link Up - speed 100000 Mbps - full-duplex\r

2537 [ 0] vf 0 local SRC MAC: 00 11 22 33 00 00\r

2538 [ 0] vf 0 remote DST MAC: 00 11 22 33 00 01\r

2539 [ 0] vf 1 local SRC MAC: 00 11 22 33 00 10\r

2540 [ 0] vf 1 remote DST MAC: 00 11 22 33 00 11\r

2541 [ 1] vf 2 local SRC MAC: 00 11 22 33 01 00\r

2542 [ 1] vf 2 remote DST MAC: 00 11 22 33 01 01\r

2543 [ 1] vf 3 local SRC MAC: 00 11 22 33 01 10\r

2544 [ 1] vf 3 remote DST MAC: 00 11 22 33 01 11\r

2545 [ 2] vf 4 local SRC MAC: 00 11 22 33 02 00\r

2546 [ 2] vf 4 remote DST MAC: 00 11 22 33 02 01\r

2547 [ 2] vf 5 local SRC MAC: 00 11 22 33 02 10\r

2548 [ 2] vf 5 remote DST MAC: 00 11 22 33 02 11\r

2549 created dl_gen_ring_up_0\r

2550 created dl_gen_ring_up_1\r

2551 created dl_gen_ring_up_2\r

2552 xran_init successful, pHandle = 0x7f7393b23040\r

2553 \r

2554 \r

2555 bbdev_init:\r

2556 Socket ID: 0\r

2557 FEC is accelerated through BBDEV: 0000:92:00.0\r

2558 wls_layer_init[wls0] nWlsMemorySize[1063256064]\r

2559 wls_lib: Open wls0 (DPDK memzone)\r

2560 wls_lib: WLS_Open 0x43f600000\r

2561 wls_lib: link: 0 <-> 1\r

2562 wls_lib: Mode 0\r

2563 wls_lib: WLS shared management memzone: wls0\r

2564 wls_lib: hugePageSize on the system is 1073741824\r

2565 wls_lib: WLS_Alloc [1063256064] bytes\r

2566 \r

2567 \r

2568 ===========================================================================================================\r

2569 PHY VERSION\r

2570 ===========================================================================================================\r

2571 Version: #DIRTY#\r

2572 IMG-date: Aug 5 2020\r

2573 IMG-time: 18:31:18\r

2574 ===========================================================================================================\r

2575 DEPENDENCIES VERSIONS\r

2576 ===========================================================================================================\r

2577 FlexRAN BBU pooling version #DIRTY#\r

2578 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r

2579 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r

2580 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r

2581 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r

2582 FlexRAN SDK bblib_llr_demapping version #DIRTY#\r

2583 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r

2584 FlexRAN SDK bblib_reed_muller version #DIRTY#\r

2585 FlexRAN SDK bblib_lte_modulation version #DIRTY#\r

2586 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r

2587 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r

2588 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r

2589 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r

2590 FlexRAN SDK bblib_fd_correlation version #DIRTY#\r

2591 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r

2592 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r

2593 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r

2594 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r

2595 FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r

2596 FlexRAN SDK bblib_fft_ifft version #DIRTY#\r

2597 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r

2598 FlexRAN SDK bblib_lte_crc version #DIRTY#\r

2599 FlexRAN SDK bblib_common version #DIRTY#\r

2600 ===========================================================================================================\r

2601 \r

2602 ===========================================================================================================\r

2603 Non BBU threads in application\r

2604 ===========================================================================================================\r

2605 nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 29438] binding on [CPU 2] [PRIO: 0] [POLICY: 1]\r

2606 wls_rx_handler (non-rt): [PID: 29445] binding on [CPU 2]\r

2607 ===========================================================================================================\r

2608 \r

2609 PHY>welcome to application console\r

2610 \r

2611 \r

2612 PHY>\r

2613 PHY>\r

2614 PHY>Received MSG_TYPE_PHY_ADD_REMOVE_CORE\r

2615 Processing MSG_TYPE_PHY_ADD_REMOVE_CORE\r

2616 phy_bbupool_set_core[0] (add): 137170526192 [0x0000001ff0001ff0] Current: 0 [0x0000000000000000]\r

2617 nr5g_gnb_mac2phy_api_set_options: PDSCH_SPLIT[4] nCellMask[0x00000001]\r

2618 nr5g_gnb_mac2phy_api_set_options: PDSCH_DL_WEIGHT_SPLIT[4] nCellMask[0x00000001]\r

2619 nr5g_gnb_mac2phy_api_set_options: PUSCH_CHANEST_SPLIT[2] nCellMask[0x00000001]\r

2620 nr5g_gnb_mac2phy_api_set_options: PUSCH_MMSE_SPLIT[4] nCellMask[0x00000001]\r

2621 nr5g_gnb_mac2phy_api_set_options: PUSCH_LLR_RX_SPLIT[2] nCellMask[0x00000001]\r

2622 nr5g_gnb_mac2phy_api_set_options: PUSCH_UL_WEIGHT_SPLIT[2] nCellMask[0x00000001]\r

2623 nr5g_gnb_mac2phy_api_set_options: FEC_DEC_NUM_ITER[3] nCellMask[0x00ffffff]\r

2624 Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r

2625 Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r

2626 Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r

2627 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0\r

2628 phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/376/uliq00_tst376.bin] filename_in_prach_iq[]\r

2629 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 1\r

2630 phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[1] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin] filename_in_prach_iq[]\r

2631 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 2\r

2632 phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[2] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin] filename_in_prach_iq[]\r

2633 Received MSG_TYPE_PHY_CONFIG_REQ: 0\r

2634 Received MSG_TYPE_PHY_CONFIG_REQ: 1\r

2635 Received MSG_TYPE_PHY_CONFIG_REQ: 2\r

2636 Processing MSG_TYPE_PHY_CONFIG_REQ: 0\r

2637 phy_bbupool_init: Changing Core Mask0 [0xf0] to [0x1ff0001ff0]\r

2638 phy_bbupool_set_config: Using cores: 0x0000001ff0001ff0 for BBU Pool nBbuPoolSleepEnable: 1\r

2639 BBU Pooling: queueId = 0, the according nCoreNum = 18, the according cpuSetMask = 0x1ff0001ff0\r

2640 BBU Pooling: gCoreIdxMap[0] = 4 is available!\r

2641 BBU Pooling: gCoreIdxMap[1] = 5 is available!\r

2642 BBU Pooling: gCoreIdxMap[2] = 6 is available!\r

2643 BBU Pooling: gCoreIdxMap[3] = 7 is available!\r

2644 BBU Pooling: gCoreIdxMap[4] = 8 is available!\r

2645 BBU Pooling: gCoreIdxMap[5] = 9 is available!\r

2646 BBU Pooling: gCoreIdxMap[6] = 10 is available!\r

2647 BBU Pooling: gCoreIdxMap[7] = 11 is available!\r

2648 BBU Pooling: gCoreIdxMap[8] = 12 is available!\r

2649 BBU Pooling: gCoreIdxMap[9] = 28 is available!\r

2650 BBU Pooling: gCoreIdxMap[10] = 29 is available!\r

2651 BBU Pooling: gCoreIdxMap[11] = 30 is available!\r

2652 BBU Pooling: gCoreIdxMap[12] = 31 is available!\r

2653 BBU Pooling: gCoreIdxMap[13] = 32 is available!\r

2654 BBU Pooling: gCoreIdxMap[14] = 33 is available!\r

2655 BBU Pooling: gCoreIdxMap[15] = 34 is available!\r

2656 BBU Pooling: gCoreIdxMap[16] = 35 is available!\r

2657 BBU Pooling: gCoreIdxMap[17] = 36 is available!\r

2658 phy_bbupool_init: Changing SrsCore Mask0 [(nil)] to [0x10000010]\r

2659 phy_bbupool_init: Changing DlbeamCore Mask0 [(nil)] to [0x7e0]\r

2660 Massive Mimo Config: nCarrierAggregationLevel[3], nMassiveMimoSrsCoresMask[0x10000010] nTotalSrsCores[2]\r

2661 Setting aside core[4] for SRS\r

2662 Setting aside core[28] for SRS\r

2663 Massive Mimo Config: nCarrierAggregationLevel[3], nMassiveMimoDlbeamCoresMask[0x7e0] nTotalDlbeamCores[6]\r

2664 Setting aside core[5] for DL beam\r

2665 Setting aside core[6] for DL beam\r

2666 Setting aside core[7] for DL beam\r

2667 Setting aside core[8] for DL beam\r

2668 Setting aside core[9] for DL beam\r

2669 Setting aside core[10] for DL beam\r

2670 BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered\r

2671 BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered\r

2672 BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered\r

2673 BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered\r

2674 BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered\r

2675 BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered\r

2676 BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered\r

2677 BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered\r

2678 BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered\r

2679 BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered\r

2680 BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered\r

2681 BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered\r

2682 BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered\r

2683 BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered\r

2684 BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered\r

2685 BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered\r

2686 BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered\r

2687 BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered\r

2688 BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered\r

2689 BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered\r

2690 BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered\r

2691 BBU Pooling: taskId = 21 taskName = DL_L1_BEAM_WEIGHT_GEN is registered\r

2692 BBU Pooling: taskId = 22 taskName = DL_L1_BEAM_WEIGHT_TX is registered\r

2693 BBU Pooling: taskId = 23 taskName = UL_L1_BEAM_WEIGHT_GEN is registered\r

2694 BBU Pooling: taskId = 24 taskName = UL_L1_BEAM_WEIGHT_TX is registered\r

2695 BBU Pooling: taskId = 25 taskName = UL_L1_SRS_CE is registered\r

2696 BBU Pooling: taskId = 26 taskName = UL_L1_SRS_REPORT is registered\r

2697 BBU Pooling: taskId = 27 taskName = UL_L1_PUSCH_CE0_PRE is registered\r

2698 BBU Pooling: taskId = 28 taskName = UL_L1_PUSCH_CE7_PRE is registered\r

2699 BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS\r

2700 BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A\r

2701 \r

2702 BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER: DL_L1_PDSCH_SYMBOL_TX\r

2703 BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST\r

2704 BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX\r

2705 BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST\r

2706 BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST UL_L1_BEAM_WEIGHT_GEN\r

2707 BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r

2708 BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7\r

2709 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r

2710 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7\r

2711 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR\r

2712 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR\r

2713 BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE\r

2714 BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A\r

2715 \r

2716 BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST\r

2717 BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST\r

2718 BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST\r

2719 BBU Pooling: next taskList of UL_L1_SRS: UL_L1_SRS_CE\r

2720 BBU Pooling: next taskList of DL_L1_POST: N/A\r

2721 \r

2722 BBU Pooling: next taskList of UL_L1_POST: N/A\r

2723 \r

2724 BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_GEN: DL_L1_BEAM_WEIGHT_TX\r

2725 BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_TX: DL_L1_POST\r

2726 BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_GEN: UL_L1_BEAM_WEIGHT_TX\r

2727 BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_TX: UL_L1_POST\r

2728 BBU Pooling: next taskList of UL_L1_SRS_CE: UL_L1_SRS_REPORT\r

2729 BBU Pooling: next taskList of UL_L1_SRS_REPORT: N/A\r

2730 \r

2731 BBU Pooling: next taskList of UL_L1_PUSCH_CE0_PRE: UL_L1_PUSCH_CE0 UL_L1_PUSCH_CE7\r

2732 BBU Pooling: next taskList of UL_L1_PUSCH_CE7_PRE: UL_L1_PUSCH_CE7\r

2733 enter RtThread Launch\r

2734 Allocated gpThreadWorker[coreIdx: 0][CoreNum: 4]: [0x7f738c000b70]\r

2735 Allocated gpThreadWorker[coreIdx: 1][CoreNum: 5]: [0x7f738c000e20]\r

2736 Allocated gpThreadWorker[coreIdx: 2][CoreNum: 6]: [0x7f738c0010d0]\r

2737 Allocated gpThreadWorker[coreIdx: 3][CoreNum: 7]: [0x7f738c001380]\r

2738 Allocated gpThreadWorker[coreIdx: 4][CoreNum: 8]: [0x7f738c001630]\r

2739 Allocated gpThreadWorker[coreIdx: 5][CoreNum: 9]: [0x7f738c0018e0]\r

2740 launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2741 \r

2742 launching Thread 0 Queue 0 uCoreIdx 0 CoreId 4 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2743 \r

2744 launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2745 \r

2746 launching Thread 3 Queue 0 uCoreIdx 3 CoreId 7 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2747 \r

2748 Allocated gpThreadWorker[coreIdx: 6][CoreNum: 10]: [0x7f738c001b90]\r

2749 launching Thread 4 Queue 0 uCoreIdx 4 CoreId 8 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2750 \r

2751 launching Thread 5 Queue 0 uCoreIdx 5 CoreId 9 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2752 \r

2753 Allocated gpThreadWorker[coreIdx: 7][CoreNum: 11]: [0x7f738c001e40]\r

2754 Allocated gpThreadWorker[coreIdx: 8][CoreNum: 12]: [0x7f738c0020f0]\r

2755 bbupool_core_main: the server's coreNum = 48, the nCore = 18,nRtCoreMask = 0x1ff0001ff0, the nFeIfCore = 0,nFeIfCoreMask = 0x0\r

2756 bbupool_core_main pthread_setaffinity_np succeed: coreId = 2, result = 0\r

2757 Allocated gpThreadWorker[coreIdx: 9][CoreNum: 28]: [0x7f738c0023a0]\r

2758 launching Thread 6 Queue 0 uCoreIdx 6 CoreId 10 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2759 \r

2760 Allocated gpThreadWorker[coreIdx: 10][CoreNum: 29]: [0x7f738c002650]\r

2761 launching Thread 7 Queue 0 uCoreIdx 7 CoreId 11 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2762 \r

2763 Allocated gpThreadWorker[coreIdx: 11][CoreNum: 30]: [0x7f738c002900]\r

2764 launching Thread 8 Queue 0 uCoreIdx 8 CoreId 12 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2765 \r

2766 launching Thread 9 Queue 0 uCoreIdx 9 CoreId 28 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2767 \r

2768 Allocated gpThreadWorker[coreIdx: 12][CoreNum: 31]: [0x7f738c002bb0]\r

2769 Allocated gpThreadWorker[coreIdx: 13][CoreNum: 32]: [0x7f738c002e60]\r

2770 launching Thread 10 Queue 0 uCoreIdx 10 CoreId 29 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2771 \r

2772 launching Thread 11 Queue 0 uCoreIdx 11 CoreId 30 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2773 \r

2774 Allocated gpThreadWorker[coreIdx: 14][CoreNum: 33]: [0x7f738c003110]\r

2775 Allocated gpThreadWorker[coreIdx: 15][CoreNum: 34]: [0x7f738c0033c0]\r

2776 launching Thread 12 Queue 0 uCoreIdx 12 CoreId 31 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2777 \r

2778 Allocated gpThreadWorker[coreIdx: 16][CoreNum: 35]: [0x7f738c003670]\r

2779 launching Thread 13 Queue 0 uCoreIdx 13 CoreId 32 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2780 \r

2781 Allocated gpThreadWorker[coreIdx: 17][CoreNum: 36]: [0x7f738c003920]\r

2782 18 thread associated with queue 0:coreIdx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17\r

2783 Leave RtThread Launch\r

2784 launching Thread 14 Queue 0 uCoreIdx 14 CoreId 33 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2785 \r

2786 launching Thread 15 Queue 0 uCoreIdx 15 CoreId 34 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2787 \r

2788 launching Thread 16 Queue 0 uCoreIdx 16 CoreId 35 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2789 \r

2790 launching Thread 17 Queue 0 uCoreIdx 17 CoreId 36 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r

2791 \r

2792 nr5g_gnb_mac2phy_api_proc_print_phy_init [0]:\r

2793 nCarrierIdx: 0\r

2794 nDMRSTypeAPos: 2\r

2795 nPhyCellId: 50\r

2796 nDLAbsFrePointA: 3500000\r

2797 nULAbsFrePointA: 3500000\r

2798 nDLBandwidth: 100\r

2799 nULBandwidth: 100\r

2800 nDLFftSize: 4096\r

2801 nULFftSize: 4096\r

2802 nSSBPwr: 0\r

2803 nSSBAbsFre: 0\r

2804 nSSBPeriod: 4\r

2805 nSSBSubcSpacing: 1\r

2806 nSSBSubcOffset: 0\r

2807 nSSBPrbOffset: 0\r

2808 nMIB[0]: 255\r

2809 nMIB[1]: 255\r

2810 nMIB[2]: 255\r

2811 nDLK0: 0\r

2812 nULK0: 0\r

2813 nSSBMask[0]: 0\r

2814 nSSBMask[1]: 0\r

2815 nNrOfTxAnt: 64\r

2816 nNrOfRxAnt: 64\r

2817 nNrOfDLPorts: 16\r

2818 nNrOfULPorts: 8\r

2819 nCarrierAggregationLevel: 2\r

2820 nFrameDuplexType: 1\r

2821 nSubcCommon: 1\r

2822 nTddPeriod: 10 (TDD)\r

2823 SlotConfig:\r

2824 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r

2825 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2826 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2827 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2828 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

2829 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

2830 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2831 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2832 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2833 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

2834 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

2835 \r

2836 nPrachConfIdx: 100\r

2837 nPrachSubcSpacing: 1\r

2838 nPrachZeroCorrConf: 1\r

2839 nPrachRestrictSet: 0\r

2840 nPrachRootSeqIdx: 0\r

2841 nPrachFreqStart: 100\r

2842 nPrachFdm: 1\r

2843 nPrachSsbRach: 0\r

2844 nPrachNrofRxRU: 4\r

2845 nCyclicPrefix: 0\r

2846 nGroupHopFlag: 0\r

2847 nSequenceHopFlag: 0\r

2848 nHoppingId: 0\r

2849 nUrllcCapable: 0\r

2850 nUrllcMiniSlotMask: 1 (0x00000001)\r

2851 read_table: File table/common/pss_table.bin of size 381 read_size: 381\r

2852 read_table: File table/common/sss_table.bin of size 128016 read_size: 128016\r

2853 read_table: File table/common/srs_zc_36_plus.bin of size 905916 read_size: 905916\r

2854 read_table: File table/common/pucch_zc_36_plus.bin of size 383040 read_size: 383040\r

2855 read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216 read_size: 81216\r

2856 read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216 read_size: 81216\r

2857 BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480\r

2858 set_slot_type SlotPattern:\r

2859 Slot: 0 1 2 3 4 5 6 7 8 9\r

2860 0 DL DL DL SP UL DL DL DL SP UL\r

2861 \r

2862 PHYDI-INIT[from 2] PhyInstance: 0\r

2863 Processing MSG_TYPE_PHY_CONFIG_REQ: 1\r

2864 nr5g_gnb_mac2phy_api_proc_print_phy_init [1]:\r

2865 nCarrierIdx: 1\r

2866 nDMRSTypeAPos: 2\r

2867 nPhyCellId: 50\r

2868 nDLAbsFrePointA: 3500000\r

2869 nULAbsFrePointA: 3500000\r

2870 nDLBandwidth: 100\r

2871 nULBandwidth: 100\r

2872 nDLFftSize: 4096\r

2873 nULFftSize: 4096\r

2874 nSSBPwr: 0\r

2875 nSSBAbsFre: 0\r

2876 nSSBPeriod: 4\r

2877 nSSBSubcSpacing: 1\r

2878 nSSBSubcOffset: 0\r

2879 nSSBPrbOffset: 0\r

2880 nMIB[0]: 255\r

2881 nMIB[1]: 255\r

2882 nMIB[2]: 255\r

2883 nDLK0: 0\r

2884 nULK0: 0\r

2885 nSSBMask[0]: 0\r

2886 nSSBMask[1]: 0\r

2887 nNrOfTxAnt: 64\r

2888 nNrOfRxAnt: 64\r

2889 nNrOfDLPorts: 16\r

2890 nNrOfULPorts: 8\r

2891 nCarrierAggregationLevel: 2\r

2892 nFrameDuplexType: 1\r

2893 nSubcCommon: 1\r

2894 nTddPeriod: 10 (TDD)\r

2895 SlotConfig:\r

2896 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r

2897 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2898 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2899 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2900 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

2901 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

2902 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2903 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2904 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2905 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

2906 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

2907 \r

2908 nPrachConfIdx: 100\r

2909 nPrachSubcSpacing: 1\r

2910 nPrachZeroCorrConf: 1\r

2911 nPrachRestrictSet: 0\r

2912 nPrachRootSeqIdx: 0\r

2913 nPrachFreqStart: 100\r

2914 nPrachFdm: 1\r

2915 nPrachSsbRach: 0\r

2916 nPrachNrofRxRU: 4\r

2917 nCyclicPrefix: 0\r

2918 nGroupHopFlag: 0\r

2919 nSequenceHopFlag: 0\r

2920 nHoppingId: 0\r

2921 nUrllcCapable: 0\r

2922 nUrllcMiniSlotMask: 1 (0x00000001)\r

2923 BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480\r

2924 set_slot_type SlotPattern:\r

2925 Slot: 0 1 2 3 4 5 6 7 8 9\r

2926 0 DL DL DL SP UL DL DL DL SP UL\r

2927 \r

2928 PHYDI-INIT[from 2] PhyInstance: 1\r

2929 Processing MSG_TYPE_PHY_CONFIG_REQ: 2\r

2930 nr5g_gnb_mac2phy_api_proc_print_phy_init [2]:\r

2931 nCarrierIdx: 2\r

2932 nDMRSTypeAPos: 2\r

2933 nPhyCellId: 50\r

2934 nDLAbsFrePointA: 3500000\r

2935 nULAbsFrePointA: 3500000\r

2936 nDLBandwidth: 100\r

2937 nULBandwidth: 100\r

2938 nDLFftSize: 4096\r

2939 nULFftSize: 4096\r

2940 nSSBPwr: 0\r

2941 nSSBAbsFre: 0\r

2942 nSSBPeriod: 4\r

2943 nSSBSubcSpacing: 1\r

2944 nSSBSubcOffset: 0\r

2945 nSSBPrbOffset: 0\r

2946 nMIB[0]: 255\r

2947 nMIB[1]: 255\r

2948 nMIB[2]: 255\r

2949 nDLK0: 0\r

2950 nULK0: 0\r

2951 nSSBMask[0]: 0\r

2952 nSSBMask[1]: 0\r

2953 nNrOfTxAnt: 64\r

2954 nNrOfRxAnt: 64\r

2955 nNrOfDLPorts: 16\r

2956 nNrOfULPorts: 8\r

2957 nCarrierAggregationLevel: 2\r

2958 nFrameDuplexType: 1\r

2959 nSubcCommon: 1\r

2960 nTddPeriod: 10 (TDD)\r

2961 SlotConfig:\r

2962 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r

2963 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2964 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2965 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2966 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

2967 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

2968 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2969 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2970 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r

2971 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r

2972 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r

2973 \r

2974 nPrachConfIdx: 100\r

2975 nPrachSubcSpacing: 1\r

2976 nPrachZeroCorrConf: 1\r

2977 nPrachRestrictSet: 0\r

2978 nPrachRootSeqIdx: 0\r

2979 nPrachFreqStart: 100\r

2980 nPrachFdm: 1\r

2981 nPrachSsbRach: 0\r

2982 nPrachNrofRxRU: 4\r

2983 nCyclicPrefix: 0\r

2984 nGroupHopFlag: 0\r

2985 nSequenceHopFlag: 0\r

2986 nHoppingId: 0\r

2987 nUrllcCapable: 0\r

2988 nUrllcMiniSlotMask: 1 (0x00000001)\r

2989 BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480\r

2990 set_slot_type SlotPattern:\r

2991 Slot: 0 1 2 3 4 5 6 7 8 9\r

2992 0 DL DL DL SP UL DL DL DL SP UL\r

2993 \r

2994 PHYDI-INIT[from 2] PhyInstance: 2\r

2995 \r

2996 ---------------------------------------------------------\r

2997 Global Variables:\r

2998 ---------------------------------------------------------\r

2999 gCarrierAggLevel: 3\r

3000 gCarrierAggLevelInit: 3\r

3001 gSupportedAVX2 1\r

3002 ---------------------------------------------------------\r

3003 \r

3004 Received MSG_TYPE_PHY_START_REQ: 0\r

3005 Received MSG_TYPE_PHY_START_REQ: 1\r

3006 Received MSG_TYPE_PHY_START_REQ: 2\r

3007 Processing MSG_TYPE_PHY_START_REQ: 0\r

3008 di_open port 0\r

3009 \r

3010 xran_init_vfs_mapping: p 0 vf 0\r

3011 xran_init_vfs_mapping: p 0 vf 1\r

3012 XRAN_UP_VF: 0x0000\r

3013 xran_timing_source_thread [CPU 22] [PID: 29437]\r

3014 xran_open [CPU 2] [PID: 29437]\r

3015 Waithing on Timing thread...\r

3016 TTI interval 500 [us]\r

3017 Start C-plane DL 71 us after TTI [trigger on sym 2]\r

3018 Start C-plane UL 200 us after TTI [trigger on sym 6]\r

3019 Start U-plane DL 196 us before OTA [offset in sym -5]\r

3020 Start U-plane UL 75 us OTA [offset in sym 3]\r

3021 C-plane to U-plane delay 125 us after TTI\r

3022 Start Sym timer 35714 ns\r

3023 di_open port 1\r

3024 \r

3025 xran_init_vfs_mapping: p 1 vf 2\r

3026 xran_init_vfs_mapping: p 1 vf 3\r

3027 Start C-plane DL 71 us after TTI [trigger on sym 2]\r

3028 Start C-plane UL 200 us after TTI [trigger on sym 6]\r

3029 Start U-plane DL 196 us before OTA [offset in sym -5]\r

3030 Start U-plane UL 75 us OTA [offset in sym 3]\r

3031 C-plane to U-plane delay 125 us after TTI\r

3032 Start Sym timer 35714 ns\r

3033 xran_open [CPU 2] [PID: 29437]\r

3034 Waithing on Timing thread...\r

3035 di_open port 2\r

3036 \r

3037 xran_init_vfs_mapping: p 2 vf 4\r

3038 xran_init_vfs_mapping: p 2 vf 5\r

3039 Start C-plane DL 71 us after TTI [trigger on sym 2]\r

3040 Start C-plane UL 200 us after TTI [trigger on sym 6]\r

3041 Start U-plane DL 196 us before OTA [offset in sym -5]\r

3042 Start U-plane UL 75 us OTA [offset in sym 3]\r

3043 C-plane to U-plane delay 125 us after TTI\r

3044 Start Sym timer 35714 ns\r

3045 O-XU 0\r

3046 HW 1\r

3047 Num cores 4\r

3048 Num ports 3\r

3049 O-RU Cat 1\r

3050 O-RU CC 3\r

3051 O-RU eAxC 16\r

3052 p:0 XRAN_JOB_TYPE_CP_DL worker id 1\r

3053 p:0 XRAN_JOB_TYPE_CP_UL worker id 1\r

3054 p:1 XRAN_JOB_TYPE_CP_DL worker id 1\r

3055 p:1 XRAN_JOB_TYPE_CP_UL worker id 1\r

3056 p:2 XRAN_JOB_TYPE_CP_DL worker id 1\r

3057 p:2 XRAN_JOB_TYPE_CP_UL worker id 1\r

3058 p:1 XRAN_JOB_TYPE_CP_DL worker id 2\r

3059 p:1 XRAN_JOB_TYPE_CP_UL worker id 2\r

3060 p:2 XRAN_JOB_TYPE_CP_DL worker id 2\r

3061 p:2 XRAN_JOB_TYPE_CP_UL worker id 2\r

3062 xran_generic_worker_thread [CPU 23] [PID: 29437]\r

3063 spawn worker 0 core 23\r

3064 xran_generic_worker_thread [CPU 24] [PID: 29437]\r

3065 spawn worker 1 core 24\r

3066 xran_generic_worker_thread [CPU 25] [PID: 29437]\r

3067 spawn worker 2 core 25\r

3068 xran_open [CPU 2] [PID: 29437]\r

3069 Waithing on Timing thread...\r

3070 ----------------------------------------------------------------------------\r

3071 mem_mgr_display_size:\r

3072 Num Memory Alloc: 38,294\r

3073 Total Memory Size: 20,049,968,118\r

3074 ----------------------------------------------------------------------------\r

3075 \r

3076 \r

3077 PHYDI-START[from 2] PhyInstance: 0, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20\r

3078 PHYDI-START[from 2] PhyInstance: 1, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20\r

3079 PHYDI-START[from 2] PhyInstance: 2, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20\r

3080 Setting nMultiCellModeDelay: 40000\r

3081 nr5g_gnb_urllc_register_call_backs: nTimerMode[0] nUrllcMiniSlotMask[0]\r

3082 port [0] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]\r

3083 port 0 has 1 CCs\r

3084 port 0 cc_id 0 is phy id 0\r

3085 XRAN front haul xran_mm_init\r

3086 xran_sector_get_instances [0]: CC 0 handle 0x7f6fe7383280\r

3087 Handle: 0xee1c8e0 Instance: 0x7f6fe7383280\r

3088 gnb_io_xran_start [0]: CC 0 handle 0x7f6fe7383280\r

3089 Sucess xran_mm_init Instance 0x7f6fe7383280\r

3090 nSectorNum 1\r

3091 ru_0_cc_0_idx_0: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432\r

3092 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool 0x44c493480\r

3093 ru_0_cc_0_idx_1: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32\r

3094 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool 0x444381640\r

3095 ru_0_cc_0_idx_2: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560\r

3096 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool 0x443dff2c0\r

3097 ru_0_cc_0_idx_3: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432\r

3098 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool 0x443c5cf40\r

3099 ru_0_cc_0_idx_4: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32\r

3100 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool 0x443ababc0\r

3101 ru_0_cc_0_idx_5: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560\r

3102 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool 0x443538840\r

3103 ru_0_cc_0_idx_6: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192\r

3104 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool 0x4433964c0\r

3105 ru_0_cc_0_idx_7: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432\r

3106 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 7] mb pool 0x4431f4140\r

3107 ru_0_cc_0_idx_8: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32\r

3108 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 8] mb pool 0x442ff1dc0\r

3109 ru_0_cc_0_idx_9: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560\r

3110 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 9] mb pool 0x441e6fa40\r

3111 port [0] gnb_io_xran_init_cp\r

3112 port [0] init xran successfully\r

3113 port [1] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]\r

3114 port 1 has 1 CCs\r

3115 port 1 cc_id 0 is phy id 1\r

3116 XRAN front haul xran_mm_init\r

3117 xran_sector_get_instances [1]: CC 0 handle 0x7f6fe7383380\r

3118 Handle: 0xee1c940 Instance: 0x7f6fe7383380\r

3119 gnb_io_xran_start [1]: CC 0 handle 0x7f6fe7383380\r

3120 Sucess xran_mm_init Instance 0x7f6fe7383280\r

3121 nSectorNum 1\r

3122 ru_1_cc_0_idx_0: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432\r

3123 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 0] mb pool 0x2a1525740\r

3124 ru_1_cc_0_idx_1: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32\r

3125 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 1] mb pool 0x299413900\r

3126 ru_1_cc_0_idx_2: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560\r

3127 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 2] mb pool 0x28f1112c0\r

3128 ru_1_cc_0_idx_3: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432\r

3129 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 3] mb pool 0x287f4fb80\r

3130 ru_1_cc_0_idx_4: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32\r

3131 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 4] mb pool 0x27fe3dd40\r

3132 ru_1_cc_0_idx_5: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560\r

3133 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 5] mb pool 0x275b3b700\r

3134 ru_1_cc_0_idx_6: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192\r

3135 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 6] mb pool 0x26e979fc0\r

3136 ru_1_cc_0_idx_7: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432\r

3137 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 7] mb pool 0x269ce9980\r

3138 ru_1_cc_0_idx_8: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32\r

3139 O-DU: thread_run start time: 08/11/20 23:05:24.000000001 UTC [500]\r

3140 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 8] mb pool 0x249d33b40\r

3141 ru_1_cc_0_idx_9: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560\r

3142 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 9] mb pool 0x2215b1500\r

3143 port [1] gnb_io_xran_init_cp\r

3144 port [1] init xran successfully\r

3145 port [2] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]\r

3146 port 2 has 1 CCs\r

3147 port 2 cc_id 0 is phy id 2\r

3148 XRAN front haul xran_mm_init\r

3149 xran_sector_get_instances [2]: CC 0 handle 0x7f6fe7383440\r

3150 Handle: 0xee1c9a0 Instance: 0x7f6fe7383440\r

3151 gnb_io_xran_start [2]: CC 0 handle 0x7f6fe7383440\r

3152 Sucess xran_mm_init Instance 0x7f6fe7383280\r

3153 nSectorNum 1\r

3154 ru_2_cc_0_idx_0: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432\r

3155 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 0] mb pool 0x203b7bdc0\r

3156 ru_2_cc_0_idx_1: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32\r

3157 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 1] mb pool 0x1fba69f80\r

3158 ru_2_cc_0_idx_2: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560\r

3159 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 2] mb pool 0x1f1767940\r

3160 ru_2_cc_0_idx_3: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432\r

3161 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 3] mb pool 0x1ea5a6200\r

3162 ru_2_cc_0_idx_4: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32\r

3163 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 4] mb pool 0x1e24943c0\r

3164 ru_2_cc_0_idx_5: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560\r

3165 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 5] mb pool 0x1d8191d80\r

3166 ru_2_cc_0_idx_6: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192\r

3167 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 6] mb pool 0x1d0fd0640\r

3168 ru_2_cc_0_idx_7: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432\r

3169 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 7] mb pool 0x1cc340000\r

3170 ru_2_cc_0_idx_8: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32\r

3171 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 8] mb pool 0x1ac38a1c0\r

3172 ru_2_cc_0_idx_9: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560\r

3173 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 9] mb pool 0x183c07b80\r

3174 port [2] gnb_io_xran_init_cp\r

3175 port [2] init xran successfully\r

3176 O-DU: XRAN start time: 08/11/20 23:05:24.384220762 UTC [500]\r

3177 BBU Pooling: enter multicell Activate!\r

3178 BBU Pooling Info: bbupool rt thread start on CoreIdx 14 coreId 33 at 118352443946329 at sf=0 with queue 0 successfully\r

3179 BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at 118352443939667 at sf=0 with queue 0 successfully\r

3180 BBU Pooling Info: bbupool rt thread start on CoreIdx 11 coreId 30 at 118352443942535 at sf=0 with queue 0 successfully\r

3181 BBU Pooling Info: bbupool rt thread start on CoreIdx 8 coreId 12 at 118352443944575 at sf=0 with queue 0 successfully\r

3182 BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0, activesfn = 4, CellNumInActSfn = 3\r

3183 BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at 118352443929961 at sf=0 with queue 0 successfully\r

3184 BBU Pooling Info: bbupool rt thread start on CoreIdx 15 coreId 34 at 118352443933301 at sf=0 with queue 0 successfully\r

3185 BBU Pooling: multiCell Activate sucessfully!\r

3186 BBU Pooling Info: bbupool rt thread start on CoreIdx 13 coreId 32 at 118352443935245 at sf=0 with queue 0 successfully\r

3187 BBU Pooling Info: bbupool rt thread start on CoreIdx 4 coreId 8 at 118352443936745 at sf=0 with queue 0 successfully\r

3188 BBU Pooling Info: bbupool rt thread start on CoreIdx 6 coreId 10 at 118352443936883 at sf=0 with queue 0 successfully\r

3189 BBU Pooling Info: bbupool rt thread start on CoreIdx 3 coreId 7 at 118352443936747 at sf=0 with queue 0 successfully\r

3190 BBU Pooling Info: bbupool rt thread start on CoreIdx 12 coreId 31 at 118352443938019 at sf=0 with queue 0 successfully\r

3191 BBU Pooling Info: bbupool rt thread start on CoreIdx 5 coreId 9 at 118352443939937 at sf=0 with queue 0 successfully\r

3192 BBU Pooling Info: bbupool rt thread start on CoreIdx 9 coreId 28 at 118352443941217 at sf=0 with queue 0 successfully\r

3193 BBU Pooling Info: bbupool rt thread start on CoreIdx 16 coreId 35 at 118352443944465 at sf=0 with queue 0 successfully\r

3194 BBU Pooling Info: bbupool rt thread start on CoreIdx 17 coreId 36 at 118352443937701 at sf=0 with queue 0 successfully\r

3195 BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 4 at 118352443926969 at sf=0 with queue 0 successfully\r

3196 BBU Pooling Info: bbupool rt thread start on CoreIdx 10 coreId 29 at 118352443928691 at sf=0 with queue 0 successfully\r

3197 BBU Pooling Info: bbupool rt thread start on CoreIdx 7 coreId 11 at 118352443931713 at sf=0 with queue 0 successfully\r

3198 phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5] gNumSlotPerSfn[20]\r

3199 ==== l1app Time: 5002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces\r

3200 ==== [o-du0][rx 3807776 pps 761555 kbps 4744396][tx 10937607 pps 2187521 kbps 26031486] [on_time 3807776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3807776]\r

3201 Pusch[ 439372 439372 439372 439372 439372 439372 439372 439372] SRS[ 292800]\r

3202 ==== [o-du1][rx 1469469 pps 293893 kbps 2684928][tx 3649817 pps 729963 kbps 9156812] [on_time 1469469 early 0 late 0 corrupt 0 pkt_dupl 144 Total 1469469]\r

3203 Pusch[ 146964 146956 146964 146956 146964 146956 146964 146956] SRS[ 293788]\r

3204 ==== [o-du2][rx 1469463 pps 293892 kbps 2684960][tx 3648883 pps 729776 kbps 9152795] [on_time 1469463 early 0 late 0 corrupt 0 pkt_dupl 144 Total 1469463]\r

3205 Pusch[ 146956 146956 146956 146956 146956 146956 146956 146956] SRS[ 293815]\r

3206 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3207 Cell DL Tput UL Tput UL BLER\r

3208 0 (Kbps) 0 0 / 0 0.00%\r

3209 1 (Kbps) 0 0 / 0 0.00%\r

3210 2 (Kbps) 0 0 / 0 0.00%\r

3211 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3212 Core Utilization [18 BBU core(s)]:\r

3213 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3214 Util %: 0 4 2 4 4 2 3 13 17 0 13 15 14 16 14 17 15 14 9.28\r

3215 Xran Id: 22 23 24 25 Master Core Util: 85 %\r

3216 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3217 ==== l1app Time: 10002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces\r

3218 ==== [o-du0][rx 5472406 pps 332926 kbps 4744396][tx 21871698 pps 2186818 kbps 26038405] [on_time 5472406 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5472406]\r

3219 Pusch[ 192084 192078 192078 192078 192078 192078 192078 192078] SRS[ 128000]\r

3220 ==== [o-du1][rx 2109680 pps 128042 kbps 2684917][tx 7297930 pps 729622 kbps 9156922] [on_time 2109680 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2109680]\r

3221 Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128004]\r

3222 ==== [o-du2][rx 2109682 pps 128043 kbps 2684993][tx 7296833 pps 729590 kbps 9156258] [on_time 2109682 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2109682]\r

3223 Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128011]\r

3224 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3225 Cell DL Tput UL Tput UL BLER\r

3226 0 (Kbps) 6,894,368 576,420 / 576,492 0.00%\r

3227 1 (Kbps) 0 0 / 0 0.00%\r

3228 2 (Kbps) 0 0 / 0 0.00%\r

3229 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3230 Core Utilization [18 BBU core(s)]:\r

3231 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3232 Util %: 15 30 34 29 26 28 26 46 50 0 40 40 43 42 44 42 48 50 35.17\r

3233 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3234 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3235 ==== l1app Time: 15003 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces\r

3236 ==== [o-du0][rx 7136544 pps 332827 kbps 4744396][tx 32806663 pps 2186993 kbps 26042173] [on_time 7136544 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7136544]\r

3237 Pusch[ 192012 192018 192018 192018 192018 192018 192018 192018] SRS[ 128000]\r

3238 ==== [o-du1][rx 2749728 pps 128009 kbps 2684895][tx 10945622 pps 729538 kbps 9155645] [on_time 2749728 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2749728]\r

3239 Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000]\r

3240 ==== [o-du2][rx 2749730 pps 128009 kbps 2684840][tx 10944272 pps 729487 kbps 9154660] [on_time 2749730 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2749730]\r

3241 Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000]\r

3242 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3243 Cell DL Tput UL Tput UL BLER\r

3244 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r

3245 1 (Kbps) 539,740 65,260 / 65,260 0.00%\r

3246 2 (Kbps) 0 0 / 0 0.00%\r

3247 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3248 Core Utilization [18 BBU core(s)]:\r

3249 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3250 Util %: 27 33 40 38 38 35 34 56 56 26 50 47 48 47 51 48 57 57 43.78\r

3251 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3252 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3253 Setting MLogMask because nMLogDelay == 0\r

3254 ==== l1app Time: 20002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [480.00..500.23..516.00] usces\r

3255 ==== [o-du0][rx 8799776 pps 332646 kbps 4744396][tx 43740623 pps 2186792 kbps 26042944] [on_time 8799776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 8799776]\r

3256 Pusch[ 191904 191904 191904 191904 191904 191904 191904 191904] SRS[ 128000]\r

3257 ==== [o-du1][rx 3389472 pps 127948 kbps 2684982][tx 14591619 pps 729199 kbps 9154093] [on_time 3389472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3389472]\r

3258 Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000]\r

3259 ==== [o-du2][rx 3389474 pps 127948 kbps 2684873][tx 14589997 pps 729145 kbps 9152608] [on_time 3389474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3389474]\r

3260 Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000]\r

3261 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3262 Cell DL Tput UL Tput UL BLER\r

3263 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r

3264 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3265 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3266 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3267 Core Utilization [18 BBU core(s)]:\r

3268 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3269 Util %: 43 47 46 43 42 43 41 61 60 27 57 56 58 57 55 56 64 62 51.00\r

3270 Xran Id: 22 23 24 25 Master Core Util: 96 %\r

3271 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3272 ==== l1app Time: 25002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [442.00..500.12..562.00] usces\r

3273 ==== [o-du0][rx 10463824 pps 332809 kbps 4744396][tx 54675513 pps 2186978 kbps 26044150] [on_time 10463824 early 0 late 0 corrupt 0 pkt_dupl 144 Total 10463824]\r

3274 Pusch[ 192006 192006 192006 192006 192006 192006 192006 192006] SRS[ 128000]\r

3275 ==== [o-du1][rx 4029487 pps 128003 kbps 2684928][tx 18237287 pps 729133 kbps 9150163] [on_time 4029487 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4029487]\r

3276 Pusch[ 64002 64002 64002 64002 64002 64002 64002 64001] SRS[ 128000]\r

3277 ==== [o-du2][rx 4029474 pps 128000 kbps 2684873][tx 18235338 pps 729068 kbps 9148513] [on_time 4029474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4029474]\r

3278 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]\r

3279 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3280 Cell DL Tput UL Tput UL BLER\r

3281 0 (Kbps) 6,896,256 576,492 / 576,492 0.00%\r

3282 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3283 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3284 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3285 Core Utilization [18 BBU core(s)]:\r

3286 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3287 Util %: 44 48 46 46 44 41 43 62 61 27 58 59 55 56 56 58 61 62 51.50\r

3288 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3289 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3290 ==== l1app Time: 30002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [435.00..500.12..562.00] usces\r

3291 ==== [o-du0][rx 12127888 pps 332812 kbps 4744396][tx 65610457 pps 2186988 kbps 26044065] [on_time 12127888 early 0 late 0 corrupt 0 pkt_dupl 144 Total 12127888]\r

3292 Pusch[ 192012 192006 192012 192006 192010 192006 192006 192006] SRS[ 128000]\r

3293 ==== [o-du1][rx 4669504 pps 128003 kbps 2685058][tx 21883550 pps 729252 kbps 9152750] [on_time 4669504 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4669504]\r

3294 Pusch[ 64002 64002 64002 64002 64002 64002 64002 64003] SRS[ 128000]\r

3295 ==== [o-du2][rx 4669498 pps 128004 kbps 2684993][tx 21881293 pps 729191 kbps 9151846] [on_time 4669498 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4669498]\r

3296 Pusch[ 64004 64004 64004 64004 64002 64002 64002 64002] SRS[ 128000]\r

3297 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3298 Cell DL Tput UL Tput UL BLER\r

3299 0 (Kbps) 6,896,256 577,069 / 577,069 0.00%\r

3300 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3301 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3302 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3303 Core Utilization [18 BBU core(s)]:\r

3304 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3305 Util %: 44 47 45 47 43 43 42 63 63 27 56 56 56 55 58 55 65 62 51.50\r

3306 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3307 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3308 ==== l1app Time: 35002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [434.00..500.12..554.00] usces\r

3309 ==== [o-du0][rx 13792256 pps 332873 kbps 4744892][tx 76545521 pps 2187012 kbps 26042901] [on_time 13792256 early 0 late 0 corrupt 0 pkt_dupl 144 Total 13792256]\r

3310 Pusch[ 192042 192048 192042 192048 192044 192048 192048 192048] SRS[ 128000]\r

3311 ==== [o-du1][rx 5309632 pps 128025 kbps 2685102][tx 25528867 pps 729063 kbps 9151639] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5309632]\r

3312 Pusch[ 64016 64016 64016 64016 64016 64016 64016 64016] SRS[ 128000]\r

3313 ==== [o-du2][rx 5309632 pps 128026 kbps 2685102][tx 25526238 pps 728989 kbps 9150147] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5309632]\r

3314 Pusch[ 64016 64016 64016 64016 64018 64018 64017 64017] SRS[ 128000]\r

3315 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3316 Cell DL Tput UL Tput UL BLER\r

3317 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r

3318 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3319 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3320 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3321 Core Utilization [18 BBU core(s)]:\r

3322 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3323 Util %: 43 48 45 47 43 41 42 66 61 27 57 57 55 56 57 56 64 62 51.50\r

3324 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3325 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3326 ==== l1app Time: 40002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [440.00..500.12..553.00] usces\r

3327 ==== [o-du0][rx 15455740 pps 332696 kbps 4744396][tx 87479892 pps 2186874 kbps 26042995] [on_time 15455740 early 0 late 0 corrupt 0 pkt_dupl 144 Total 15455740]\r

3328 Pusch[ 191940 191940 191940 191940 191940 191940 191940 191940] SRS[ 127964]\r

3329 ==== [o-du1][rx 5949408 pps 127955 kbps 2684764][tx 29174424 pps 729111 kbps 9150009] [on_time 5949408 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5949408]\r

3330 Pusch[ 63980 63980 63980 63980 63980 63980 63980 63980] SRS[ 127936]\r

3331 ==== [o-du2][rx 5949410 pps 127955 kbps 2684840][tx 29171380 pps 729028 kbps 9148386] [on_time 5949410 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5949410]\r

3332 Pusch[ 63980 63980 63980 63980 63980 63980 63981 63981] SRS[ 127936]\r

3333 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3334 Cell DL Tput UL Tput UL BLER\r

3335 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r

3336 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3337 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3338 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3339 Core Utilization [18 BBU core(s)]:\r

3340 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3341 Util %: 44 48 44 45 42 42 43 63 63 27 57 56 55 58 56 56 64 62 51.39\r

3342 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3343 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3344 ==== l1app Time: 45002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [436.00..500.12..556.00] usces\r

3345 ==== [o-du0][rx 17119776 pps 332807 kbps 4743900][tx 98415119 pps 2187045 kbps 26043843] [on_time 17119776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 17119776]\r

3346 Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[ 128036]\r

3347 ==== [o-du1][rx 6589472 pps 128012 kbps 2684753][tx 32820214 pps 729158 kbps 9154170] [on_time 6589472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 6589472]\r

3348 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064]\r

3349 ==== [o-du2][rx 6589474 pps 128012 kbps 2684753][tx 32816780 pps 729080 kbps 9152613] [on_time 6589474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 6589474]\r

3350 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064]\r

3351 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3352 Cell DL Tput UL Tput UL BLER\r

3353 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r

3354 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3355 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3356 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3357 Core Utilization [18 BBU core(s)]:\r

3358 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3359 Util %: 44 47 46 47 43 42 42 61 63 27 56 58 56 56 58 57 63 65 51.72\r

3360 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3361 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3362 ==== l1app Time: 50002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [436.00..500.12..551.00] usces\r

3363 ==== [o-du0][rx 18783776 pps 332800 kbps 4744396][tx 109350065 pps 2186989 kbps 26043142] [on_time 18783776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 18783776]\r

3364 Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[ 128000]\r

3365 ==== [o-du1][rx 7229472 pps 128000 kbps 2684928][tx 36466505 pps 729258 kbps 18302595] [on_time 7229472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7229472]\r

3366 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]\r

3367 ==== [o-du2][rx 7229474 pps 128000 kbps 2684895][tx 36462749 pps 729193 kbps 9148265] [on_time 7229474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7229474]\r

3368 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]\r

3369 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3370 Cell DL Tput UL Tput UL BLER\r

3371 0 (Kbps) 6,896,256 576,492 / 576,492 0.00%\r

3372 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3373 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r

3374 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3375 Core Utilization [18 BBU core(s)]:\r

3376 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r

3377 Util %: 43 47 45 47 43 41 41 62 63 27 57 55 57 56 55 57 62 66 51.33\r

3378 Xran Id: 22 23 24 25 Master Core Util: 95 %\r

3379 -------------------------------------------------------------------------------------------------------------------------------------------------------\r

3380 \r

3381 7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::\r

3382 \r

3383 [root@xran flexran] cd ./bin/nr5g/gnb/testmac\r

3384 \r

3385 8. To execute test case type::\r

3386 \r

3387 ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r

3388 \r

3389 where output corresponding to Test MAC::\r

3390 \r

3391 root@icelake-scs1-1 testmac]# ./l2.sh --testfile=./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg\r

3392 kernel.sched_rt_runtime_us = -1\r

3393 kernel.shmmax = 2147483648\r

3394 kernel.shmall = 2147483648\r

3395 Note: Forwarding request to 'systemctl disable irqbalance.service'.\r

3396 start 5GNR Test MAC\r

3397 =========================\r

3398 5GNR Testmac Application\r

3399 =========================\r

3400 testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: testmac_cfg.xml\r

3401 \r

3402 \r

3403 ---------------------------\r

3404 TestMacCfg.xml Version: 20.08\r

3405 ---------------------------\r

3406 \r

3407 --version=20.08\r

3408 --wls_dev_name=wls0\r

3409 --wlsMemorySize=0x3F600000\r

3410 --dpdkIovaMode=0\r

3411 --PhyStartMode=1\r

3412 --PhyStartPeriod=40\r

3413 --PhyStartCount=0\r

3414 --MlogSubframes=128\r

3415 --MlogCores=3\r

3416 --MlogSize=2048\r

3417 --latencyTest=0\r

3418 --wlsRxThread=1, 90, 0\r

3419 --systemThread=0, 0, 0\r

3420 --runThread=0, 89, 0\r

3421 --urllcThread=16, 90, 0\r

3422 \r

3423 wls_dev_filename: wls0\r

3424 sys_reg_signal_handler:[err] signal handler in NULL\r

3425 sys_reg_signal_handler:[err] signal handler in NULL\r

3426 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1496523032 [Hz]\r

3427 Ticks per usec 1496\r

3428 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r

3429 mlogSubframes (128), mlogCores(3), mlogSize(2048)\r

3430 localMLogTimerInit\r

3431 System clock (rdtsc) resolution 1496526140 [Hz]\r

3432 Ticks per us 1496\r

3433 MLog Storage: 0x7f821905d100 -> 0x7f821911d920 [ 788512 bytes ]\r

3434 localMLogFreqReg: 1496. Storing: 1496\r

3435 Mlog Open successful\r

3436 \r

3437 Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0 --iova-mode=pa\r

3438 EAL: Detected 48 lcore(s)\r

3439 EAL: Detected 1 NUMA nodes\r

3440 EAL: Auto-detected process type: SECONDARY\r

3441 EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket_29473_6b9e031eaf8b\r

3442 EAL: Selected IOVA mode 'PA'\r

3443 EAL: Probing VFIO support...\r

3444 EAL: PCI device 0000:01:00.0 on NUMA socket 0\r

3445 EAL: probe driver: 8086:1533 net_e1000_igb\r

3446 EAL: PCI device 0000:18:00.0 on NUMA socket 0\r

3447 EAL: probe driver: 8086:1563 net_ixgbe\r

3448 EAL: PCI device 0000:18:00.1 on NUMA socket 0\r

3449 EAL: probe driver: 8086:1563 net_ixgbe\r

3450 EAL: PCI device 0000:8c:00.0 on NUMA socket 0\r

3451 EAL: probe driver: 8086:d58 net_i40e\r

3452 EAL: PCI device 0000:8c:00.1 on NUMA socket 0\r

3453 EAL: probe driver: 8086:d58 net_i40e\r

3454 EAL: PCI device 0000:90:00.0 on NUMA socket 0\r

3455 EAL: probe driver: 8086:d58 net_i40e\r

3456 EAL: PCI device 0000:90:00.1 on NUMA socket 0\r

3457 EAL: probe driver: 8086:d58 net_i40e\r

3458 wls_lib: Open wls0 (DPDK memzone)\r

3459 wls_lib: WLS_Open 0x43f600000\r

3460 wls_lib: link: 1 <-> 0\r

3461 wls_lib: Mode 1\r

3462 wls_lib: WLS shared management memzone: wls0\r

3463 wls_lib: hugePageSize on the system is 1073741824\r

3464 wls_lib: WLS_Alloc [1063256064] bytes\r

3465 wls_lib: Connecting to remote peer ...\r

3466 wls_lib: Connected to remote peer\r

3467 wls_mac_create_mem_array: pMemArray[0xf354350] pMemArrayMemory[0x400000000] totalSize[1063256064] nBlockSize[262144] numBlocks[4056]\r

3468 WLS_EnqueueBlock [1]\r

3469 WLS inited ok [383]\r

3470 \r

3471 \r

3472 ===========================================================================================================\r

3473 TESTMAC VERSION\r

3474 ===========================================================================================================\r

3475 \r

3476 $Version: #DIRTY# $ (x86)\r

3477 IMG-date: Aug 5 2020\r

3478 IMG-time: 18:32:53\r

3479 ===========================================================================================================\r

3480 \r

3481 \r

3482 ===========================================================================================================\r

3483 Testmac threads in application\r

3484 ===========================================================================================================\r

3485 testmac_run_thread: [PID: 29477] binding on [CPU 0] [PRIO: 89] [POLICY: 1]\r

3486 wls_mac_rx_task: [PID: 29476] binding on [CPU 1] [PRIO: 90] [POLICY: 1]\r

3487 ===========================================================================================================\r

3488 \r

3489 testmac_set_phy_start: mode[1], period[40], count[0]\r

3490 \r

3491 testmac_run_load_files:\r

3492 Loading DL Config Files:\r

3493 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg\r

3494 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg\r

3495 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg\r

3496 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg\r

3497 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg\r

3498 Loading UL Config Files:\r

3499 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg\r

3500 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg\r

3501 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg\r

3502 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_10mhz.cfg\r

3503 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_20mhz.cfg\r

3504 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_40mhz.cfg\r

3505 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg\r

3506 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg\r

3507 Loading FD Config Files:\r

3508 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg\r

3509 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg\r

3510 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg\r

3511 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg\r

3512 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg\r

3513 testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg\r

3514 \r

3515 TESTMAC DL TESTS:\r

3516 Numerology[0] Bandwidth[5]\r

3517 1001 1002 1003 1004 1005 1006 1007 1008\r

3518 Numerology[0] Bandwidth[10]\r

3519 1001 1002 1003 1004 1005 1006 1007 1008\r

3520 Numerology[0] Bandwidth[20]\r

3521 1001 1002 1003 1004 1005 1006 1007 1008\r

3522 Numerology[1] Bandwidth[100]\r

3523 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211\r

3524 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221\r

3525 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241\r

3526 1242 1243 1244 1245 1250 1251 1252 1260 1261 1262\r

3527 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272\r

3528 1300 1301 1302 1303 1304 1305 1402 1404 1408 1416\r

3529 1500 1501 1502 1503 1504 1505 1506 2213 2214 2215\r

3530 2217 2218 2219 2223 2224 2225 2227 2228 2229 2500\r

3531 2501 2502 2503 2504 3213 3214 3215 3217 3218 3219\r

3532 3223 3224 3225 3227 3228 3229\r

3533 Numerology[3] Bandwidth[100]\r

3534 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011\r

3535 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031\r

3536 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003\r

3537 3030\r

3538 \r

3539 TESTMAC UL TESTS:\r

3540 Numerology[0] Bandwidth[5]\r

3541 1001 1002 1003 1069 1070 1071 1072 1073 1074 1075\r

3542 1076 1077\r

3543 Numerology[0] Bandwidth[10]\r

3544 1001 1002 1069 1070 1071 1072 1073 1074 1075 1076\r

3545 1077\r

3546 Numerology[0] Bandwidth[20]\r

3547 1001 1002 1003 1004 1005 1006 1007 1008 1069 1070\r

3548 1071 1072 1073 1074 1075 1076 1077\r

3549 Numerology[1] Bandwidth[10]\r

3550 1069 1070 1071 1072 1073 1074 1075 1076 1077\r

3551 Numerology[1] Bandwidth[20]\r

3552 1069 1070 1071 1072 1073 1074 1075 1076 1077\r

3553 Numerology[1] Bandwidth[40]\r

3554 1069 1070 1071 1072 1073 1074 1075 1076 1077\r

3555 Numerology[1] Bandwidth[100]\r

3556 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038\r

3557 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074\r

3558 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092\r

3559 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105\r

3560 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117\r

3561 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132\r

3562 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142\r

3563 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160\r

3564 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170\r

3565 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206\r

3566 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216\r

3567 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233\r

3568 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421\r

3569 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431\r

3570 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504\r

3571 1505 1506 1507 1508 1512 1513 1514 1515 1516 1540\r

3572 1541 1542 1563 1564 1565 1566 1567 1568 1569 1570\r

3573 1571 1572 1573 1574 1575 1576 1577 1600 1601 1602\r

3574 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612\r

3575 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622\r

3576 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632\r

3577 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642\r

3578 1700 1701 1702 1969 1970 1971 1972 1973 1974 1975\r

3579 1976 1977 2236 2237 3236 3237\r

3580 Numerology[3] Bandwidth[100]\r

3581 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012\r

3582 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026\r

3583 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036\r

3584 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051\r

3585 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065\r

3586 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084\r

3587 1085 1086 2001 2002 2003 3001 3002 3003\r

3588 \r

3589 TESTMAC FD TESTS:\r

3590 Numerology[0] Bandwidth[5]\r

3591 1001 6001 8001 10001 12001\r

3592 Numerology[0] Bandwidth[10]\r

3593 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002\r

3594 6002 8002 10002 12002 1003\r

3595 Numerology[0] Bandwidth[20]\r

3596 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021\r

3597 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201\r

3598 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221\r

3599 1222 1223 1224 1225 1226 1227 1228\r

3600 Numerology[1] Bandwidth[40]\r

3601 1001 1002 1003\r

3602 Numerology[1] Bandwidth[100]\r

3603 1001 1002 1200 1201 1202 1203 1204 1205 1206 1207\r

3604 1208 1209 1210 1300 1301 1302 1303 1304 1305 1306\r

3605 1307 1308 1350 1351 1352 1353 1354 1355 1356 1357\r

3606 1358 1359 1370 1371 1372 1373 1374 1375 1376 1377\r

3607 1378 1401 1402 1403 1404 1405 1406 1411 1412 1490\r

3608 1494 1500 1501 1502 1503 1504 1510 1511 1512 1513\r

3609 1514 1515 1520 1521 1522 1523 1524 1525 1526 1527\r

3610 1528 1529 1530 1531 1532 1540 1541 1700 1701 1702\r

3611 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529\r

3612 2530 2531 2532 3524 3525 3526 3527 3528 3529 3530\r

3613 3531 3532 4524 4525 4526 4527 4528 4529 4530 4531\r

3614 4532\r

3615 Numerology[3] Bandwidth[100]\r

3616 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011\r

3617 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080\r

3618 1081 1082 2001 3001\r

3619 testmac_run_parse_file Parsing config file: ./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg\r

3620 testmac_set_phy_start: mode[4], period[0], count[100200]\r

3621 Adding setoption pdsch_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]\r

3622 Adding setoption pdsch_dl_weight_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]\r

3623 Adding setoption pusch_chan_est_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]\r

3624 Adding setoption pusch_mmse_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]\r

3625 Adding setoption pusch_llr_rx_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]\r

3626 Adding setoption pusch_ul_weight_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]\r

3627 Adding setoption timer_multi_cell [numTests: 0] [nCellMask: 0xffffffff] [nOption: 10000] [pMacOptions: 10000 / 0x00002710]\r

3628 Adding setoption fec_dec_num_iter [numTests: 0] [nCellMask: 0xffffffff] [nOption: 3] [pMacOptions: -253 / 0xffffff03]\r

3629 Adding SetCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[137170526192 / 0x0000001ff0001ff0]\r

3630 Adding SetDlbeamCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[2016 / 0x00000000000007e0]\r

3631 Adding SetSrsCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[268435472 / 0x0000000010000010]\r

3632 Setting Testmac System Core: 2\r

3633 Setting Testmac Run Core: 2\r

3634 Setting Testmac Wls Core: 3\r

3635 Adding Test[3370]. NumCarr[3], Current Directory: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/\r

3636 Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg\r

3637 Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r

3638 Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r

3639 \r

3640 testmac_set_multi_cell_timer: 10000\r

3641 \r

3642 \r

3643 \r

3644 \r

3645 ----------------------------------------------------------------------------------------\r

3646 Running Test[3370]. NumCarr[3], Current Directory: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/\r

3647 Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg\r

3648 Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r

3649 Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r

3650 TESTMAC>welcome to application console\r

3651 \r

3652 MLogRestart\r

3653 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r

3654 mlogSubframes (128), mlogCores(3), mlogSize(2048)\r

3655 localMLogTimerInit\r

3656 System clock (rdtsc) resolution 1496525908 [Hz]\r

3657 Ticks per us 1496\r

3658 MLog Storage: 0x7f8208000900 -> 0x7f82080c1120 [ 788512 bytes ]\r

3659 localMLogFreqReg: 1496. Storing: 1496\r

3660 Mlog Open successful\r

3661 \r

3662 testmac_mac2phy_set_num_cells: Setting Max Cells: 3\r

3663 testmac_config_parse: test_num[3370] test_type[2] numcarrier[3]\r

3664 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r

3665 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(1)\r

3666 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(2)\r

3667 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r

3668 Queueing MSG_TYPE_PHY_CONFIG_REQ(0)\r

3669 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(1)\r

3670 Queueing MSG_TYPE_PHY_CONFIG_REQ(1)\r

3671 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(2)\r

3672 Queueing MSG_TYPE_PHY_CONFIG_REQ(2) and sending list\r

3673 Received MSG_TYPE_PHY_CONFIG_RESP(0)\r

3674 Queueing MSG_TYPE_PHY_START_REQ(0)\r

3675 Received MSG_TYPE_PHY_CONFIG_RESP(1)\r

3676 Queueing MSG_TYPE_PHY_START_REQ(1)\r

3677 Received MSG_TYPE_PHY_CONFIG_RESP(2)\r

3678 Queueing MSG_TYPE_PHY_START_REQ(2) and sending list\r

3679 Received MSG_TYPE_PHY_START_RESP(0)\r

3680 Received MSG_TYPE_PHY_START_RESP(1)\r

3681 Received MSG_TYPE_PHY_START_RESP(2)\r

3682 ==== testmac Time: 5000 ms NumCarrier: 3 Total Proc Time: [ 0.00.. 6.30.. 19.00] usces====\r

3683 Core Utilization [Core: 3] [Util %: 0.42%]\r

3684 ==== testmac Time: 10000 ms NumCarrier: 3 Total Proc Time: [ 6.00..116.80..206.00] usces====\r

3685 Core Utilization [Core: 3] [Util %: 27.86%]\r

3686 ==== testmac Time: 20000 ms NumCarrier: 3 Total Proc Time: [ 10.00..156.33..260.00] usces====\r

3687 Core Utilization [Core: 3] [Util %: 32.31%]\r

3688 ==== testmac Time: 25000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.33..260.00] usces====\r

3689 Core Utilization [Core: 3] [Util %: 32.30%]\r

3690 ==== testmac Time: 30000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.44..256.00] usces====\r

3691 Core Utilization [Core: 3] [Util %: 32.32%]\r

3692 ==== testmac Time: 35000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.42..258.00] usces====\r

3693 Core Utilization [Core: 3] [Util %: 32.32%]\r

3694 ==== testmac Time: 40000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.45..258.00] usces====\r

3695 Core Utilization [Core: 3] [Util %: 32.33%]\r

3696 ==== testmac Time: 45000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.40..282.00] usces====\r

3697 Core Utilization [Core: 3] [Util %: 32.32%]\r

3698 \r

3699 TESTMAC>==== testmac Time: 50000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.39..260.00] usces====\r

3700 Core Utilization [Core: 3] [Util %: 32.31%]\r

3701 Received MSG_TYPE_PHY_STOP_RESP(0)\r

3702 Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(0)\r

3703 Received MSG_TYPE_PHY_STOP_RESP(1)\r

3704 Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(1)\r

3705 Received MSG_TYPE_PHY_STOP_RESP(2)\r

3706 Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(2) and sending list\r

3707 Received MSG_TYPE_PHY_SHUTDOWN_RESP(2)\r

3708 Received MSG_TYPE_PHY_SHUTDOWN_RESP(0)\r

3709 Received MSG_TYPE_PHY_SHUTDOWN_RESP(1)\r

3710 MLogPrint: ext_filename((null).bin)\r

3711 Opening MLog File: testmac-mlog-c0.bin\r

3712 MLog file testmac-mlog-c0.bin closed\r

3713 Mlog Print successful\r

3714 Test[FD_mu1_100mhz_3370] Completed\r

3715 wls_mac_free_list_all:\r

3716 nTotalBlocks[4056] nAllocBlocks[1010] nFreeBlocks[3046]\r

3717 nTotalAllocCnt[4538427] nTotalFreeCnt[4537417] Diff[1010]\r

3718 nDlBufAllocCnt[3609068] nDlBufFreeCnt[3609068] Diff[0]\r

3719 nUlBufAllocCnt[929359] nUlBufFreeCnt[928349] Diff[1010]\r

3720 \r

3721 All Tests Completed, Total run 1 Tests, PASS 1 Tests, and FAIL 0 Tests\r