1 .. Copyright (c) 2019-2022 Intel
3 .. Licensed under the Apache License, Version 2.0 (the "License");
4 .. you may not use this file except in compliance with the License.
5 .. You may obtain a copy of the License at
7 .. http://www.apache.org/licenses/LICENSE-2.0
9 .. Unless required by applicable law or agreed to in writing, software
10 .. distributed under the License is distributed on an "AS IS" BASIS,
11 .. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 .. See the License for the specific language governing permissions and
13 .. limitations under the License.
22 A.1 Setup Configuration
23 -----------------------
24 The configuration shown in Figure 26 shows how to set up a test
25 environment to execute O-RAN scenarios where O-DU and 0-RU are simulated
26 using the sample application provided with the FlexRAN release package.
27 This setup allows development and prototyping as well as testing of
28 O-RAN specific functionality. The O-DU side can be instantiated with a
29 full 5G NR L1 reference as well. The configuration differences of the 5G
30 NR l1app configuration are provided below. Steps for running the sample
31 application on the O-DU side and O-RU side are the same, except
32 configuration file options may be different.
34 .. image:: images/Setup-for-O-RAN-Testing.jpg
36 :alt: Figure 27. Setup for O-RAN Testing
38 Figure 27. Setup for O-RAN Testing
42 .. image:: images/Setup-for-O-RAN-Testing-with-PHY-and-Configuration-C3.jpg
44 :alt: Figure 28. Setup for O-RAN Testing with PHY and Configuration C3
46 Figure 28. Setup for O-RAN Testing with PHY and Configuration C3
50 .. image:: images/Setup-for-O-RAN-Testing-with-PHY-and-Configuration-C3-for-Massive-MIMO.jpg
52 :alt: Figure 29. Setup for O-RAN Testing with PHY and Configuration C3 for
54 Figure 29. Setup for O-RAN Testing with PHY and Configuration C3 for
62 Each server in *Figure 27* requires the following:
64 - Wolfpass server according to recommended BOM for FlexRAN such as
65 Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20
66 cores (two sockets) or higher
68 - Wilson City or Coyotee Pass server with Intel® Xeon® Icelake CPU for
69 Massive-MIMO with L1 pipeline testing
73 - Intel® Virtualization Technology Enabled
75 - Intel® VT for Directed I/O - Enabled
77 - ACS Control - Enabled
79 - Coherency Support - Disabled
81 - Front Haul networking cards:
83 - Intel® Ethernet Converged Network Adapter XL710-QDA2
85 - Intel® Ethernet Converged Network Adapter XXV710-DA2
87 - Intel® Ethernet Converged Network Adapter E810-CQDA2
89 - Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000
91 - Back (Mid) Haul networking card can be either:
93 - Intel® Ethernet Connection X722 for 10GBASE-T
95 - Intel® 82599ES 10-Gigabit SFI/SFP+ Network Connection
97 - Other networking cards capable of HW timestamping for PTP synchronization.
99 - Both Back (mid) Haul and Front Haul NIC require support for PTP HW timestamping.
101 The recommended configuration for NICs is::
106 firmware-version: 8.20 0x80009bd4 1.2879.0
107 expansion-rom-version:
108 bus-info: 0000:21:00.0
109 supports-statistics: yes
111 supports-eeprom-access: yes
112 supports-register-dump: yes
113 supports-priv-flags: yes
115 Time stamping parameters for enp33s0f0:
117 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
118 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
119 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
120 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
121 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
122 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
123 PTP Hardware Clock: 4
124 Hardware Transmit Timestamp Modes:
125 off (HWTSTAMP_TX_OFF)
127 Hardware Receive Filter Modes:
128 none (HWTSTAMP_FILTER_NONE)
129 ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
130 ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
131 ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
132 ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
133 ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
134 ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
135 ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
136 ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
137 ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
138 ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
139 ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
141 The recommended configuration for Columbiaville NICs (base on Intel®
142 Ethernet 800 Series (Columbiaville) CVL 2.3 release is::
147 firmware-version: 2.3 0x80005D18
148 expansion-rom-version:
149 bus-info: 0000:51:00.0
150 supports-statistics: yes
152 supports-eeprom-access: yes
153 supports-register-dump: yes
154 supports-priv-flags: yes
156 Time stamping parameters for enp81s0f0:
158 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
159 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
160 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
161 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
162 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
163 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
164 PTP Hardware Clock: 1
165 Hardware Transmit Timestamp Modes:
166 off (HWTSTAMP_TX_OFF)
168 Hardware Receive Filter Modes:
169 none (HWTSTAMP_FILTER_NONE)
170 all (HWTSTAMP_FILTER_ALL)
172 Recommended version of
174 ICE COMMS Package version 1.3.24.0
176 *Note*. If your firmware version does not match with the ones in the output
177 images, you can download the correct version from the Intel Download
178 Center. It is Intel's repository for the latest software and drivers
179 for Intel products. The NVM Update Packages for Windows*, Linux*,
180 ESX*, FreeBSD*, and EFI/EFI2 are located at:
184 https://downloadcenter.intel.com/download/24769 (700 series)
186 https://downloadcenter.intel.com/download/29736 (E810 series)
188 PTP Grand Master is required to be available in the network to provide
189 synchronization of both O-DU and RU to GPS time.
191 The software package includes Linux\* CentOS\* operating system and RT
192 patch according to FlexRAN Reference Solution Cloud-Native Setup
193 document (refer to Table 2). Only real-time HOST is required.
195 1.Install Intel® C++ Compiler v19.0.3
197 2.Download DPDK v20.11.3
199 3.Patch DPDK with FlexRAN BBDev patch as per given release.
201 4.Double check that FlexRAN DPDK patch includes changes below relevant
202 to O-RAN Front haul::
205 diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
206 index 85a6a86..236fbe0 100644
207 --- a/drivers/net/i40e/i40e_ethdev.c
208 +++ b/drivers/net/i40e/i40e_ethdev.c
209 @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
210 /* Map queues with MSIX interrupt */
211 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
212 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
213 - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
214 + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE);
215 i40e_vsi_enable_queues_intr(main_vsi);
217 /* Map VMDQ VSI queues with MSIX interrupt */
218 @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
219 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
221 + i40e_aq_debug_write_global_register(hw,
225 /* enable FDIR MSIX interrupt */
226 if (pf->fdir.fdir_vsi) {
227 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
228 diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
229 index 001c301..6f9ffdb 100644
230 --- a/drivers/net/i40e/i40e_ethdev_vf.c
231 +++ b/drivers/net/i40e/i40e_ethdev_vf.c
232 @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off {
234 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
235 map_info->num_vectors = 1;
236 - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
237 + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE;
238 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
239 /* Alway use default dynamic MSIX interrupt */
240 map_info->vecmap[0].vector_id = vector_id;
241 diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
242 index 26b1927..018eb8f 100644
243 --- a/drivers/net/ixgbe/ixgbe_ethdev.c
244 +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
245 @@ -3705,7 +3705,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
246 * except for 82598EB, which remains constant.
248 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
249 - hw->mac.type != ixgbe_mac_82598EB)
250 + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != ixgbe_mac_82599EB)
251 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
253 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
254 diff --git a/lib/librte_eal/common/include/rte_dev.h b/lib/librte_eal/common/include/rte_dev.h
259 diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
260 index de189daba..d9aff341c 100644
261 --- a/drivers/net/ice/ice_ethdev.c
262 +++ b/drivers/net/ice/ice_ethdev.c
263 @@ -2604,8 +2604,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
265 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
266 base_queue + i, msix_vect);
267 - /* set ITR0 value */
268 - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
270 + * Empirical configuration for optimal real time latency
271 + * reduced interrupt throttling to 2 ms
272 + * Columbiaville pre-PRQ : local patch subject to change
274 + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
275 + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), QRX_ITR_NO_EXPR_M);
276 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
277 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
280 5.Build and install the DPDK.::
282 See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html
286 6.Make sure that the i40e is patched with the code below to get the
287 best latency of packet processing.::
288 --- i40e.h 2018-11-30 11:27:00.000000000 +0000
289 +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000
292 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
293 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
294 - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
295 + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
296 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
297 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
298 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
300 --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000
301 +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000
302 @@ -15296,6 +15296,9 @@
303 pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;
304 /* print a string summarizing features */
305 i40e_print_features(pf);
307 + /* write to this register to clear rx descriptor */
308 + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL);
312 A.3 Configuration of System
313 ---------------------------
314 1.Boot Linux with the following arguments::
317 BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro
318 crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt
319 usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
320 intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll
321 hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G
322 isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20
325 2.Boot Linux with the following arguments for Icelake CPU::
328 BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64
329 root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root
330 rd.lvm.lv=centos/swap rhgb quiet intel_iommu=off usbcore.autosuspend=-1
331 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
332 intel_pstate=disable cgroup_disable=memory mce=off hugepagesz=1G
333 hugepages=40 hugepagesz=2M hugepages=0 default_hugepagesz=1G
334 isolcpus=1-23,25-47 rcu_nocbs=1-23,25-47 kthread_cpus=0 irqaffinity=0
337 3.Download from Intel Website and install updated version of i40e
338 driver if needed. The current recommended version of i40e is 2.14.13.
339 However, any latest version of i40e after 2.9.21 expected to be
340 functional for O-RAN FH.
342 4.For Columbiaville download Intel® Ethernet 800 Series (Columbiaville)
343 CVL2.3 B0/C0 Sampling Sample Validation Kit (SVK) from Intel Customer
344 Content Library. The current recommended version of ICE driver is
345 1.3.2 with ICE COMMS Package version 1.3.24.0. IAVF recommended
348 5.Identify PCIe Bus address of the Front Haul NIC (Fortville)::
351 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
352 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
353 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
354 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
356 6.Identify PCIe Bus address of the Front Haul NIC (Columbiaville)::
359 18:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)
360 18:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)
361 18:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)
362 18:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)
363 51:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)
364 51:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)
365 51:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)
366 51:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)
368 7.Identify the Ethernet device name::
373 firmware-version: 8.20 0x80009bd4 1.2879.0
374 expansion-rom-version:
375 bus-info: 0000:21:00.0
376 supports-statistics: yes
378 supports-eeprom-access: yes
379 supports-register-dump: yes
380 supports-priv-flags: yesEnable
387 firmware-version: 2.3 0x80005D18
388 expansion-rom-version:
389 bus-info: 0000:51:00.0
390 supports-statistics: yes
392 supports-eeprom-access: yes
393 supports-register-dump: yes
394 supports-priv-flags: yes
396 8. Enable 3 virtual functions (VFs) on the each of two ports of each
401 echo 0 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs
402 echo 0 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs
404 echo 0 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs
405 echo 0 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs
410 echo 3 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs
411 echo 3 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs
413 echo 3 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs
414 echo 3 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs
425 echo " Usage $0 qos with 0<= qos <= 7 with 0 as a default if no qos is provided"
430 ip link set enp136s0f0 vf 0 mac 00:11:22:33:00:00 vlan 1 qos $b
431 ip link set enp136s0f1 vf 0 mac 00:11:22:33:00:10 vlan 1 qos $b
433 ip link set enp136s0f0 vf 1 mac 00:11:22:33:01:00 vlan 2 qos $b
434 ip link set enp136s0f1 vf 1 mac 00:11:22:33:01:10 vlan 2 qos $b
436 ip link set enp136s0f0 vf 2 mac 00:11:22:33:02:00 vlan 3 qos $b
437 ip link set enp136s0f1 vf 2 mac 00:11:22:33:02:10 vlan 3 qos $b
440 ip link set enp134s0f0 vf 0 mac 00:11:22:33:00:01 vlan 1 qos $b
441 ip link set enp134s0f1 vf 0 mac 00:11:22:33:00:11 vlan 1 qos $b
443 ip link set enp134s0f0 vf 1 mac 00:11:22:33:01:01 vlan 2 qos $b
444 ip link set enp134s0f1 vf 1 mac 00:11:22:33:01:11 vlan 2 qos $b
446 ip link set enp134s0f0 vf 2 mac 00:11:22:33:02:01 vlan 3 qos $b
447 ip link set enp134s0f1 vf 2 mac 00:11:22:33:02:11 vlan 3 qos $b
449 where output is next::
453 9: enp134s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
454 link/ether 3c:fd:fe:b9:f9:60 brd ff:ff:ff:ff:ff:ff
455 vf 0 MAC 00:11:22:33:00:01, vlan 1, spoof checking on, link-state auto, trust off
456 vf 1 MAC 00:11:22:33:01:01, vlan 2, spoof checking on, link-state auto, trust off
457 vf 2 MAC 00:11:22:33:02:01, vlan 3, spoof checking on, link-state auto, trust off
458 11: enp134s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
459 link/ether 3c:fd:fe:b9:f9:61 brd ff:ff:ff:ff:ff:ff
460 vf 0 MAC 00:11:22:33:00:11, vlan 1, spoof checking on, link-state auto, trust off
461 vf 1 MAC 00:11:22:33:01:11, vlan 2, spoof checking on, link-state auto, trust off
462 vf 2 MAC 00:11:22:33:02:11, vlan 3, spoof checking on, link-state auto, trust off
463 12: enp136s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
464 link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff
465 vf 0 MAC 00:11:22:33:00:00, vlan 1, spoof checking on, link-state auto, trust off
466 vf 1 MAC 00:11:22:33:01:00, vlan 2, spoof checking on, link-state auto, trust off
467 vf 2 MAC 00:11:22:33:02:00, vlan 3, spoof checking on, link-state auto, trust off
468 14: enp136s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
469 link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff
470 vf 0 MAC 00:11:22:33:00:10, vlan 1, spoof checking on, link-state auto, trust off
471 vf 1 MAC 00:11:22:33:01:10, vlan 2, spoof checking on, link-state auto, trust off
472 vf 2 MAC 00:11:22:33:02:10, vlan 3, spoof checking on, link-state auto, trust off
478 More information about VFs supported by Intel NICs can be found at
479 https://doc.dpdk.org/guides/nics/intel_vf.html.
481 The resulting configuration can look like the listing below, where six
482 new VFs were added for each O-DU and O-RU port::
485 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
486 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
487 86:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
488 86:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
489 86:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
490 86:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
491 86:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
492 86:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
493 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
494 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
495 88:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
496 88:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
497 88:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
498 88:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
499 88:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
500 88:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
502 9. Example where O-DU and O-RU simulation run on the same system:
510 echo 1 > /proc/sys/kernel/core_uses_pid
512 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_du.cfg --num_eth_vfs 6 \
513 --vf_addr_o_xu_a "0000:88:02.0,0000:88:0a.0" \
514 --vf_addr_o_xu_b "0000:88:02.1,0000:88:0a.1" \
515 --vf_addr_o_xu_c "0000:88:02.2,0000:88:0a.2"
523 echo 1 > /proc/sys/kernel/core_uses_pid
525 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg --num_eth_vfs 6 \
526 --vf_addr_o_xu_a "0000:86:02.0,0000:86:0a.0" \
527 --vf_addr_o_xu_b "0000:86:02.1,0000:86:0a.1" \
528 --vf_addr_o_xu_c "0000:86:02.2,0000:86:0a.2"
531 Install and Configure Sample Application
532 ========================================
534 To install and configure the sample application:
536 1.Set up the environment::
538 For Skylake and Cascadelake
539 export GTEST_ROOT=`pwd`/gtest-1.7.0
540 export RTE_SDK=`pwd`/dpdk-20.11.3
541 export RTE_TARGET=x86_64-native-linuxapp-icc
542 export DIR_WIRELESS_SDK_ROOT=`pwd`/wireless_sdk
543 export WIRELESS_SDK_TARGET_ISA=avx512
544 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
545 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
546 export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
547 export XRAN_DIR=`pwd`/flexran_xran
550 export GTEST_ROOT=`pwd`/gtest-1.7.0
551 export RTE_SDK=`pwd`/dpdk-20.11
552 export RTE_TARGET=x86_64-native-linuxapp-icc
553 export DIR_WIRELESS_SDK_ROOT=`pwd`/wireless_sdk
554 export WIRELESS_SDK_TARGET_ISA=snc
555 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
556 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
557 export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
558 export XRAN_DIR=`pwd`/flexran_xran
560 2.export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library::
562 [turner@xran home]$ cd $MLOG_DIR
563 [turner@xran xran]$ ./build.sh
565 3.Compile xRAN library and test the application::
567 [turner@xran home]$ cd $XRAN_DIR
568 [turner@xran xran]$ ./build.sh
570 4.Configure the sample app.
572 IQ samples can be generated using Octave\* and script
573 libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64
574 compatible with get_test.m)
576 Other IQ sample test vectors can be used as well. The format of IQ
577 samples is binary int16_t I and Q for N slots of the OTA RF signal. For
578 example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms =
579 3548160 bytes per antenna. Refer to comments in gen_test.m to correctly
580 specify the configuration for IQ test vector generation.
582 Update usecase_du.dat (or usecase_ru.cfg) with a suitable configuration
585 Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable
586 configuration for your scenario.
588 Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1
589 used for U-plane and C-plane correspondingly.
591 5.Run the application using run_o_du.sh (run_o_ru.sh).
593 Install and Configure FlexRAN 5G NR L1 Application
594 ==================================================
596 The 5G NR layer 1 application can be used for executing the scenario for
597 mmWave with either the RU sample application or just the O-DU side. The
598 current release supports the constant configuration of the slot pattern
599 and RB allocation on the PHY side. The build process follows the same
600 basic steps as for the sample application above and is similar to
601 compiling 5G NR l1app for mmWave with Front Haul FPGA. Please follow the
602 general build process in the FlexRAN 5G NR Reference Solution L1 User
603 Guide (refer to *Table 2*.)
605 1.xRAN library is enabled by default l1 application.
607 2.Build the 5G NR L1 application using the command::
609 ./flexran_build.sh -r 5gnr_mmw -i avx512 -m sdk -m fb -m mlog –m wls -m
610 5gnr_l1app_mmw -m xran -m 5gnr_testmac
612 3.Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and
613 xrancfg_sub6.xml (or other xml if it is mmwave or massive MIMO). ::
616 <version>20.08</version>
617 <!-- numbers of O-RU connected to O-DU. All O-RUs are the same
618 capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
620 <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
621 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>
622 <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link
624 <oRuLinesNumber>1</oRuLinesNumber>
627 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>
628 <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>
629 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>
630 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>
633 <PciBusAddoRu1Vf0>0000:51:01.4</PciBusAddoRu1Vf0>
634 <PciBusAddoRu1Vf1>0000:51:01.5</PciBusAddoRu1Vf1>
635 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>
636 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>
639 <PciBusAddoRu2Vf0>0000:51:02.0</PciBusAddoRu2Vf0>
640 <PciBusAddoRu2Vf1>0000:51:02.1</PciBusAddoRu2Vf1>
641 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>
642 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>
645 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>
646 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>
647 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>
648 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>
650 <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->
651 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>
652 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>
653 <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->
654 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>
655 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>
657 <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->
658 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>
659 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>
660 <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->
661 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>
662 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>
664 <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->
665 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>
666 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>
667 <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->
668 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>
669 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>
671 <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->
672 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>
673 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>
674 <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->
675 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>
676 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>
678 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
679 <oRu0NumCc>12</oRu0NumCc>
680 <!-- First Phy instance ID mapped to this O-RU CC0 -->
681 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>
682 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
683 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>
684 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
685 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>
686 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
687 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>
688 <!-- First Phy instance ID mapped to this O-RU CC0 -->
689 <oRu0Cc4PhyId>4</oRu0Cc4PhyId>
690 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
691 <oRu0Cc5PhyId>5</oRu0Cc5PhyId>
692 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
693 <oRu0Cc6PhyId>6</oRu0Cc6PhyId>
694 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
695 <oRu0Cc7PhyId>7</oRu0Cc7PhyId>
696 <!-- First Phy instance ID mapped to this O-RU CC0 -->
697 <oRu0Cc8PhyId>8</oRu0Cc8PhyId>
698 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
699 <oRu0Cc9PhyId>9</oRu0Cc9PhyId>
700 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
701 <oRu0Cc10PhyId>10</oRuCc10PhyId>
702 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
703 <oRu0Cc11PhyId>11</oRu0Cc11PhyId>
705 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
706 <oRu1NumCc>1</oRu1NumCc>
707 <!-- First Phy instance ID mapped to this O-RU CC0 -->
708 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>
709 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
710 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>
711 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
712 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>
713 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
714 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>
716 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
717 <oRu2NumCc>1</oRu2NumCc>
718 <!-- First Phy instance ID mapped to this O-RU CC0 -->
719 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>
720 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
721 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>
722 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
723 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>
724 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
725 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>
727 <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
728 <xRANThread>19, 96, 0</xRANThread>
730 <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
731 <xRANWorker>0x8000000000, 96, 0</xRANWorker>
732 <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
733 <Category>0</Category>
735 <!-- XRAN: enable sleep on PMD cores -->
736 <xranPmdSleep>0</xranPmdSleep>
739 <Tadv_cp_dl>25</Tadv_cp_dl>
740 <!-- Reception Window C-plane DL-->
741 <T2a_min_cp_dl>50</T2a_min_cp_dl>
742 <T2a_max_cp_dl>140</T2a_max_cp_dl>
743 <!-- Reception Window C-plane UL-->
744 <T2a_min_cp_ul>50</T2a_min_cp_ul>
745 <T2a_max_cp_ul>140</T2a_max_cp_ul>
746 <!-- Reception Window U-plane -->
747 <T2a_min_up>25</T2a_min_up>
748 <T2a_max_up>140</T2a_max_up>
749 <!-- Transmission Window U-plane -->
750 <Ta3_min>20</Ta3_min>
751 <Ta3_max>32</Ta3_max>
753 <!-- O-DU Settings -->
756 <!-- VLAN Tag used for C-Plane -->
757 <c_plane_vlan_tag>1</c_plane_vlan_tag>
758 <u_plane_vlan_tag>2</u_plane_vlan_tag>
760 <!-- Transmission Window Fast C-plane DL -->
761 <T1a_min_cp_dl>70</T1a_min_cp_dl>
762 <T1a_max_cp_dl>100</T1a_max_cp_dl>
763 <!-- Transmission Window Fast C-plane UL -->
764 <T1a_min_cp_ul>60</T1a_min_cp_ul>
765 <T1a_max_cp_ul>70</T1a_max_cp_ul>
766 <!-- Transmission Window U-plane -->
767 <T1a_min_up>35</T1a_min_up>
768 <T1a_max_up>50</T1a_max_up>
769 <!-- Reception Window U-Plane-->
771 <Ta4_max>45</Ta4_max>
773 <!-- Enable Control Plane -->
774 <EnableCp>1</EnableCp>
776 <DynamicSectionEna>0</DynamicSectionEna>
777 <!-- Enable Dynamic section allocation for UL -->
778 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>
779 <xRANSFNWrap>0</xRANSFNWrap>
780 <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is
781 transmitted (used for testing. If 0, then value is used from
783 <xRANNumDLPRBs>0</xRANNumDLPRBs>
784 <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is
785 received (used for testing. If 0, then value is used from
787 <xRANNumULPRBs>0</xRANNumULPRBs>
788 <!-- refer to alpha as defined in section 9.7.2 of O-RAN spec. this
789 value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->
790 <Gps_Alpha>0</Gps_Alpha>
791 <!-- beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~
793 <Gps_Beta>0</Gps_Beta>
795 <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
796 <xranCompMethod>0</xranCompMethod>
798 <oRu0nPrbElemDl>1</oRu0nPrbElemDl>
799 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex,
800 bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor,
802 <!-- weight base beams -->
803 <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>
804 <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>
805 <oRu0PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu0PrbElemDl2>
806 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>
807 <oRu0PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>
808 <oRu0PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>
809 <oRu0PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>
810 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>
812 <oRu0nPrbElemUl>1</nPrbElemUl>
814 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex,
815 bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor,
817 <!-- weight base beams -->
818 <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>
819 <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>
820 <oRu0PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemUl2>
821 <oRu0PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>
822 <oRu0PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>
823 <oRu0PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>
824 <oRu0PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>
825 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>
830 4.Modify bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs).::
832 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0
833 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1
835 5.Use configuration of test mac per::
837 /bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
839 <!-- mmWave mu 3 100MHz -->
840 TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg
842 6.To execute l1app with O-DU functionality according to O-RAN
843 Fronthaul specification, enter::
845 [root@xran flexran] cd ./bin/nr5g/gnb/l1
846 [root@xran l1]#./l1.sh –xran
848 where output corresponding L1 is::
850 [root@sc12-xran-sub6 l1]# ./l1.sh -xranmmw Radio mode with XRAN - mmWave 100Mhz
852 kernel.sched_rt_runtime_us = -1
853 kernel.shmmax = 2147483648
854 kernel.shmall = 2147483648
855 Note: Forwarding request to 'systemctl disable irqbalance.service'.
856 using configuration file phycfg_xran_mmw.xml
857 >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran_mmw.xml
858 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#
859 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#
860 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#
861 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#
862 FlexRAN SDK bblib_llr_demapping version #DIRTY#
863 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#
864 FlexRAN SDK bblib_reed_muller version #DIRTY#
865 FlexRAN SDK bblib_lte_modulation version #DIRTY#
866 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#
867 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#
868 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#
869 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#
870 FlexRAN SDK bblib_fd_correlation version #DIRTY#
871 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#
872 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#
873 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#
874 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#
875 FlexRAN SDK bblib_prach_5gnr version #DIRTY#
876 FlexRAN SDK bblib_fft_ifft version #DIRTY#
877 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#
878 FlexRAN SDK bblib_common version #DIRTY#
879 FlexRAN SDK bblib_lte_crc version #DIRTY#
880 FlexRAN SDK bblib_lte_dft_idft version #DIRTY#
881 FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY#
882 FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY#
883 FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY#
884 FlexRAN SDK bblib_zf_matrix_gen version #DIRTY#
885 FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY#
887 =========================
891 =========================
893 ---------------------------
895 PhyCfg.xml Version: 20.04
897 ---------------------------
905 --wlsMemorySize=0x3F600000
911 --iqLogDumpToFile=0x0
917 --dpdkMemorySize=8192
921 --dpdkBasebandFecMode=1
923 --dpdkBasebandDevice=0000:1f:00.1
929 --ferryBridgeEthPort=1
931 --ferryBridgeSyncPorts=0
933 --ferryBridgeOptCableLoopback=0
935 --radioCfg0PCIeEthDev=0000:19:00.0
949 --radioCfg0Cell0PhyId=0
951 --radioCfg0Cell1PhyId=1
953 --radioCfg0Cell2PhyId=2
955 --radioCfg0Cell3PhyId=3
957 --radioCfg0Cell4PhyId=4
959 --radioCfg0Cell5PhyId=5
961 --radioCfg0riuMac=11:22:33:44:55:66
963 --radioCfg1PCIeEthDev=0000:03:00.1
977 --radioCfg1Cell0PhyId=2
979 --radioCfg1Cell1PhyId=3
981 --radioCfg1Cell2PhyId=2
983 --radioCfg1Cell3PhyId=3
985 --radioCfg1riuMac=ac:1f:6b:2c:9f:07
987 --radioCfg2PCIeEthDev=0000:05:00.0
1001 --radioCfg2Cell0PhyId=4
1003 --radioCfg2Cell1PhyId=5
1005 --radioCfg2Cell2PhyId=2
1007 --radioCfg2Cell3PhyId=3
1009 --radioCfg2riuMac=ac:1f:6b:2c:9f:07
1011 --radioCfg3PCIeEthDev=0000:05:00.1
1013 --radioCfg3DpdkRx=12
1015 --radioCfg3DpdkTx=13
1023 --radioCfg3NumCell=2
1025 --radioCfg3Cell0PhyId=6
1027 --radioCfg3Cell1PhyId=7
1029 --radioCfg3Cell2PhyId=2
1031 --radioCfg3Cell3PhyId=3
1033 --radioCfg3riuMac=ac:1f:6b:2c:9f:07
1035 --radioCfg4PCIeEthDev=0000:00:08.0
1037 --radioCfg4DpdkRx=14
1039 --radioCfg4DpdkTx=15
1047 --radioCfg4NumCell=2
1049 --radioCfg4Cell0PhyId=8
1051 --radioCfg4Cell1PhyId=9
1053 --radioCfg4Cell2PhyId=2
1055 --radioCfg4Cell3PhyId=3
1057 --radioCfg4riuMac=ac:1f:6b:2c:9f:07
1059 --radioCfg5PCIeEthDev=0000:08:00.0
1061 --radioCfg5DpdkRx=16
1063 --radioCfg5DpdkTx=16
1071 --radioCfg5NumCell=2
1073 --radioCfg5Cell0PhyId=10
1075 --radioCfg5Cell1PhyId=11
1077 --radioCfg5Cell2PhyId=2
1079 --radioCfg5Cell3PhyId=3
1081 --radioCfg5riuMac=ac:1f:6b:2c:9f:07
1083 --radioCfg6PCIeEthDev=0000:00:05.0
1085 --radioCfg6DpdkRx=16
1087 --radioCfg6DpdkTx=16
1095 --radioCfg6NumCell=2
1097 --radioCfg6Cell0PhyId=12
1099 --radioCfg6Cell1PhyId=13
1101 --radioCfg6Cell2PhyId=2
1103 --radioCfg6Cell3PhyId=3
1105 --radioCfg6riuMac=ac:1f:6b:2c:9f:07
1107 --radioCfg7PCIeEthDev=0000:00:06.0
1109 --radioCfg7DpdkRx=16
1111 --radioCfg7DpdkTx=16
1119 --radioCfg7NumCell=2
1121 --radioCfg7Cell0PhyId=14
1123 --radioCfg7Cell1PhyId=15
1125 --radioCfg7Cell2PhyId=2
1127 --radioCfg7Cell3PhyId=3
1129 --radioCfg7riuMac=ac:1f:6b:2c:9f:07
1147 --PdschSymbolSplit=0
1149 --PdschDlWeightSplit=0
1153 --PuschChanEstSplit=0
1159 --PuschUlWeightSplit=0
1161 --FecDecEarlyTermDisable=0
1167 --llrOutDecimalDigit=2
1169 --IrcEnableThreshold=-10
1177 --prachDetectThreshold=10000
1185 --systemThread=0, 0, 0
1187 --timerThread=0, 96, 0
1189 --xRANThread=4, 96, 0
1191 --xRANWorker=0x0, 96, 0
1193 --FpgaDriverCpuInfo=2, 96, 0
1195 --FrontHaulCpuInfo=3, 96, 0
1197 --radioDpdkMaster=2, 99, 0
1199 --BbuPoolSleepEnable=1
1201 --BbuPoolThreadCorePriority=94
1203 --BbuPoolThreadCorePolicy=0
1205 --BbuPoolThreadDefault_0_63=0x68
1207 --BbuPoolThreadDefault_64_127=0x0
1209 --BbuPoolThreadSrs_0_63=0x0
1211 --BbuPoolThreadSrs_64_127=0x0
1213 --BbuPoolThreadDlbeam_0_63=0x0
1215 --BbuPoolThreadDlbeam_64_127=0x0
1217 --BbuPoolThreadUrllc=8
1219 --FrontHaulTimeAdvance=9450
1225 --nFecFpgaVersionMu3=0xFC101800
1227 --nFecFpgaVersionMu0_1=0x0319d420
1229 --nFhFpgaVersionMu3=0x8001000F
1231 --nFhFpgaVersionMu0_1=0x90010008
1233 --dpdkXranDeviceCP=0000:21:02.1
1235 --dpdkXranDeviceUP=0000:21:02.0
1237 --DuMac=00:11:22:33:44:66
1239 --RuMac=00:11:22:33:44:55
1265 --c_plane_vlan_tag=1
1267 --u_plane_vlan_tag=2
1285 --DynamicSectionEna=0
1301 --PrbElemDl0=0,48,0,14,1,1,1,9,1
1303 --PrbElemDl1=48,48,0,14,2,1,1,9,1
1305 --PrbElemDl2=96,48,0,14,3,1,1,9,1
1307 --PrbElemDl3=144,48,0,14,4,1,1,9,1
1309 --PrbElemDl4=144,36,0,14,5,1,1,9,1
1311 --PrbElemDl5=180,36,0,14,6,1,1,9,1
1313 --PrbElemDl6=216,36,0,14,7,1,1,9,1
1315 --PrbElemDl7=252,21,0,14,8,1,1,9,1
1319 --PrbElemUl0=0,48,0,14,1,1,1,9,1
1321 --PrbElemUl1=48,48,0,14,2,1,1,9,1
1323 --PrbElemUl2=72,36,0,14,3,1,1,9,1
1325 --PrbElemUl3=108,36,0,14,4,1,1,9,1
1327 --PrbElemUl4=144,36,0,14,5,1,1,9,1
1329 --PrbElemUl5=180,36,0,14,6,1,1,9,1
1331 --PrbElemUl6=216,36,0,14,7,1,1,9,1
1333 --PrbElemUl7=252,21,0,14,8,1,1,9,1
1337 --StreamIp=127.0.0.1
1341 wls_dev_filename: wls0
1343 phycfg_apply: Initialize Radio Interface with XRAN library
1345 Setting FecEncSplit to 1 to run on HW accelerator
1347 Setting FecDecSplit to 1 to run on HW accelerator
1349 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution
1354 MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(20),
1355 mlogSize(3084) mlog_mask (-1)
1357 mlogSubframes (128), mlogCores(20), mlogSize(3084)
1361 System clock (rdtsc) resolution 1596250020 [Hz]
1365 MLog Storage: 0x7f6e5b0e3100 -> 0x7f6e5b86b52c [ 7898156 bytes ]
1367 localMLogFreqReg: 1596. Storing: 1596
1369 Mlog Open successful
1373 di_xran_cfg_setup successful
1379 hw-accelerated bbdev 0000:1f:00.1
1381 total cores 40 c_mask 0x14 core 4 [id] system_core 2 [id] pkt_proc_core
1382 0x0 [mask] pkt_aux_core 0 [id] timing_core 4 [id]
1384 xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x14 -n2
1385 --iova-mode=pa --socket-mem=8192 --socket-limit=8192 --proc-type=auto
1386 --file-prefix wls0 -w 0000:00:00.0 -w 0000:1f:00.1
1388 EAL: Detected 40 lcore(s)
1390 EAL: Detected 1 NUMA nodes
1392 EAL: Auto-detected process type: PRIMARY
1394 EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket
1396 EAL: Selected IOVA mode 'PA'
1398 EAL: No available hugepages reported in hugepages-2048kB
1400 EAL: Probing VFIO support...
1402 EAL: VFIO support initialized
1404 EAL: PCI device 0000:1f:00.1 on NUMA socket 0
1406 EAL: probe driver: 8086:d90 intel_fpga_5gnr_fec_vf
1408 EAL: using IOMMU type 1 (Type 1)
1410 EAL: PCI device 0000:21:02.0 on NUMA socket 0
1412 EAL: probe driver: 8086:154c net_i40e_vf
1414 initializing port 0 for TX, drv=net_i40e_vf
1416 Port 0 MAC: 00 11 22 33 44 66
1418 Port 0: nb_rxd 4096 nb_txd 4096
1420 Checking link status portid [0] EAL: PCI device 0000:21:02.1 on NUMA
1423 EAL: probe driver: 8086:154c net_i40e_vf
1425 initializing port 1 for TX, drv=net_i40e_vf
1427 Port 1 MAC: 00 11 22 33 44 66
1429 Port 1: nb_rxd 4096 nb_txd 4096
1431 Checking link status portid [1] vf 0 local SRC MAC: 00 11 22 33 44 66
1433 vf 0 remote DST MAC: 00 11 22 33 44 55
1435 vf 1 local SRC MAC: 00 11 22 33 44 66
1437 vf 1 remote DST MAC: 00 11 22 33 44 55
1439 xran_init successful, pHandle = 0x5581f440
1445 FEC is accelerated through BBDEV: 0000:1f:00.1
1447 wls_layer_init[wls0] nWlsMemorySize[1063256064]
1449 wls_lib: Open wls0 (DPDK memzone)
1451 wls_lib: WLS_Open 0x2bf600000
1453 wls_lib: link: 0 <-> 1
1457 wls_lib: WLS shared management memzone: wls0
1459 wls_lib: hugePageSize on the system is 1073741824
1461 wls_lib: WLS_Alloc [1063256064] bytes
1463 ===========================================================================================================
1467 ===========================================================================================================
1471 IMG-date: Apr 27 2020
1475 ===========================================================================================================
1477 DEPENDENCIES VERSIONS
1479 ===========================================================================================================
1481 FlexRAN BBU pooling version #DIRTY#
1483 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#
1485 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#
1487 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#
1489 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#
1491 FlexRAN SDK bblib_llr_demapping version #DIRTY#
1493 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#
1495 FlexRAN SDK bblib_reed_muller version #DIRTY#
1497 FlexRAN SDK bblib_lte_modulation version #DIRTY#
1499 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#
1501 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#
1503 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#
1505 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#
1507 FlexRAN SDK bblib_fd_correlation version #DIRTY#
1509 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#
1511 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#
1513 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#
1515 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#
1517 FlexRAN SDK bblib_prach_5gnr version #DIRTY#
1519 FlexRAN SDK bblib_fft_ifft version #DIRTY#
1521 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#
1523 FlexRAN SDK bblib_lte_crc version #DIRTY#
1525 FlexRAN SDK bblib_common version #DIRTY#
1527 ===========================================================================================================
1529 ===========================================================================================================
1531 Non BBU threads in application
1533 ===========================================================================================================
1535 nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 112583] binding on [CPU 0]
1536 [PRIO: 0] [POLICY: 1]
1538 wls_rx_handler (non-rt): [PID: 112587] binding on [CPU 0]
1540 ===========================================================================================================
1542 PHY>welcome to application console
1544 PHY>Received MSG_TYPE_PHY_UL_IQ_SAMPLES
1546 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0
1548 phydi_read_write_iq_samples: direction[1] nNumerologyMult[8]
1549 fftSize[1024, 11088, SRS: 792] numSubframe[80] numAntenna[2] numPorts[2]
1550 nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1]
1551 PhaseCompensationEnable[0]
1552 filename_in_ul_iq[/home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/mu3_100mhz/2/../../../ul/mu3_100mhz/1/uliq00_tst1.bin]
1553 filename_in_prach_iq[]
1555 Received MSG_TYPE_PHY_CONFIG_REQ: 0
1557 Processing MSG_TYPE_PHY_CONFIG_REQ: 0
1559 phy_bbupool_set_config: Using cores: 0x0000000000000068 for BBU Pool
1560 nBbuPoolSleepEnable: 1
1562 BBU Pooling: queueId = 0, the according nCoreNum = 3, the according
1565 BBU Pooling: gCoreIdxMap[0] = 3 is available!
1567 BBU Pooling: gCoreIdxMap[1] = 5 is available!
1569 BBU Pooling: gCoreIdxMap[2] = 6 is available!
1571 BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered
1573 BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered
1575 BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered
1577 BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered
1579 BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered
1581 BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered
1583 BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered
1585 BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered
1587 BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered
1589 BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered
1591 BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered
1593 BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered
1595 BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered
1597 BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered
1599 BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered
1601 BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered
1603 BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered
1605 BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered
1607 BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered
1609 BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered
1611 BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered
1613 BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB
1614 DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS
1616 BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A
1618 BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER:
1619 DL_L1_PDSCH_SYMBOL_TX
1621 BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST
1623 BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX
1625 BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST
1627 BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST
1629 BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0
1632 BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7
1634 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0
1637 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7
1639 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR
1641 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR
1643 BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE
1645 BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A
1647 BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST
1649 BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST
1651 BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST
1653 BBU Pooling: next taskList of UL_L1_SRS: UL_L1_POST
1655 BBU Pooling: next taskList of DL_L1_POST: N/A
1657 BBU Pooling: next taskList of UL_L1_POST: N/A
1659 enter RtThread Launch
1661 3 thread associated with queue 0:coreIdx 0 1 2
1663 Leave RtThread Launch
1665 launching Thread 0 Queue 0 uCoreIdx 0 CoreId 3 Priority 94 Policy 1
1666 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
1668 launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1
1669 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
1671 launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1
1672 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
1674 bbupool_core_main: the server's coreNum = 40, the nCore = 3,nRtCoreMask
1675 = 0x68, the nFeIfCore = 0,nFeIfCoreMask = 0x0
1677 bbupool_core_main pthread_setaffinity_np succeed: coreId = 0, result = 0
1679 nr5g_gnb_mac2phy_api_proc_print_phy_init [0]:
1687 nDLAbsFrePointA: 27968160
1689 nULAbsFrePointA: 27968160
1733 nCarrierAggregationLevel: 0
1743 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10
1746 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
1748 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
1750 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
1752 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
1754 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
1758 nPrachSubcSpacing: 3
1760 nPrachZeroCorrConf: 2
1762 nPrachRestrictSet: 0
1782 read_table: File table/common/pss_table.bin of size 381 read_size: 381
1784 read_table: File table/common/sss_table.bin of size 128016 read_size:
1787 read_table: File table/common/srs_zc_36_plus.bin of size 905916
1790 read_table: File table/common/pucch_zc_36_plus.bin of size 383040
1793 read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216
1796 read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216
1799 BBU Pooling Info: maximum period length was configured, preMaxSF = 8000,
1802 set_slot_type SlotPattern:
1808 PHYDI-INIT[from 0] PhyInstance: 0
1810 ---------------------------------------------------------
1814 ---------------------------------------------------------
1818 gCarrierAggLevelInit: 1
1822 ---------------------------------------------------------
1824 Received MSG_TYPE_PHY_START_REQ: 0
1826 Processing MSG_TYPE_PHY_START_REQ: 0
1834 xran_timing_source_thread [CPU 4] [PID: 112582]
1836 O-DU: thread_run start time: 04/27/20 20:20:33.000000010 UTC [125]
1838 Start C-plane DL 25 us after TTI [trigger on sym 3]
1840 Start C-plane UL 55 us after TTI [trigger on sym 7]
1842 Start U-plane DL 50 us before OTA [offset in sym -5]
1844 Start U-plane UL 45 us OTA [offset in sym 6]
1846 C-plane to U-plane delay 25 us after TTI
1848 Start Sym timer 8928 ns
1852 PHYDI-START[from 0] PhyInstance: 0, Mode: 4, Count: 100040207, Period:
1853 0, NumSlotPerSfn: 80
1855 gnb_start_xran: gxRANStarted[0] CC 1 Ant 4 AntElm 0
1857 XRAN front haul xran_mm_init
1859 xran_sector_get_instances [0]: CC 0 handle 0x7f6e397307c0
1861 Handle: 0x1994ce00 Instance: 0x7f6e397307c0
1863 gnb_start_xran [0]: CC 0 handle 0x7f6e397307c0
1865 Sucess xran_mm_init Instance 0x7f6e397307c0
1869 ru_0_cc_0_idx_0: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 0]
1870 nNumberOfBuffers 2240 nBufferSize 5856
1872 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool
1875 ru_0_cc_0_idx_1: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 1]
1876 nNumberOfBuffers 35840 nBufferSize 24
1878 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool
1881 ru_0_cc_0_idx_2: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 2]
1882 nNumberOfBuffers 2240 nBufferSize 48416
1884 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool
1887 ru_0_cc_0_idx_3: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 3]
1888 nNumberOfBuffers 2240 nBufferSize 5856
1890 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool
1893 ru_0_cc_0_idx_4: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 4]
1894 nNumberOfBuffers 35840 nBufferSize 24
1896 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool
1899 ru_0_cc_0_idx_5: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 5]
1900 nNumberOfBuffers 2240 nBufferSize 48416
1902 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool
1905 ru_0_cc_0_idx_6: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 6]
1906 nNumberOfBuffers 2240 nBufferSize 8192
1908 CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool
1913 init xran successfully
1915 ----------------------------------------------------------------------------
1917 mem_mgr_display_size:
1919 Num Memory Alloc: 5,186
1921 Total Memory Size: 4,389,524,920
1923 ----------------------------------------------------------------------------
1925 BBU Pooling: enter multicell Activate!
1927 BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at
1928 547270377116554 at sf=0 with queue 0 successfully
1930 BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0,
1931 activesfn = 4, CellNumInActSfn = 1
1933 BBU Pooling: multiCell Activate sucessfully!
1935 BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 3 at
1936 547270377104408 at sf=0 with queue 0 successfully
1938 BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at
1939 547270377117634 at sf=0 with queue 0 successfully
1941 phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5]
1944 ==== l1app Time: 5001 ms NumCarrier: 1 NumBbuCores: 3 rxPcktCnt: 93621
1945 rachPcktCnt 46811 Total Proc Time: [ 62.00.. 98.39..209.00] usces====
1947 ==== [o-du][rx 619683 pps 123936 kbps 2621619][tx 1996407 pps 399281
1948 kbps 9181862] [on_time 619683 early 0 late 0 corrupt 0 pkt_dupl 16 Total
1949 619683] IO Util: 79.61 %
1951 7.To execute testmac with O-DU functionality according to O-RAN
1952 Fronthaul specification, enter::
1954 [root@xran flexran] cd ./bin/nr5g/gnb/testmac
1956 8.To execute test case type::
1958 ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
1960 where output corresponding to Test MAC::
1962 [root@sc12-xran-sub6 testmac]# ./l2.sh
1963 --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
1964 kernel.sched_rt_runtime_us = -1
1966 kernel.shmmax = 2147483648
1968 kernel.shmall = 2147483648
1970 Note: Forwarding request to 'systemctl disable irqbalance.service'.
1974 =========================
1976 5GNR Testmac Application
1978 =========================
1980 testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command
1981 line. Using default File: testmac_cfg.xml
1983 ---------------------------
1985 TestMacCfg.xml Version: 20.04
1987 ---------------------------
1993 --wlsMemorySize=0x3F600000
2009 --wlsRxThread=1, 90, 0
2011 --systemThread=0, 0, 0
2013 --runThread=0, 89, 0
2015 --urllcThread=19, 90, 0
2017 wls_dev_filename: wls0
2019 sys_reg_signal_handler:[err] signal handler in NULL
2021 sys_reg_signal_handler:[err] signal handler in NULL
2023 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution
2028 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3),
2029 mlogSize(2048) mlog_mask (-1)
2031 mlogSubframes (128), mlogCores(3), mlogSize(2048)
2035 System clock (rdtsc) resolution 1596250375 [Hz]
2039 MLog Storage: 0x7f84cae86100 -> 0x7f84caf46920 [ 788512 bytes ]
2041 localMLogFreqReg: 1596. Storing: 1596
2043 Mlog Open successful
2045 Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0
2048 EAL: Detected 40 lcore(s)
2050 EAL: Detected 1 NUMA nodes
2052 EAL: Auto-detected process type: SECONDARY
2054 EAL: Multi-process socket
2055 /var/run/dpdk/wls0/mp_socket_112640_1f1baf0a9b316
2057 EAL: Selected IOVA mode 'PA'
2059 EAL: Probing VFIO support...
2061 EAL: VFIO support initialized
2063 EAL: PCI device 0000:19:00.0 on NUMA socket 0
2065 EAL: probe driver: 8086:d58 net_i40e
2067 EAL: PCI device 0000:19:00.1 on NUMA socket 0
2069 EAL: probe driver: 8086:d58 net_i40e
2071 EAL: PCI device 0000:1d:00.0 on NUMA socket 0
2073 EAL: probe driver: 8086:d58 net_i40e
2075 EAL: PCI device 0000:1d:00.1 on NUMA socket 0
2077 EAL: probe driver: 8086:d58 net_i40e
2079 EAL: PCI device 0000:21:00.0 on NUMA socket 0
2081 EAL: probe driver: 8086:158b net_i40e
2083 EAL: PCI device 0000:21:00.1 on NUMA socket 0
2085 EAL: probe driver: 8086:158b net_i40e
2087 EAL: PCI device 0000:21:02.0 on NUMA socket 0
2089 EAL: probe driver: 8086:154c net_i40e_vf
2091 EAL: using IOMMU type 1 (Type 1)
2093 EAL: PCI device 0000:21:02.1 on NUMA socket 0
2095 EAL: probe driver: 8086:154c net_i40e_vf
2097 EAL: PCI device 0000:21:0a.0 on NUMA socket 0
2099 EAL: probe driver: 8086:154c net_i40e_vf
2101 EAL: 0000:21:0a.0 cannot find TAILQ entry for PCI device!
2103 EAL: Requested device 0000:21:0a.0 cannot be used
2105 EAL: PCI device 0000:21:0a.1 on NUMA socket 0
2107 EAL: probe driver: 8086:154c net_i40e_vf
2109 EAL: 0000:21:0a.1 cannot find TAILQ entry for PCI device!
2111 EAL: Requested device 0000:21:0a.1 cannot be used
2113 EAL: PCI device 0000:67:00.0 on NUMA socket 0
2115 EAL: probe driver: 8086:37d2 net_i40e
2117 EAL: PCI device 0000:67:00.1 on NUMA socket 0
2119 EAL: probe driver: 8086:37d2 net_i40e
2121 wls_lib: Open wls0 (DPDK memzone)
2123 wls_lib: WLS_Open 0x2bf600000
2125 wls_lib: link: 1 <-> 0
2129 wls_lib: WLS shared management memzone: wls0
2131 wls_lib: hugePageSize on the system is 1073741824
2133 wls_lib: WLS_Alloc [1063256064] bytes
2135 wls_lib: Connecting to remote peer ...
2137 wls_lib: Connected to remote peer
2139 wls_mac_create_mem_array: pMemArray[0xf3500f0]
2140 pMemArrayMemory[0x280000000] totalSize[1063256064] nBlockSize[262144]
2143 WLS_EnqueueBlock [1]
2147 ===========================================================================================================
2151 ===========================================================================================================
2153 $Version: #DIRTY# $ (x86)
2155 IMG-date: Apr 27 2020
2159 ===========================================================================================================
2161 ===========================================================================================================
2163 Testmac threads in application
2165 ===========================================================================================================
2167 testmac_run_thread: [PID: 112644] binding on [CPU 0] [PRIO: 89] [POLICY:
2170 wls_mac_rx_task: [PID: 112643] binding on [CPU 1] [PRIO: 90] [POLICY: 1]
2172 ===========================================================================================================
2174 testmac_set_phy_start: mode[1], period[40], count[0]
2176 testmac_run_load_files:
2178 Loading DL Config Files:
2180 testmac_run_parse_file Parsing config file:
2181 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg
2183 testmac_run_parse_file Parsing config file:
2184 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg
2186 testmac_run_parse_file Parsing config file:
2187 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg
2189 testmac_run_parse_file Parsing config file:
2190 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg
2192 testmac_run_parse_file Parsing config file:
2193 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg
2195 Loading UL Config Files:
2197 testmac_run_parse_file Parsing config file:
2198 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg
2200 testmac_run_parse_file Parsing config file:
2201 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg
2203 testmac_run_parse_file Parsing config file:
2204 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg
2206 testmac_run_parse_file Parsing config file:
2207 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg
2209 testmac_run_parse_file Parsing config file:
2210 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg
2212 Loading FD Config Files:
2214 testmac_run_parse_file Parsing config file:
2215 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg
2217 testmac_run_parse_file Parsing config file:
2218 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg
2220 testmac_run_parse_file Parsing config file:
2221 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg
2223 testmac_run_parse_file Parsing config file:
2224 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg
2226 testmac_run_parse_file Parsing config file:
2227 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg
2229 testmac_run_parse_file Parsing config file:
2230 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg
2234 Numerology[0] Bandwidth[5]
2236 1001 1002 1003 1004 1005 1006 1007 1008
2238 Numerology[0] Bandwidth[10]
2240 1001 1002 1003 1004 1005 1006 1007 1008
2242 Numerology[0] Bandwidth[20]
2244 1001 1002 1003 1004 1005 1006 1007 1008
2246 Numerology[1] Bandwidth[100]
2248 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211
2250 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
2252 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241
2254 1242 1243 1244 1245 1250 1251 1252 1300 1301 1302
2256 1303 1304 1305 1402 1404 1408 1416 1500 1501 1502
2258 1503 1504 1505 1506 2213 2214 2215 2217 2218 2219
2260 2223 2224 2225 2227 2228 2229 2500 2501 2502 2503
2262 2504 3213 3214 3215 3217 3218 3219 3223 3224 3225
2266 Numerology[3] Bandwidth[100]
2268 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011
2270 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031
2272 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003
2278 Numerology[0] Bandwidth[5]
2282 Numerology[0] Bandwidth[10]
2286 Numerology[0] Bandwidth[20]
2288 1001 1002 1003 1004 1005 1006 1007 1008
2290 Numerology[1] Bandwidth[100]
2292 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038
2294 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074
2296 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092
2298 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105
2300 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117
2302 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132
2304 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
2306 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160
2308 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
2310 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206
2312 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216
2314 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233
2316 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421
2318 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
2320 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504
2322 1505 1506 1507 1508 1511 1512 1513 1514 1515 1516
2324 1540 1541 1542 1563 1564 1565 1566 1567 1568 1569
2326 1570 1571 1572 1573 1574 1600 1601 1602 1603 1604
2328 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614
2330 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624
2332 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634
2334 1635 1636 1637 1638 1639 1640 1641 1642 1700 1701
2338 Numerology[3] Bandwidth[100]
2340 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012
2342 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026
2344 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
2346 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051
2348 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065
2350 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084
2352 1085 1086 2001 2002 2003 3001 3002 3003
2356 Numerology[0] Bandwidth[5]
2358 1001 6001 8001 10001 12001
2360 Numerology[0] Bandwidth[10]
2362 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002
2364 6002 8002 10002 12002 1003
2366 Numerology[0] Bandwidth[20]
2368 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021
2370 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201
2372 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221
2374 1222 1223 1224 1225 1226 1227 1228
2376 Numerology[1] Bandwidth[40]
2380 Numerology[1] Bandwidth[100]
2382 1001 1200 1201 1202 1203 1204 1205 1206 1207 1208
2384 1209 1210 1300 1301 1302 1303 1304 1305 1306 1307
2386 1308 1350 1351 1352 1353 1354 1355 1356 1357 1358
2388 1370 1371 1372 1373 1401 1402 1403 1404 1405 1406
2390 1411 1412 1490 1494 1500 1501 1502 1503 1504 1510
2392 1511 1512 1513 1514 1515 1520 1521 1522 1523 1524
2394 1525 1526 1527 1528 1529 1530 1531 1532 1540 1541
2396 1700 1701 1702 2520 2521 2522 2523 2524 2525 2526
2398 2527 2528 2529 2530 2531 2532 3524 3525 3526 3527
2400 3528 3529 3530 3531 3532 4524 4525 4526 4527 4528
2404 Numerology[3] Bandwidth[100]
2406 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011
2408 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080
2412 testmac_run_parse_file Parsing config file:
2413 ./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
2415 testmac_set_phy_start: mode[4], period[0], count[100040200]
2417 Adding Test[1002]. NumCarr[1], Current Directory:
2418 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/
2420 Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg
2422 ----------------------------------------------------------------------------------------
2424 Running Test[1002]. NumCarr[1], Current Directory:
2425 /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/
2427 Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg
2429 TESTMAC>welcome to application console
2433 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3),
2434 mlogSize(2048) mlog_mask (-1)
2436 mlogSubframes (128), mlogCores(3), mlogSize(2048)
2440 System clock (rdtsc) resolution 1596249901 [Hz]
2444 MLog Storage: 0x7f84bc000900 -> 0x7f84bc0c1120 [ 788512 bytes ]
2446 localMLogFreqReg: 1596. Storing: 1596
2448 Mlog Open successful
2450 testmac_mac2phy_set_num_cells: Setting Max Cells: 1
2452 testmac_config_parse: test_num[1002] test_type[2] numcarrier[1]
2454 host_config_set_int Error(nPrachSsbRach, 3): Out of range: [min(0),
2457 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0)
2459 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0)
2461 Queueing MSG_TYPE_PHY_CONFIG_REQ(0) and sending list
2463 Received MSG_TYPE_PHY_CONFIG_RESP(0)
2465 Queueing MSG_TYPE_PHY_START_REQ(0) and sending list
2467 Received MSG_TYPE_PHY_START_RESP(0)
2469 ==== testmac Time: 5000 ms NumCarrier: 1 Total Proc Time: [ 0.00..
2470 4.11.. 14.00] usces====
2472 Core Utilization [Core: 1] [Util %: 2.97%]
2474 ==== testmac Time: 10000 ms NumCarrier: 1 Total Proc Time: [ 2.00..
2475 4.10.. 13.00] usces====
2477 Core Utilization [Core: 1] [Util %: 4.81%]
2479 ==== testmac Time: 15000 ms NumCarrier: 1 Total Proc Time: [ 2.00..
2480 4.10.. 6.00] usces====
2482 Configure FlexRAN 5G NR L1 Application for Multiple O-RUs with Multiple Numerologies
2483 ====================================================================================
2485 The 5G NR layer 1 application can be used for executing the scenario for
2486 multiple cells with multiple numerologies. The current release supports
2487 the constant configuration of different numerologies on different O-RU
2488 ports. It is required that the first O-RU (O-RU0) to be configured with
2489 highest numerology. The configuration procedure is similar as described
2490 in above section. Please refer to the configuration file located in
2491 bin\nr5g\gnb\l1\orancfg\sub3_mu0_20mhz_sub6_mu1_100mhz_4x4\gnb\xrancfg_sub6_oru.xml
2493 Install and Configure FlexRAN 5G NR L1 Application for Massive - MIMO
2494 =====================================================================
2496 The 5G NR layer 1 application can be used for executing the scenario for
2497 Massive-MIMO with either the RU sample application or just the O-DU
2498 side. 3 cells scenario with 64T64R Massive MIMO is targeted for Icelake
2499 system with Columbiavile NIC. The current release supports the constant
2500 configuration of the slot pattern and RB allocation on the PHY side.
2501 Please follow the general build process in the FlexRAN 5G NR Reference
2502 Solution L1 User Guide (refer to Table 2.)
2504 1.xRAN library is enabled by default l1 application.
2506 2.Build the 5G NR L1 application using the command::
2508 ./flexran_build.sh -r 5gnr_l1app_sub6 -i snc -m sdk -m fb -m mlog –m wls
2509 -m 5gnr_l1app_mmw -m xran -m 5gnr_testmac
2511 3.Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml.::
2514 <version>20.08</version>
2515 <!-- numbers of O-RU connected to O-DU. All O-RUs are the same
2516 capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
2518 <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
2519 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>
2520 <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link
2522 <oRuLinesNumber>2</oRuLinesNumber>
2523 <!-- (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane
2524 and U-Plane use dedicated VFs -->
2525 <oRuCUon1Vf>1</oRuCUon1Vf>
2528 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>
2529 <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>
2530 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>
2531 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>
2534 <PciBusAddoRu1Vf0>0000:51:01.2</PciBusAddoRu1Vf0>
2535 <PciBusAddoRu1Vf1>0000:51:01.3</PciBusAddoRu1Vf1>
2536 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>
2537 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>
2540 <PciBusAddoRu2Vf0>0000:51:01.4</PciBusAddoRu2Vf0>
2541 <PciBusAddoRu2Vf1>0000:51:01.5</PciBusAddoRu2Vf1>
2542 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>
2543 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>
2546 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>
2547 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>
2548 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>
2549 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>
2551 <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->
2552 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>
2553 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>
2554 <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->
2555 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>
2556 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>
2558 <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->
2559 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>
2560 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>
2561 <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->
2562 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>
2563 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>
2565 <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->
2566 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>
2567 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>
2568 <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->
2569 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>
2570 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>
2572 <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->
2573 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>
2574 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>
2575 <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->
2576 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>
2577 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>
2579 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
2580 <oRu0NumCc>1</oRu0NumCc>
2581 <!-- First Phy instance ID mapped to this O-RU CC0 -->
2582 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>
2583 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
2584 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>
2585 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
2586 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>
2587 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
2588 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>
2590 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
2591 <oRu1NumCc>1</oRu1NumCc>
2592 <!-- First Phy instance ID mapped to this O-RU CC0 -->
2593 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>
2594 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
2595 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>
2596 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
2597 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>
2598 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
2599 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>
2601 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
2602 <oRu2NumCc>1</oRu2NumCc>
2603 <!-- First Phy instance ID mapped to this O-RU CC0 -->
2604 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>
2605 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
2606 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>
2607 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
2608 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>
2609 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
2610 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>
2612 <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
2613 <xRANThread>22, 96, 0</xRANThread>
2615 <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
2616 <xRANWorker>0x3800000, 96, 0</xRANWorker>
2617 <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
2618 <Category>1</Category>
2620 <!-- XRAN: enable sleep on PMD cores -->
2621 <xranPmdSleep>0</xranPmdSleep>
2623 <!-- RU Settings -->
2624 <Tadv_cp_dl>25</Tadv_cp_dl>
2625 <!-- Reception Window C-plane DL-->
2626 <T2a_min_cp_dl>285</T2a_min_cp_dl>
2627 <T2a_max_cp_dl>429</T2a_max_cp_dl>
2628 <!-- Reception Window C-plane UL-->
2629 <T2a_min_cp_ul>285</T2a_min_cp_ul>
2630 <T2a_max_cp_ul>429</T2a_max_cp_ul>
2631 <!-- Reception Window U-plane -->
2632 <T2a_min_up>71</T2a_min_up>
2633 <T2a_max_up>428</T2a_max_up>
2634 <!-- Transmission Window U-plane -->
2635 <Ta3_min>20</Ta3_min>
2636 <Ta3_max>32</Ta3_max>
2638 <!-- O-DU Settings -->
2641 <!-- VLAN Tag used for C-Plane -->
2642 <c_plane_vlan_tag>1</c_plane_vlan_tag>
2643 <u_plane_vlan_tag>2</u_plane_vlan_tag>
2645 <!-- Transmission Window Fast C-plane DL -->
2646 <T1a_min_cp_dl>258</T1a_min_cp_dl>
2647 <T1a_max_cp_dl>429</T1a_max_cp_dl>
2648 <!-- Transmission Window Fast C-plane UL -->
2649 <T1a_min_cp_ul>285</T1a_min_cp_ul>
2650 <T1a_max_cp_ul>300</T1a_max_cp_ul>
2651 <!-- Transmission Window U-plane -->
2652 <T1a_min_up>96</T1a_min_up>
2653 <T1a_max_up>196</T1a_max_up>
2654 <!-- Reception Window U-Plane-->
2655 <Ta4_min>0</Ta4_min>
2656 <Ta4_max>75</Ta4_max>
2658 <!-- Enable Control Plane -->
2659 <EnableCp>1</EnableCp>
2661 <DynamicSectionEna>0</DynamicSectionEna>
2662 <!-- Enable Dynamic section allocation for UL -->
2663 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>
2664 <xRANSFNWrap>1</xRANSFNWrap>
2666 <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is
2667 transmitted (used for testing. If 0, then value is used from
2670 <xRANNumDLPRBs>0</xRANNumDLPRBs>
2672 <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is
2673 received (used for testing. If 0, then value is used from
2676 <xRANNumULPRBs>0</xRANNumULPRBs>
2678 <!-- refer to alpha as defined in section 9.7.2 of O-RAN spec. this
2679 value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->
2681 <Gps_Alpha>0</Gps_Alpha>
2683 <!-- beta value as defined in section 9.7.2 of O-RAN spec. range -32767
2686 <Gps_Beta>0</Gps_Beta>
2688 <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
2689 <xranCompMethod>1</xranCompMethod>
2691 <oRu0nPrbElemDl>6</oRu0nPrbElemDl>
2692 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex,
2693 bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor,
2695 <!-- weight base beams -->
2696 <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>
2697 <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>
2698 <oRu0PrbElemDl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl2>
2699 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>
2700 <oRu0PrbElemDl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>
2701 <oRu0PrbElemDl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>
2702 <oRu0PrbElemDl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>
2703 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>
2705 <!-- extType = 11 -->
2706 <oRu0ExtBfwDl0>2,24,0,0,9,1</oRu0ExtBfwDl0>
2707 <oRu0ExtBfwDl1>2,24,0,0,9,1</oRu0ExtBfwDl1>
2708 <oRu0ExtBfwDl2>2,24,0,0,9,1</oRu0ExtBfwDl2>
2709 <oRu0ExtBfwDl3>2,24,0,0,9,1</oRu0ExtBfwDl3>
2710 <oRu0ExtBfwDl4>2,24,0,0,9,1</oRu0ExtBfwDl4>
2711 <oRu0ExtBfwDl5>2,17,0,0,9,1</oRu0ExtBfwDl5>
2713 <oRu0nPrbElemUl>6</oRu0nPrbElemUl>
2714 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2715 <!-- weight base beams -->
2716 <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>
2717 <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>
2718 <oRu0PrbElemUl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl2>
2719 <oRu0PrbElemUl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>
2720 <oRu0PrbElemUl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>
2721 <oRu0PrbElemUl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>
2722 <oRu0PrbElemUl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>
2723 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>
2725 <!-- extType = 11 -->
2726 <oRu0ExtBfwUl0>2,24,0,0,9,1</oRu0ExtBfwUl0>
2727 <oRu0ExtBfwUl1>2,24,0,0,9,1</oRu0ExtBfwUl1>
2728 <oRu0ExtBfwUl2>2,24,0,0,9,1</oRu0ExtBfwUl2>
2729 <oRu0ExtBfwUl3>2,24,0,0,9,1</oRu0ExtBfwUl3>
2730 <oRu0ExtBfwUl4>2,24,0,0,9,1</oRu0ExtBfwUl4>
2731 <oRu0ExtBfwUl5>2,17,0,0,9,1</oRu0ExtBfwUl5>
2733 <oRu0nPrbElemSrs>1</oRu0nPrbElemSrs>
2734 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2735 <!-- weight base beams -->
2736 <oRu0PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs0>
2738 <oRu1nPrbElemDl>2</oRu1nPrbElemDl>
2739 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2740 <!-- weight base beams -->
2741 <oRu1PrbElemDl0>0,48,0,14,0,1,1,9,1,0,0</oRu1PrbElemDl0>
2742 <oRu1PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemDl1>
2743 <oRu1PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu1PrbElemDl2>
2744 <oRu1PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu1PrbElemDl3>
2745 <oRu1PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemDl4>
2746 <oRu1PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemDl5>
2747 <oRu1PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemDl6>
2748 <oRu1PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemDl7>
2750 <!-- extType = 11 -->
2751 <oRu1ExtBfwDl0>2,24,0,0,9,1</oRu1ExtBfwDl0>
2752 <oRu1ExtBfwDl1>2,24,0,0,9,1</oRu1ExtBfwDl1>
2754 <oRu1nPrbElemUl>2</oRu1nPrbElemUl>
2755 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2756 <!-- weight base beams -->
2757 <oRu1PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu1PrbElemUl0>
2758 <oRu1PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemUl1>
2759 <oRu1PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu1PrbElemUl2>
2760 <oRu1PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu1PrbElemUl3>
2761 <oRu1PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemUl4>
2762 <oRu1PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemUl5>
2763 <oRu1PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemUl6>
2764 <oRu1PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemUl7>
2766 <!-- extType = 11 -->
2767 <oRu1ExtBfwUl0>2,24,0,0,9,1</oRu1ExtBfwUl0>
2768 <oRu1ExtBfwUl1>2,24,0,0,9,1</oRu1ExtBfwUl1>
2770 <oRu1nPrbElemSrs>1</oRu1nPrbElemSrs>
2771 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2772 <!-- weight base beams -->
2773 <oRu1PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs0>
2775 <oRu2nPrbElemDl>2</oRu2nPrbElemDl>
2776 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2777 <!-- weight base beams -->
2778 <oRu2PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemDl0>
2779 <oRu2PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemDl1>
2780 <oRu2PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu2PrbElemDl2>
2781 <oRu2PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu2PrbElemDl3>
2782 <oRu2PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemDl4>
2783 <oRu2PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemDl5>
2784 <oRu2PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemDl6>
2785 <oRu2PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemDl7>
2787 <!-- extType = 11 -->
2788 <oRu2ExtBfwDl0>2,24,0,0,9,1</oRu2ExtBfwDl0>
2789 <oRu2ExtBfwDl1>2,24,0,0,9,1</oRu2ExtBfwDl1>
2791 <oRu2nPrbElemUl>2</oRu2nPrbElemUl>
2792 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2793 <!-- weight base beams -->
2794 <oRu2PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemUl0>
2795 <oRu2PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemUl1>
2796 <oRu2PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu2PrbElemUl2>
2797 <oRu2PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu2PrbElemUl3>
2798 <oRu2PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemUl4>
2799 <oRu2PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemUl5>
2800 <oRu2PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemUl6>
2801 <oRu2PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemUl7>
2803 <!-- extType = 11 -->
2804 <oRu2ExtBfwUl0>2,24,0,0,9,1</oRu2ExtBfwUl0>
2805 <oRu2ExtBfwUl1>2,24,0,0,9,1</oRu2ExtBfwUl1>
2807 <oRu2nPrbElemSrs>1</oRu2nPrbElemSrs>
2808 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
2809 <!-- weight base beams -->
2810 <oRu2PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs0>
2814 4.Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs).::
2816 ethDevice0=0000:51:01.0
2817 ethDevice1=0000:51:01.1
2818 ethDevice2=0000:51:01.2
2819 ethDevice3=0000:51:01.3
2820 ethDevice4=0000:51:01.4
2821 ethDevice5=0000:51:01.5
2828 fecDevice0=0000:92:00.0
2830 5.Use configuration of test mac per::
2832 /bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
2834 TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg,
2835 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg,
2836 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
2838 6.To execute l1app with O-DU functionality according to O-RAN
2839 Fronthaul specification, enter::
2841 [root@xran flexran] cd ./bin/nr5g/gnb/l1
2843 Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB)
2847 kernel.sched_rt_runtime_us = -1
2849 kernel.shmmax = 2147483648
2851 kernel.shmall = 2147483648
2853 Note: Forwarding request to 'systemctl disable irqbalance.service'.
2855 using configuration file phycfg_xran.xml
2857 using configuration file xrancfg_sub6_mmimo.xml
2859 >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran.xml
2860 --xranfile=xrancfg_sub6_mmimo.xml
2862 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#
2864 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#
2866 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#
2868 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#
2870 FlexRAN SDK bblib_llr_demapping version #DIRTY#
2872 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#
2874 FlexRAN SDK bblib_reed_muller version #DIRTY#
2876 FlexRAN SDK bblib_lte_modulation version #DIRTY#
2878 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#
2880 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#
2882 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#
2884 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#
2886 FlexRAN SDK bblib_fd_correlation version #DIRTY#
2888 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#
2890 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#
2892 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#
2894 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#
2896 FlexRAN SDK bblib_prach_5gnr version #DIRTY#
2898 FlexRAN SDK bblib_fft_ifft version #DIRTY#
2900 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#
2902 FlexRAN SDK bblib_lte_ldpc_decoder version #DIRTY#
2904 FlexRAN SDK bblib_lte_ldpc_encoder version #DIRTY#
2906 FlexRAN SDK bblib_lte_LDPC_ratematch version #DIRTY#
2908 FlexRAN SDK bblib_lte_rate_dematching_5gnr version #DIRTY#
2910 FlexRAN SDK bblib_common version #DIRTY#
2912 FlexRAN SDK bblib_lte_crc version #DIRTY#
2914 FlexRAN SDK bblib_lte_dft_idft version #DIRTY#
2916 FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY#
2918 FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY#
2920 FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY#
2922 FlexRAN SDK bblib_zf_matrix_gen version #DIRTY#
2924 FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY#
2926 =========================
2928 5GNR PHY Application
2930 =========================
2932 --------------------------------------------------------
2934 File[phycfg_xran.xml] Version: 20.08
2936 --------------------------------------------------------
2940 --successiveNoApi=15
2944 --wlsMemorySize=0x3F600000
2956 --dpdkMemorySize=18432
2960 --dpdkBasebandFecMode=1
2962 --dpdkBasebandDevice=0000:92:00.0
2968 --ferryBridgeEthPort=1
2970 --ferryBridgeSyncPorts=0
2972 --ferryBridgeOptCableLoopback=0
2974 --radioCfg0PCIeEthDev=0000:19:00.0
2986 --radioCfg0NumCell=1
2988 --radioCfg0Cell0PhyId=0
2990 --radioCfg0Cell1PhyId=1
2992 --radioCfg0Cell2PhyId=2
2994 --radioCfg0Cell3PhyId=3
2996 --radioCfg0Cell4PhyId=4
2998 --radioCfg0Cell5PhyId=5
3000 --radioCfg0riuMac=11:22:33:44:55:66
3002 --radioCfg1PCIeEthDev=0000:03:00.1
3014 --radioCfg1NumCell=1
3016 --radioCfg1Cell0PhyId=2
3018 --radioCfg1Cell1PhyId=3
3020 --radioCfg1Cell2PhyId=2
3022 --radioCfg1Cell3PhyId=3
3024 --radioCfg1riuMac=ac:1f:6b:2c:9f:07
3026 --radioCfg2PCIeEthDev=0000:05:00.0
3028 --radioCfg2DpdkRx=10
3030 --radioCfg2DpdkTx=11
3038 --radioCfg2NumCell=2
3040 --radioCfg2Cell0PhyId=4
3042 --radioCfg2Cell1PhyId=5
3044 --radioCfg2Cell2PhyId=2
3046 --radioCfg2Cell3PhyId=3
3048 --radioCfg2riuMac=ac:1f:6b:2c:9f:07
3050 --radioCfg3PCIeEthDev=0000:05:00.1
3052 --radioCfg3DpdkRx=12
3054 --radioCfg3DpdkTx=13
3062 --radioCfg3NumCell=2
3064 --radioCfg3Cell0PhyId=6
3066 --radioCfg3Cell1PhyId=7
3068 --radioCfg3Cell2PhyId=2
3070 --radioCfg3Cell3PhyId=3
3072 --radioCfg3riuMac=ac:1f:6b:2c:9f:07
3074 --radioCfg4PCIeEthDev=0000:00:08.0
3076 --radioCfg4DpdkRx=14
3078 --radioCfg4DpdkTx=15
3086 --radioCfg4NumCell=2
3088 --radioCfg4Cell0PhyId=8
3090 --radioCfg4Cell1PhyId=9
3092 --radioCfg4Cell2PhyId=2
3094 --radioCfg4Cell3PhyId=3
3096 --radioCfg4riuMac=ac:1f:6b:2c:9f:07
3098 --radioCfg5PCIeEthDev=0000:08:00.0
3100 --radioCfg5DpdkRx=16
3102 --radioCfg5DpdkTx=16
3110 --radioCfg5NumCell=2
3112 --radioCfg5Cell0PhyId=10
3114 --radioCfg5Cell1PhyId=11
3116 --radioCfg5Cell2PhyId=2
3118 --radioCfg5Cell3PhyId=3
3120 --radioCfg5riuMac=ac:1f:6b:2c:9f:07
3122 --radioCfg6PCIeEthDev=0000:00:05.0
3124 --radioCfg6DpdkRx=16
3126 --radioCfg6DpdkTx=16
3134 --radioCfg6NumCell=2
3136 --radioCfg6Cell0PhyId=12
3138 --radioCfg6Cell1PhyId=13
3140 --radioCfg6Cell2PhyId=2
3142 --radioCfg6Cell3PhyId=3
3144 --radioCfg6riuMac=ac:1f:6b:2c:9f:07
3146 --radioCfg7PCIeEthDev=0000:00:06.0
3148 --radioCfg7DpdkRx=16
3150 --radioCfg7DpdkTx=16
3158 --radioCfg7NumCell=2
3160 --radioCfg7Cell0PhyId=14
3162 --radioCfg7Cell1PhyId=15
3164 --radioCfg7Cell2PhyId=2
3166 --radioCfg7Cell3PhyId=3
3168 --radioCfg7riuMac=ac:1f:6b:2c:9f:07
3186 --PdschSymbolSplit=0
3188 --PdschDlWeightSplit=0
3192 --PuschChanEstSplit=0
3198 --PuschUlWeightSplit=0
3200 --FecDecEarlyTermDisable=0
3206 --llrOutDecimalDigit=2
3208 --IrcEnableThreshold=-10
3218 --prachDetectThreshold=0
3226 --systemThread=2, 0, 0
3228 --timerThread=0, 96, 0
3230 --FpgaDriverCpuInfo=3, 96, 0
3232 --FrontHaulCpuInfo=3, 96, 0
3234 --radioDpdkMaster=2, 99, 0
3236 --BbuPoolSleepEnable=1
3238 --BbuPoolThreadCorePriority=94
3240 --BbuPoolThreadCorePolicy=0
3242 --BbuPoolThreadDefault_0_63=0xF0
3244 --BbuPoolThreadDefault_64_127=0x0
3246 --BbuPoolThreadSrs_0_63=0x0
3248 --BbuPoolThreadSrs_64_127=0x0
3250 --BbuPoolThreadDlbeam_0_63=0x0
3252 --BbuPoolThreadDlbeam_64_127=0x0
3254 --BbuPoolThreadUrllc=0x100
3256 --FrontHaulTimeAdvance=7450
3262 --nFecFpgaVersionMu3=0x20010900
3264 --nFecFpgaVersionMu0_1=0x0423D420
3266 --nFhFpgaVersionMu3=0x8001000F
3268 --nFhFpgaVersionMu0_1=0x90010008
3272 --StreamIp=10.255.83.5
3276 wls_dev_filename: wls0
3278 phycfg_apply: Initialize Radio Interface with XRAN library
3280 Setting FecEncSplit to 1 to run on HW accelerator
3282 Setting FecDecSplit to 1 to run on HW accelerator
3284 --------------------------------------------------------
3286 File[xrancfg_sub6_mmimo.xml] Version: 20.08
3288 --------------------------------------------------------
3294 --oRuEthLinkSpeed=25
3300 --PciBusAddoRu0Vf0=0000:51:01.0
3302 --PciBusAddoRu0Vf1=0000:51:01.1
3304 --PciBusAddoRu0Vf2=0000:51:01.2
3306 --PciBusAddoRu0Vf3=0000:51:01.3
3308 --PciBusAddoRu1Vf0=0000:51:01.2
3310 --PciBusAddoRu1Vf1=0000:51:01.3
3312 --PciBusAddoRu1Vf2=0000:51:01.6
3314 --PciBusAddoRu1Vf3=0000:51:01.7
3316 --PciBusAddoRu2Vf0=0000:51:01.4
3318 --PciBusAddoRu2Vf1=0000:51:01.5
3320 --PciBusAddoRu2Vf2=0000:51:02.2
3322 --PciBusAddoRu2Vf3=0000:51:02.3
3324 --PciBusAddoRu3Vf0=0000:00:00.0
3326 --PciBusAddoRu3Vf1=0000:00:00.0
3328 --PciBusAddoRu3Vf2=0000:00:00.0
3330 --PciBusAddoRu3Vf3=0000:00:00.0
3332 --oRuRem0Mac0=00:11:22:33:00:01
3334 --oRuRem0Mac1=00:11:22:33:00:11
3336 --oRuRem0Mac2=00:11:22:33:00:21
3338 --oRuRem0Mac3=00:11:22:33:00:31
3340 --oRuRem1Mac0=00:11:22:33:01:01
3342 --oRuRem1Mac1=00:11:22:33:01:11
3344 --oRuRem1Mac2=00:11:22:33:01:21
3346 --oRuRem1Mac3=00:11:22:33:01:31
3348 --oRuRem2Mac0=00:11:22:33:02:01
3350 --oRuRem2Mac1=00:11:22:33:02:11
3352 --oRuRem2Mac2=00:11:22:33:02:21
3354 --oRuRem2Mac3=00:11:22:33:02:31
3356 --oRuRem3Mac0=00:11:22:33:03:01
3358 --oRuRem3Mac1=00:11:22:33:03:11
3360 --oRuRem3Mac2=00:11:22:33:03:21
3362 --oRuRem3Mac3=00:11:22:33:03:31
3394 --xRANThread=22, 96, 0
3396 --xRANWorker=0x3800000, 96, 0
3422 --c_plane_vlan_tag=1
3424 --u_plane_vlan_tag=2
3444 --DynamicSectionEna=0
3446 --DynamicSectionEnaUL=0
3462 --oRu0PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0
3464 --oRu0PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0
3466 --oRu0PrbElemDl2=96,48,0,14,2,1,1,9,1,0,0
3468 --oRu0PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0
3470 --oRu0PrbElemDl4=192,48,0,14,5,1,1,9,1,0,0
3472 --oRu0PrbElemDl5=240,33,0,14,6,1,1,9,1,0,0
3474 --oRu0PrbElemDl6=240,33,0,14,7,1,1,9,1,0,0
3476 --oRu0PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0
3478 --oRu0ExtBfwDl0=2,24,0,0,9,1
3480 --oRu0ExtBfwDl1=2,24,0,0,9,1
3482 --oRu0ExtBfwDl2=2,24,0,0,9,1
3484 --oRu0ExtBfwDl3=2,24,0,0,9,1
3486 --oRu0ExtBfwDl4=2,24,0,0,9,1
3488 --oRu0ExtBfwDl5=2,17,0,0,9,1
3492 --oRu0PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0
3494 --oRu0PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0
3496 --oRu0PrbElemUl2=96,48,0,14,2,1,1,9,1,0,0
3498 --oRu0PrbElemUl3=144,48,0,14,4,1,1,9,1,0,0
3500 --oRu0PrbElemUl4=192,48,0,14,5,1,1,9,1,0,0
3502 --oRu0PrbElemUl5=240,33,0,14,6,1,1,9,1,0,0
3504 --oRu0PrbElemUl6=240,33,0,14,7,1,1,9,1,0,0
3506 --oRu0PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0
3508 --oRu0ExtBfwUl0=2,24,0,0,9,1
3510 --oRu0ExtBfwUl1=2,24,0,0,9,1
3512 --oRu0ExtBfwUl2=2,24,0,0,9,1
3514 --oRu0ExtBfwUl3=2,24,0,0,9,1
3516 --oRu0ExtBfwUl4=2,24,0,0,9,1
3518 --oRu0ExtBfwUl5=2,17,0,0,9,1
3522 --oRu0PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0
3526 --oRu1PrbElemDl0=0,48,0,14,0,1,1,9,1,0,0
3528 --oRu1PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0
3530 --oRu1PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0
3532 --oRu1PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0
3534 --oRu1PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0
3536 --oRu1PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0
3538 --oRu1PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0
3540 --oRu1PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0
3542 --oRu1ExtBfwDl0=2,24,0,0,9,1
3544 --oRu1ExtBfwDl1=2,24,0,0,9,1
3548 --oRu1PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0
3550 --oRu1PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0
3552 --oRu1PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0
3554 --oRu1PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0
3556 --oRu1PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0
3558 --oRu1PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0
3560 --oRu1PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0
3562 --oRu1PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0
3564 --oRu1ExtBfwUl0=2,24,0,0,9,1
3566 --oRu1ExtBfwUl1=2,24,0,0,9,1
3570 --oRu1PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0
3574 --oRu2PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0
3576 --oRu2PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0
3578 --oRu2PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0
3580 --oRu2PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0
3582 --oRu2PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0
3584 --oRu2PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0
3586 --oRu2PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0
3588 --oRu2PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0
3590 --oRu2ExtBfwDl0=2,24,0,0,9,1
3592 --oRu2ExtBfwDl1=2,24,0,0,9,1
3596 --oRu2PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0
3598 --oRu2PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0
3600 --oRu2PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0
3602 --oRu2PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0
3604 --oRu2PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0
3606 --oRu2PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0
3608 --oRu2PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0
3610 --oRu2PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0
3612 --oRu2ExtBfwUl0=2,24,0,0,9,1
3614 --oRu2ExtBfwUl1=2,24,0,0,9,1
3618 --oRu2PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0
3620 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution
3625 MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(40),
3626 mlogSize(10000) mlog_mask (-1)
3628 mlogSubframes (128), mlogCores(40), mlogSize(10000)
3632 System clock (rdtsc) resolution 1496525824 [Hz]
3636 MLog Storage: 0x7f7403835100 -> 0x7f740690b830 [ 51210032 bytes ]
3638 localMLogFreqReg: 1496. Storing: 1496
3640 Mlog Open successful
3644 num_o_ru 3 EthLinesNumber 2 where VFs 1 per EthLine
3646 VF[0] 0000:51:01.0 [C+U Plane]
3648 VF[1] 0000:51:01.1 [C+U Plane]
3650 VF[2] 0000:51:01.2 [C+U Plane]
3652 VF[3] 0000:51:01.3 [C+U Plane]
3654 VF[4] 0000:51:01.4 [C+U Plane]
3656 VF[5] 0000:51:01.5 [C+U Plane]
3658 oRu0nPrbElemDl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb
3659 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3660 BeamFormingType 1 scaler 0 remask 0x0
3662 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3663 bfwIqWidth 9, bfwCompMeth 1
3665 oRu0nPrbElemDl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb
3666 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3667 BeamFormingType 1 scaler 0 remask 0x0
3669 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3670 bfwIqWidth 9, bfwCompMeth 1
3672 oRu0nPrbElemDl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb
3673 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3674 BeamFormingType 1 scaler 0 remask 0x0
3676 (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3677 bfwIqWidth 9, bfwCompMeth 1
3679 oRu0nPrbElemDl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb
3680 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9
3681 BeamFormingType 1 scaler 0 remask 0x0
3683 (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3684 bfwIqWidth 9, bfwCompMeth 1
3686 oRu0nPrbElemDl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb
3687 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9
3688 BeamFormingType 1 scaler 0 remask 0x0
3690 (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3691 bfwIqWidth 9, bfwCompMeth 1
3693 oRu0nPrbElemDl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb
3694 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9
3695 BeamFormingType 1 scaler 0 remask 0x0
3697 (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0,
3698 bfwIqWidth 9, bfwCompMeth 1
3700 oRu0nPrbElemUl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb
3701 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3702 BeamFormingType 1 scaler 0 remask 0x0
3704 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3705 bfwIqWidth 9, bfwCompMeth 1
3707 oRu0nPrbElemUl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb
3708 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3709 BeamFormingType 1 scaler 0 remask 0x0
3711 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3712 bfwIqWidth 9, bfwCompMeth 1
3714 oRu0nPrbElemUl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb
3715 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3716 BeamFormingType 1 scaler 0 remask 0x0
3718 (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3719 bfwIqWidth 9, bfwCompMeth 1
3721 oRu0nPrbElemUl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb
3722 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9
3723 BeamFormingType 1 scaler 0 remask 0x0
3725 (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3726 bfwIqWidth 9, bfwCompMeth 1
3728 oRu0nPrbElemUl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb
3729 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9
3730 BeamFormingType 1 scaler 0 remask 0x0
3732 (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3733 bfwIqWidth 9, bfwCompMeth 1
3735 oRu0nPrbElemUl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb
3736 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9
3737 BeamFormingType 1 scaler 0 remask 0x0
3739 (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0,
3740 bfwIqWidth 9, bfwCompMeth 1
3742 oRu0nPrbElemSrs0: oRu0: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb
3743 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3744 BeamFormingType 1 scaler 0 remask 0x0
3746 oRu1nPrbElemDl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb
3747 14,nBeamIndex 0, bf_weight_update 1 compMethod 1, iqWidth 9
3748 BeamFormingType 1 scaler 0 remask 0x0
3750 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3751 bfwIqWidth 9, bfwCompMeth 1
3753 oRu1nPrbElemDl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb
3754 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3755 BeamFormingType 1 scaler 0 remask 0x0
3757 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3758 bfwIqWidth 9, bfwCompMeth 1
3760 oRu1nPrbElemUl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb
3761 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3762 BeamFormingType 1 scaler 0 remask 0x0
3764 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3765 bfwIqWidth 9, bfwCompMeth 1
3767 oRu1nPrbElemUl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb
3768 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3769 BeamFormingType 1 scaler 0 remask 0x0
3771 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3772 bfwIqWidth 9, bfwCompMeth 1
3774 oRu1nPrbElemSrs0: oRu1: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb
3775 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3776 BeamFormingType 1 scaler 0 remask 0x0
3778 oRu2nPrbElemDl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb
3779 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3780 BeamFormingType 1 scaler 0 remask 0x0
3782 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3783 bfwIqWidth 9, bfwCompMeth 1
3785 oRu2nPrbElemDl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb
3786 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3787 BeamFormingType 1 scaler 0 remask 0x0
3789 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3790 bfwIqWidth 9, bfwCompMeth 1
3792 oRu2nPrbElemUl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb
3793 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3794 BeamFormingType 1 scaler 0 remask 0x0
3796 (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3797 bfwIqWidth 9, bfwCompMeth 1
3799 oRu2nPrbElemUl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb
3800 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9
3801 BeamFormingType 1 scaler 0 remask 0x0
3803 (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0,
3804 bfwIqWidth 9, bfwCompMeth 1
3806 oRu2nPrbElemSrs0: oRu2: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb
3807 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9
3808 BeamFormingType 1 scaler 0 remask 0x0
3810 gnb_io_xran_cfg_setup successful
3818 PF Eth line speed 25G
3820 PF Eth lines per O-xU port 2
3824 hw-accelerated bbdev 0000:92:00.0
3826 total cores 48 c_mask 0x3c00004 core 22 [id] system_core 2 [id]
3827 pkt_proc_core 0x3800000 [mask] pkt_aux_core 0 [id] timing_core 22 [id]
3829 xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x3c00004 -n2
3830 --iova-mode=pa --socket-mem=18432 --socket-limit=18432 --proc-type=auto
3831 --file-prefix wls0 -w 0000:00:00.0 -w 0000:92:00.0
3833 EAL: Detected 48 lcore(s)
3835 EAL: Detected 1 NUMA nodes
3837 EAL: Auto-detected process type: PRIMARY
3839 EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket
3841 EAL: Selected IOVA mode 'PA'
3843 EAL: No available hugepages reported in hugepages-2048kB
3845 EAL: Probing VFIO support...
3847 EAL: PCI device 0000:92:00.0 on NUMA socket 0
3849 EAL: probe driver: 8086:d8f intel_fpga_5gnr_fec_pf
3851 xran_init_mbuf_pool: socket 0
3853 EAL: PCI device 0000:51:01.0 on NUMA socket 0
3855 EAL: probe driver: 8086:1889 net_iavf
3857 initializing port 0 for TX, drv=net_iavf
3859 Port 0 MAC: 00 11 22 33 00 00
3861 Port 0: nb_rxd 4096 nb_txd 4096
3865 [0] mempool_small__0
3867 iavf_init_rss(): RSS is enabled by PF by default
3869 Checking link status portid [0] ... done
3871 Port 0 Link Up - speed 100000 Mbps - full-duplex
3873 EAL: PCI device 0000:51:01.1 on NUMA socket 0
3875 EAL: probe driver: 8086:1889 net_iavf
3877 initializing port 1 for TX, drv=net_iavf
3879 Port 1 MAC: 00 11 22 33 00 10
3881 Port 1: nb_rxd 4096 nb_txd 4096
3885 [1] mempool_small__1
3887 iavf_init_rss(): RSS is enabled by PF by default
3889 Checking link status portid [1] ... done
3891 Port 1 Link Up - speed 100000 Mbps - full-duplex
3893 EAL: PCI device 0000:51:01.2 on NUMA socket 0
3895 EAL: probe driver: 8086:1889 net_iavf
3897 initializing port 2 for TX, drv=net_iavf
3899 Port 2 MAC: 00 11 22 33 01 00
3901 Port 2: nb_rxd 4096 nb_txd 4096
3905 [2] mempool_small__2
3907 iavf_init_rss(): RSS is enabled by PF by default
3909 Checking link status portid [2] ... done
3911 Port 2 Link Up - speed 100000 Mbps - full-duplex
3913 EAL: PCI device 0000:51:01.3 on NUMA socket 0
3915 EAL: probe driver: 8086:1889 net_iavf
3917 initializing port 3 for TX, drv=net_iavf
3919 Port 3 MAC: 00 11 22 33 01 10
3921 Port 3: nb_rxd 4096 nb_txd 4096
3925 [3] mempool_small__3
3927 iavf_init_rss(): RSS is enabled by PF by default
3929 Checking link status portid [3] ... done
3931 Port 3 Link Up - speed 100000 Mbps - full-duplex
3933 EAL: PCI device 0000:51:01.4 on NUMA socket 0
3935 EAL: probe driver: 8086:1889 net_iavf
3937 initializing port 4 for TX, drv=net_iavf
3939 Port 4 MAC: 00 11 22 33 02 00
3941 Port 4: nb_rxd 4096 nb_txd 4096
3945 [4] mempool_small__4
3947 iavf_init_rss(): RSS is enabled by PF by default
3949 Checking link status portid [4] ... done
3951 Port 4 Link Up - speed 100000 Mbps - full-duplex
3953 EAL: PCI device 0000:51:01.5 on NUMA socket 0
3955 EAL: probe driver: 8086:1889 net_iavf
3957 initializing port 5 for TX, drv=net_iavf
3959 Port 5 MAC: 00 11 22 33 02 10
3961 Port 5: nb_rxd 4096 nb_txd 4096
3965 [5] mempool_small__5
3967 iavf_init_rss(): RSS is enabled by PF by default
3969 Checking link status portid [5] ... done
3971 Port 5 Link Up - speed 100000 Mbps - full-duplex
3973 [ 0] vf 0 local SRC MAC: 00 11 22 33 00 00
3975 [ 0] vf 0 remote DST MAC: 00 11 22 33 00 01
3977 [ 0] vf 1 local SRC MAC: 00 11 22 33 00 10
3979 [ 0] vf 1 remote DST MAC: 00 11 22 33 00 11
3981 [ 1] vf 2 local SRC MAC: 00 11 22 33 01 00
3983 [ 1] vf 2 remote DST MAC: 00 11 22 33 01 01
3985 [ 1] vf 3 local SRC MAC: 00 11 22 33 01 10
3987 [ 1] vf 3 remote DST MAC: 00 11 22 33 01 11
3989 [ 2] vf 4 local SRC MAC: 00 11 22 33 02 00
3991 [ 2] vf 4 remote DST MAC: 00 11 22 33 02 01
3993 [ 2] vf 5 local SRC MAC: 00 11 22 33 02 10
3995 [ 2] vf 5 remote DST MAC: 00 11 22 33 02 11
3997 created dl_gen_ring_up_0
3999 created dl_gen_ring_up_1
4001 created dl_gen_ring_up_2
4003 xran_init successful, pHandle = 0x7f7393b23040
4009 FEC is accelerated through BBDEV: 0000:92:00.0
4011 wls_layer_init[wls0] nWlsMemorySize[1063256064]
4013 wls_lib: Open wls0 (DPDK memzone)
4015 wls_lib: WLS_Open 0x43f600000
4017 wls_lib: link: 0 <-> 1
4021 wls_lib: WLS shared management memzone: wls0
4023 wls_lib: hugePageSize on the system is 1073741824
4025 wls_lib: WLS_Alloc [1063256064] bytes
4027 ===========================================================================================================
4031 ===========================================================================================================
4035 IMG-date: Aug 5 2020
4039 ===========================================================================================================
4041 DEPENDENCIES VERSIONS
4043 ===========================================================================================================
4045 FlexRAN BBU pooling version #DIRTY#
4047 FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#
4049 FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#
4051 FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#
4053 FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#
4055 FlexRAN SDK bblib_llr_demapping version #DIRTY#
4057 FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#
4059 FlexRAN SDK bblib_reed_muller version #DIRTY#
4061 FlexRAN SDK bblib_lte_modulation version #DIRTY#
4063 FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#
4065 FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#
4067 FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#
4069 FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#
4071 FlexRAN SDK bblib_fd_correlation version #DIRTY#
4073 FlexRAN SDK bblib_scramble_5gnr version #DIRTY#
4075 FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#
4077 FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#
4079 FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#
4081 FlexRAN SDK bblib_prach_5gnr version #DIRTY#
4083 FlexRAN SDK bblib_fft_ifft version #DIRTY#
4085 FlexRAN SDK bblib_pucch_5gnr version #DIRTY#
4087 FlexRAN SDK bblib_lte_crc version #DIRTY#
4089 FlexRAN SDK bblib_common version #DIRTY#
4091 ===========================================================================================================
4093 ===========================================================================================================
4095 Non BBU threads in application
4097 ===========================================================================================================
4099 nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 29438] binding on [CPU 2]
4100 [PRIO: 0] [POLICY: 1]
4102 wls_rx_handler (non-rt): [PID: 29445] binding on [CPU 2]
4104 ===========================================================================================================
4106 PHY>welcome to application console
4112 PHY>Received MSG_TYPE_PHY_ADD_REMOVE_CORE
4114 Processing MSG_TYPE_PHY_ADD_REMOVE_CORE
4116 phy_bbupool_set_core[0] (add): 137170526192 [0x0000001ff0001ff0]
4117 Current: 0 [0x0000000000000000]
4119 nr5g_gnb_mac2phy_api_set_options: PDSCH_SPLIT[4] nCellMask[0x00000001]
4121 nr5g_gnb_mac2phy_api_set_options: PDSCH_DL_WEIGHT_SPLIT[4]
4122 nCellMask[0x00000001]
4124 nr5g_gnb_mac2phy_api_set_options: PUSCH_CHANEST_SPLIT[2]
4125 nCellMask[0x00000001]
4127 nr5g_gnb_mac2phy_api_set_options: PUSCH_MMSE_SPLIT[4]
4128 nCellMask[0x00000001]
4130 nr5g_gnb_mac2phy_api_set_options: PUSCH_LLR_RX_SPLIT[2]
4131 nCellMask[0x00000001]
4133 nr5g_gnb_mac2phy_api_set_options: PUSCH_UL_WEIGHT_SPLIT[2]
4134 nCellMask[0x00000001]
4136 nr5g_gnb_mac2phy_api_set_options: FEC_DEC_NUM_ITER[3]
4137 nCellMask[0x00ffffff]
4139 Received MSG_TYPE_PHY_UL_IQ_SAMPLES
4141 Received MSG_TYPE_PHY_UL_IQ_SAMPLES
4143 Received MSG_TYPE_PHY_UL_IQ_SAMPLES
4145 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0
4147 phydi_read_write_iq_samples: direction[1] nNumerologyMult[2]
4148 fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64]
4149 numPorts[8] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1]
4150 PhaseCompensationEnable[0]
4151 filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/376/uliq00_tst376.bin]
4152 filename_in_prach_iq[]
4154 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 1
4156 phydi_read_write_iq_samples: direction[1] nNumerologyMult[2]
4157 fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64]
4158 numPorts[8] nIsRadioMode[1] carrNum[1] TimerModeFreqDomain[1]
4159 PhaseCompensationEnable[0]
4160 filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin]
4161 filename_in_prach_iq[]
4163 Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 2
4165 phydi_read_write_iq_samples: direction[1] nNumerologyMult[2]
4166 fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64]
4167 numPorts[8] nIsRadioMode[1] carrNum[2] TimerModeFreqDomain[1]
4168 PhaseCompensationEnable[0]
4169 filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin]
4170 filename_in_prach_iq[]
4172 Received MSG_TYPE_PHY_CONFIG_REQ: 0
4174 Received MSG_TYPE_PHY_CONFIG_REQ: 1
4176 Received MSG_TYPE_PHY_CONFIG_REQ: 2
4178 Processing MSG_TYPE_PHY_CONFIG_REQ: 0
4180 phy_bbupool_init: Changing Core Mask0 [0xf0] to [0x1ff0001ff0]
4182 phy_bbupool_set_config: Using cores: 0x0000001ff0001ff0 for BBU Pool
4183 nBbuPoolSleepEnable: 1
4185 BBU Pooling: queueId = 0, the according nCoreNum = 18, the according
4186 cpuSetMask = 0x1ff0001ff0
4188 BBU Pooling: gCoreIdxMap[0] = 4 is available!
4190 BBU Pooling: gCoreIdxMap[1] = 5 is available!
4192 BBU Pooling: gCoreIdxMap[2] = 6 is available!
4194 BBU Pooling: gCoreIdxMap[3] = 7 is available!
4196 BBU Pooling: gCoreIdxMap[4] = 8 is available!
4198 BBU Pooling: gCoreIdxMap[5] = 9 is available!
4200 BBU Pooling: gCoreIdxMap[6] = 10 is available!
4202 BBU Pooling: gCoreIdxMap[7] = 11 is available!
4204 BBU Pooling: gCoreIdxMap[8] = 12 is available!
4206 BBU Pooling: gCoreIdxMap[9] = 28 is available!
4208 BBU Pooling: gCoreIdxMap[10] = 29 is available!
4210 BBU Pooling: gCoreIdxMap[11] = 30 is available!
4212 BBU Pooling: gCoreIdxMap[12] = 31 is available!
4214 BBU Pooling: gCoreIdxMap[13] = 32 is available!
4216 BBU Pooling: gCoreIdxMap[14] = 33 is available!
4218 BBU Pooling: gCoreIdxMap[15] = 34 is available!
4220 BBU Pooling: gCoreIdxMap[16] = 35 is available!
4222 BBU Pooling: gCoreIdxMap[17] = 36 is available!
4224 phy_bbupool_init: Changing SrsCore Mask0 [(nil)] to [0x10000010]
4226 phy_bbupool_init: Changing DlbeamCore Mask0 [(nil)] to [0x7e0]
4228 Massive Mimo Config: nCarrierAggregationLevel[3],
4229 nMassiveMimoSrsCoresMask[0x10000010] nTotalSrsCores[2]
4231 Setting aside core[4] for SRS
4233 Setting aside core[28] for SRS
4235 Massive Mimo Config: nCarrierAggregationLevel[3],
4236 nMassiveMimoDlbeamCoresMask[0x7e0] nTotalDlbeamCores[6]
4238 Setting aside core[5] for DL beam
4240 Setting aside core[6] for DL beam
4242 Setting aside core[7] for DL beam
4244 Setting aside core[8] for DL beam
4246 Setting aside core[9] for DL beam
4248 Setting aside core[10] for DL beam
4250 BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered
4252 BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered
4254 BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered
4256 BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered
4258 BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered
4260 BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered
4262 BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered
4264 BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered
4266 BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered
4268 BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered
4270 BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered
4272 BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered
4274 BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered
4276 BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered
4278 BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered
4280 BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered
4282 BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered
4284 BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered
4286 BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered
4288 BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered
4290 BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered
4292 BBU Pooling: taskId = 21 taskName = DL_L1_BEAM_WEIGHT_GEN is registered
4294 BBU Pooling: taskId = 22 taskName = DL_L1_BEAM_WEIGHT_TX is registered
4296 BBU Pooling: taskId = 23 taskName = UL_L1_BEAM_WEIGHT_GEN is registered
4298 BBU Pooling: taskId = 24 taskName = UL_L1_BEAM_WEIGHT_TX is registered
4300 BBU Pooling: taskId = 25 taskName = UL_L1_SRS_CE is registered
4302 BBU Pooling: taskId = 26 taskName = UL_L1_SRS_REPORT is registered
4304 BBU Pooling: taskId = 27 taskName = UL_L1_PUSCH_CE0_PRE is registered
4306 BBU Pooling: taskId = 28 taskName = UL_L1_PUSCH_CE7_PRE is registered
4308 BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB
4309 DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS
4311 BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A
4313 BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER:
4314 DL_L1_PDSCH_SYMBOL_TX
4316 BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST
4318 BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX
4320 BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST
4322 BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST
4323 UL_L1_BEAM_WEIGHT_GEN
4325 BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0
4328 BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7
4330 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0
4333 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7
4335 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR
4337 BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR
4339 BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE
4341 BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A
4343 BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST
4345 BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST
4347 BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST
4349 BBU Pooling: next taskList of UL_L1_SRS: UL_L1_SRS_CE
4351 BBU Pooling: next taskList of DL_L1_POST: N/A
4353 BBU Pooling: next taskList of UL_L1_POST: N/A
4355 BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_GEN:
4356 DL_L1_BEAM_WEIGHT_TX
4358 BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_TX: DL_L1_POST
4360 BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_GEN:
4361 UL_L1_BEAM_WEIGHT_TX
4363 BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_TX: UL_L1_POST
4365 BBU Pooling: next taskList of UL_L1_SRS_CE: UL_L1_SRS_REPORT
4367 BBU Pooling: next taskList of UL_L1_SRS_REPORT: N/A
4369 BBU Pooling: next taskList of UL_L1_PUSCH_CE0_PRE: UL_L1_PUSCH_CE0
4372 BBU Pooling: next taskList of UL_L1_PUSCH_CE7_PRE: UL_L1_PUSCH_CE7
4374 enter RtThread Launch
4376 Allocated gpThreadWorker[coreIdx: 0][CoreNum: 4]: [0x7f738c000b70]
4378 Allocated gpThreadWorker[coreIdx: 1][CoreNum: 5]: [0x7f738c000e20]
4380 Allocated gpThreadWorker[coreIdx: 2][CoreNum: 6]: [0x7f738c0010d0]
4382 Allocated gpThreadWorker[coreIdx: 3][CoreNum: 7]: [0x7f738c001380]
4384 Allocated gpThreadWorker[coreIdx: 4][CoreNum: 8]: [0x7f738c001630]
4386 Allocated gpThreadWorker[coreIdx: 5][CoreNum: 9]: [0x7f738c0018e0]
4388 launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1
4389 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4391 launching Thread 0 Queue 0 uCoreIdx 0 CoreId 4 Priority 94 Policy 1
4392 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4394 launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1
4395 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4397 launching Thread 3 Queue 0 uCoreIdx 3 CoreId 7 Priority 94 Policy 1
4398 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4400 Allocated gpThreadWorker[coreIdx: 6][CoreNum: 10]: [0x7f738c001b90]
4402 launching Thread 4 Queue 0 uCoreIdx 4 CoreId 8 Priority 94 Policy 1
4403 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4405 launching Thread 5 Queue 0 uCoreIdx 5 CoreId 9 Priority 94 Policy 1
4406 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4408 Allocated gpThreadWorker[coreIdx: 7][CoreNum: 11]: [0x7f738c001e40]
4410 Allocated gpThreadWorker[coreIdx: 8][CoreNum: 12]: [0x7f738c0020f0]
4412 bbupool_core_main: the server's coreNum = 48, the nCore = 18,nRtCoreMask
4413 = 0x1ff0001ff0, the nFeIfCore = 0,nFeIfCoreMask = 0x0
4415 bbupool_core_main pthread_setaffinity_np succeed: coreId = 2, result = 0
4417 Allocated gpThreadWorker[coreIdx: 9][CoreNum: 28]: [0x7f738c0023a0]
4419 launching Thread 6 Queue 0 uCoreIdx 6 CoreId 10 Priority 94 Policy 1
4420 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4422 Allocated gpThreadWorker[coreIdx: 10][CoreNum: 29]: [0x7f738c002650]
4424 launching Thread 7 Queue 0 uCoreIdx 7 CoreId 11 Priority 94 Policy 1
4425 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4427 Allocated gpThreadWorker[coreIdx: 11][CoreNum: 30]: [0x7f738c002900]
4429 launching Thread 8 Queue 0 uCoreIdx 8 CoreId 12 Priority 94 Policy 1
4430 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4432 launching Thread 9 Queue 0 uCoreIdx 9 CoreId 28 Priority 94 Policy 1
4433 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4435 Allocated gpThreadWorker[coreIdx: 12][CoreNum: 31]: [0x7f738c002bb0]
4437 Allocated gpThreadWorker[coreIdx: 13][CoreNum: 32]: [0x7f738c002e60]
4439 launching Thread 10 Queue 0 uCoreIdx 10 CoreId 29 Priority 94 Policy 1
4440 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4442 launching Thread 11 Queue 0 uCoreIdx 11 CoreId 30 Priority 94 Policy 1
4443 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4445 Allocated gpThreadWorker[coreIdx: 14][CoreNum: 33]: [0x7f738c003110]
4447 Allocated gpThreadWorker[coreIdx: 15][CoreNum: 34]: [0x7f738c0033c0]
4449 launching Thread 12 Queue 0 uCoreIdx 12 CoreId 31 Priority 94 Policy 1
4450 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4452 Allocated gpThreadWorker[coreIdx: 16][CoreNum: 35]: [0x7f738c003670]
4454 launching Thread 13 Queue 0 uCoreIdx 13 CoreId 32 Priority 94 Policy 1
4455 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4457 Allocated gpThreadWorker[coreIdx: 17][CoreNum: 36]: [0x7f738c003920]
4459 18 thread associated with queue 0:coreIdx 0 1 2 3 4 5 6 7 8 9 10 11 12
4462 Leave RtThread Launch
4464 launching Thread 14 Queue 0 uCoreIdx 14 CoreId 33 Priority 94 Policy 1
4465 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4467 launching Thread 15 Queue 0 uCoreIdx 15 CoreId 34 Priority 94 Policy 1
4468 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4470 launching Thread 16 Queue 0 uCoreIdx 16 CoreId 35 Priority 94 Policy 1
4471 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4473 launching Thread 17 Queue 0 uCoreIdx 17 CoreId 36 Priority 94 Policy 1
4474 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1
4476 nr5g_gnb_mac2phy_api_proc_print_phy_init [0]:
4484 nDLAbsFrePointA: 3500000
4486 nULAbsFrePointA: 3500000
4530 nCarrierAggregationLevel: 2
4536 nTddPeriod: 10 (TDD)
4540 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10
4543 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4545 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4547 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4549 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
4551 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
4553 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4555 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4557 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4559 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
4561 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
4565 nPrachSubcSpacing: 1
4567 nPrachZeroCorrConf: 1
4569 nPrachRestrictSet: 0
4573 nPrachFreqStart: 100
4591 nUrllcMiniSlotMask: 1 (0x00000001)
4593 read_table: File table/common/pss_table.bin of size 381 read_size: 381
4595 read_table: File table/common/sss_table.bin of size 128016 read_size:
4598 read_table: File table/common/srs_zc_36_plus.bin of size 905916
4601 read_table: File table/common/pucch_zc_36_plus.bin of size 383040
4604 read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216
4607 read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216
4610 BBU Pooling Info: maximum period length was configured, preMaxSF =
4611 20480, postMasSF = 20480
4613 set_slot_type SlotPattern:
4615 Slot: 0 1 2 3 4 5 6 7 8 9
4617 0 DL DL DL SP UL DL DL DL SP UL
4619 PHYDI-INIT[from 2] PhyInstance: 0
4621 Processing MSG_TYPE_PHY_CONFIG_REQ: 1
4623 nr5g_gnb_mac2phy_api_proc_print_phy_init [1]:
4631 nDLAbsFrePointA: 3500000
4633 nULAbsFrePointA: 3500000
4677 nCarrierAggregationLevel: 2
4683 nTddPeriod: 10 (TDD)
4687 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10
4690 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4692 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4694 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4696 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
4698 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
4700 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4702 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4704 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4706 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
4708 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
4712 nPrachSubcSpacing: 1
4714 nPrachZeroCorrConf: 1
4716 nPrachRestrictSet: 0
4720 nPrachFreqStart: 100
4738 nUrllcMiniSlotMask: 1 (0x00000001)
4740 BBU Pooling Info: maximum period length was configured, preMaxSF =
4741 20480, postMasSF = 20480
4743 set_slot_type SlotPattern:
4745 Slot: 0 1 2 3 4 5 6 7 8 9
4747 0 DL DL DL SP UL DL DL DL SP UL
4749 PHYDI-INIT[from 2] PhyInstance: 1
4751 Processing MSG_TYPE_PHY_CONFIG_REQ: 2
4753 nr5g_gnb_mac2phy_api_proc_print_phy_init [2]:
4761 nDLAbsFrePointA: 3500000
4763 nULAbsFrePointA: 3500000
4807 nCarrierAggregationLevel: 2
4813 nTddPeriod: 10 (TDD)
4817 Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10
4820 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4822 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4824 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4826 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
4828 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
4830 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4832 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4834 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL
4836 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL
4838 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL
4842 nPrachSubcSpacing: 1
4844 nPrachZeroCorrConf: 1
4846 nPrachRestrictSet: 0
4850 nPrachFreqStart: 100
4868 nUrllcMiniSlotMask: 1 (0x00000001)
4870 BBU Pooling Info: maximum period length was configured, preMaxSF =
4871 20480, postMasSF = 20480
4873 set_slot_type SlotPattern:
4875 Slot: 0 1 2 3 4 5 6 7 8 9
4877 0 DL DL DL SP UL DL DL DL SP UL
4879 PHYDI-INIT[from 2] PhyInstance: 2
4881 ---------------------------------------------------------
4885 ---------------------------------------------------------
4889 gCarrierAggLevelInit: 3
4893 ---------------------------------------------------------
4895 Received MSG_TYPE_PHY_START_REQ: 0
4897 Received MSG_TYPE_PHY_START_REQ: 1
4899 Received MSG_TYPE_PHY_START_REQ: 2
4901 Processing MSG_TYPE_PHY_START_REQ: 0
4905 xran_init_vfs_mapping: p 0 vf 0
4907 xran_init_vfs_mapping: p 0 vf 1
4911 xran_timing_source_thread [CPU 22] [PID: 29437]
4913 xran_open [CPU 2] [PID: 29437]
4915 Waithing on Timing thread...
4917 TTI interval 500 [us]
4919 Start C-plane DL 71 us after TTI [trigger on sym 2]
4921 Start C-plane UL 200 us after TTI [trigger on sym 6]
4923 Start U-plane DL 196 us before OTA [offset in sym -5]
4925 Start U-plane UL 75 us OTA [offset in sym 3]
4927 C-plane to U-plane delay 125 us after TTI
4929 Start Sym timer 35714 ns
4933 xran_init_vfs_mapping: p 1 vf 2
4935 xran_init_vfs_mapping: p 1 vf 3
4937 Start C-plane DL 71 us after TTI [trigger on sym 2]
4939 Start C-plane UL 200 us after TTI [trigger on sym 6]
4941 Start U-plane DL 196 us before OTA [offset in sym -5]
4943 Start U-plane UL 75 us OTA [offset in sym 3]
4945 C-plane to U-plane delay 125 us after TTI
4947 Start Sym timer 35714 ns
4949 xran_open [CPU 2] [PID: 29437]
4951 Waithing on Timing thread...
4955 xran_init_vfs_mapping: p 2 vf 4
4957 xran_init_vfs_mapping: p 2 vf 5
4959 Start C-plane DL 71 us after TTI [trigger on sym 2]
4961 Start C-plane UL 200 us after TTI [trigger on sym 6]
4963 Start U-plane DL 196 us before OTA [offset in sym -5]
4965 Start U-plane UL 75 us OTA [offset in sym 3]
4967 C-plane to U-plane delay 125 us after TTI
4969 Start Sym timer 35714 ns
4985 p:0 XRAN_JOB_TYPE_CP_DL worker id 1
4987 p:0 XRAN_JOB_TYPE_CP_UL worker id 1
4989 p:1 XRAN_JOB_TYPE_CP_DL worker id 1
4991 p:1 XRAN_JOB_TYPE_CP_UL worker id 1
4993 p:2 XRAN_JOB_TYPE_CP_DL worker id 1
4995 p:2 XRAN_JOB_TYPE_CP_UL worker id 1
4997 p:1 XRAN_JOB_TYPE_CP_DL worker id 2
4999 p:1 XRAN_JOB_TYPE_CP_UL worker id 2
5001 p:2 XRAN_JOB_TYPE_CP_DL worker id 2
5003 p:2 XRAN_JOB_TYPE_CP_UL worker id 2
5005 xran_generic_worker_thread [CPU 23] [PID: 29437]
5007 spawn worker 0 core 23
5009 xran_generic_worker_thread [CPU 24] [PID: 29437]
5011 spawn worker 1 core 24
5013 xran_generic_worker_thread [CPU 25] [PID: 29437]
5015 spawn worker 2 core 25
5017 xran_open [CPU 2] [PID: 29437]
5019 Waithing on Timing thread...
5021 ----------------------------------------------------------------------------
5023 mem_mgr_display_size:
5025 Num Memory Alloc: 38,294
5027 Total Memory Size: 20,049,968,118
5029 ----------------------------------------------------------------------------
5031 PHYDI-START[from 2] PhyInstance: 0, Mode: 4, Count: 100207, Period: 0,
5034 PHYDI-START[from 2] PhyInstance: 1, Mode: 4, Count: 100207, Period: 0,
5037 PHYDI-START[from 2] PhyInstance: 2, Mode: 4, Count: 100207, Period: 0,
5040 Setting nMultiCellModeDelay: 40000
5042 nr5g_gnb_urllc_register_call_backs: nTimerMode[0] nUrllcMiniSlotMask[0]
5044 port [0] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64
5045 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]
5049 port 0 cc_id 0 is phy id 0
5051 XRAN front haul xran_mm_init
5053 xran_sector_get_instances [0]: CC 0 handle 0x7f6fe7383280
5055 Handle: 0xee1c8e0 Instance: 0x7f6fe7383280
5057 gnb_io_xran_start [0]: CC 0 handle 0x7f6fe7383280
5059 Sucess xran_mm_init Instance 0x7f6fe7383280
5063 ru_0_cc_0_idx_0: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 0]
5064 nNumberOfBuffers 8960 nBufferSize 14432
5066 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool
5069 ru_0_cc_0_idx_1: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 1]
5070 nNumberOfBuffers 286720 nBufferSize 32
5072 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool
5075 ru_0_cc_0_idx_2: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 2]
5076 nNumberOfBuffers 8960 nBufferSize 12560
5078 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool
5081 ru_0_cc_0_idx_3: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 3]
5082 nNumberOfBuffers 8960 nBufferSize 14432
5084 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool
5087 ru_0_cc_0_idx_4: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 4]
5088 nNumberOfBuffers 286720 nBufferSize 32
5090 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool
5093 ru_0_cc_0_idx_5: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 5]
5094 nNumberOfBuffers 8960 nBufferSize 12560
5096 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool
5099 ru_0_cc_0_idx_6: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 6]
5100 nNumberOfBuffers 8960 nBufferSize 8192
5102 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool
5105 ru_0_cc_0_idx_7: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 7]
5106 nNumberOfBuffers 35840 nBufferSize 14432
5108 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 7] mb pool
5111 ru_0_cc_0_idx_8: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 8]
5112 nNumberOfBuffers 1146880 nBufferSize 32
5114 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 8] mb pool
5117 ru_0_cc_0_idx_9: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 9]
5118 nNumberOfBuffers 35840 nBufferSize 12560
5120 CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 9] mb pool
5123 port [0] gnb_io_xran_init_cp
5125 port [0] init xran successfully
5127 port [1] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64
5128 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]
5132 port 1 cc_id 0 is phy id 1
5134 XRAN front haul xran_mm_init
5136 xran_sector_get_instances [1]: CC 0 handle 0x7f6fe7383380
5138 Handle: 0xee1c940 Instance: 0x7f6fe7383380
5140 gnb_io_xran_start [1]: CC 0 handle 0x7f6fe7383380
5142 Sucess xran_mm_init Instance 0x7f6fe7383280
5146 ru_1_cc_0_idx_0: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 0]
5147 nNumberOfBuffers 8960 nBufferSize 14432
5149 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 0] mb pool
5152 ru_1_cc_0_idx_1: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 1]
5153 nNumberOfBuffers 286720 nBufferSize 32
5155 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 1] mb pool
5158 ru_1_cc_0_idx_2: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 2]
5159 nNumberOfBuffers 8960 nBufferSize 12560
5161 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 2] mb pool
5164 ru_1_cc_0_idx_3: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 3]
5165 nNumberOfBuffers 8960 nBufferSize 14432
5167 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 3] mb pool
5170 ru_1_cc_0_idx_4: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 4]
5171 nNumberOfBuffers 286720 nBufferSize 32
5173 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 4] mb pool
5176 ru_1_cc_0_idx_5: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 5]
5177 nNumberOfBuffers 8960 nBufferSize 12560
5179 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 5] mb pool
5182 ru_1_cc_0_idx_6: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 6]
5183 nNumberOfBuffers 8960 nBufferSize 8192
5185 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 6] mb pool
5188 ru_1_cc_0_idx_7: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 7]
5189 nNumberOfBuffers 35840 nBufferSize 14432
5191 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 7] mb pool
5194 ru_1_cc_0_idx_8: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 8]
5195 nNumberOfBuffers 1146880 nBufferSize 32
5197 O-DU: thread_run start time: 08/11/20 23:05:24.000000001 UTC [500]
5199 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 8] mb pool
5202 ru_1_cc_0_idx_9: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 9]
5203 nNumberOfBuffers 35840 nBufferSize 12560
5205 CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 9] mb pool
5208 port [1] gnb_io_xran_init_cp
5210 port [1] init xran successfully
5212 port [2] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64
5213 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]
5217 port 2 cc_id 0 is phy id 2
5219 XRAN front haul xran_mm_init
5221 xran_sector_get_instances [2]: CC 0 handle 0x7f6fe7383440
5223 Handle: 0xee1c9a0 Instance: 0x7f6fe7383440
5225 gnb_io_xran_start [2]: CC 0 handle 0x7f6fe7383440
5227 Sucess xran_mm_init Instance 0x7f6fe7383280
5231 ru_2_cc_0_idx_0: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 0]
5232 nNumberOfBuffers 8960 nBufferSize 14432
5234 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 0] mb pool
5237 ru_2_cc_0_idx_1: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 1]
5238 nNumberOfBuffers 286720 nBufferSize 32
5240 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 1] mb pool
5243 ru_2_cc_0_idx_2: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 2]
5244 nNumberOfBuffers 8960 nBufferSize 12560
5246 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 2] mb pool
5249 ru_2_cc_0_idx_3: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 3]
5250 nNumberOfBuffers 8960 nBufferSize 14432
5252 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 3] mb pool
5255 ru_2_cc_0_idx_4: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 4]
5256 nNumberOfBuffers 286720 nBufferSize 32
5258 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 4] mb pool
5261 ru_2_cc_0_idx_5: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 5]
5262 nNumberOfBuffers 8960 nBufferSize 12560
5264 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 5] mb pool
5267 ru_2_cc_0_idx_6: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 6]
5268 nNumberOfBuffers 8960 nBufferSize 8192
5270 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 6] mb pool
5273 ru_2_cc_0_idx_7: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 7]
5274 nNumberOfBuffers 35840 nBufferSize 14432
5276 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 7] mb pool
5279 ru_2_cc_0_idx_8: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 8]
5280 nNumberOfBuffers 1146880 nBufferSize 32
5282 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 8] mb pool
5285 ru_2_cc_0_idx_9: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 9]
5286 nNumberOfBuffers 35840 nBufferSize 12560
5288 CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 9] mb pool
5291 port [2] gnb_io_xran_init_cp
5293 port [2] init xran successfully
5295 O-DU: XRAN start time: 08/11/20 23:05:24.384220762 UTC [500]
5297 BBU Pooling: enter multicell Activate!
5299 BBU Pooling Info: bbupool rt thread start on CoreIdx 14 coreId 33 at
5300 118352443946329 at sf=0 with queue 0 successfully
5302 BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at
5303 118352443939667 at sf=0 with queue 0 successfully
5305 BBU Pooling Info: bbupool rt thread start on CoreIdx 11 coreId 30 at
5306 118352443942535 at sf=0 with queue 0 successfully
5308 BBU Pooling Info: bbupool rt thread start on CoreIdx 8 coreId 12 at
5309 118352443944575 at sf=0 with queue 0 successfully
5311 BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0,
5312 activesfn = 4, CellNumInActSfn = 3
5314 BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at
5315 118352443929961 at sf=0 with queue 0 successfully
5317 BBU Pooling Info: bbupool rt thread start on CoreIdx 15 coreId 34 at
5318 118352443933301 at sf=0 with queue 0 successfully
5320 BBU Pooling: multiCell Activate sucessfully!
5322 BBU Pooling Info: bbupool rt thread start on CoreIdx 13 coreId 32 at
5323 118352443935245 at sf=0 with queue 0 successfully
5325 BBU Pooling Info: bbupool rt thread start on CoreIdx 4 coreId 8 at
5326 118352443936745 at sf=0 with queue 0 successfully
5328 BBU Pooling Info: bbupool rt thread start on CoreIdx 6 coreId 10 at
5329 118352443936883 at sf=0 with queue 0 successfully
5331 BBU Pooling Info: bbupool rt thread start on CoreIdx 3 coreId 7 at
5332 118352443936747 at sf=0 with queue 0 successfully
5334 BBU Pooling Info: bbupool rt thread start on CoreIdx 12 coreId 31 at
5335 118352443938019 at sf=0 with queue 0 successfully
5337 BBU Pooling Info: bbupool rt thread start on CoreIdx 5 coreId 9 at
5338 118352443939937 at sf=0 with queue 0 successfully
5340 BBU Pooling Info: bbupool rt thread start on CoreIdx 9 coreId 28 at
5341 118352443941217 at sf=0 with queue 0 successfully
5343 BBU Pooling Info: bbupool rt thread start on CoreIdx 16 coreId 35 at
5344 118352443944465 at sf=0 with queue 0 successfully
5346 BBU Pooling Info: bbupool rt thread start on CoreIdx 17 coreId 36 at
5347 118352443937701 at sf=0 with queue 0 successfully
5349 BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 4 at
5350 118352443926969 at sf=0 with queue 0 successfully
5352 BBU Pooling Info: bbupool rt thread start on CoreIdx 10 coreId 29 at
5353 118352443928691 at sf=0 with queue 0 successfully
5355 BBU Pooling Info: bbupool rt thread start on CoreIdx 7 coreId 11 at
5356 118352443931713 at sf=0 with queue 0 successfully
5358 phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5]
5361 ==== l1app Time: 5002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [
5362 0.00.. 0.00.. 0.00] usces
5364 ==== [o-du0][rx 3807776 pps 761555 kbps 4744396][tx 10937607 pps 2187521
5365 kbps 26031486] [on_time 3807776 early 0 late 0 corrupt 0 pkt_dupl 144
5368 Pusch[ 439372 439372 439372 439372 439372 439372 439372 439372] SRS[
5371 ==== [o-du1][rx 1469469 pps 293893 kbps 2684928][tx 3649817 pps 729963
5372 kbps 9156812] [on_time 1469469 early 0 late 0 corrupt 0 pkt_dupl 144
5375 Pusch[ 146964 146956 146964 146956 146964 146956 146964 146956] SRS[
5378 ==== [o-du2][rx 1469463 pps 293892 kbps 2684960][tx 3648883 pps 729776
5379 kbps 9152795] [on_time 1469463 early 0 late 0 corrupt 0 pkt_dupl 144
5382 Pusch[ 146956 146956 146956 146956 146956 146956 146956 146956] SRS[
5385 -------------------------------------------------------------------------------------------------------------------------------------------------------
5387 Cell DL Tput UL Tput UL BLER
5389 0 (Kbps) 0 0 / 0 0.00%
5391 1 (Kbps) 0 0 / 0 0.00%
5393 2 (Kbps) 0 0 / 0 0.00%
5395 -------------------------------------------------------------------------------------------------------------------------------------------------------
5397 Core Utilization [18 BBU core(s)]:
5399 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5401 Util %: 0 4 2 4 4 2 3 13 17 0 13 15 14 16 14 17 15 14 9.28
5403 Xran Id: 22 23 24 25 Master Core Util: 85 %
5405 -------------------------------------------------------------------------------------------------------------------------------------------------------
5407 ==== l1app Time: 10002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [
5408 0.00.. 0.00.. 0.00] usces
5410 ==== [o-du0][rx 5472406 pps 332926 kbps 4744396][tx 21871698 pps 2186818
5411 kbps 26038405] [on_time 5472406 early 0 late 0 corrupt 0 pkt_dupl 144
5414 Pusch[ 192084 192078 192078 192078 192078 192078 192078 192078] SRS[
5417 ==== [o-du1][rx 2109680 pps 128042 kbps 2684917][tx 7297930 pps 729622
5418 kbps 9156922] [on_time 2109680 early 0 late 0 corrupt 0 pkt_dupl 144
5421 Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128004]
5423 ==== [o-du2][rx 2109682 pps 128043 kbps 2684993][tx 7296833 pps 729590
5424 kbps 9156258] [on_time 2109682 early 0 late 0 corrupt 0 pkt_dupl 144
5427 Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128011]
5429 -------------------------------------------------------------------------------------------------------------------------------------------------------
5431 Cell DL Tput UL Tput UL BLER
5433 0 (Kbps) 6,894,368 576,420 / 576,492 0.00%
5435 1 (Kbps) 0 0 / 0 0.00%
5437 2 (Kbps) 0 0 / 0 0.00%
5439 -------------------------------------------------------------------------------------------------------------------------------------------------------
5441 Core Utilization [18 BBU core(s)]:
5443 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5445 Util %: 15 30 34 29 26 28 26 46 50 0 40 40 43 42 44 42 48 50 35.17
5447 Xran Id: 22 23 24 25 Master Core Util: 95 %
5449 -------------------------------------------------------------------------------------------------------------------------------------------------------
5451 ==== l1app Time: 15003 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [
5452 0.00.. 0.00.. 0.00] usces
5454 ==== [o-du0][rx 7136544 pps 332827 kbps 4744396][tx 32806663 pps 2186993
5455 kbps 26042173] [on_time 7136544 early 0 late 0 corrupt 0 pkt_dupl 144
5458 Pusch[ 192012 192018 192018 192018 192018 192018 192018 192018] SRS[
5461 ==== [o-du1][rx 2749728 pps 128009 kbps 2684895][tx 10945622 pps 729538
5462 kbps 9155645] [on_time 2749728 early 0 late 0 corrupt 0 pkt_dupl 144
5465 Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000]
5467 ==== [o-du2][rx 2749730 pps 128009 kbps 2684840][tx 10944272 pps 729487
5468 kbps 9154660] [on_time 2749730 early 0 late 0 corrupt 0 pkt_dupl 144
5471 Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000]
5473 -------------------------------------------------------------------------------------------------------------------------------------------------------
5475 Cell DL Tput UL Tput UL BLER
5477 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%
5479 1 (Kbps) 539,740 65,260 / 65,260 0.00%
5481 2 (Kbps) 0 0 / 0 0.00%
5483 -------------------------------------------------------------------------------------------------------------------------------------------------------
5485 Core Utilization [18 BBU core(s)]:
5487 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5489 Util %: 27 33 40 38 38 35 34 56 56 26 50 47 48 47 51 48 57 57 43.78
5491 Xran Id: 22 23 24 25 Master Core Util: 95 %
5493 -------------------------------------------------------------------------------------------------------------------------------------------------------
5495 Setting MLogMask because nMLogDelay == 0
5497 ==== l1app Time: 20002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5498 [480.00..500.23..516.00] usces
5500 ==== [o-du0][rx 8799776 pps 332646 kbps 4744396][tx 43740623 pps 2186792
5501 kbps 26042944] [on_time 8799776 early 0 late 0 corrupt 0 pkt_dupl 144
5504 Pusch[ 191904 191904 191904 191904 191904 191904 191904 191904] SRS[
5507 ==== [o-du1][rx 3389472 pps 127948 kbps 2684982][tx 14591619 pps 729199
5508 kbps 9154093] [on_time 3389472 early 0 late 0 corrupt 0 pkt_dupl 144
5511 Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000]
5513 ==== [o-du2][rx 3389474 pps 127948 kbps 2684873][tx 14589997 pps 729145
5514 kbps 9152608] [on_time 3389474 early 0 late 0 corrupt 0 pkt_dupl 144
5517 Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000]
5519 -------------------------------------------------------------------------------------------------------------------------------------------------------
5521 Cell DL Tput UL Tput UL BLER
5523 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%
5525 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5527 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5529 -------------------------------------------------------------------------------------------------------------------------------------------------------
5531 Core Utilization [18 BBU core(s)]:
5533 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5535 Util %: 43 47 46 43 42 43 41 61 60 27 57 56 58 57 55 56 64 62 51.00
5537 Xran Id: 22 23 24 25 Master Core Util: 96 %
5539 -------------------------------------------------------------------------------------------------------------------------------------------------------
5541 ==== l1app Time: 25002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5542 [442.00..500.12..562.00] usces
5544 ==== [o-du0][rx 10463824 pps 332809 kbps 4744396][tx 54675513 pps
5545 2186978 kbps 26044150] [on_time 10463824 early 0 late 0 corrupt 0
5546 pkt_dupl 144 Total 10463824]
5548 Pusch[ 192006 192006 192006 192006 192006 192006 192006 192006] SRS[
5551 ==== [o-du1][rx 4029487 pps 128003 kbps 2684928][tx 18237287 pps 729133
5552 kbps 9150163] [on_time 4029487 early 0 late 0 corrupt 0 pkt_dupl 144
5555 Pusch[ 64002 64002 64002 64002 64002 64002 64002 64001] SRS[ 128000]
5557 ==== [o-du2][rx 4029474 pps 128000 kbps 2684873][tx 18235338 pps 729068
5558 kbps 9148513] [on_time 4029474 early 0 late 0 corrupt 0 pkt_dupl 144
5561 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]
5563 -------------------------------------------------------------------------------------------------------------------------------------------------------
5565 Cell DL Tput UL Tput UL BLER
5567 0 (Kbps) 6,896,256 576,492 / 576,492 0.00%
5569 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5571 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5573 -------------------------------------------------------------------------------------------------------------------------------------------------------
5575 Core Utilization [18 BBU core(s)]:
5577 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5579 Util %: 44 48 46 46 44 41 43 62 61 27 58 59 55 56 56 58 61 62 51.50
5581 Xran Id: 22 23 24 25 Master Core Util: 95 %
5583 -------------------------------------------------------------------------------------------------------------------------------------------------------
5585 ==== l1app Time: 30002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5586 [435.00..500.12..562.00] usces
5588 ==== [o-du0][rx 12127888 pps 332812 kbps 4744396][tx 65610457 pps
5589 2186988 kbps 26044065] [on_time 12127888 early 0 late 0 corrupt 0
5590 pkt_dupl 144 Total 12127888]
5592 Pusch[ 192012 192006 192012 192006 192010 192006 192006 192006] SRS[
5595 ==== [o-du1][rx 4669504 pps 128003 kbps 2685058][tx 21883550 pps 729252
5596 kbps 9152750] [on_time 4669504 early 0 late 0 corrupt 0 pkt_dupl 144
5599 Pusch[ 64002 64002 64002 64002 64002 64002 64002 64003] SRS[ 128000]
5601 ==== [o-du2][rx 4669498 pps 128004 kbps 2684993][tx 21881293 pps 729191
5602 kbps 9151846] [on_time 4669498 early 0 late 0 corrupt 0 pkt_dupl 144
5605 Pusch[ 64004 64004 64004 64004 64002 64002 64002 64002] SRS[ 128000]
5607 -------------------------------------------------------------------------------------------------------------------------------------------------------
5609 Cell DL Tput UL Tput UL BLER
5611 0 (Kbps) 6,896,256 577,069 / 577,069 0.00%
5613 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5615 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5617 -------------------------------------------------------------------------------------------------------------------------------------------------------
5619 Core Utilization [18 BBU core(s)]:
5621 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5623 Util %: 44 47 45 47 43 43 42 63 63 27 56 56 56 55 58 55 65 62 51.50
5625 Xran Id: 22 23 24 25 Master Core Util: 95 %
5627 -------------------------------------------------------------------------------------------------------------------------------------------------------
5629 ==== l1app Time: 35002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5630 [434.00..500.12..554.00] usces
5632 ==== [o-du0][rx 13792256 pps 332873 kbps 4744892][tx 76545521 pps
5633 2187012 kbps 26042901] [on_time 13792256 early 0 late 0 corrupt 0
5634 pkt_dupl 144 Total 13792256]
5636 Pusch[ 192042 192048 192042 192048 192044 192048 192048 192048] SRS[
5639 ==== [o-du1][rx 5309632 pps 128025 kbps 2685102][tx 25528867 pps 729063
5640 kbps 9151639] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144
5643 Pusch[ 64016 64016 64016 64016 64016 64016 64016 64016] SRS[ 128000]
5645 ==== [o-du2][rx 5309632 pps 128026 kbps 2685102][tx 25526238 pps 728989
5646 kbps 9150147] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144
5649 Pusch[ 64016 64016 64016 64016 64018 64018 64017 64017] SRS[ 128000]
5651 -------------------------------------------------------------------------------------------------------------------------------------------------------
5653 Cell DL Tput UL Tput UL BLER
5655 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%
5657 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5659 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5661 -------------------------------------------------------------------------------------------------------------------------------------------------------
5663 Core Utilization [18 BBU core(s)]:
5665 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5667 Util %: 43 48 45 47 43 41 42 66 61 27 57 57 55 56 57 56 64 62 51.50
5669 Xran Id: 22 23 24 25 Master Core Util: 95 %
5671 -------------------------------------------------------------------------------------------------------------------------------------------------------
5673 ==== l1app Time: 40002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5674 [440.00..500.12..553.00] usces
5676 ==== [o-du0][rx 15455740 pps 332696 kbps 4744396][tx 87479892 pps
5677 2186874 kbps 26042995] [on_time 15455740 early 0 late 0 corrupt 0
5678 pkt_dupl 144 Total 15455740]
5680 Pusch[ 191940 191940 191940 191940 191940 191940 191940 191940] SRS[
5683 ==== [o-du1][rx 5949408 pps 127955 kbps 2684764][tx 29174424 pps 729111
5684 kbps 9150009] [on_time 5949408 early 0 late 0 corrupt 0 pkt_dupl 144
5687 Pusch[ 63980 63980 63980 63980 63980 63980 63980 63980] SRS[ 127936]
5689 ==== [o-du2][rx 5949410 pps 127955 kbps 2684840][tx 29171380 pps 729028
5690 kbps 9148386] [on_time 5949410 early 0 late 0 corrupt 0 pkt_dupl 144
5693 Pusch[ 63980 63980 63980 63980 63980 63980 63981 63981] SRS[ 127936]
5695 -------------------------------------------------------------------------------------------------------------------------------------------------------
5697 Cell DL Tput UL Tput UL BLER
5699 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%
5701 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5703 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5705 -------------------------------------------------------------------------------------------------------------------------------------------------------
5707 Core Utilization [18 BBU core(s)]:
5709 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5711 Util %: 44 48 44 45 42 42 43 63 63 27 57 56 55 58 56 56 64 62 51.39
5713 Xran Id: 22 23 24 25 Master Core Util: 95 %
5715 -------------------------------------------------------------------------------------------------------------------------------------------------------
5717 ==== l1app Time: 45002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5718 [436.00..500.12..556.00] usces
5720 ==== [o-du0][rx 17119776 pps 332807 kbps 4743900][tx 98415119 pps
5721 2187045 kbps 26043843] [on_time 17119776 early 0 late 0 corrupt 0
5722 pkt_dupl 144 Total 17119776]
5724 Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[
5727 ==== [o-du1][rx 6589472 pps 128012 kbps 2684753][tx 32820214 pps 729158
5728 kbps 9154170] [on_time 6589472 early 0 late 0 corrupt 0 pkt_dupl 144
5731 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064]
5733 ==== [o-du2][rx 6589474 pps 128012 kbps 2684753][tx 32816780 pps 729080
5734 kbps 9152613] [on_time 6589474 early 0 late 0 corrupt 0 pkt_dupl 144
5737 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064]
5739 -------------------------------------------------------------------------------------------------------------------------------------------------------
5741 Cell DL Tput UL Tput UL BLER
5743 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%
5745 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5747 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5749 -------------------------------------------------------------------------------------------------------------------------------------------------------
5751 Core Utilization [18 BBU core(s)]:
5753 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5755 Util %: 44 47 46 47 43 42 42 61 63 27 56 58 56 56 58 57 63 65 51.72
5757 Xran Id: 22 23 24 25 Master Core Util: 95 %
5759 -------------------------------------------------------------------------------------------------------------------------------------------------------
5761 ==== l1app Time: 50002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time:
5762 [436.00..500.12..551.00] usces
5764 ==== [o-du0][rx 18783776 pps 332800 kbps 4744396][tx 109350065 pps
5765 2186989 kbps 26043142] [on_time 18783776 early 0 late 0 corrupt 0
5766 pkt_dupl 144 Total 18783776]
5768 Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[
5771 ==== [o-du1][rx 7229472 pps 128000 kbps 2684928][tx 36466505 pps 729258
5772 kbps 18302595] [on_time 7229472 early 0 late 0 corrupt 0 pkt_dupl 144
5775 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]
5777 ==== [o-du2][rx 7229474 pps 128000 kbps 2684895][tx 36462749 pps 729193
5778 kbps 9148265] [on_time 7229474 early 0 late 0 corrupt 0 pkt_dupl 144
5781 Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]
5783 -------------------------------------------------------------------------------------------------------------------------------------------------------
5785 Cell DL Tput UL Tput UL BLER
5787 0 (Kbps) 6,896,256 576,492 / 576,492 0.00%
5789 1 (Kbps) 539,814 65,260 / 65,260 0.00%
5791 2 (Kbps) 539,814 65,260 / 65,260 0.00%
5793 -------------------------------------------------------------------------------------------------------------------------------------------------------
5795 Core Utilization [18 BBU core(s)]:
5797 Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg
5799 Util %: 43 47 45 47 43 41 41 62 63 27 57 55 57 56 55 57 62 66 51.33
5801 Xran Id: 22 23 24 25 Master Core Util: 95 %
5803 -------------------------------------------------------------------------------------------------------------------------------------------------------
5805 7.To execute testmac with O-DU functionality according to O-RAN
5806 Fronthaul specification, enter::
5808 [root@xran flexran] cd ./bin/nr5g/gnb/testmac
5810 8.To execute test case type::
5812 --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
5814 where output corresponding to Test MAC::
5816 [root@icelake-scs1-1 testmac]# ./l2.sh
5817 --testfile=./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
5819 kernel.sched_rt_runtime_us = -1
5821 kernel.shmmax = 2147483648
5823 kernel.shmall = 2147483648
5825 Note: Forwarding request to 'systemctl disable irqbalance.service'.
5829 =========================
5831 5GNR Testmac Application
5833 =========================
5835 testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command
5836 line. Using default File: testmac_cfg.xml
5838 ---------------------------
5840 TestMacCfg.xml Version: 20.08
5842 ---------------------------
5848 --wlsMemorySize=0x3F600000
5866 --wlsRxThread=1, 90, 0
5868 --systemThread=0, 0, 0
5870 --runThread=0, 89, 0
5872 --urllcThread=16, 90, 0
5874 wls_dev_filename: wls0
5876 sys_reg_signal_handler:[err] signal handler in NULL
5878 sys_reg_signal_handler:[err] signal handler in NULL
5880 timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution
5885 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3),
5886 mlogSize(2048) mlog_mask (-1)
5888 mlogSubframes (128), mlogCores(3), mlogSize(2048)
5892 System clock (rdtsc) resolution 1496526140 [Hz]
5896 MLog Storage: 0x7f821905d100 -> 0x7f821911d920 [ 788512 bytes ]
5898 localMLogFreqReg: 1496. Storing: 1496
5900 Mlog Open successful
5902 Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0
5905 EAL: Detected 48 lcore(s)
5907 EAL: Detected 1 NUMA nodes
5909 EAL: Auto-detected process type: SECONDARY
5911 EAL: Multi-process socket
5912 /var/run/dpdk/wls0/mp_socket_29473_6b9e031eaf8b
5914 EAL: Selected IOVA mode 'PA'
5916 EAL: Probing VFIO support...
5918 EAL: PCI device 0000:01:00.0 on NUMA socket 0
5920 EAL: probe driver: 8086:1533 net_e1000_igb
5922 EAL: PCI device 0000:18:00.0 on NUMA socket 0
5924 EAL: probe driver: 8086:1563 net_ixgbe
5926 EAL: PCI device 0000:18:00.1 on NUMA socket 0
5928 EAL: probe driver: 8086:1563 net_ixgbe
5930 EAL: PCI device 0000:8c:00.0 on NUMA socket 0
5932 EAL: probe driver: 8086:d58 net_i40e
5934 EAL: PCI device 0000:8c:00.1 on NUMA socket 0
5936 EAL: probe driver: 8086:d58 net_i40e
5938 EAL: PCI device 0000:90:00.0 on NUMA socket 0
5940 EAL: probe driver: 8086:d58 net_i40e
5942 EAL: PCI device 0000:90:00.1 on NUMA socket 0
5944 EAL: probe driver: 8086:d58 net_i40e
5946 wls_lib: Open wls0 (DPDK memzone)
5948 wls_lib: WLS_Open 0x43f600000
5950 wls_lib: link: 1 <-> 0
5954 wls_lib: WLS shared management memzone: wls0
5956 wls_lib: hugePageSize on the system is 1073741824
5958 wls_lib: WLS_Alloc [1063256064] bytes
5960 wls_lib: Connecting to remote peer ...
5962 wls_lib: Connected to remote peer
5964 wls_mac_create_mem_array: pMemArray[0xf354350]
5965 pMemArrayMemory[0x400000000] totalSize[1063256064] nBlockSize[262144]
5968 WLS_EnqueueBlock [1]
5972 ===========================================================================================================
5976 ===========================================================================================================
5978 $Version: #DIRTY# $ (x86)
5980 IMG-date: Aug 5 2020
5984 ===========================================================================================================
5986 ===========================================================================================================
5988 Testmac threads in application
5990 ===========================================================================================================
5992 testmac_run_thread: [PID: 29477] binding on [CPU 0] [PRIO: 89] [POLICY:
5995 wls_mac_rx_task: [PID: 29476] binding on [CPU 1] [PRIO: 90] [POLICY: 1]
5997 ===========================================================================================================
5999 testmac_set_phy_start: mode[1], period[40], count[0]
6001 testmac_run_load_files:
6003 Loading DL Config Files:
6005 testmac_run_parse_file Parsing config file:
6006 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg
6008 testmac_run_parse_file Parsing config file:
6009 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg
6011 testmac_run_parse_file Parsing config file:
6012 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg
6014 testmac_run_parse_file Parsing config file:
6015 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg
6017 testmac_run_parse_file Parsing config file:
6018 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg
6020 Loading UL Config Files:
6022 testmac_run_parse_file Parsing config file:
6023 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg
6025 testmac_run_parse_file Parsing config file:
6026 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg
6028 testmac_run_parse_file Parsing config file:
6029 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg
6031 testmac_run_parse_file Parsing config file:
6032 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_10mhz.cfg
6034 testmac_run_parse_file Parsing config file:
6035 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_20mhz.cfg
6037 testmac_run_parse_file Parsing config file:
6038 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_40mhz.cfg
6040 testmac_run_parse_file Parsing config file:
6041 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg
6043 testmac_run_parse_file Parsing config file:
6044 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg
6046 Loading FD Config Files:
6048 testmac_run_parse_file Parsing config file:
6049 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg
6051 testmac_run_parse_file Parsing config file:
6052 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg
6054 testmac_run_parse_file Parsing config file:
6055 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg
6057 testmac_run_parse_file Parsing config file:
6058 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg
6060 testmac_run_parse_file Parsing config file:
6061 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg
6063 testmac_run_parse_file Parsing config file:
6064 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg
6068 Numerology[0] Bandwidth[5]
6070 1001 1002 1003 1004 1005 1006 1007 1008
6072 Numerology[0] Bandwidth[10]
6074 1001 1002 1003 1004 1005 1006 1007 1008
6076 Numerology[0] Bandwidth[20]
6078 1001 1002 1003 1004 1005 1006 1007 1008
6080 Numerology[1] Bandwidth[100]
6082 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211
6084 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
6086 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241
6088 1242 1243 1244 1245 1250 1251 1252 1260 1261 1262
6090 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
6092 1300 1301 1302 1303 1304 1305 1402 1404 1408 1416
6094 1500 1501 1502 1503 1504 1505 1506 2213 2214 2215
6096 2217 2218 2219 2223 2224 2225 2227 2228 2229 2500
6098 2501 2502 2503 2504 3213 3214 3215 3217 3218 3219
6100 3223 3224 3225 3227 3228 3229
6102 Numerology[3] Bandwidth[100]
6104 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011
6106 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031
6108 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003
6114 Numerology[0] Bandwidth[5]
6116 1001 1002 1003 1069 1070 1071 1072 1073 1074 1075
6120 Numerology[0] Bandwidth[10]
6122 1001 1002 1069 1070 1071 1072 1073 1074 1075 1076
6126 Numerology[0] Bandwidth[20]
6128 1001 1002 1003 1004 1005 1006 1007 1008 1069 1070
6130 1071 1072 1073 1074 1075 1076 1077
6132 Numerology[1] Bandwidth[10]
6134 1069 1070 1071 1072 1073 1074 1075 1076 1077
6136 Numerology[1] Bandwidth[20]
6138 1069 1070 1071 1072 1073 1074 1075 1076 1077
6140 Numerology[1] Bandwidth[40]
6142 1069 1070 1071 1072 1073 1074 1075 1076 1077
6144 Numerology[1] Bandwidth[100]
6146 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038
6148 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074
6150 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092
6152 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105
6154 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117
6156 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132
6158 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
6160 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160
6162 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
6164 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206
6166 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216
6168 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233
6170 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421
6172 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
6174 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504
6176 1505 1506 1507 1508 1512 1513 1514 1515 1516 1540
6178 1541 1542 1563 1564 1565 1566 1567 1568 1569 1570
6180 1571 1572 1573 1574 1575 1576 1577 1600 1601 1602
6182 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612
6184 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622
6186 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632
6188 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
6190 1700 1701 1702 1969 1970 1971 1972 1973 1974 1975
6192 1976 1977 2236 2237 3236 3237
6194 Numerology[3] Bandwidth[100]
6196 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012
6198 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026
6200 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
6202 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051
6204 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065
6206 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084
6208 1085 1086 2001 2002 2003 3001 3002 3003
6212 Numerology[0] Bandwidth[5]
6214 1001 6001 8001 10001 12001
6216 Numerology[0] Bandwidth[10]
6218 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002
6220 6002 8002 10002 12002 1003
6222 Numerology[0] Bandwidth[20]
6224 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021
6226 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201
6228 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221
6230 1222 1223 1224 1225 1226 1227 1228
6232 Numerology[1] Bandwidth[40]
6236 Numerology[1] Bandwidth[100]
6238 1001 1002 1200 1201 1202 1203 1204 1205 1206 1207
6240 1208 1209 1210 1300 1301 1302 1303 1304 1305 1306
6242 1307 1308 1350 1351 1352 1353 1354 1355 1356 1357
6244 1358 1359 1370 1371 1372 1373 1374 1375 1376 1377
6246 1378 1401 1402 1403 1404 1405 1406 1411 1412 1490
6248 1494 1500 1501 1502 1503 1504 1510 1511 1512 1513
6250 1514 1515 1520 1521 1522 1523 1524 1525 1526 1527
6252 1528 1529 1530 1531 1532 1540 1541 1700 1701 1702
6254 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529
6256 2530 2531 2532 3524 3525 3526 3527 3528 3529 3530
6258 3531 3532 4524 4525 4526 4527 4528 4529 4530 4531
6262 Numerology[3] Bandwidth[100]
6264 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011
6266 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080
6270 testmac_run_parse_file Parsing config file:
6271 ./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
6273 testmac_set_phy_start: mode[4], period[0], count[100200]
6275 Adding setoption pdsch_split [numTests: 0] [nCellMask: 0x00000001]
6276 [nOption: 4] [pMacOptions: 260 / 0x00000104]
6278 Adding setoption pdsch_dl_weight_split [numTests: 0] [nCellMask:
6279 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]
6281 Adding setoption pusch_chan_est_split [numTests: 0] [nCellMask:
6282 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]
6284 Adding setoption pusch_mmse_split [numTests: 0] [nCellMask: 0x00000001]
6285 [nOption: 4] [pMacOptions: 260 / 0x00000104]
6287 Adding setoption pusch_llr_rx_split [numTests: 0] [nCellMask:
6288 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]
6290 Adding setoption pusch_ul_weight_split [numTests: 0] [nCellMask:
6291 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]
6293 Adding setoption timer_multi_cell [numTests: 0] [nCellMask: 0xffffffff]
6294 [nOption: 10000] [pMacOptions: 10000 / 0x00002710]
6296 Adding setoption fec_dec_num_iter [numTests: 0] [nCellMask: 0xffffffff]
6297 [nOption: 3] [pMacOptions: -253 / 0xffffff03]
6299 Adding SetCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[137170526192 /
6302 Adding SetDlbeamCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[2016 /
6305 Adding SetSrsCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[268435472 /
6308 Setting Testmac System Core: 2
6310 Setting Testmac Run Core: 2
6312 Setting Testmac Wls Core: 3
6314 Adding Test[3370]. NumCarr[3], Current Directory:
6315 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/
6317 Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg
6319 Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
6321 Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
6323 testmac_set_multi_cell_timer: 10000
6325 ----------------------------------------------------------------------------------------
6327 Running Test[3370]. NumCarr[3], Current Directory:
6328 /home/vzakharc/master/../master_aux/flexran_l1_5g_test/
6330 Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg
6332 Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
6334 Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
6336 TESTMAC>welcome to application console
6340 MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3),
6341 mlogSize(2048) mlog_mask (-1)
6343 mlogSubframes (128), mlogCores(3), mlogSize(2048)
6347 System clock (rdtsc) resolution 1496525908 [Hz]
6351 MLog Storage: 0x7f8208000900 -> 0x7f82080c1120 [ 788512 bytes ]
6353 localMLogFreqReg: 1496. Storing: 1496
6355 Mlog Open successful
6357 testmac_mac2phy_set_num_cells: Setting Max Cells: 3
6359 testmac_config_parse: test_num[3370] test_type[2] numcarrier[3]
6361 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0)
6363 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(1)
6365 Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(2)
6367 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0)
6369 Queueing MSG_TYPE_PHY_CONFIG_REQ(0)
6371 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(1)
6373 Queueing MSG_TYPE_PHY_CONFIG_REQ(1)
6375 Received MSG_TYPE_PHY_UL_IQ_SAMPLES(2)
6377 Queueing MSG_TYPE_PHY_CONFIG_REQ(2) and sending list
6379 Received MSG_TYPE_PHY_CONFIG_RESP(0)
6381 Queueing MSG_TYPE_PHY_START_REQ(0)
6383 Received MSG_TYPE_PHY_CONFIG_RESP(1)
6385 Queueing MSG_TYPE_PHY_START_REQ(1)
6387 Received MSG_TYPE_PHY_CONFIG_RESP(2)
6389 Queueing MSG_TYPE_PHY_START_REQ(2) and sending list
6391 Received MSG_TYPE_PHY_START_RESP(0)
6393 Received MSG_TYPE_PHY_START_RESP(1)
6395 Received MSG_TYPE_PHY_START_RESP(2)
6397 ==== testmac Time: 5000 ms NumCarrier: 3 Total Proc Time: [ 0.00..
6398 6.30.. 19.00] usces====
6400 Core Utilization [Core: 3] [Util %: 0.42%]
6402 ==== testmac Time: 10000 ms NumCarrier: 3 Total Proc Time: [
6403 6.00..116.80..206.00] usces====
6405 Core Utilization [Core: 3] [Util %: 27.86%]
6407 ==== testmac Time: 20000 ms NumCarrier: 3 Total Proc Time: [
6408 10.00..156.33..260.00] usces====
6410 Core Utilization [Core: 3] [Util %: 32.31%]
6412 ==== testmac Time: 25000 ms NumCarrier: 3 Total Proc Time: [
6413 11.00..156.33..260.00] usces====
6415 Core Utilization [Core: 3] [Util %: 32.30%]
6417 ==== testmac Time: 30000 ms NumCarrier: 3 Total Proc Time: [
6418 11.00..156.44..256.00] usces====
6420 Core Utilization [Core: 3] [Util %: 32.32%]
6422 ==== testmac Time: 35000 ms NumCarrier: 3 Total Proc Time: [
6423 11.00..156.42..258.00] usces====
6425 Core Utilization [Core: 3] [Util %: 32.32%]
6427 ==== testmac Time: 40000 ms NumCarrier: 3 Total Proc Time: [
6428 11.00..156.45..258.00] usces====
6430 Core Utilization [Core: 3] [Util %: 32.33%]
6432 ==== testmac Time: 45000 ms NumCarrier: 3 Total Proc Time: [
6433 11.00..156.40..282.00] usces====
6435 Core Utilization [Core: 3] [Util %: 32.32%]
6437 TESTMAC>==== testmac Time: 50000 ms NumCarrier: 3 Total Proc Time: [
6438 11.00..156.39..260.00] usces====
6440 Core Utilization [Core: 3] [Util %: 32.31%]
6442 Received MSG_TYPE_PHY_STOP_RESP(0)
6444 Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(0)
6446 Received MSG_TYPE_PHY_STOP_RESP(1)
6448 Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(1)
6450 Received MSG_TYPE_PHY_STOP_RESP(2)
6452 Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(2) and sending list
6454 Received MSG_TYPE_PHY_SHUTDOWN_RESP(2)
6456 Received MSG_TYPE_PHY_SHUTDOWN_RESP(0)
6458 Received MSG_TYPE_PHY_SHUTDOWN_RESP(1)
6460 MLogPrint: ext_filename((null).bin)
6462 Opening MLog File: testmac-mlog-c0.bin
6464 MLog file testmac-mlog-c0.bin closed
6466 Mlog Print successful
6468 Test[FD_mu1_100mhz_3370] Completed
6470 wls_mac_free_list_all:
6472 nTotalBlocks[4056] nAllocBlocks[1010] nFreeBlocks[3046]
6474 nTotalAllocCnt[4538427] nTotalFreeCnt[4537417] Diff[1010]
6476 nDlBufAllocCnt[3609068] nDlBufFreeCnt[3609068] Diff[0]
6478 nUlBufAllocCnt[929359] nUlBufFreeCnt[928349] Diff[1010]
6480 All Tests Completed, Total run 1 Tests, PASS 1 Tests, and FAIL 0 Tests
Code Review / o-du / phy.git / blob