+struct xran_ethdi_ctx {
+ struct xran_io_cfg io_cfg;
+ struct rte_ether_addr entities[XRAN_VF_MAX][ID_MAX];
+ uint16_t vf2xran_port[XRAN_VF_MAX];
+ uint16_t vf_and_q2pc_id[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX];
+ struct xran_eaxc_info vf_and_q2cid[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX];
+ uint16_t rxq_per_port[XRAN_VF_MAX];
+
+ struct rte_ring *tx_ring[XRAN_VF_MAX];
+ struct rte_ring *rx_ring[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX];
+
+ struct rte_ring *up_dl_pkt_gen_ring[XRAN_PORTS_NUM];
+
+ struct xran_worker_config time_wrk_cfg; /**< core doing polling of time */
+ struct xran_worker_config pkt_wrk_cfg[RTE_MAX_LCORE]; /**< worker cores */
+
+ phy_encoder_poll_fn bbdev_enc; /**< call back to poll BBDev encoder */
+ phy_decoder_poll_fn bbdev_dec; /**< call back to poll BBDev decoder */
+
+ uint32_t pkt_proc_core_id; /**< core used for processing DPDK timer cb */
+ uint32_t num_workers; /**< number of workers */
+ uint32_t worker_core[XRAN_MAX_WORKERS]; /**< id of core used as worker */
+
+ uint64_t rx_vf_queue_cnt[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX];
+};
+
+enum xran_mbuf_mem_op_id {