-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF\r
-ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app\r
-\r
-numSlots=10 #number of slots per IQ files\r
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0\r
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0\r
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0\r
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0\r
-antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1\r
-antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1\r
-antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1\r
-antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1\r
-antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2\r
-antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2\r
-antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2\r
-antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2\r
-antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3\r
-antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3\r
-antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3\r
-antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3\r
-\r
-antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0\r
-antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0\r
-antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0\r
-antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0\r
-antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1\r
-antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1\r
-antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1\r
-antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1\r
-antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2\r
-antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2\r
-antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2\r
-antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2\r
-antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3\r
-antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3\r
-antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3\r
-antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3\r
-\r
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration\r
-prachConfigIndex=189\r
-\r
-srsEanble=1 # Enable (1)| disable (0) SRS \r
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)\r
-\r
-antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin \r
-antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin \r
-antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin \r
-antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin \r
-antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin \r
-antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin \r
-antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin \r
-antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin \r
-\r
-#DL PRB / % Used RBs UL PRB / % Used RBs\r
-#33% 90 33% 90\r
-\r
-###########################################################\r
-##Section Settings\r
-DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used \r
-\r
-nPrbElemDl=4\r
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType\r
-# weight base beams \r
-PrbElemDl0=0,48,0,14,1,1,1,9,1\r
-PrbElemDl1=48,48,0,14,2,1,1,9,1\r
-PrbElemDl2=96,48,0,14,3,1,1,9,1\r
-PrbElemDl3=144,48,0,14,4,1,1,9,1\r
-\r
-nPrbElemUl=2\r
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType\r
-# weight base beams \r
-PrbElemUl0=0,48,0,14,1,1,1,9,1\r
-PrbElemUl1=48,48,0,14,2,1,1,9,1\r
-\r
-###########################################################\r
-\r
-## control of IQ byte order\r
-iqswap=0 #do swap of IQ before send buffer to eth\r
-nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order\r
-compression=1 # (1) compression enabled (0) compression disabled\r
-\r
-##Debug\r
-debugStop=1 #stop app on 1pps boundary (gps_second % 30)\r
-debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary\r
-bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode\r
-\r
-CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled\r
-\r
-##O-RU Settings\r
-totalBFWeights=32 # Total number of Beamforming Weights on RU\r
-\r
-Tadv_cp_dl=25 # in us\r
- # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages\r
-#Reception Window C-plane DL\r
-T2a_min_cp_dl=285 # 285.42us\r
-T2a_max_cp_dl=429 # 428.12us\r
-\r
-#Reception Window C-plane UL\r
-T2a_min_cp_ul=285 # 285.42us\r
-T2a_max_cp_ul=429 # 428.12us\r
-\r
-#Reception Window U-plane\r
-T2a_min_up=71 # 71.35in us\r
-T2a_max_up=428 # 428.12us\r
-\r
-#Transmission Window\r
-Ta3_min=20 # in us \r
-Ta3_max=32 # in us \r
-\r
-###########################################################\r
-##O-DU Settings\r
-#C-plane\r
-#Transmission Window Fast C-plane DL\r
-T1a_min_cp_dl=285\r
-T1a_max_cp_dl=429\r
-\r
-##Transmission Window Fast C-plane UL\r
-T1a_min_cp_ul=285\r
-T1a_max_cp_ul=300\r
-\r
-#U-plane\r
-##Transmission Window\r
-T1a_min_up=96 #71 + 25 us\r
-T1a_max_up=196 #71 + 25 us\r
-\r
-#Reception Window\r
-Ta4_min=0 # in us \r
-Ta4_max=75 # in us \r
-###########################################################\r
-\r
+llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+numSlots=10 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
+antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
+antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
+antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0
+antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1
+antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1
+antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1
+antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1
+antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2
+antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2
+antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2
+antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2
+antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3
+antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
+antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
+antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
+
+rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+prachConfigIndex=189
+
+srsEanble=1 # Enable (1)| disable (0) SRS
+srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+
+antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin
+antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin
+antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin
+antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin
+antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin
+antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin
+antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin
+antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin
+antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin
+
+#DL PRB / % Used RBs UL PRB / % Used RBs
+#33% 90 33% 90
+
+###########################################################
+##Section Settings
+DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
+
+nPrbElemDl=4
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemDl0=0,48,0,14,1,1,1,9,1
+PrbElemDl1=48,48,0,14,2,1,1,9,1
+PrbElemDl2=96,48,0,14,3,1,1,9,1
+PrbElemDl3=144,48,0,14,4,1,1,9,1
+
+nPrbElemUl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+# weight base beams
+PrbElemUl0=0,48,0,14,1,1,1,9,1
+PrbElemUl1=48,48,0,14,2,1,1,9,1
+
+###########################################################
+
+## control of IQ byte order
+iqswap=0 #do swap of IQ before send buffer to eth
+nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
+compression=1 # (1) compression enabled (0) compression disabled
+
+##Debug
+debugStop=1 #stop app on 1pps boundary (gps_second % 30)
+debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary
+bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode
+
+CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled
+
+##O-RU Settings
+totalBFWeights=32 # Total number of Beamforming Weights on RU
+
+Tadv_cp_dl=25 # in us
+ # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages
+#Reception Window C-plane DL
+T2a_min_cp_dl=285 # 285.42us
+T2a_max_cp_dl=429 # 428.12us
+
+#Reception Window C-plane UL
+T2a_min_cp_ul=285 # 285.42us
+T2a_max_cp_ul=429 # 428.12us
+
+#Reception Window U-plane
+T2a_min_up=71 # 71.35in us
+T2a_max_up=428 # 428.12us
+
+#Transmission Window
+Ta3_min=20 # in us
+Ta3_max=32 # in us
+
+###########################################################
+##O-DU Settings
+#C-plane
+#Transmission Window Fast C-plane DL
+T1a_min_cp_dl=285
+T1a_max_cp_dl=429
+
+##Transmission Window Fast C-plane UL
+T1a_min_cp_ul=285
+T1a_max_cp_ul=300
+
+#U-plane
+##Transmission Window
+T1a_min_up=96 #71 + 25 us
+T1a_max_up=196 #71 + 25 us
+
+#Reception Window
+Ta4_min=0 # in us
+Ta4_max=75 # in us
+###########################################################
+