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* INTC Contribution to the O-RAN F Release for O-DU Low
[o-du/phy.git]
/
fhi_lib
/
app
/
usecase
/
cat_b
/
mu1_100mhz
/
101
/
config_file_o_ru.dat
diff --git
a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat
b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat
index
7a9ed73
..
f6c147f
100644
(file)
--- a/
fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat
+++ b/
fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat
@@
-78,7
+78,7
@@
ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
-numSlots=
1
0 #number of slots per IQ files
+numSlots=
2
0 #number of slots per IQ files
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0
antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0
antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0
@@
-113,11
+113,14
@@
antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3
antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3
-rachE
an
ble=0 # Enable (1)| disable (0) PRACH configuration
+rachE
na
ble=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin
antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin
@@
-160,10
+163,10
@@
antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
nPrbElemDl=2
DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used
nPrbElemDl=2
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
, Scalefactor, REMask
# weight base beams
# weight base beams
-PrbElemDl0=0,64,0,14,0,1,
1,9,1
-PrbElemDl1=64,26,0,14,1,1,
1,9,1
+PrbElemDl0=0,64,0,14,0,1,
4,3,1,5064,4095
+PrbElemDl1=64,26,0,14,1,1,
4,3,1,5064,4095
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
nPrbElemUl=2
#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
@@
-171,12
+174,15
@@
nPrbElemUl=2
PrbElemUl0=0,64,0,14,0,1,1,9,1
PrbElemUl1=64,26,0,14,1,1,1,9,1
PrbElemUl0=0,64,0,14,0,1,1,9,1
PrbElemUl1=64,26,0,14,1,1,1,9,1
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
###########################################################
## control of IQ byte order
iqswap=0 #do swap of IQ before send buffer to eth
nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order
-compression=
0
# (1) compression enabled (0) compression disabled
+compression=
1
# (1) compression enabled (0) compression disabled
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)
##Debug
debugStop=1 #stop app on 1pps boundary (gps_second % 30)