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* INTC Contribution to the O-RAN F Release for O-DU Low
[o-du/phy.git]
/
fhi_lib
/
app
/
usecase
/
cat_b
/
mu1_100mhz
/
101
/
config_file_o_du.dat
diff --git
a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat
b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat
index
2fa96ef
..
49f7f39
100644
(file)
--- a/
fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat
+++ b/
fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat
@@
-116,11
+116,14
@@
UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX anten
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
-rachE
an
ble=0 # Enable (1)| disable (0) PRACH configuration
+rachE
na
ble=0 # Enable (1)| disable (0) PRACH configuration
prachConfigIndex=189
prachConfigIndex=189
-srsEanble=1 # Enable (1)| disable (0) SRS
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3 # scheduled SRS slot within TDD period
+srsNdmOffset=3 # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4 # TX duration for NDM SRTS U-Plane (numberof of symbols)
###########################################################
##Section Settings
###########################################################
##Section Settings
@@
-145,6
+148,10
@@
PrbElemUl1=64,26,0,14,1,1,1,9,1
# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
ExtBfwUl0=64,2,0,0,9,1
ExtBfwUl1=13,2,0,0,9,1
# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
ExtBfwUl0=64,2,0,0,9,1
ExtBfwUl1=13,2,0,0,9,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
###########################################################
## control of IQ byte order
###########################################################
## control of IQ byte order