1 /******************************************************************************
3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * @brief XRAN layer common functionality for both lls-CU and RU as well as C-plane and
23 * @ingroup group_source_xran
24 * @author Intel Corporation
29 #include <arpa/inet.h>
33 #include "xran_frame_struct.h"
34 #include "xran_printf.h"
38 XRAN_BW_5_0_MHZ = 5, XRAN_BW_10_0_MHZ = 10, XRAN_BW_15_0_MHZ = 15, XRAN_BW_20_0_MHZ = 20, XRAN_BW_25_0_MHZ = 25,
39 XRAN_BW_30_0_MHZ = 30, XRAN_BW_40_0_MHZ = 40, XRAN_BW_50_0_MHZ = 50, XRAN_BW_60_0_MHZ = 60, XRAN_BW_70_0_MHZ = 70,
40 XRAN_BW_80_0_MHZ = 80, XRAN_BW_90_0_MHZ = 90, XRAN_BW_100_0_MHZ = 100, XRAN_BW_200_0_MHZ = 200, XRAN_BW_400_0_MHZ = 400
43 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
44 static uint16_t nNumRbsPerSymF1[3][13] =
46 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
47 {25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0}, // Numerology 0 (15KHz)
48 {11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273}, // Numerology 1 (30KHz)
49 {0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135} // Numerology 2 (60KHz)
52 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
53 static uint16_t nNumRbsPerSymF2[2][4] =
55 // 50Mhz 100MHz 200MHz 400MHz
56 {66, 132, 264, 0}, // Numerology 2 (60KHz)
57 {32, 66, 132, 264} // Numerology 3 (120KHz)
60 // 38.211 - Table 4.2.1
61 static uint16_t nSubCarrierSpacing[5] =
70 // TTI interval in us (slot duration)
71 static uint16_t nTtiInterval[4] =
79 // F1 Tables 38.101-1 Table F.5.3. Window length for normal CP
80 static uint16_t nCpSizeF1[3][13][2] =
82 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
83 {{40, 36}, {80, 72}, {120, 108}, {160, 144}, {160, 144}, {240, 216}, {320, 288}, {320, 288}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}}, // Numerology 0 (15KHz)
84 {{22, 18}, {44, 36}, {66, 54}, {88, 72}, {88, 72}, {132, 108}, {176, 144}, {176, 144}, {264, 216}, {264, 216}, {352, 288}, {352, 288}, {352, 288}}, // Numerology 1 (30KHz)
85 { {0, 0}, {26, 18}, {39, 27}, {52, 36}, {52, 36}, {78, 54}, {104, 72}, {104, 72}, {156, 108}, {156, 108}, {208, 144}, {208, 144}, {208, 144}}, // Numerology 2 (60KHz)
88 // F2 Tables 38.101-2 Table F.5.3. Window length for normal CP
89 static int16_t nCpSizeF2[2][4][2] =
91 // 50Mhz 100MHz 200MHz 400MHz
92 { {0, 0}, {104, 72}, {208, 144}, {416, 288}}, // Numerology 2 (60KHz)
93 {{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
96 static uint32_t xran_fs_max_slot_num = 8000;
97 static uint32_t xran_fs_max_slot_num_SFN = 20480; /* max slot number counted as SFN is 0-1023 */
98 static uint16_t xran_fs_num_slot_tdd_loop[XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP };
99 static uint16_t xran_fs_num_dl_sym_sp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
100 static uint16_t xran_fs_num_ul_sym_sp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
101 static uint8_t xran_fs_slot_type[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}};
102 static uint8_t xran_fs_slot_symb_type[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{XRAN_SLOT_TYPE_INVALID}}};
103 static float xran_fs_ul_rate[XRAN_MAX_SECTOR_NR] = {0.0};
104 static float xran_fs_dl_rate[XRAN_MAX_SECTOR_NR] = {0.0};
106 extern uint16_t xran_max_frame;
108 uint32_t xran_fs_get_tti_interval(uint8_t nMu)
112 return nTtiInterval[nMu];
116 printf("ERROR: %s Mu[%d] is not valid, setting to 0\n",__FUNCTION__, nMu);
117 return nTtiInterval[0];
121 uint32_t xran_fs_get_scs(uint8_t nMu)
125 return nSubCarrierSpacing[nMu];
129 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
135 //-------------------------------------------------------------------------------------------
136 /** @ingroup group_nr5g_source_phy_common
138 * @param[in] nNumerology - Numerology determine sub carrier spacing, Value: 0->4 0: 15khz, 1: 30khz, 2: 60khz 3: 120khz, 4: 240khz
139 * @param[in] nBandwidth - Carrier bandwidth for in MHz. Value: 5->400
140 * @param[in] nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
142 * @return Number of RBs in cell
145 * Returns number of RBs based on 38.101-1 and 38.101-2 for the cell
148 //-------------------------------------------------------------------------------------------
149 uint16_t xran_fs_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
154 if (nAbsFrePointA <= 6000000)
156 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
161 case XRAN_BW_5_0_MHZ:
162 numRBs = nNumRbsPerSymF1[nNumerology][0];
165 case XRAN_BW_10_0_MHZ:
166 numRBs = nNumRbsPerSymF1[nNumerology][1];
169 case XRAN_BW_15_0_MHZ:
170 numRBs = nNumRbsPerSymF1[nNumerology][2];
173 case XRAN_BW_20_0_MHZ:
174 numRBs = nNumRbsPerSymF1[nNumerology][3];
177 case XRAN_BW_25_0_MHZ:
178 numRBs = nNumRbsPerSymF1[nNumerology][4];
181 case XRAN_BW_30_0_MHZ:
182 numRBs = nNumRbsPerSymF1[nNumerology][5];
185 case XRAN_BW_40_0_MHZ:
186 numRBs = nNumRbsPerSymF1[nNumerology][6];
189 case XRAN_BW_50_0_MHZ:
190 numRBs = nNumRbsPerSymF1[nNumerology][7];
193 case XRAN_BW_60_0_MHZ:
194 numRBs = nNumRbsPerSymF1[nNumerology][8];
197 case XRAN_BW_70_0_MHZ:
198 numRBs = nNumRbsPerSymF1[nNumerology][9];
201 case XRAN_BW_80_0_MHZ:
202 numRBs = nNumRbsPerSymF1[nNumerology][10];
205 case XRAN_BW_90_0_MHZ:
206 numRBs = nNumRbsPerSymF1[nNumerology][11];
209 case XRAN_BW_100_0_MHZ:
210 numRBs = nNumRbsPerSymF1[nNumerology][12];
221 if ((nNumerology >= 2) && (nNumerology <= 3))
223 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
226 case XRAN_BW_50_0_MHZ:
227 numRBs = nNumRbsPerSymF2[nNumerology-2][0];
230 case XRAN_BW_100_0_MHZ:
231 numRBs = nNumRbsPerSymF2[nNumerology-2][1];
234 case XRAN_BW_200_0_MHZ:
235 numRBs = nNumRbsPerSymF2[nNumerology-2][2];
238 case XRAN_BW_400_0_MHZ:
239 numRBs = nNumRbsPerSymF2[nNumerology-2][3];
252 printf("ERROR: %s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA);
256 printf("%s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA, numRBs);
262 //-------------------------------------------------------------------------------------------
263 /** @ingroup phy_cal_nrarfcn
265 * @param[in] center frequency
270 * This calculates NR-ARFCN value according to center frequency
273 //-------------------------------------------------------------------------------------------
274 uint32_t xran_fs_cal_nrarfcn(uint32_t nCenterFreq)
276 uint32_t nDeltaFglobal,nFoffs,nNoffs;
277 uint32_t nNRARFCN = 0;
279 if(nCenterFreq > 0 && nCenterFreq < 3000*1000)
285 else if(nCenterFreq >= 3000*1000 && nCenterFreq < 24250*1000)
291 else if(nCenterFreq >= 24250*1000 && nCenterFreq <= 100000*1000)
299 printf("@@@@ incorrect center frerquency %d\n",nCenterFreq);
303 nNRARFCN = ((nCenterFreq - nFoffs)/nDeltaFglobal) + nNoffs;
305 printf("%s: nCenterFreq[%d] nDeltaFglobal[%d] nFoffs[%d] nNoffs[%d] nNRARFCN[%d]\n", __FUNCTION__, nCenterFreq, nDeltaFglobal, nFoffs, nNoffs, nNRARFCN);
309 uint32_t xran_fs_slot_limit_init(int32_t tti_interval_us)
311 xran_fs_max_slot_num = (1000/tti_interval_us)*1000;
312 xran_fs_max_slot_num_SFN = (1000/tti_interval_us)*(xran_max_frame+1)*10;
313 return xran_fs_max_slot_num;
316 uint32_t xran_fs_get_max_slot(void)
318 return xran_fs_max_slot_num;
321 uint32_t xran_fs_get_max_slot_SFN(void)
323 return xran_fs_max_slot_num_SFN;
326 int32_t xran_fs_slot_limit(int32_t nSfIdx)
329 nSfIdx += xran_fs_max_slot_num;
332 while (nSfIdx >= xran_fs_max_slot_num) {
333 nSfIdx -= xran_fs_max_slot_num;
339 void xran_fs_clear_slot_type(uint32_t nPhyInstanceId)
341 xran_fs_ul_rate[nPhyInstanceId] = 0.0;
342 xran_fs_dl_rate[nPhyInstanceId] = 0.0;
343 xran_fs_num_slot_tdd_loop[nPhyInstanceId] = 1;
346 int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig)
348 uint32_t nSlotNum, nSymNum, nVal, i, j;
349 uint32_t numDlSym, numUlSym, numGuardSym;
350 uint32_t numDlSlots = 0, numUlSlots = 0, numSpDlSlots = 0, numSpUlSlots = 0, numSpSlots = 0;
351 char sSlotPattern[XRAN_SLOT_TYPE_LAST][10] = {"IN\0", "DL\0", "UL\0", "SP\0", "FD\0"};
353 // nPhyInstanceId Carrier ID
354 // nFrameDuplexType 0 = FDD 1 = TDD
355 // nTddPeriod Tdd Periodicity
356 // psSlotConfig[80] Slot Config Structure for nTddPeriod Slots
358 xran_fs_ul_rate[nPhyInstanceId] = 0.0;
359 xran_fs_dl_rate[nPhyInstanceId] = 0.0;
360 xran_fs_num_slot_tdd_loop[nPhyInstanceId] = nTddPeriod;
362 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
364 xran_fs_slot_type[nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID;
365 xran_fs_num_dl_sym_sp[nPhyInstanceId][i] = 0;
366 xran_fs_num_ul_sym_sp[nPhyInstanceId][i] = 0;
369 if (nFrameDuplexType == XRAN_FDD)
371 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
373 xran_fs_slot_type[nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD;
374 for(j = 0; j < XRAN_NUM_OF_SYMBOL_PER_SLOT; j++)
375 xran_fs_slot_symb_type[nPhyInstanceId][i][j] = XRAN_SYMBOL_TYPE_FDD;
377 xran_fs_num_slot_tdd_loop[nPhyInstanceId] = 1;
378 xran_fs_dl_rate[nPhyInstanceId] = 1.0;
379 xran_fs_ul_rate[nPhyInstanceId] = 1.0;
383 for (nSlotNum = 0; nSlotNum < nTddPeriod; nSlotNum++)
388 for (nSymNum = 0; nSymNum < XRAN_NUM_OF_SYMBOL_PER_SLOT; nSymNum++)
390 switch(psSlotConfig[nSlotNum].nSymbolType[nSymNum])
392 case XRAN_SYMBOL_TYPE_DL:
394 xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_DL;
396 case XRAN_SYMBOL_TYPE_GUARD:
397 xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_GUARD;
401 xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_UL;
407 print_dbg("nSlotNum[%d] : numDlSym[%d] numGuardSym[%d] numUlSym[%d] ", nSlotNum, numDlSym, numGuardSym, numUlSym);
409 if ((numUlSym == 0) && (numGuardSym == 0))
411 xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL;
413 print_dbg("XRAN_SLOT_TYPE_DL\n");
415 else if ((numDlSym == 0) && (numGuardSym == 0))
417 xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL;
419 print_dbg("XRAN_SLOT_TYPE_UL\n");
423 xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP;
425 print_dbg("XRAN_SLOT_TYPE_SP\n");
430 xran_fs_num_dl_sym_sp[nPhyInstanceId][nSlotNum] = numDlSym;
435 xran_fs_num_ul_sym_sp[nPhyInstanceId][nSlotNum] = numUlSym;
438 print_dbg(" numDlSlots[%d] numUlSlots[%d] numSpSlots[%d] numSpDlSlots[%d] numSpUlSlots[%d]\n", numDlSlots, numUlSlots, numSpSlots, numSpDlSlots, numSpUlSlots);
441 xran_fs_dl_rate[nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod;
442 xran_fs_ul_rate[nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod;
445 print_dbg("%s: nPhyInstanceId[%d] nFrameDuplexType[%d], nTddPeriod[%d]\n",
446 __FUNCTION__, nPhyInstanceId, nFrameDuplexType, nTddPeriod);
448 print_dbg("DLRate[%f] ULRate[%f]\n", xran_fs_dl_rate[nPhyInstanceId], xran_fs_ul_rate[nPhyInstanceId]);
450 nVal = (xran_fs_num_slot_tdd_loop[nPhyInstanceId] < 10) ? xran_fs_num_slot_tdd_loop[nPhyInstanceId] : 10;
452 print_dbg("SlotPattern:\n");
454 for (nSlotNum = 0; nSlotNum < nVal; nSlotNum++)
456 print_dbg("%d ", nSlotNum);
460 print_dbg(" %3d ", 0);
461 for (nSlotNum = 0, i = 0; nSlotNum < xran_fs_num_slot_tdd_loop[nPhyInstanceId]; nSlotNum++)
463 print_dbg("%s ", sSlotPattern[xran_fs_slot_type[nPhyInstanceId][nSlotNum]]);
465 if ((i == 10) && ((nSlotNum+1) < xran_fs_num_slot_tdd_loop[nPhyInstanceId]))
468 print_dbg(" %3d ", nSlotNum);
477 int32_t xran_fs_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType)
479 int32_t nSfIdxMod, nSfType, ret = 0;
481 nSfIdxMod = xran_fs_slot_limit(nSlotdx) % ((xran_fs_num_slot_tdd_loop[nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[nCellIdx]: 1);
482 nSfType = xran_fs_slot_type[nCellIdx][nSfIdxMod];
484 if (nSfType == nType)
488 else if (nSfType == XRAN_SLOT_TYPE_SP)
490 if ((nType == XRAN_SLOT_TYPE_DL) && xran_fs_num_dl_sym_sp[nCellIdx][nSfIdxMod])
495 if ((nType == XRAN_SLOT_TYPE_UL) && xran_fs_num_ul_sym_sp[nCellIdx][nSfIdxMod])
500 else if (nSfType == XRAN_SLOT_TYPE_FDD)
508 int32_t xran_fs_get_symbol_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx)
510 int32_t nSfIdxMod, nSfType, ret = 0;
512 nSfIdxMod = xran_fs_slot_limit(nSlotdx) % ((xran_fs_num_slot_tdd_loop[nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[nCellIdx]: 1);
514 return xran_fs_slot_symb_type[nCellIdx][nSfIdxMod][nSymbIdx];