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3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
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14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
21 * @brief XRAN layer common functionality for both lls-CU and RU as well as C-plane and
24 * @ingroup group_source_xran
25 * @author Intel Corporation
30 #include <arpa/inet.h>
34 #include "xran_frame_struct.h"
35 #include "xran_printf.h"
39 XRAN_BW_5_0_MHZ = 5, XRAN_BW_10_0_MHZ = 10, XRAN_BW_15_0_MHZ = 15, XRAN_BW_20_0_MHZ = 20, XRAN_BW_25_0_MHZ = 25,
40 XRAN_BW_30_0_MHZ = 30, XRAN_BW_40_0_MHZ = 40, XRAN_BW_50_0_MHZ = 50, XRAN_BW_60_0_MHZ = 60, XRAN_BW_70_0_MHZ = 70,
41 XRAN_BW_80_0_MHZ = 80, XRAN_BW_90_0_MHZ = 90, XRAN_BW_100_0_MHZ = 100, XRAN_BW_200_0_MHZ = 200, XRAN_BW_400_0_MHZ = 400
44 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
45 static uint16_t nNumRbsPerSymF1[3][13] =
47 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
48 {25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0}, // Numerology 0 (15KHz)
49 {11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273}, // Numerology 1 (30KHz)
50 {0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135} // Numerology 2 (60KHz)
53 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
54 static uint16_t nNumRbsPerSymF2[2][4] =
56 // 50Mhz 100MHz 200MHz 400MHz
57 {66, 132, 264, 0}, // Numerology 2 (60KHz)
58 {32, 66, 132, 264} // Numerology 3 (120KHz)
61 // 38.211 - Table 4.2.1
62 static uint16_t nSubCarrierSpacing[5] =
71 // TTI interval in us (slot duration)
72 static uint16_t nTtiInterval[4] =
80 // F1 Tables 38.101-1 Table F.5.3. Window length for normal CP
81 static uint16_t nCpSizeF1[3][13][2] =
83 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
84 {{40, 36}, {80, 72}, {120, 108}, {160, 144}, {160, 144}, {240, 216}, {320, 288}, {320, 288}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}}, // Numerology 0 (15KHz)
85 {{22, 18}, {44, 36}, {66, 54}, {88, 72}, {88, 72}, {132, 108}, {176, 144}, {176, 144}, {264, 216}, {264, 216}, {352, 288}, {352, 288}, {352, 288}}, // Numerology 1 (30KHz)
86 { {0, 0}, {26, 18}, {39, 27}, {52, 36}, {52, 36}, {78, 54}, {104, 72}, {104, 72}, {156, 108}, {156, 108}, {208, 144}, {208, 144}, {208, 144}}, // Numerology 2 (60KHz)
89 // F2 Tables 38.101-2 Table F.5.3. Window length for normal CP
90 static int16_t nCpSizeF2[2][4][2] =
92 // 50Mhz 100MHz 200MHz 400MHz
93 { {0, 0}, {104, 72}, {208, 144}, {416, 288}}, // Numerology 2 (60KHz)
94 {{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
97 static uint32_t xran_fs_max_slot_num = 8000;
98 static uint16_t xran_fs_num_slot_tdd_loop[XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP };
99 static uint16_t xran_fs_num_dl_sym_sp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
100 static uint16_t xran_fs_num_ul_sym_sp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
101 static uint8_t xran_fs_slot_type[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}};
102 static uint8_t xran_fs_slot_symb_type[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{XRAN_SLOT_TYPE_INVALID}}};
103 static float xran_fs_ul_rate[XRAN_MAX_SECTOR_NR] = {0.0};
104 static float xran_fs_dl_rate[XRAN_MAX_SECTOR_NR] = {0.0};
106 uint32_t xran_fs_get_tti_interval(uint8_t nMu)
110 return nTtiInterval[nMu];
114 printf("ERROR: %s Mu[%d] is not valid, setting to 0\n",__FUNCTION__, nMu);
115 return nTtiInterval[0];
119 uint32_t xran_fs_get_scs(uint8_t nMu)
123 return nSubCarrierSpacing[nMu];
127 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
133 //-------------------------------------------------------------------------------------------
134 /** @ingroup group_nr5g_source_phy_common
136 * @param[in] nNumerology - Numerology determine sub carrier spacing, Value: 0->4 0: 15khz, 1: 30khz, 2: 60khz 3: 120khz, 4: 240khz
137 * @param[in] nBandwidth - Carrier bandwidth for in MHz. Value: 5->400
138 * @param[in] nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
140 * @return Number of RBs in cell
143 * Returns number of RBs based on 38.101-1 and 38.101-2 for the cell
146 //-------------------------------------------------------------------------------------------
147 uint16_t xran_fs_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
152 if (nAbsFrePointA <= 6000000)
154 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
159 case XRAN_BW_5_0_MHZ:
160 numRBs = nNumRbsPerSymF1[nNumerology][0];
163 case XRAN_BW_10_0_MHZ:
164 numRBs = nNumRbsPerSymF1[nNumerology][1];
167 case XRAN_BW_15_0_MHZ:
168 numRBs = nNumRbsPerSymF1[nNumerology][2];
171 case XRAN_BW_20_0_MHZ:
172 numRBs = nNumRbsPerSymF1[nNumerology][3];
175 case XRAN_BW_25_0_MHZ:
176 numRBs = nNumRbsPerSymF1[nNumerology][4];
179 case XRAN_BW_30_0_MHZ:
180 numRBs = nNumRbsPerSymF1[nNumerology][5];
183 case XRAN_BW_40_0_MHZ:
184 numRBs = nNumRbsPerSymF1[nNumerology][6];
187 case XRAN_BW_50_0_MHZ:
188 numRBs = nNumRbsPerSymF1[nNumerology][7];
191 case XRAN_BW_60_0_MHZ:
192 numRBs = nNumRbsPerSymF1[nNumerology][8];
195 case XRAN_BW_70_0_MHZ:
196 numRBs = nNumRbsPerSymF1[nNumerology][9];
199 case XRAN_BW_80_0_MHZ:
200 numRBs = nNumRbsPerSymF1[nNumerology][10];
203 case XRAN_BW_90_0_MHZ:
204 numRBs = nNumRbsPerSymF1[nNumerology][11];
207 case XRAN_BW_100_0_MHZ:
208 numRBs = nNumRbsPerSymF1[nNumerology][12];
219 if ((nNumerology >= 2) && (nNumerology <= 3))
221 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
224 case XRAN_BW_50_0_MHZ:
225 numRBs = nNumRbsPerSymF2[nNumerology-2][0];
228 case XRAN_BW_100_0_MHZ:
229 numRBs = nNumRbsPerSymF2[nNumerology-2][1];
232 case XRAN_BW_200_0_MHZ:
233 numRBs = nNumRbsPerSymF2[nNumerology-2][2];
236 case XRAN_BW_400_0_MHZ:
237 numRBs = nNumRbsPerSymF2[nNumerology-2][3];
250 printf("ERROR: %s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA);
254 printf("%s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA, numRBs);
260 //-------------------------------------------------------------------------------------------
261 /** @ingroup phy_cal_nrarfcn
263 * @param[in] center frequency
268 * This calculates NR-ARFCN value according to center frequency
271 //-------------------------------------------------------------------------------------------
272 uint32_t xran_fs_cal_nrarfcn(uint32_t nCenterFreq)
274 uint32_t nDeltaFglobal,nFoffs,nNoffs;
275 uint32_t nNRARFCN = 0;
277 if(nCenterFreq > 0 && nCenterFreq < 3000*1000)
283 else if(nCenterFreq >= 3000*1000 && nCenterFreq < 24250*1000)
289 else if(nCenterFreq >= 24250*1000 && nCenterFreq <= 100000*1000)
297 printf("@@@@ incorrect center frerquency %d\n",nCenterFreq);
301 nNRARFCN = ((nCenterFreq - nFoffs)/nDeltaFglobal) + nNoffs;
303 printf("%s: nCenterFreq[%d] nDeltaFglobal[%d] nFoffs[%d] nNoffs[%d] nNRARFCN[%d]\n", __FUNCTION__, nCenterFreq, nDeltaFglobal, nFoffs, nNoffs, nNRARFCN);
307 uint32_t xran_fs_slot_limit_init(int32_t tti_interval_us)
309 xran_fs_max_slot_num = (1000/tti_interval_us)*1000;
310 return xran_fs_max_slot_num;
313 uint32_t xran_fs_get_max_slot(void)
315 return xran_fs_max_slot_num;
318 int32_t xran_fs_slot_limit(int32_t nSfIdx)
321 nSfIdx += xran_fs_max_slot_num;
324 while (nSfIdx >= xran_fs_max_slot_num) {
325 nSfIdx -= xran_fs_max_slot_num;
331 void xran_fs_clear_slot_type(uint32_t nPhyInstanceId)
333 xran_fs_ul_rate[nPhyInstanceId] = 0.0;
334 xran_fs_dl_rate[nPhyInstanceId] = 0.0;
335 xran_fs_num_slot_tdd_loop[nPhyInstanceId] = 1;
338 int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig)
340 uint32_t nSlotNum, nSymNum, nVal, i, j;
341 uint32_t numDlSym, numUlSym, numGuardSym;
342 uint32_t numDlSlots = 0, numUlSlots = 0, numSpDlSlots = 0, numSpUlSlots = 0, numSpSlots = 0;
343 char sSlotPattern[XRAN_SLOT_TYPE_LAST][10] = {"IN\0", "DL\0", "UL\0", "SP\0", "FD\0"};
345 // nPhyInstanceId Carrier ID
346 // nFrameDuplexType 0 = FDD 1 = TDD
347 // nTddPeriod Tdd Periodicity
348 // psSlotConfig[80] Slot Config Structure for nTddPeriod Slots
350 xran_fs_ul_rate[nPhyInstanceId] = 0.0;
351 xran_fs_dl_rate[nPhyInstanceId] = 0.0;
352 xran_fs_num_slot_tdd_loop[nPhyInstanceId] = nTddPeriod;
354 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
356 xran_fs_slot_type[nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID;
357 xran_fs_num_dl_sym_sp[nPhyInstanceId][i] = 0;
358 xran_fs_num_ul_sym_sp[nPhyInstanceId][i] = 0;
361 if (nFrameDuplexType == XRAN_FDD)
363 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
365 xran_fs_slot_type[nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD;
366 for(j = 0; j < XRAN_NUM_OF_SYMBOL_PER_SLOT; j++)
367 xran_fs_slot_symb_type[nPhyInstanceId][i][j] = XRAN_SYMBOL_TYPE_FDD;
369 xran_fs_num_slot_tdd_loop[nPhyInstanceId] = 1;
370 xran_fs_dl_rate[nPhyInstanceId] = 1.0;
371 xran_fs_ul_rate[nPhyInstanceId] = 1.0;
375 for (nSlotNum = 0; nSlotNum < nTddPeriod; nSlotNum++)
380 for (nSymNum = 0; nSymNum < XRAN_NUM_OF_SYMBOL_PER_SLOT; nSymNum++)
382 switch(psSlotConfig[nSlotNum].nSymbolType[nSymNum])
384 case XRAN_SYMBOL_TYPE_DL:
386 xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_DL;
388 case XRAN_SYMBOL_TYPE_GUARD:
389 xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_GUARD;
393 xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_UL;
399 print_dbg("nSlotNum[%d] : numDlSym[%d] numGuardSym[%d] numUlSym[%d] ", nSlotNum, numDlSym, numGuardSym, numUlSym);
401 if ((numUlSym == 0) && (numGuardSym == 0))
403 xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL;
405 print_dbg("XRAN_SLOT_TYPE_DL\n");
407 else if ((numDlSym == 0) && (numGuardSym == 0))
409 xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL;
411 print_dbg("XRAN_SLOT_TYPE_UL\n");
415 xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP;
417 print_dbg("XRAN_SLOT_TYPE_SP\n");
422 xran_fs_num_dl_sym_sp[nPhyInstanceId][nSlotNum] = numDlSym;
427 xran_fs_num_ul_sym_sp[nPhyInstanceId][nSlotNum] = numUlSym;
430 print_dbg(" numDlSlots[%d] numUlSlots[%d] numSpSlots[%d] numSpDlSlots[%d] numSpUlSlots[%d]\n", numDlSlots, numUlSlots, numSpSlots, numSpDlSlots, numSpUlSlots);
433 xran_fs_dl_rate[nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod;
434 xran_fs_ul_rate[nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod;
437 print_dbg("%s: nPhyInstanceId[%d] nFrameDuplexType[%d], nTddPeriod[%d]\n",
438 __FUNCTION__, nPhyInstanceId, nFrameDuplexType, nTddPeriod);
440 print_dbg("DLRate[%f] ULRate[%f]\n", xran_fs_dl_rate[nPhyInstanceId], xran_fs_ul_rate[nPhyInstanceId]);
442 nVal = (xran_fs_num_slot_tdd_loop[nPhyInstanceId] < 10) ? xran_fs_num_slot_tdd_loop[nPhyInstanceId] : 10;
444 print_dbg("SlotPattern:\n");
446 for (nSlotNum = 0; nSlotNum < nVal; nSlotNum++)
448 print_dbg("%d ", nSlotNum);
452 print_dbg(" %3d ", 0);
453 for (nSlotNum = 0, i = 0; nSlotNum < xran_fs_num_slot_tdd_loop[nPhyInstanceId]; nSlotNum++)
455 print_dbg("%s ", sSlotPattern[xran_fs_slot_type[nPhyInstanceId][nSlotNum]]);
457 if ((i == 10) && ((nSlotNum+1) < xran_fs_num_slot_tdd_loop[nPhyInstanceId]))
460 print_dbg(" %3d ", nSlotNum);
469 int32_t xran_fs_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType)
471 int32_t nSfIdxMod, nSfType, ret = 0;
473 nSfIdxMod = xran_fs_slot_limit(nSlotdx) % ((xran_fs_num_slot_tdd_loop[nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[nCellIdx]: 1);
474 nSfType = xran_fs_slot_type[nCellIdx][nSfIdxMod];
476 if (nSfType == nType)
480 else if (nSfType == XRAN_SLOT_TYPE_SP)
482 if ((nType == XRAN_SLOT_TYPE_DL) && xran_fs_num_dl_sym_sp[nCellIdx][nSfIdxMod])
487 if ((nType == XRAN_SLOT_TYPE_UL) && xran_fs_num_ul_sym_sp[nCellIdx][nSfIdxMod])
492 else if (nSfType == XRAN_SLOT_TYPE_FDD)
500 int32_t xran_fs_get_symbol_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx)
502 int32_t nSfIdxMod, nSfType, ret = 0;
504 nSfIdxMod = xran_fs_slot_limit(nSlotdx) % ((xran_fs_num_slot_tdd_loop[nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[nCellIdx]: 1);
506 return xran_fs_slot_symb_type[nCellIdx][nSfIdxMod][nSymbIdx];